X-Git-Url: http://git.sourceforge.jp/view?p=pf3gnuchains%2Fgcc-fork.git;a=blobdiff_plain;f=gcc%2Fdoc%2Finvoke.texi;h=a67d6637c497937aad999ae3f3872a84746f3c62;hp=ecfa5fe3e286ea213bdb455fcd5530f410f696ce;hb=5ff22aea8fd9b39bfa3329bae1e78326c098d716;hpb=4bd4c50203093f79151be52fbdda2c35e70cf8d7 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ecfa5fe3e28..a67d6637c49 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -549,7 +549,13 @@ Objective-C and Objective-C++ Dialects}. -minline-sqrt-min-latency -minline-sqrt-max-throughput @gol -mno-dwarf2-asm -mearly-stop-bits @gol -mfixed-range=@var{register-range} -mtls-size=@var{tls-size} @gol --mtune=@var{cpu-type} -mt -pthread -milp32 -mlp64} +-mtune=@var{cpu-type} -mt -pthread -milp32 -mlp64 @gol +-mno-sched-br-data-spec -msched-ar-data-spec -mno-sched-control-spec @gol +-msched-br-in-data-spec -msched-ar-in-data-spec -msched-in-control-spec @gol +-msched-ldc -mno-sched-control-ldc -mno-sched-spec-verbose @gol +-mno-sched-prefer-non-data-spec-insns @gol +-mno-sched-prefer-non-control-spec-insns @gol +-mno-sched-count-spec-in-critical-path} @emph{M32R/D Options} @gccoptlist{-m32r2 -m32rx -m32r @gol @@ -670,6 +676,7 @@ See RS/6000 and PowerPC Options. -mspe=yes -mspe=no @gol -mvrsave -mno-vrsave @gol -mmulhw -mno-mulhw @gol +-mdlmzb -mno-dlmzb @gol -mfloat-gprs=yes -mfloat-gprs=no -mfloat-gprs=single -mfloat-gprs=double @gol -mprototype -mno-prototype @gol -msim -mmvme -mads -myellowknife -memb -msdata @gol @@ -766,8 +773,8 @@ See S/390 and zSeries Options. -fverbose-asm -fpack-struct[=@var{n}] -fstack-check @gol -fstack-limit-register=@var{reg} -fstack-limit-symbol=@var{sym} @gol -fargument-alias -fargument-noalias @gol --fargument-noalias-global -fleading-underscore @gol --ftls-model=@var{model} @gol +-fargument-noalias-global -fargument-noalias-anything +-fleading-underscore -ftls-model=@var{model} @gol -ftrapv -fwrapv -fbounds-check @gol -fvisibility -fopenmp} @end table @@ -3716,13 +3723,13 @@ Annotate the assembler output with miscellaneous debugging information. @itemx -fdump-rtl-bbro @opindex dB @opindex fdump-rtl-bbro -Dump after block reordering, to @file{@var{file}.30.bbro}. +Dump after block reordering, to @file{@var{file}.148r.bbro}. @item -dc @itemx -fdump-rtl-combine @opindex dc @opindex fdump-rtl-combine -Dump after instruction combination, to the file @file{@var{file}.17.combine}. +Dump after instruction combination, to the file @file{@var{file}.129r.combine}. @item -dC @itemx -fdump-rtl-ce1 @@ -3731,9 +3738,9 @@ Dump after instruction combination, to the file @file{@var{file}.17.combine}. @opindex fdump-rtl-ce1 @opindex fdump-rtl-ce2 @option{-dC} and @option{-fdump-rtl-ce1} enable dumping after the -first if conversion, to the file @file{@var{file}.11.ce1}. @option{-dC} +first if conversion, to the file @file{@var{file}.117r.ce1}. @option{-dC} and @option{-fdump-rtl-ce2} enable dumping after the second if -conversion, to the file @file{@var{file}.18.ce2}. +conversion, to the file @file{@var{file}.130r.ce2}. @item -dd @itemx -fdump-rtl-btl @@ -3755,7 +3762,7 @@ normal output. @itemx -fdump-rtl-ce3 @opindex dE @opindex fdump-rtl-ce3 -Dump after the third if conversion, to @file{@var{file}.28.ce3}. +Dump after the third if conversion, to @file{@var{file}.146r.ce3}. @item -df @itemx -fdump-rtl-cfg @@ -3764,15 +3771,15 @@ Dump after the third if conversion, to @file{@var{file}.28.ce3}. @opindex fdump-rtl-cfg @opindex fdump-rtl-life @option{-df} and @option{-fdump-rtl-cfg} enable dumping after control -and data flow analysis, to @file{@var{file}.08.cfg}. @option{-df} +and data flow analysis, to @file{@var{file}.116r.cfg}. @option{-df} and @option{-fdump-rtl-cfg} enable dumping dump after life analysis, -to @file{@var{file}.16.life}. +to @file{@var{file}.128r.life1} and @file{@var{file}.135r.life2}. @item -dg @itemx -fdump-rtl-greg @opindex dg @opindex fdump-rtl-greg -Dump after global register allocation, to @file{@var{file}.23.greg}. +Dump after global register allocation, to @file{@var{file}.139r.greg}. @item -dG @itemx -fdump-rtl-gcse @@ -3781,9 +3788,9 @@ Dump after global register allocation, to @file{@var{file}.23.greg}. @opindex fdump-rtl-gcse @opindex fdump-rtl-bypass @option{-dG} and @option{-fdump-rtl-gcse} enable dumping after GCSE, to -@file{@var{file}.05.gcse}. @option{-dG} and @option{-fdump-rtl-bypass} +@file{@var{file}.114r.gcse}. @option{-dG} and @option{-fdump-rtl-bypass} enable dumping after jump bypassing and control flow optimizations, to -@file{@var{file}.07.bypass}. +@file{@var{file}.115r.bypass}. @item -dh @itemx -fdump-rtl-eh @@ -3795,25 +3802,25 @@ Dump after finalization of EH handling code, to @file{@var{file}.02.eh}. @itemx -fdump-rtl-sibling @opindex di @opindex fdump-rtl-sibling -Dump after sibling call optimizations, to @file{@var{file}.01.sibling}. +Dump after sibling call optimizations, to @file{@var{file}.106r.sibling}. @item -dj @itemx -fdump-rtl-jump @opindex dj @opindex fdump-rtl-jump -Dump after the first jump optimization, to @file{@var{file}.03.jump}. +Dump after the first jump optimization, to @file{@var{file}.112r.jump}. @item -dk @itemx -fdump-rtl-stack @opindex dk @opindex fdump-rtl-stack -Dump after conversion from registers to stack, to @file{@var{file}.33.stack}. +Dump after conversion from registers to stack, to @file{@var{file}.152r.stack}. @item -dl @itemx -fdump-rtl-lreg @opindex dl @opindex fdump-rtl-lreg -Dump after local register allocation, to @file{@var{file}.22.lreg}. +Dump after local register allocation, to @file{@var{file}.138r.lreg}. @item -dL @itemx -fdump-rtl-loop2 @@ -3822,33 +3829,33 @@ Dump after local register allocation, to @file{@var{file}.22.lreg}. @option{-dL} and @option{-fdump-rtl-loop2} enable dumping after the loop optimization pass, to @file{@var{file}.119r.loop2}, @file{@var{file}.120r.loop2_init}, -@file{@var{file}.121r.loop2_invariant}, +@file{@var{file}.121r.loop2_invariant}, and @file{@var{file}.125r.loop2_done}. @item -dm @itemx -fdump-rtl-sms @opindex dm @opindex fdump-rtl-sms -Dump after modulo scheduling, to @file{@var{file}.20.sms}. +Dump after modulo scheduling, to @file{@var{file}.136r.sms}. @item -dM @itemx -fdump-rtl-mach @opindex dM @opindex fdump-rtl-mach Dump after performing the machine dependent reorganization pass, to -@file{@var{file}.35.mach}. +@file{@var{file}.155r.mach}. @item -dn @itemx -fdump-rtl-rnreg @opindex dn @opindex fdump-rtl-rnreg -Dump after register renumbering, to @file{@var{file}.29.rnreg}. +Dump after register renumbering, to @file{@var{file}.147r.rnreg}. @item -dN @itemx -fdump-rtl-regmove @opindex dN @opindex fdump-rtl-regmove -Dump after the register move pass, to @file{@var{file}.19.regmove}. +Dump after the register move pass, to @file{@var{file}.132r.regmove}. @item -do @itemx -fdump-rtl-postreload @@ -3860,20 +3867,20 @@ Dump after post-reload optimizations, to @file{@var{file}.24.postreload}. @itemx -fdump-rtl-expand @opindex dr @opindex fdump-rtl-expand -Dump after RTL generation, to @file{@var{file}.00.expand}. +Dump after RTL generation, to @file{@var{file}.104r.expand}. @item -dR @itemx -fdump-rtl-sched2 @opindex dR @opindex fdump-rtl-sched2 -Dump after the second scheduling pass, to @file{@var{file}.32.sched2}. +Dump after the second scheduling pass, to @file{@var{file}.150r.sched2}. @item -ds @itemx -fdump-rtl-cse @opindex ds @opindex fdump-rtl-cse Dump after CSE (including the jump optimization that sometimes follows -CSE), to @file{@var{file}.04.cse}. +CSE), to @file{@var{file}.113r.cse}. @item -dS @itemx -fdump-rtl-sched @@ -3886,13 +3893,13 @@ Dump after the first scheduling pass, to @file{@var{file}.21.sched}. @opindex dt @opindex fdump-rtl-cse2 Dump after the second CSE pass (including the jump optimization that -sometimes follows CSE), to @file{@var{file}.15.cse2}. +sometimes follows CSE), to @file{@var{file}.127r.cse2}. @item -dT @itemx -fdump-rtl-tracer @opindex dT @opindex fdump-rtl-tracer -Dump after running tracer, to @file{@var{file}.12.tracer}. +Dump after running tracer, to @file{@var{file}.118r.tracer}. @item -dV @itemx -fdump-rtl-vpt @@ -3903,25 +3910,25 @@ Dump after running tracer, to @file{@var{file}.12.tracer}. @option{-dV} and @option{-fdump-rtl-vpt} enable dumping after the value profile transformations, to @file{@var{file}.10.vpt}. @option{-dV} and @option{-fdump-rtl-vartrack} enable dumping after variable tracking, -to @file{@var{file}.34.vartrack}. +to @file{@var{file}.154r.vartrack}. @item -dw @itemx -fdump-rtl-flow2 @opindex dw @opindex fdump-rtl-flow2 -Dump after the second flow pass, to @file{@var{file}.26.flow2}. +Dump after the second flow pass, to @file{@var{file}.142r.flow2}. @item -dz @itemx -fdump-rtl-peephole2 @opindex dz @opindex fdump-rtl-peephole2 -Dump after the peephole pass, to @file{@var{file}.27.peephole2}. +Dump after the peephole pass, to @file{@var{file}.145r.peephole2}. @item -dZ @itemx -fdump-rtl-web @opindex dZ @opindex fdump-rtl-web -Dump after live range splitting, to @file{@var{file}.14.web}. +Dump after live range splitting, to @file{@var{file}.126r.web}. @item -da @itemx -fdump-rtl-all @@ -6176,6 +6183,21 @@ interblock scheduling. The default value is 100. The minimum probability (in percents) of reaching a source block for interblock speculative scheduling. The default value is 40. +@item max-sched-extend-regions-iters +The maximum number of iterations through CFG to extend regions. +0 - disable region extension, +N - do at most N iterations. +The default value is 2. + +@item max-sched-insn-conflict-delay +The maximum conflict delay for an insn to be considered for speculative motion. +The default value is 3. + +@item sched-spec-prob-cutoff +The minimal probability of speculation success (in percents), so that +speculative insn will be scheduled. +The default value is 40. + @item max-last-value-rtl The maximum size measured as number of RTLs that can be recorded in an expression @@ -9718,6 +9740,113 @@ The 32-bit environment sets int, long and pointer to 32 bits. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits. These are HP-UX specific flags. +@item -mno-sched-br-data-spec +@itemx -msched-br-data-spec +@opindex -mno-sched-br-data-spec +@opindex -msched-br-data-spec +(Dis/En)able data speculative scheduling before reload. +This will result in generation of the ld.a instructions and +the corresponding check instructions (ld.c / chk.a). +The default is 'disable'. + +@item -msched-ar-data-spec +@itemx -mno-sched-ar-data-spec +@opindex -msched-ar-data-spec +@opindex -mno-sched-ar-data-spec +(En/Dis)able data speculative scheduling after reload. +This will result in generation of the ld.a instructions and +the corresponding check instructions (ld.c / chk.a). +The default is 'enable'. + +@item -mno-sched-control-spec +@itemx -msched-control-spec +@opindex -mno-sched-control-spec +@opindex -msched-control-spec +(Dis/En)able control speculative scheduling. This feature is +available only during region scheduling (i.e. before reload). +This will result in generation of the ld.s instructions and +the corresponding check instructions chk.s . +The default is 'disable'. + +@item -msched-br-in-data-spec +@itemx -mno-sched-br-in-data-spec +@opindex -msched-br-in-data-spec +@opindex -mno-sched-br-in-data-spec +(En/Dis)able speculative scheduling of the instructions that +are dependent on the data speculative loads before reload. +This is effective only with @option{-msched-br-data-spec} enabled. +The default is 'enable'. + +@item -msched-ar-in-data-spec +@itemx -mno-sched-ar-in-data-spec +@opindex -msched-ar-in-data-spec +@opindex -mno-sched-ar-in-data-spec +(En/Dis)able speculative scheduling of the instructions that +are dependent on the data speculative loads after reload. +This is effective only with @option{-msched-ar-data-spec} enabled. +The default is 'enable'. + +@item -msched-in-control-spec +@itemx -mno-sched-in-control-spec +@opindex -msched-in-control-spec +@opindex -mno-sched-in-control-spec +(En/Dis)able speculative scheduling of the instructions that +are dependent on the control speculative loads. +This is effective only with @option{-msched-control-spec} enabled. +The default is 'enable'. + +@item -msched-ldc +@itemx -mno-sched-ldc +@opindex -msched-ldc +@opindex -mno-sched-ldc +(En/Dis)able use of simple data speculation checks ld.c . +If disabled, only chk.a instructions will be emitted to check +data speculative loads. +The default is 'enable'. + +@item -mno-sched-control-ldc +@itemx -msched-control-ldc +@opindex -mno-sched-control-ldc +@opindex -msched-control-ldc +(Dis/En)able use of ld.c instructions to check control speculative loads. +If enabled, in case of control speculative load with no speculatively +scheduled dependent instructions this load will be emitted as ld.sa and +ld.c will be used to check it. +The default is 'disable'. + +@item -mno-sched-spec-verbose +@itemx -msched-spec-verbose +@opindex -mno-sched-spec-verbose +@opindex -msched-spec-verbose +(Dis/En)able printing of the information about speculative motions. + +@item -mno-sched-prefer-non-data-spec-insns +@itemx -msched-prefer-non-data-spec-insns +@opindex -mno-sched-prefer-non-data-spec-insns +@opindex -msched-prefer-non-data-spec-insns +If enabled, data speculative instructions will be choosen for schedule +only if there are no other choices at the moment. This will make +the use of the data speculation much more conservative. +The default is 'disable'. + +@item -mno-sched-prefer-non-control-spec-insns +@itemx -msched-prefer-non-control-spec-insns +@opindex -mno-sched-prefer-non-control-spec-insns +@opindex -msched-prefer-non-control-spec-insns +If enabled, control speculative instructions will be choosen for schedule +only if there are no other choices at the moment. This will make +the use of the control speculation much more conservative. +The default is 'disable'. + +@item -mno-sched-count-spec-in-critical-path +@itemx -msched-count-spec-in-critical-path +@opindex -mno-sched-count-spec-in-critical-path +@opindex -msched-count-spec-in-critical-path +If enabled, speculative depedencies will be considered during +computation of the instructions priorities. This will make the use of the +speculation a bit more conservative. +The default is 'disable'. + @end table @node M32C Options @@ -11106,7 +11235,7 @@ following options: @option{-maltivec}, @option{-mfprnd}, @option{-mhard-float}, @option{-mmfcrf}, @option{-mmultiple}, @option{-mnew-mnemonics}, @option{-mpopcntb}, @option{-mpower}, @option{-mpower2}, @option{-mpowerpc64}, @option{-mpowerpc-gpopt}, -@option{-mpowerpc-gfxopt}, @option{-mstring}, @option{-mmulhw}. +@option{-mpowerpc-gfxopt}, @option{-mstring}, @option{-mmulhw}, @option{dlmzb}. The particular options set for any particular CPU will vary between compiler versions, depending on what setting seems to produce optimal code for that CPU; @@ -11370,6 +11499,14 @@ multiply-accumulate instructions on the IBM 405 and 440 processors. These instructions are generated by default when targetting those processors. +@item -mdlmzb +@itemx -mno-dlmzb +@opindex mdlmzb +@opindex mno-dlmzb +Generate code that uses (does not use) the string-search @samp{dlmzb} +instruction on the IBM 405 and 440 processors. This instruction is +generated by default when targetting those processors. + @item -mno-bit-align @itemx -mbit-align @opindex mno-bit-align @@ -13195,9 +13332,11 @@ of 128KB@. Note that this may only work with the GNU linker. @item -fargument-alias @itemx -fargument-noalias @itemx -fargument-noalias-global +@itemx -fargument-noalias-anything @opindex fargument-alias @opindex fargument-noalias @opindex fargument-noalias-global +@opindex fargument-noalias-anything Specify the possible relationships among parameters and between parameters and global data. @@ -13207,6 +13346,8 @@ alias each other and may alias global storage.@* each other, but may alias global storage.@* @option{-fargument-noalias-global} specifies that arguments do not alias each other and do not alias global storage. +@option{-fargument-noalias-anything} specifies that arguments do not +alias any other storage. Each language will automatically use whatever option is required by the language standard. You should not need to use these options yourself.