X-Git-Url: http://git.sourceforge.jp/view?p=pf3gnuchains%2Fgcc-fork.git;a=blobdiff_plain;f=gcc%2Fdoc%2Finvoke.texi;h=23a0f4af9dc727dd83c2acf812febeeeb3ca88a5;hp=ec91be0852eb57b1bd8feffbfa772301d17df64f;hb=578e34563f159ce091cda0b8f3fd8a2da30c297c;hpb=f1ae4a25c5b52232b591fcbb0eba3e9f964aa500 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ec91be0852e..23a0f4af9dc 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1,5 +1,5 @@ @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, -@c 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 +@c 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 @c Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. @@ -11,7 +11,7 @@ @c man begin COPYRIGHT Copyright @copyright{} 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, -1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 +1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document @@ -190,11 +190,11 @@ in the following sections. -fno-nonansi-builtins -fno-operator-names @gol -fno-optional-diags -fpermissive @gol -fno-pretty-templates @gol --frepo -fno-rtti -fstats -ftemplate-depth-@var{n} @gol +-frepo -fno-rtti -fstats -ftemplate-depth=@var{n} @gol -fno-threadsafe-statics -fuse-cxa-atexit -fno-weak -nostdinc++ @gol -fno-default-inline -fvisibility-inlines-hidden @gol -fvisibility-ms-compat @gol --Wabi -Wctor-dtor-privacy @gol +-Wabi -Wconversion-null -Wctor-dtor-privacy @gol -Wnon-virtual-dtor -Wreorder @gol -Weffc++ -Wstrict-null-sentinel @gol -Wno-non-template-friend -Wold-style-cast @gol @@ -259,7 +259,7 @@ Objective-C and Objective-C++ Dialects}. -Wstrict-overflow -Wstrict-overflow=@var{n} @gol -Wswitch -Wswitch-default -Wswitch-enum -Wsync-nand @gol -Wsystem-headers -Wtrigraphs -Wtype-limits -Wundef -Wuninitialized @gol --Wunknown-pragmas -Wno-pragmas -Wunreachable-code @gol +-Wunknown-pragmas -Wno-pragmas @gol -Wunsuffixed-float-constants -Wunused -Wunused-function @gol -Wunused-label -Wunused-parameter -Wno-unused-result -Wunused-value -Wunused-variable @gol -Wvariadic-macros -Wvla @gol @@ -312,7 +312,7 @@ Objective-C and Objective-C++ Dialects}. -frandom-seed=@var{string} -fsched-verbose=@var{n} @gol -fsel-sched-verbose -fsel-sched-dump-cfg -fsel-sched-pipelining-verbose @gol -ftest-coverage -ftime-report -fvar-tracking @gol --fvar-tracking-assigments -fvar-tracking-assignments-toggle @gol +-fvar-tracking-assignments -fvar-tracking-assignments-toggle @gol -g -g@var{level} -gtoggle -gcoff -gdwarf-@var{version} @gol -ggdb -gstabs -gstabs+ -gstrict-dwarf -gno-strict-dwarf @gol -gvms -gxcoff -gxcoff+ @gol @@ -321,7 +321,7 @@ Objective-C and Objective-C++ Dialects}. -femit-struct-debug-baseonly -femit-struct-debug-reduced @gol -femit-struct-debug-detailed@r{[}=@var{spec-list}@r{]} @gol -p -pg -print-file-name=@var{library} -print-libgcc-file-name @gol --print-multi-directory -print-multi-lib @gol +-print-multi-directory -print-multi-lib -print-multi-os-directory @gol -print-prog-name=@var{program} -print-search-dirs -Q @gol -print-sysroot -print-sysroot-headers-suffix @gol -save-temps -save-temps=cwd -save-temps=obj -time@r{[}=@var{file}@r{]}} @@ -367,8 +367,7 @@ Objective-C and Objective-C++ Dialects}. -freciprocal-math -fregmove -frename-registers -freorder-blocks @gol -freorder-blocks-and-partition -freorder-functions @gol -frerun-cse-after-loop -freschedule-modulo-scheduled-loops @gol --frounding-math -fsched2-use-superblocks @gol --fsched2-use-traces -fsched-pressure @gol +-frounding-math -fsched2-use-superblocks -fsched-pressure @gol -fsched-spec-load -fsched-spec-load-dangerous @gol -fsched-stalled-insns-dep[=@var{n}] -fsched-stalled-insns[=@var{n}] @gol -fsched-group-heuristic -fsched-critical-path-heuristic @gol @@ -391,7 +390,7 @@ Objective-C and Objective-C++ Dialects}. -funit-at-a-time -funroll-all-loops -funroll-loops @gol -funsafe-loop-optimizations -funsafe-math-optimizations -funswitch-loops @gol -fvariable-expansion-in-unroller -fvect-cost-model -fvpt -fweb @gol --fwhole-program -fwhopr -fwpa -use-linker-plugin @gol +-fwhole-program -fwhopr -fwpa -fuse-linker-plugin @gol --param @var{name}=@var{value} -O -O0 -O1 -O2 -O3 -Os} @@ -593,8 +592,8 @@ Objective-C and Objective-C++ Dialects}. -mincoming-stack-boundary=@var{num} -mcld -mcx16 -msahf -mmovbe -mcrc32 -mrecip @gol -mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol --maes -mpclmul @gol --msse4a -m3dnow -mpopcnt -mabm -mfma4 @gol +-maes -mpclmul -mfused-madd @gol +-msse4a -m3dnow -mpopcnt -mabm -mfma4 -mxop -mlwp @gol -mthreads -mno-align-stringops -minline-all-stringops @gol -minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol -mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol @@ -631,6 +630,10 @@ Objective-C and Objective-C++ Dialects}. @emph{IA-64/VMS Options} @gccoptlist{-mvms-return-codes -mdebug-main=@var{prefix} -mmalloc64} +@emph{LM32 Options} +@gccoptlist{-mbarrel-shift-enabled -mdivide-enabled -mmultiply-enabled @gol +-msign-extend-enabled -muser-enabled} + @emph{M32R/D Options} @gccoptlist{-m32r2 -m32rx -m32r @gol -mdebug @gol @@ -709,7 +712,7 @@ Objective-C and Objective-C++ Dialects}. -mbranch-cost=@var{num} -mbranch-likely -mno-branch-likely @gol -mfp-exceptions -mno-fp-exceptions @gol -mvr4130-align -mno-vr4130-align -msynci -mno-synci @gol --mrelax-pic-calls -mno-relax-pic-calls} +-mrelax-pic-calls -mno-relax-pic-calls -mmcount-ra-address} @emph{MMIX Options} @gccoptlist{-mlibfuncs -mno-libfuncs -mepsilon -mno-epsilon -mabi=gnu @gol @@ -783,6 +786,18 @@ See RS/6000 and PowerPC Options. -msim -mmvme -mads -myellowknife -memb -msdata @gol -msdata=@var{opt} -mvxworks -G @var{num} -pthread} +@emph{RX Options} +@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol +-mcpu= -patch=@gol +-mbig-endian-data -mlittle-endian-data @gol +-msmall-data @gol +-msim -mno-sim@gol +-mas100-syntax -mno-as100-syntax@gol +-mrelax@gol +-mmax-constant-size=@gol +-mint-register=@gol +-msave-acc-in-interrupts} + @emph{S/390 and zSeries Options} @gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol -mhard-float -msoft-float -mhard-dfp -mno-hard-dfp @gol @@ -836,7 +851,11 @@ See RS/6000 and PowerPC Options. -msafe-dma -munsafe-dma @gol -mbranch-hints @gol -msmall-mem -mlarge-mem -mstdmain @gol --mfixed-range=@var{register-range}} +-mfixed-range=@var{register-range} @gol +-mea32 -mea64 @gol +-maddress-space-conversion -mno-address-space-conversion @gol +-mcache-size=@var{cache-size} @gol +-matomic-updates -mno-atomic-updates} @emph{System V Options} @gccoptlist{-Qy -Qn -YP,@var{paths} -Ym,@var{dir}} @@ -863,7 +882,8 @@ See i386 and x86-64 Options. @emph{i386 and x86-64 Windows Options} @gccoptlist{-mconsole -mcygwin -mno-cygwin -mdll --mnop-fun-dllimport -mthread -municode -mwin32 -mwindows} +-mnop-fun-dllimport -mthread -municode -mwin32 -mwindows +-fno-set-stack-executable} @emph{Xstormy16 Options} @gccoptlist{-msim} @@ -1405,7 +1425,7 @@ accepts: @cindex ISO support @item -ansi @opindex ansi -In C mode, this is equivalent to @samp{-std=c89}. In C++ mode, it is +In C mode, this is equivalent to @samp{-std=c90}. In C++ mode, it is equivalent to @samp{-std=c++98}. This turns off certain features of GCC that are incompatible with ISO @@ -1447,12 +1467,12 @@ Determine the language standard. @xref{Standards,,Language Standards Supported by GCC}, for details of these standard versions. This option is currently only supported when compiling C or C++. -The compiler can accept several base standards, such as @samp{c89} or +The compiler can accept several base standards, such as @samp{c90} or @samp{c++98}, and GNU dialects of those standards, such as -@samp{gnu89} or @samp{gnu++98}. By specifying a base standard, the +@samp{gnu90} or @samp{gnu++98}. By specifying a base standard, the compiler will accept all programs following that standard and those using GNU extensions that do not contradict it. For example, -@samp{-std=c89} turns off certain features of GCC that are +@samp{-std=c90} turns off certain features of GCC that are incompatible with ISO C90, such as the @code{asm} and @code{typeof} keywords, but not other GNU extensions that do not have a meaning in ISO C90, such as omitting the middle term of a @code{?:} @@ -1462,13 +1482,14 @@ those features change the meaning of the base standard and some strict-conforming programs may be rejected. The particular standard is used by @option{-pedantic} to identify which features are GNU extensions given that version of the standard. For example -@samp{-std=gnu89 -pedantic} would warn about C++ style @samp{//} +@samp{-std=gnu90 -pedantic} would warn about C++ style @samp{//} comments, while @samp{-std=gnu99 -pedantic} would not. A value for this option must be provided; possible values are @table @samp -@item c89 +@item c90 +@itemx c89 @itemx iso9899:1990 Support all ISO C90 programs (certain GNU extensions that conflict with ISO C90 are disabled). Same as @option{-ansi} for C code. @@ -1484,7 +1505,8 @@ ISO C99. Note that this standard is not yet fully supported; see @w{@uref{http://gcc.gnu.org/c99status.html}} for more information. The names @samp{c9x} and @samp{iso9899:199x} are deprecated. -@item gnu89 +@item gnu90 +@itemx gnu89 GNU dialect of ISO C90 (including some C99 features). This is the default for C code. @@ -1527,7 +1549,8 @@ C99 mode. Using this option is roughly equivalent to adding the The option @option{-fno-gnu89-inline} explicitly tells GCC to use the C99 semantics for @code{inline} when in C99 or gnu99 mode (i.e., it specifies the default behavior). This option was first supported in -GCC 4.3. This option is not supported in C89 or gnu89 mode. +GCC 4.3. This option is not supported in @option{-std=c90} or +@option{-std=gnu90} mode. The preprocessor macros @code{__GNUC_GNU_INLINE__} and @code{__GNUC_STDC_INLINE__} may be used to check which semantics are @@ -1760,6 +1783,13 @@ are fixed. The default is version 2. +Version 3 corrects an error in mangling a constant address as a +template argument. + +Version 4 implements a standard mangling for vector types. + +See also @option{-Wabi}. + @item -fno-access-control @opindex fno-access-control Turn off all access checking. This switch is mainly useful for working @@ -1945,7 +1975,7 @@ unambiguous base classes. Emit statistics about front-end processing at the end of the compilation. This information is generally only useful to the G++ development team. -@item -ftemplate-depth-@var{n} +@item -ftemplate-depth=@var{n} @opindex ftemplate-depth Set the maximum instantiation depth for template classes to @var{n}. A limit on the template instantiation depth is needed to detect @@ -2076,7 +2106,30 @@ You should rewrite your code to avoid these warnings if you are concerned about the fact that code generated by G++ may not be binary compatible with code generated by other compilers. -The known incompatibilities at this point include: +The known incompatibilities in @option{-fabi-version=2} (the default) include: + +@itemize @bullet + +@item +A template with a non-type template parameter of reference type is +mangled incorrectly: +@smallexample +extern int N; +template struct S @{@}; +void n (S) @{2@} +@end smallexample + +This is fixed in @option{-fabi-version=3}. + +@item +SIMD vector types declared using @code{__attribute ((vector_size))} are +mangled in a non-standard way that does not allow for overloading of +functions taking vectors of different sizes. + +The mangling is changed in @option{-fabi-version=4}. +@end itemize + +The known incompatibilities in @option{-fabi-version=1} include: @itemize @bullet @@ -2792,7 +2845,7 @@ be quite different from @option{-pedantic}. We don't have plans to support such a feature in the near future. Where the standard specified with @option{-std} represents a GNU -extended dialect of C, such as @samp{gnu89} or @samp{gnu99}, there is a +extended dialect of C, such as @samp{gnu90} or @samp{gnu99}, there is a corresponding @dfn{base standard}, the version of ISO C on which the GNU extended dialect is based. Warnings from @option{-pedantic} are given where they are required by the base standard. (It would not make sense @@ -3461,7 +3514,7 @@ incomplete types. Runs in the frontend only. Level 3 (default for @option{-Wstrict-aliasing}): Should have very few false positives and few false negatives. Slightly slower than levels 1 or 2 when optimization is enabled. -Takes care of the common punn+dereference pattern in the frontend: +Takes care of the common pun+dereference pattern in the frontend: @code{*(int*)&some_float}. If optimization is enabled, it also runs in the backend, where it deals with multiple statement cases using flow-sensitive points-to information. @@ -3817,14 +3870,19 @@ changed by the conversion like in @code{abs (2.0)}. Warnings about conversions between signed and unsigned integers can be disabled by using @option{-Wno-sign-conversion}. -For C++, also warn for conversions between @code{NULL} and non-pointer -types; confusing overload resolution for user-defined conversions; and -conversions that will never use a type conversion operator: -conversions to @code{void}, the same type, a base class or a reference -to them. Warnings about conversions between signed and unsigned -integers are disabled by default in C++ unless +For C++, also warn for confusing overload resolution for user-defined +conversions; and conversions that will never use a type conversion +operator: conversions to @code{void}, the same type, a base class or a +reference to them. Warnings about conversions between signed and +unsigned integers are disabled by default in C++ unless @option{-Wsign-conversion} is explicitly enabled. +@item -Wno-conversion-null @r{(C++ and Objective-C++ only)} +@opindex Wconversion-null +@opindex Wno-conversion-null +Do not warn for conversions between @code{NULL} and non-pointer +types. @option{-Wconversion-null} is enabled by default. + @item -Wempty-body @opindex Wempty-body @opindex Wno-empty-body @@ -4171,29 +4229,6 @@ cases where multiple declaration is valid and changes nothing. @opindex Wno-nested-externs Warn if an @code{extern} declaration is encountered within a function. -@item -Wunreachable-code -@opindex Wunreachable-code -@opindex Wno-unreachable-code -Warn if the compiler detects that code will never be executed. - -This option is intended to warn when the compiler detects that at -least a whole line of source code will never be executed, because -some condition is never satisfied or because it is after a -procedure that never returns. - -It is possible for this option to produce a warning even though there -are circumstances under which part of the affected line can be executed, -so care should be taken when removing apparently-unreachable code. - -For instance, when a function is inlined, a warning may mean that the -line is unreachable in only one inlined copy of the function. - -This option is not made part of @option{-Wall} because in a debugging -version of a program there is often substantial code which checks -correct functioning of the program and is, hopefully, unreachable -because the program does work. Another common use of unreachable -code is to provide behavior which is selectable at compile-time. - @item -Winline @opindex Winline @opindex Wno-inline @@ -4310,7 +4345,7 @@ standard's minimum limit, but very portable programs should avoid using longer strings. The limit applies @emph{after} string constant concatenation, and does -not count the trailing NUL@. In C89, the limit was 509 characters; in +not count the trailing NUL@. In C90, the limit was 509 characters; in C99, it was raised to 4095. C++98 does not specify a normative minimum maximum, so we do not diagnose overlength strings in C++@. @@ -5339,6 +5374,11 @@ file name. Dump each function after applying vectorization of loops. The file name is made by appending @file{.vect} to the source file name. +@item slp +@opindex fdump-tree-slp +Dump each function after applying vectorization of basic blocks. The file name +is made by appending @file{.slp} to the source file name. + @item vrp @opindex fdump-tree-vrp Dump each function after Value Range Propagation (VRP). The file name @@ -5364,14 +5404,16 @@ inner-most, single-bb, single-entry/exit loops. This is the same verbosity level that @option{-fdump-tree-vect-stats} uses. Higher verbosity levels mean either more information dumped for each reported loop, or same amount of information reported for more loops: -If @var{n}=3, alignment related information is added to the reports. -If @var{n}=4, data-references related information (e.g.@: memory dependences, +if @var{n}=3, vectorizer cost model information is reported. +If @var{n}=4, alignment related information is added to the reports. +If @var{n}=5, data-references related information (e.g.@: memory dependences, memory access-patterns) is added to the reports. -If @var{n}=5, the vectorizer reports also non-vectorized inner-most loops +If @var{n}=6, the vectorizer reports also non-vectorized inner-most loops that did not pass the first analysis phase (i.e., may not be countable, or may have complicated control-flow). -If @var{n}=6, the vectorizer reports also non-vectorized nested loops. -For @var{n}=7, all the information the vectorizer generates during its +If @var{n}=7, the vectorizer reports also non-vectorized nested loops. +If @var{n}=8, SLP related information is added to the reports. +For @var{n}=9, all the information the vectorizer generates during its analysis and transformation is reported. This is the same verbosity level that @option{-fdump-tree-vect-details} uses. @@ -5392,7 +5434,7 @@ On targets that use instruction scheduling, this option controls the amount of debugging output the scheduler prints. This information is written to standard error, unless @option{-fdump-rtl-sched1} or @option{-fdump-rtl-sched2} is specified, in which case it is output -to the usual dump listing file, @file{.sched} or @file{.sched2} +to the usual dump listing file, @file{.sched1} or @file{.sched2} respectively. However for @var{n} greater than nine, the output is always printed to standard error. @@ -5531,6 +5573,16 @@ that enable them. The directory name is separated from the switches by @samp{-}, without spaces between multiple switches. This is supposed to ease shell-processing. +@item -print-multi-os-directory +@opindex print-multi-os-directory +Print the path to OS libraries for the selected +multilib, relative to some @file{lib} subdirectory. If OS libraries are +present in the @file{lib} subdirectory and no multilibs are used, this is +usually just @file{.}, if OS libraries are present in @file{lib@var{suffix}} +sibling directories this prints e.g.@: @file{../lib64}, @file{../lib} or +@file{../lib32}, or if OS libraries are present in @file{lib/@var{subdir}} +subdirectories it prints e.g.@: @file{amd64}, @file{sparcv9} or @file{ev6}. + @item -print-prog-name=@var{program} @opindex print-prog-name Like @option{-print-file-name}, but searches for a program such as @samp{cpp}. @@ -5628,8 +5680,9 @@ each of them. Not all optimizations are controlled directly by a flag. Only optimizations that have a flag are listed in this section. -Most of the optimizations are not enabled if a @option{-O} level is not set on -the command line, even if individual optimization flags are specified. +Most optimizations are only enabled if an @option{-O} level is set on +the command line. Otherwise they are disabled, even if individual +optimization flags are specified. Depending on the target and how GCC was configured, a slightly different set of optimizations may be enabled at each @option{-O} level than @@ -5723,8 +5776,7 @@ invoking @option{-O2} on programs that use computed gotos. Optimize yet more. @option{-O3} turns on all optimizations specified by @option{-O2} and also turns on the @option{-finline-functions}, @option{-funswitch-loops}, @option{-fpredictive-commoning}, -@option{-fgcse-after-reload}, @option{-ftree-vectorize} and -@option{-fira-loop-pressure} options. +@option{-fgcse-after-reload} and @option{-ftree-vectorize} options. @item -O0 @opindex O0 @@ -5906,7 +5958,7 @@ release to an another. In C, emit @code{static} functions that are declared @code{inline} into the object file, even if the function has been inlined into all of its callers. This switch does not affect functions using the -@code{extern inline} extension in GNU C89@. In C++, emit any and all +@code{extern inline} extension in GNU C90@. In C++, emit any and all inline functions into the object file. @item -fkeep-static-consts @@ -6225,9 +6277,10 @@ architectures with big regular register files. @opindex fira-loop-pressure Use IRA to evaluate register pressure in loops for decision to move loop invariants. Usage of this option usually results in generation -of faster and smaller code but can slow compiler down. +of faster and smaller code on machines with big register files (>= 32 +registers) but it can slow compiler down. -This option is enabled at level @option{-O3}. +This option is enabled at level @option{-O3} for some targets. @item -fno-ira-share-save-slots @opindex fno-ira-share-save-slots @@ -6264,7 +6317,7 @@ helps machines that have slow floating point or memory load instructions by allowing other instructions to be issued until the result of the load or floating point instruction is required. -Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}. +Enabled at levels @option{-O2}, @option{-O3}. @item -fschedule-insns2 @opindex fschedule-insns2 @@ -6389,19 +6442,6 @@ This is enabled by default when scheduling is enabled, i.e.@: with @option{-fschedule-insns} or @option{-fschedule-insns2} or at @option{-O2} or higher. -@item -fsched2-use-traces -@opindex fsched2-use-traces -Use @option{-fsched2-use-superblocks} algorithm when scheduling after register -allocation and additionally perform code duplication in order to increase the -size of superblocks using tracer pass. See @option{-ftracer} for details on -trace formation. - -This mode should produce faster but significantly longer programs. Also -without @option{-fbranch-probabilities} the traces constructed may not -match the reality and hurt the performance. This only makes -sense when scheduling after register allocation, i.e.@: with -@option{-fschedule-insns2} or at @option{-O2} or higher. - @item -freschedule-modulo-scheduled-loops @opindex freschedule-modulo-scheduled-loops The modulo scheduling comes before the traditional scheduling, if a loop @@ -6635,7 +6675,9 @@ Graphite loop transformation infrastructure. Perform loop strip mining transformations on loops. Strip mining splits a loop into two nested loops. The outer loop has strides equal to the strip size and the inner loop has strides of the -original loop within a strip. For example, given a loop like: +original loop within a strip. The strip length can be changed +using the @option{loop-block-tile-size} parameter. For example, +given a loop like: @smallexample DO I = 1, N A(I) = A(I) + C @@ -6643,8 +6685,8 @@ ENDDO @end smallexample loop strip mining will transform the loop as if the user had written: @smallexample -DO II = 1, N, 4 - DO I = II, min (II + 3, N) +DO II = 1, N, 51 + DO I = II, min (II + 50, N) A(I) = A(I) + C ENDDO ENDDO @@ -6657,7 +6699,9 @@ enable the Graphite loop transformation infrastructure. @item -floop-block Perform loop blocking transformations on loops. Blocking strip mines each loop in the loop nest such that the memory accesses of the -element loops fit inside caches. For example, given a loop like: +element loops fit inside caches. The strip length can be changed +using the @option{loop-block-tile-size} parameter. For example, given +a loop like: @smallexample DO I = 1, N DO J = 1, M @@ -6667,10 +6711,10 @@ ENDDO @end smallexample loop blocking will transform the loop as if the user had written: @smallexample -DO II = 1, N, 64 - DO JJ = 1, M, 64 - DO I = II, min (II + 63, N) - DO J = JJ, min (JJ + 63, M) +DO II = 1, N, 51 + DO JJ = 1, M, 51 + DO I = II, min (II + 50, N) + DO J = JJ, min (JJ + 50, M) A(J, I) = B(I) + C(J) ENDDO ENDDO @@ -6787,6 +6831,11 @@ enabled by default at @option{-O} and higher. Perform loop vectorization on trees. This flag is enabled by default at @option{-O3}. +@item -ftree-slp-vectorize +@opindex ftree-slp-vectorize +Perform basic block vectorization on trees. This flag is enabled by default at +@option{-O3} and when @option{-ftree-vectorize} is enabled. + @item -ftree-vect-loop-version @opindex ftree-vect-loop-version Perform loop versioning when doing loop vectorization on trees. When a loop @@ -7249,11 +7298,11 @@ If object files containing GIMPLE bytecode are stored in a library archive, say @file{libfoo.a}, it is possible to extract and use them in an LTO link if you are using @command{gold} as the linker (which, in turn requires GCC to be configured with @option{--enable-gold}). -To enable this feature, use the flag @option{-use-linker-plugin} at +To enable this feature, use the flag @option{-fuse-linker-plugin} at link-time: @smallexample -gcc -o myprog -O2 -flto -use-linker-plugin a.o b.o -lfoo +gcc -o myprog -O2 -flto -fuse-linker-plugin a.o b.o -lfoo @end smallexample With the linker plugin enabled, @command{gold} will extract the needed @@ -7261,7 +7310,7 @@ GIMPLE files from @file{libfoo.a} and pass them on to the running GCC to make them part of the aggregated GIMPLE image to be optimized. If you are not using @command{gold} and/or do not specify -@option{-use-linker-plugin} then the objects inside @file{libfoo.a} +@option{-fuse-linker-plugin} then the objects inside @file{libfoo.a} will be extracted and linked as usual, but they will not participate in the LTO optimization process. @@ -7278,6 +7327,10 @@ types of hosts. The bytecode files are versioned and there is a strict version check, so bytecode files generated in one version of GCC will not work with an older/newer version of GCC. +Link time optimization does not play well with generating debugging +information. Combining @option{-flto} or @option{-fwhopr} with +@option{-g} is experimental. + This option is disabled by default. @item -fwhopr @@ -7294,6 +7347,8 @@ that otherwise would not fit in memory. This option enables Disabled by default. +This option is experimental. + @item -fwpa @opindex fwpa This is an internal option used by GCC when compiling with @@ -7346,7 +7401,7 @@ files in LTO mode (via @option{-fwhopr} or @option{-flto}). Disabled by default. -@item -use-linker-plugin +@item -fuse-linker-plugin Enables the extraction of objects with GIMPLE bytecode information from library archives. This option relies on features available only in @command{gold}, so to use this you must configure GCC with @@ -7523,7 +7578,9 @@ thus cannot be used on a code which relies on rounding behavior like and thus may not be used when ordered comparisons are required. This option requires that both @option{-fno-signed-zeros} and @option{-fno-trapping-math} be in effect. Moreover, it doesn't make -much sense with @option{-frounding-math}. +much sense with @option{-frounding-math}. For Fortran the option +is automatically enabled when both @option{-fno-signed-zeros} and +@option{-fno-trapping-math} are in effect. The default is @option{-fno-associative-math}. @@ -7695,7 +7752,7 @@ debug information format adopted by the target, however, it can make debugging impossible, since variables will no longer stay in a ``home register''. -Enabled by default with @option{-funroll-loops}. +Enabled by default with @option{-funroll-loops} and @option{-fpeel-loops}. @item -ftracer @opindex ftracer @@ -7848,7 +7905,7 @@ to the hottest structure frequency in the program is less than this parameter, then structure reorganization is not applied to this structure. The default is 10. -@item predictable-branch-cost-outcome +@item predictable-branch-outcome When branch is predicted to be taken with probability lower than this threshold (in percent), then it is considered well predictable. The default is 10. @@ -8041,6 +8098,9 @@ The maximum number of insns of a completely peeled loop. @item max-completely-peel-times The maximum number of iterations of a loop to be suitable for complete peeling. +@item max-completely-peel-loop-nest-depth +The maximum depth of a loop nest suitable for complete peeling. + @item max-unswitch-insns The maximum number of insns of an unswitched loop. @@ -8415,6 +8475,15 @@ with more basic blocks than this parameter won't have loop invariant motion optimization performed on them. The default value of the parameter is 1000 for -O1 and 10000 for -O2 and above. +@item max-vartrack-size +Sets a maximum number of hash table slots to use during variable +tracking dataflow analysis of any function. If this limit is exceeded +with variable tracking at assignments enabled, analysis for that +function is retried without it, after removing all debug insns from +the function. If the limit is exceeded even without debug insns, var +tracking analysis is completely disabled for the function. Setting +the parameter to zero makes it unlimited. + @item min-nondebug-insn-uid Use uids starting at this parameter for nondebug insns. The range below the parameter is reserved exclusively for debug insns created by @@ -8427,6 +8496,24 @@ parameters only when their cumulative size is less or equal to @option{ipa-sra-ptr-growth-factor} times the size of the original pointer parameter. +@item graphite-max-nb-scop-params +To avoid exponential effects in the Graphite loop transforms, the +number of parameters in a Static Control Part (SCoP) is bounded. The +default value is 10 parameters. A variable whose value is unknown at +compile time and defined outside a SCoP is a parameter of the SCoP. + +@item graphite-max-bbs-per-function +To avoid exponential effects in the detection of SCoPs, the size of +the functions analyzed by Graphite is bounded. The default value is +100 basic blocks. + +@item loop-block-tile-size +Loop blocking or strip mining transforms, enabled with +@option{-floop-block} or @option{-floop-strip-mine}, strip mine each +loop in the loop nest by a given number of iterations. The strip +length can be changed using the @option{loop-block-tile-size} +parameter. The default value is 51 iterations. + @end table @end table @@ -9507,6 +9594,7 @@ platform. * i386 and x86-64 Windows Options:: * IA-64 Options:: * IA-64/VMS Options:: +* LM32 Options:: * M32C Options:: * M32R/D Options:: * M680x0 Options:: @@ -9520,6 +9608,7 @@ platform. * picoChip Options:: * PowerPC Options:: * RS/6000 and PowerPC Options:: +* RX Options:: * S/390 and zSeries Options:: * Score Options:: * SH Options:: @@ -9722,7 +9811,7 @@ assembly code. Permissible names are: @samp{arm2}, @samp{arm250}, @samp{arm10e}, @samp{arm1020e}, @samp{arm1022e}, @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp}, @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s}, -@samp{cortex-a8}, @samp{cortex-a9}, +@samp{cortex-a5}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m3}, @samp{cortex-m1}, @samp{cortex-m0}, @@ -9760,10 +9849,13 @@ of the @option{-mcpu=} option. Permissible names are: @samp{armv2}, @opindex mfp This specifies what floating point hardware (or hardware emulation) is available on the target. Permissible names are: @samp{fpa}, @samp{fpe2}, -@samp{fpe3}, @samp{maverick}, @samp{vfp}, @samp{vfpv3}, @samp{vfpv3-d16}, -@samp{neon}, and @samp{neon-fp16}. @option{-mfp} and @option{-mfpe} -are synonyms for @option{-mfpu}=@samp{fpe}@var{number}, for compatibility -with older versions of GCC@. +@samp{fpe3}, @samp{maverick}, @samp{vfp}, @samp{vfpv3}, @samp{vfpv3-fp16}, +@samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd}, @samp{vfpv3xd-fp16}, +@samp{neon}, @samp{neon-fp16}, @samp{vfpv4}, @samp{vfpv4-d16}, +@samp{fpv4-sp-d16} and @samp{neon-vfpv4}. +@option{-mfp} and @option{-mfpe} are synonyms for +@option{-mfpu}=@samp{fpe}@var{number}, for compatibility with older versions +of GCC@. If @option{-msoft-float} is specified this specifies the format of floating point values. @@ -10933,7 +11025,7 @@ These @samp{-m} options are defined for the DEC Alpha/VMS implementations: @table @gcctabopt @item -mvms-return-codes @opindex mvms-return-codes -Return VMS condition codes from main. The default is to return POSIX +Return VMS condition codes from main. The default is to return POSIX style condition (e.g.@: error) codes. @item -mdebug-main=@var{prefix} @@ -11645,36 +11737,36 @@ instruction set support. @item k6 AMD K6 CPU with MMX instruction set support. @item k6-2, k6-3 -Improved versions of AMD K6 CPU with MMX and 3dNOW!@: instruction set support. +Improved versions of AMD K6 CPU with MMX and 3DNow!@: instruction set support. @item athlon, athlon-tbird -AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW!@: and SSE prefetch instructions +AMD Athlon CPU with MMX, 3dNOW!, enhanced 3DNow!@: and SSE prefetch instructions support. @item athlon-4, athlon-xp, athlon-mp -Improved AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW!@: and full SSE +Improved AMD Athlon CPU with MMX, 3DNow!, enhanced 3DNow!@: and full SSE instruction set support. @item k8, opteron, athlon64, athlon-fx AMD K8 core based CPUs with x86-64 instruction set support. (This supersets -MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW!@: and 64-bit instruction set extensions.) +MMX, SSE, SSE2, 3DNow!, enhanced 3DNow!@: and 64-bit instruction set extensions.) @item k8-sse3, opteron-sse3, athlon64-sse3 Improved versions of k8, opteron and athlon64 with SSE3 instruction set support. @item amdfam10, barcelona AMD Family 10h core based CPUs with x86-64 instruction set support. (This -supersets MMX, SSE, SSE2, SSE3, SSE4A, 3dNOW!, enhanced 3dNOW!, ABM and 64-bit +supersets MMX, SSE, SSE2, SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bit instruction set extensions.) @item winchip-c6 IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction set support. @item winchip2 -IDT Winchip2 CPU, dealt in same way as i486 with additional MMX and 3dNOW!@: +IDT Winchip2 CPU, dealt in same way as i486 with additional MMX and 3DNow!@: instruction set support. @item c3 -Via C3 CPU with MMX and 3dNOW!@: instruction set support. (No scheduling is +Via C3 CPU with MMX and 3DNow!@: instruction set support. (No scheduling is implemented for this chip.) @item c3-2 Via C3-2 CPU with MMX and SSE instruction set support. (No scheduling is implemented for this chip.) @item geode -Embedded AMD CPU with MMX and 3dNOW! instruction set support. +Embedded AMD CPU with MMX and 3DNow!@: instruction set support. @end table While picking a specific @var{cpu-type} will schedule things appropriately @@ -11977,6 +12069,10 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @itemx -mno-sse4a @itemx -mfma4 @itemx -mno-fma4 +@itemx -mxop +@itemx -mno-xop +@itemx -mlwp +@itemx -mno-lwp @itemx -m3dnow @itemx -mno-3dnow @itemx -mpopcnt @@ -11990,8 +12086,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @opindex m3dnow @opindex mno-3dnow These switches enable or disable the use of instructions in the MMX, -SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AES, PCLMUL, SSE4A, FMA4, ABM or -3DNow!@: extended instruction sets. +SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AES, PCLMUL, SSE4A, FMA4, XOP, +LWP, ABM or 3DNow!@: extended instruction sets. These extensions are also available as built-in functions: see @ref{X86 Built-in Functions}, for details of the functions enabled and disabled by these switches. @@ -12010,6 +12106,13 @@ supported architecture, using the appropriate flags. In particular, the file containing the CPU detection code should be compiled without these options. +@item -mfused-madd +@itemx -mno-fused-madd +@opindex mfused-madd +@opindex mno-fused-madd +Do (don't) generate code that uses the fused multiply/add or multiply/subtract +instructions. The default is to use these instructions. + @item -mcld @opindex mcld This option instructs GCC to emit a @code{cld} instruction in the prologue @@ -12064,6 +12167,10 @@ Note that while the throughput of the sequence is higher than the throughput of the non-reciprocal instruction, the precision of the sequence can be decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994). +Note that GCC implements 1.0f/sqrtf(x) in terms of RSQRTSS (or RSQRTPS) +already with @option{-ffast-math} (or the above option combination), and +doesn't need @option{-mrecip}. + @item -mveclibabi=@var{type} @opindex mveclibabi Specifies the ABI type to use for vectorizing intrinsics using an @@ -12341,7 +12448,7 @@ Do not generate inline code for sqrt. @opindex mfused-madd @opindex mno-fused-madd Do (don't) generate code that uses the fused multiply/add or multiply/subtract -instructions. The default is to use these instructions. +instructions. The default is to use these instructions. @item -mno-dwarf2-asm @itemx -mdwarf2-asm @@ -12527,6 +12634,35 @@ routine for the debugger. Default to 64bit memory allocation routines. @end table +@node LM32 Options +@subsection LM32 Options +@cindex LM32 options + +These @option{-m} options are defined for the Lattice Mico32 architecture: + +@table @gcctabopt +@item -mbarrel-shift-enabled +@opindex mbarrel-shift-enabled +Enable barrel-shift instructions. + +@item -mdivide-enabled +@opindex mdivide-enabled +Enable divide and modulus instructions. + +@item -mmultiply-enabled +@opindex multiply-enabled +Enable multiply instructions. + +@item -msign-extend-enabled +@opindex msign-extend-enabled +Enable sign extend instructions. + +@item -muser-enabled +@opindex muser-enabled +Enable user-defined instructions. + +@end table + @node M32C Options @subsection M32C Options @cindex M32C options @@ -14182,6 +14318,27 @@ an assembler and a linker that supports the @code{.reloc} assembly directive and @code{-mexplicit-relocs} is in effect. With @code{-mno-explicit-relocs}, this optimization can be performed by the assembler and the linker alone without help from the compiler. + +@item -mmcount-ra-address +@itemx -mno-mcount-ra-address +@opindex mmcount-ra-address +@opindex mno-mcount-ra-address +Emit (do not emit) code that allows @code{_mcount} to modify the +calling function's return address. When enabled, this option extends +the usual @code{_mcount} interface with a new @var{ra-address} +parameter, which has type @code{intptr_t *} and is passed in register +@code{$12}. @code{_mcount} can then modify the return address by +doing both of the following: +@itemize +@item +Returning the new address in register @code{$31}. +@item +Storing the new address in @code{*@var{ra-address}}, +if @var{ra-address} is nonnull. +@end itemize + +The default is @option{-mno-mcount-ra-address}. + @end table @node MMIX Options @@ -14631,10 +14788,10 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400}, @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823}, @samp{860}, @samp{970}, @samp{8540}, @samp{a2}, @samp{e300c2}, -@samp{e300c3}, @samp{e500mc}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, -@samp{power}, @samp{power2}, @samp{power3}, @samp{power4}, -@samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, @samp{power7}, -@samp{common}, @samp{powerpc}, @samp{powerpc64}, @samp{rios}, +@samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{ec603e}, @samp{G3}, +@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3}, +@samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, +@samp{power7}, @samp{common}, @samp{powerpc}, @samp{powerpc64}, @samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}. @option{-mcpu=common} selects a completely generic processor. Code @@ -14953,7 +15110,7 @@ stored, which means code that walks the stack frame across interrupts or signals may get corrupted data. @item -mavoid-indexed-addresses -@item -mno-avoid-indexed-addresses +@itemx -mno-avoid-indexed-addresses @opindex mavoid-indexed-addresses @opindex mno-avoid-indexed-addresses Generate code that tries to avoid (not avoid) the use of indexed load @@ -15352,6 +15509,150 @@ This option sets flags for both the preprocessor and linker. @end table +@node RX Options +@subsection RX Options +@cindex RX Options + +These command line options are defined for RX targets: + +@table @gcctabopt +@item -m64bit-doubles +@itemx -m32bit-doubles +@opindex m64bit-doubles +@opindex m32bit-doubles +Make the @code{double} data type be 64-bits (@option{-m64bit-doubles}) +or 32-bits (@option{-m32bit-doubles}) in size. The default is +@option{-m32bit-doubles}. @emph{Note} RX floating point hardware only +works on 32-bit values, which is why the default is +@option{-m32bit-doubles}. + +@item -fpu +@itemx -nofpu +@opindex fpu +@opindex nofpu +Enables (@option{-fpu}) or disables (@option{-nofpu}) the use of RX +floating point hardware. The default is enabled for the @var{RX600} +series and disabled for the @var{RX200} series. + +Floating point instructions will only be generated for 32-bit floating +point values however, so if the @option{-m64bit-doubles} option is in +use then the FPU hardware will not be used for doubles. + +@emph{Note} If the @option{-fpu} option is enabled then +@option{-funsafe-math-optimizations} is also enabled automatically. +This is because the RX FPU instructions are themselves unsafe. + +@item -mcpu=@var{name} +@itemx -patch=@var{name} +@opindex -mcpu +@opindex -patch +Selects the type of RX CPU to be targeted. Currently three types are +supported, the generic @var{RX600} and @var{RX200} series hardware and +the specific @var{RX610} cpu. The default is @var{RX600}. + +The only difference between @var{RX600} and @var{RX610} is that the +@var{RX610} does not support the @code{MVTIPL} instruction. + +The @var{RX200} series does not have a hardware floating point unit +and so @option{-nofpu} is enabled by default when this type is +selected. + +@item -mbig-endian-data +@itemx -mlittle-endian-data +@opindex mbig-endian-data +@opindex mlittle-endian-data +Store data (but not code) in the big-endian format. The default is +@option{-mlittle-endian-data}, ie to store data in the little endian +format. + +@item -msmall-data-limit=@var{N} +@opindex msmall-data-limit +Specifies the maximum size in bytes of global and static variables +which can be placed into the small data area. Using the small data +area can lead to smaller and faster code, but the size of area is +limited and it is up to the programmer to ensure that the area does +not overflow. Also when the small data area is used one of the RX's +registers (@code{r13}) is reserved for use pointing to this area, so +it is no longer available for use by the compiler. This could result +in slower and/or larger code if variables which once could have been +held in @code{r13} are now pushed onto the stack. + +Note, common variables (variables which have not been initialised) and +constants are not placed into the small data area as they are assigned +to other sections in the output executable. + +The default value is zero, which disables this feature. Note, this +feature is not enabled by default with higher optimization levels +(@option{-O2} etc) because of the potentially detrimental effects of +reserving register @code{r13}. It is up to the programmer to +experiment and discover whether this feature is of benefit to their +program. + +@item -msim +@itemx -mno-sim +@opindex msim +@opindex mno-sim +Use the simulator runtime. The default is to use the libgloss board +specific runtime. + +@item -mas100-syntax +@itemx -mno-as100-syntax +@opindex mas100-syntax +@opindex mno-as100-syntax +When generating assembler output use a syntax that is compatible with +Renesas's AS100 assembler. This syntax can also be handled by the GAS +assembler but it has some restrictions so generating it is not the +default option. + +@item -mmax-constant-size=@var{N} +@opindex mmax-constant-size +Specifies the maximum size, in bytes, of a constant that can be used as +an operand in a RX instruction. Although the RX instruction set does +allow constants of up to 4 bytes in length to be used in instructions, +a longer value equates to a longer instruction. Thus in some +circumstances it can be beneficial to restrict the size of constants +that are used in instructions. Constants that are too big are instead +placed into a constant pool and referenced via register indirection. + +The value @var{N} can be between 0 and 4. A value of 0 (the default) +or 4 means that constants of any size are allowed. + +@item -mrelax +@opindex mrelax +Enable linker relaxation. Linker relaxation is a process whereby the +linker will attempt to reduce the size of a program by finding shorter +versions of various instructions. Disabled by default. + +@item -mint-register=@var{N} +@opindex mint-register +Specify the number of registers to reserve for fast interrupt handler +functions. The value @var{N} can be between 0 and 4. A value of 1 +means that register @code{r13} will be reserved for the exclusive use +of fast interrupt handlers. A value of 2 reserves @code{r13} and +@code{r12}. A value of 3 reserves @code{r13}, @code{r12} and +@code{r11}, and a value of 4 reserves @code{r13} through @code{r10}. +A value of 0, the default, does not reserve any registers. + +@item -msave-acc-in-interrupts +@opindex msave-acc-in-interrupts +Specifies that interrupt handler functions should preserve the +accumulator register. This is only necessary if normal code might use +the accumulator register, for example because it performs 64-bit +multiplications. The default is to ignore the accumulator as this +makes the interrupt handlers faster. + +@end table + +@emph{Note:} The generic GCC command line @option{-ffixed-@var{reg}} +has special significance to the RX port when used with the +@code{interrupt} function attribute. This attribute indicates a +function intended to process fast interrupts. GCC will will ensure +that it only uses the registers @code{r10}, @code{r11}, @code{r12} +and/or @code{r13} and only provided that the normal use of the +corresponding registers have been restricted via the +@option{-ffixed-@var{reg}} or @option{-mint-register} command line +options. + @node S/390 and zSeries Options @subsection S/390 and zSeries Options @cindex S/390 and zSeries Options @@ -16231,6 +16532,46 @@ useful when compiling kernel code. A register range is specified as two registers separated by a dash. Multiple register ranges can be specified separated by a comma. +@item -mea32 +@itemx -mea64 +@opindex mea32 +@opindex mea64 +Compile code assuming that pointers to the PPU address space accessed +via the @code{__ea} named address space qualifier are either 32 or 64 +bits wide. The default is 32 bits. As this is an ABI changing option, +all object code in an executable must be compiled with the same setting. + +@item -maddress-space-conversion +@itemx -mno-address-space-conversion +@opindex maddress-space-conversion +@opindex mno-address-space-conversion +Allow/disallow treating the @code{__ea} address space as superset +of the generic address space. This enables explicit type casts +between @code{__ea} and generic pointer as well as implicit +conversions of generic pointers to @code{__ea} pointers. The +default is to allow address space pointer conversions. + +@item -mcache-size=@var{cache-size} +@opindex mcache-size +This option controls the version of libgcc that the compiler links to an +executable and selects a software-managed cache for accessing variables +in the @code{__ea} address space with a particular cache size. Possible +options for @var{cache-size} are @samp{8}, @samp{16}, @samp{32}, @samp{64} +and @samp{128}. The default cache size is 64KB. + +@item -matomic-updates +@itemx -mno-atomic-updates +@opindex matomic-updates +@opindex mno-atomic-updates +This option controls the version of libgcc that the compiler links to an +executable and selects whether atomic updates to the software-managed +cache of PPU-side variables are used. If you use atomic updates, changes +to a PPU variable from SPU code using the @code{__ea} named address space +qualifier will not interfere with changes to other PPU variables residing +in the same cache line from PPU code. If you do not use atomic updates, +such interference may occur; however, writing back cache lines will be +more efficient. The default behavior is to use atomic updates. + @item -mdual-nops @itemx -mdual-nops=@var{n} @opindex mdual-nops @@ -16517,7 +16858,7 @@ that MinGW-specific thread support is to be used. @opindex municode This option is available for mingw-w64 targets. It specifies that the UNICODE macro is getting pre-defined and that the -unicode capable runtime startup code is choosen. +unicode capable runtime startup code is chosen. @item -mwin32 @opindex mwin32 @@ -16533,6 +16874,14 @@ specifies that a GUI application is to be generated by instructing the linker to set the PE header subsystem type appropriately. +@item -fno-set-stack-executable +@opindex fno-set-stack-executable +This option is available for MinGW targets. It specifies that +the executable flag for stack used by nested functions isn't +set. This is necessary for binaries running in kernel mode of +Windows, as there the user32 API, which is used to set executable +privileges, isn't available. + @item -mpe-aligned-commons @opindex mpe-aligned-commons This option is available for Cygwin and MinGW targets. It