X-Git-Url: http://git.sourceforge.jp/view?p=pf3gnuchains%2Fgcc-fork.git;a=blobdiff_plain;f=gcc%2Fconfig%2Frs6000%2Frs6000.md;h=fc57e5b3833c06ec9b00981775a21b19511af168;hp=cfdd3c32c49b24b90418cb33ef55496e1b725b9d;hb=086571a4b1555c2ad4267c8eeae1903d9344f1f3;hpb=90ee70af2585812c270a2fd76b41d9f8b7371173

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index cfdd3c32c49..fc57e5b3833 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1,6 +1,7 @@
 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+;; Free Software Foundation, Inc.
 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
 
 ;; This file is part of GCC.
@@ -34,6 +35,10 @@
    (UNSPEC_MOVSI_GOT		8)
    (UNSPEC_MV_CR_OV		9)	; move_from_CR_ov_bit
    (UNSPEC_FCTIWZ		10)
+   (UNSPEC_FRIM			11)
+   (UNSPEC_FRIN			12)
+   (UNSPEC_FRIP			13)
+   (UNSPEC_FRIZ			14)
    (UNSPEC_LD_MPIC		15)	; load_macho_picbase
    (UNSPEC_MPIC_CORRECT		16)	; macho_correct_pic
    (UNSPEC_TLSGD		17)
@@ -52,13 +57,21 @@
    (UNSPEC_FIX_TRUNC_TF		30)	; fadd, rounding towards zero
    (UNSPEC_MV_CR_GT		31)	; move_from_CR_eq_bit
    (UNSPEC_STFIWX		32)
-   (UNSPEC_SYNC			33)
-   (UNSPEC_SYNC_OP		34)
-   (UNSPEC_SYNC_SWAP		35)
-   (UNSPEC_LWSYNC		36)
-   (UNSPEC_ISYNC		37)
-   (UNSPEC_POPCNTB		38)
-   (UNSPEC_FRES			39)
+   (UNSPEC_POPCNTB		33)
+   (UNSPEC_FRES			34)
+   (UNSPEC_SP_SET		35)
+   (UNSPEC_SP_TEST		36)
+   (UNSPEC_SYNC			37)
+   (UNSPEC_LWSYNC		38)
+   (UNSPEC_ISYNC		39)
+   (UNSPEC_SYNC_OP		40)
+   (UNSPEC_ATOMIC		41)
+   (UNSPEC_CMPXCHG		42)
+   (UNSPEC_XCHG			43)
+   (UNSPEC_AND			44)
+   (UNSPEC_DLMZB		45)
+   (UNSPEC_DLMZB_CR		46)
+   (UNSPEC_DLMZB_STRLEN		47)
   ])
 
 ;;
@@ -67,12 +80,14 @@
 
 (define_constants
   [(UNSPECV_BLOCK		0)
+   (UNSPECV_LL			1)	; load-locked
+   (UNSPECV_SC			2)	; store-conditional
    (UNSPECV_EH_RR		9)	; eh_reg_restore
   ])
 
 ;; Define an insn type attribute.  This is used in function unit delay
 ;; computations.
-(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
+(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c"
   (const_string "integer"))
 
 ;; Length (in bytes).
@@ -127,6 +142,9 @@
 ; Any supported integer mode that fits in one register.
 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
 
+; extend modes for DImode
+(define_mode_macro QHSI [QI HI SI])
+
 ; SImode or DImode, even if DImode doesn't fit in GPRs.
 (define_mode_macro SDI [SI DI])
 
@@ -137,47 +155,50 @@
 ; Any hardware-supported floating-point mode
 (define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
   (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
-  (TF "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
+  (TF "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
 
 ; Various instructions that come in SI and DI forms.
 ; A generic w/d attribute, for things like cmpw/cmpd.
-(define_mode_attr wd [(SI "w") (DI "d")])
+(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
+
+; DImode bits
+(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
 
 
 ;; Start with fixed-point load and store insns.  Here we put only the more
 ;; complex forms.  Basic data transfer is done later.
 
-(define_expand "zero_extendqidi2"
+(define_expand "zero_extend<mode>di2"
   [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
+	(zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
   "TARGET_POWERPC64"
   "")
 
-(define_insn ""
+(define_insn "*zero_extend<mode>di2_internal1"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
+	(zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
   "TARGET_POWERPC64"
   "@
-   lbz%U1%X1 %0,%1
-   rldicl %0,%1,0,56"
+   l<wd>z%U1%X1 %0,%1
+   rldicl %0,%1,0,<dbits>"
   [(set_attr "type" "load,*")])
 
-(define_insn ""
+(define_insn "*zero_extend<mode>di2_internal2"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
+	(compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
 		    (const_int 0)))
    (clobber (match_scratch:DI 2 "=r,r"))]
   "TARGET_64BIT"
   "@
-   rldicl. %2,%1,0,56
+   rldicl. %2,%1,0,<dbits>
    #"
   [(set_attr "type" "compare")
    (set_attr "length" "4,8")])
 
 (define_split
   [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
+	(compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
 		    (const_int 0)))
    (clobber (match_scratch:DI 2 ""))]
   "TARGET_POWERPC64 && reload_completed"
@@ -188,22 +209,22 @@
 		    (const_int 0)))]
   "")
 
-(define_insn ""
+(define_insn "*zero_extend<mode>di2_internal3"
   [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
+	(compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
 		    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
 	(zero_extend:DI (match_dup 1)))]
   "TARGET_64BIT"
   "@
-   rldicl. %0,%1,0,56
+   rldicl. %0,%1,0,<dbits>
    #"
   [(set_attr "type" "compare")
    (set_attr "length" "4,8")])
 
 (define_split
   [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
+	(compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
 		    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "")
 	(zero_extend:DI (match_dup 1)))]
@@ -273,73 +294,6 @@
 		    (const_int 0)))]
   "")
 
-(define_expand "zero_extendhidi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
-  "TARGET_POWERPC64"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
-  "TARGET_POWERPC64"
-  "@
-   lhz%U1%X1 %0,%1
-   rldicl %0,%1,0,48"
-  [(set_attr "type" "load,*")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 "=r,r"))]
-  "TARGET_64BIT"
-  "@
-   rldicl. %2,%1,0,48
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 2)
-	(zero_extend:DI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:DI (match_dup 1)))]
-  "TARGET_64BIT"
-  "@
-   rldicl. %0,%1,0,48
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(zero_extend:DI (match_dup 1)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(zero_extend:DI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
 (define_expand "extendhidi2"
   [(set (match_operand:DI 0 "gpc_reg_operand" "")
 	(sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
@@ -407,73 +361,6 @@
 		    (const_int 0)))]
   "")
 
-(define_expand "zero_extendsidi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
-  "TARGET_POWERPC64"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
-  "TARGET_POWERPC64"
-  "@
-   lwz%U1%X1 %0,%1
-   rldicl %0,%1,0,32"
-  [(set_attr "type" "load,*")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 "=r,r"))]
-  "TARGET_64BIT"
-  "@
-   rldicl. %2,%1,0,32
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 2)
-	(zero_extend:DI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:DI (match_dup 1)))]
-  "TARGET_64BIT"
-  "@
-   rldicl. %0,%1,0,32
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(zero_extend:DI (match_dup 1)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(zero_extend:DI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
 (define_expand "extendsidi2"
   [(set (match_operand:DI 0 "gpc_reg_operand" "")
 	(sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
@@ -995,6 +882,536 @@
   [(set_attr "type" "compare")
    (set_attr "length" "4,8")])
 
+;; IBM 405 and 440 half-word multiplication operations.
+
+(define_insn "*macchwc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (plus:SI (mult:SI (ashiftrt:SI
+                                       (match_operand:SI 2 "gpc_reg_operand" "r")
+                                       (const_int 16))
+                                      (sign_extend:SI
+                                       (match_operand:HI 1 "gpc_reg_operand" "r")))
+                             (match_operand:SI 4 "gpc_reg_operand" "0"))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (ashiftrt:SI
+                           (match_dup 2)
+                           (const_int 16))
+                          (sign_extend:SI
+                           (match_dup 1)))
+                 (match_dup 4)))]
+  "TARGET_MULHW"
+  "macchw. %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*macchw"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (ashiftrt:SI
+                           (match_operand:SI 2 "gpc_reg_operand" "r")
+                           (const_int 16))
+                          (sign_extend:SI
+                           (match_operand:HI 1 "gpc_reg_operand" "r")))
+                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
+  "TARGET_MULHW"
+  "macchw %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*macchwuc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (plus:SI (mult:SI (lshiftrt:SI
+                                       (match_operand:SI 2 "gpc_reg_operand" "r")
+                                       (const_int 16))
+                                      (zero_extend:SI
+                                       (match_operand:HI 1 "gpc_reg_operand" "r")))
+                             (match_operand:SI 4 "gpc_reg_operand" "0"))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (lshiftrt:SI
+                           (match_dup 2)
+                           (const_int 16))
+                          (zero_extend:SI
+                           (match_dup 1)))
+                 (match_dup 4)))]
+  "TARGET_MULHW"
+  "macchwu. %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*macchwu"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (lshiftrt:SI
+                           (match_operand:SI 2 "gpc_reg_operand" "r")
+                           (const_int 16))
+                          (zero_extend:SI
+                           (match_operand:HI 1 "gpc_reg_operand" "r")))
+                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
+  "TARGET_MULHW"
+  "macchwu %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*machhwc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (plus:SI (mult:SI (ashiftrt:SI
+                                       (match_operand:SI 1 "gpc_reg_operand" "%r")
+                                       (const_int 16))
+                                      (ashiftrt:SI
+                                       (match_operand:SI 2 "gpc_reg_operand" "r")
+                                       (const_int 16)))
+                             (match_operand:SI 4 "gpc_reg_operand" "0"))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (ashiftrt:SI
+                           (match_dup 1)
+                           (const_int 16))
+                          (ashiftrt:SI
+                           (match_dup 2)
+                           (const_int 16)))
+                 (match_dup 4)))]
+  "TARGET_MULHW"
+  "machhw. %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*machhw"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (ashiftrt:SI
+                           (match_operand:SI 1 "gpc_reg_operand" "%r")
+                           (const_int 16))
+                          (ashiftrt:SI
+                           (match_operand:SI 2 "gpc_reg_operand" "r")
+                           (const_int 16)))
+                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
+  "TARGET_MULHW"
+  "machhw %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*machhwuc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (plus:SI (mult:SI (lshiftrt:SI
+                                       (match_operand:SI 1 "gpc_reg_operand" "%r")
+                                       (const_int 16))
+                                      (lshiftrt:SI
+                                       (match_operand:SI 2 "gpc_reg_operand" "r")
+                                       (const_int 16)))
+                             (match_operand:SI 4 "gpc_reg_operand" "0"))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (lshiftrt:SI
+                           (match_dup 1)
+                           (const_int 16))
+                          (lshiftrt:SI
+                           (match_dup 2)
+                           (const_int 16)))
+                 (match_dup 4)))]
+  "TARGET_MULHW"
+  "machhwu. %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*machhwu"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (lshiftrt:SI
+                           (match_operand:SI 1 "gpc_reg_operand" "%r")
+                           (const_int 16))
+                          (lshiftrt:SI
+                           (match_operand:SI 2 "gpc_reg_operand" "r")
+                           (const_int 16)))
+                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
+  "TARGET_MULHW"
+  "machhwu %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*maclhwc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (plus:SI (mult:SI (sign_extend:SI
+                                       (match_operand:HI 1 "gpc_reg_operand" "%r"))
+                                      (sign_extend:SI
+                                       (match_operand:HI 2 "gpc_reg_operand" "r")))
+                             (match_operand:SI 4 "gpc_reg_operand" "0"))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (sign_extend:SI
+                           (match_dup 1))
+                          (sign_extend:SI
+                           (match_dup 2)))
+                 (match_dup 4)))]
+  "TARGET_MULHW"
+  "maclhw. %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*maclhw"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (sign_extend:SI
+                           (match_operand:HI 1 "gpc_reg_operand" "%r"))
+                          (sign_extend:SI
+                           (match_operand:HI 2 "gpc_reg_operand" "r")))
+                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
+  "TARGET_MULHW"
+  "maclhw %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*maclhwuc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (plus:SI (mult:SI (zero_extend:SI
+                                       (match_operand:HI 1 "gpc_reg_operand" "%r"))
+                                      (zero_extend:SI
+                                       (match_operand:HI 2 "gpc_reg_operand" "r")))
+                             (match_operand:SI 4 "gpc_reg_operand" "0"))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (zero_extend:SI
+                           (match_dup 1))
+                          (zero_extend:SI
+                           (match_dup 2)))
+                 (match_dup 4)))]
+  "TARGET_MULHW"
+  "maclhwu. %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*maclhwu"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (plus:SI (mult:SI (zero_extend:SI
+                           (match_operand:HI 1 "gpc_reg_operand" "%r"))
+                          (zero_extend:SI
+                           (match_operand:HI 2 "gpc_reg_operand" "r")))
+                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
+  "TARGET_MULHW"
+  "maclhwu %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*nmacchwc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
+                              (mult:SI (ashiftrt:SI
+                                        (match_operand:SI 2 "gpc_reg_operand" "r")
+                                        (const_int 16))
+                                       (sign_extend:SI
+                                        (match_operand:HI 1 "gpc_reg_operand" "r"))))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (minus:SI (match_dup 4)
+                  (mult:SI (ashiftrt:SI
+                            (match_dup 2)
+                            (const_int 16))
+                           (sign_extend:SI
+                            (match_dup 1)))))]
+  "TARGET_MULHW"
+  "nmacchw. %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*nmacchw"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
+                  (mult:SI (ashiftrt:SI
+                            (match_operand:SI 2 "gpc_reg_operand" "r")
+                            (const_int 16))
+                           (sign_extend:SI
+                            (match_operand:HI 1 "gpc_reg_operand" "r")))))]
+  "TARGET_MULHW"
+  "nmacchw %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*nmachhwc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
+                              (mult:SI (ashiftrt:SI
+                                        (match_operand:SI 1 "gpc_reg_operand" "%r")
+                                        (const_int 16))
+                                       (ashiftrt:SI
+                                        (match_operand:SI 2 "gpc_reg_operand" "r")
+                                        (const_int 16))))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (minus:SI (match_dup 4)
+                  (mult:SI (ashiftrt:SI
+                            (match_dup 1)
+                            (const_int 16))
+                           (ashiftrt:SI
+                            (match_dup 2)
+                            (const_int 16)))))]
+  "TARGET_MULHW"
+  "nmachhw. %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*nmachhw"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
+                  (mult:SI (ashiftrt:SI
+                            (match_operand:SI 1 "gpc_reg_operand" "%r")
+                            (const_int 16))
+                           (ashiftrt:SI
+                            (match_operand:SI 2 "gpc_reg_operand" "r")
+                            (const_int 16)))))]
+  "TARGET_MULHW"
+  "nmachhw %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*nmaclhwc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
+                              (mult:SI (sign_extend:SI
+                                        (match_operand:HI 1 "gpc_reg_operand" "%r"))
+                                       (sign_extend:SI
+                                        (match_operand:HI 2 "gpc_reg_operand" "r"))))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (minus:SI (match_dup 4)
+                  (mult:SI (sign_extend:SI
+                            (match_dup 1))
+                           (sign_extend:SI
+                            (match_dup 2)))))]
+  "TARGET_MULHW"
+  "nmaclhw. %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*nmaclhw"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
+                  (mult:SI (sign_extend:SI
+                            (match_operand:HI 1 "gpc_reg_operand" "%r"))
+                           (sign_extend:SI
+                            (match_operand:HI 2 "gpc_reg_operand" "r")))))]
+  "TARGET_MULHW"
+  "nmaclhw %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mulchwc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (mult:SI (ashiftrt:SI
+                              (match_operand:SI 2 "gpc_reg_operand" "r")
+                              (const_int 16))
+                             (sign_extend:SI
+                              (match_operand:HI 1 "gpc_reg_operand" "r")))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (ashiftrt:SI
+                  (match_dup 2)
+                  (const_int 16))
+                 (sign_extend:SI
+                  (match_dup 1))))]
+  "TARGET_MULHW"
+  "mulchw. %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mulchw"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (ashiftrt:SI
+                  (match_operand:SI 2 "gpc_reg_operand" "r")
+                  (const_int 16))
+                 (sign_extend:SI
+                  (match_operand:HI 1 "gpc_reg_operand" "r"))))]
+  "TARGET_MULHW"
+  "mulchw %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mulchwuc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (mult:SI (lshiftrt:SI
+                              (match_operand:SI 2 "gpc_reg_operand" "r")
+                              (const_int 16))
+                             (zero_extend:SI
+                              (match_operand:HI 1 "gpc_reg_operand" "r")))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (lshiftrt:SI
+                  (match_dup 2)
+                  (const_int 16))
+                 (zero_extend:SI
+                  (match_dup 1))))]
+  "TARGET_MULHW"
+  "mulchwu. %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mulchwu"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (lshiftrt:SI
+                  (match_operand:SI 2 "gpc_reg_operand" "r")
+                  (const_int 16))
+                 (zero_extend:SI
+                  (match_operand:HI 1 "gpc_reg_operand" "r"))))]
+  "TARGET_MULHW"
+  "mulchwu %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mulhhwc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (mult:SI (ashiftrt:SI
+                              (match_operand:SI 1 "gpc_reg_operand" "%r")
+                              (const_int 16))
+                             (ashiftrt:SI
+                              (match_operand:SI 2 "gpc_reg_operand" "r")
+                              (const_int 16)))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (ashiftrt:SI
+                  (match_dup 1)
+                  (const_int 16))
+                 (ashiftrt:SI
+                  (match_dup 2)
+                  (const_int 16))))]
+  "TARGET_MULHW"
+  "mulhhw. %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mulhhw"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (ashiftrt:SI
+                  (match_operand:SI 1 "gpc_reg_operand" "%r")
+                  (const_int 16))
+                 (ashiftrt:SI
+                  (match_operand:SI 2 "gpc_reg_operand" "r")
+                  (const_int 16))))]
+  "TARGET_MULHW"
+  "mulhhw %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mulhhwuc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (mult:SI (lshiftrt:SI
+                              (match_operand:SI 1 "gpc_reg_operand" "%r")
+                              (const_int 16))
+                             (lshiftrt:SI
+                              (match_operand:SI 2 "gpc_reg_operand" "r")
+                              (const_int 16)))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (lshiftrt:SI
+                  (match_dup 1)
+                  (const_int 16))
+                 (lshiftrt:SI
+                  (match_dup 2)
+                  (const_int 16))))]
+  "TARGET_MULHW"
+  "mulhhwu. %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mulhhwu"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (lshiftrt:SI
+                  (match_operand:SI 1 "gpc_reg_operand" "%r")
+                  (const_int 16))
+                 (lshiftrt:SI
+                  (match_operand:SI 2 "gpc_reg_operand" "r")
+                  (const_int 16))))]
+  "TARGET_MULHW"
+  "mulhhwu %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mullhwc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (mult:SI (sign_extend:SI
+                              (match_operand:HI 1 "gpc_reg_operand" "%r"))
+                             (sign_extend:SI
+                              (match_operand:HI 2 "gpc_reg_operand" "r")))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (sign_extend:SI
+                  (match_dup 1))
+                 (sign_extend:SI
+                  (match_dup 2))))]
+  "TARGET_MULHW"
+  "mullhw. %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mullhw"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (sign_extend:SI
+                  (match_operand:HI 1 "gpc_reg_operand" "%r"))
+                 (sign_extend:SI
+                  (match_operand:HI 2 "gpc_reg_operand" "r"))))]
+  "TARGET_MULHW"
+  "mullhw %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mullhwuc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (compare:CC (mult:SI (zero_extend:SI
+                              (match_operand:HI 1 "gpc_reg_operand" "%r"))
+                             (zero_extend:SI
+                              (match_operand:HI 2 "gpc_reg_operand" "r")))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (zero_extend:SI
+                  (match_dup 1))
+                 (zero_extend:SI
+                  (match_dup 2))))]
+  "TARGET_MULHW"
+  "mullhwu. %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+(define_insn "*mullhwu"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (mult:SI (zero_extend:SI
+                  (match_operand:HI 1 "gpc_reg_operand" "%r"))
+                 (zero_extend:SI
+                  (match_operand:HI 2 "gpc_reg_operand" "r"))))]
+  "TARGET_MULHW"
+  "mullhwu %0, %1, %2"
+  [(set_attr "type" "imul3")])
+
+;; IBM 405 and 440 string-search dlmzb instruction support.
+(define_insn "dlmzb"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+        (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
+                    (match_operand:SI 2 "gpc_reg_operand" "r")]
+                   UNSPEC_DLMZB_CR))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (unspec:SI [(match_dup 1)
+                    (match_dup 2)]
+                   UNSPEC_DLMZB))]
+  "TARGET_DLMZB"
+  "dlmzb. %0, %1, %2")
+
+(define_expand "strlensi"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+        (unspec:SI [(match_operand:BLK 1 "general_operand" "")
+                    (match_operand:QI 2 "const_int_operand" "")
+                    (match_operand 3 "const_int_operand" "")]
+                   UNSPEC_DLMZB_STRLEN))
+   (clobber (match_scratch:CC 4 "=x"))]
+  "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
+{
+  rtx result = operands[0];
+  rtx src = operands[1];
+  rtx search_char = operands[2];
+  rtx align = operands[3];
+  rtx addr, scratch_string, word1, word2, scratch_dlmzb;
+  rtx loop_label, end_label, mem, cr0, cond;
+  if (search_char != const0_rtx
+      || GET_CODE (align) != CONST_INT
+      || INTVAL (align) < 8)
+        FAIL;
+  word1 = gen_reg_rtx (SImode);
+  word2 = gen_reg_rtx (SImode);
+  scratch_dlmzb = gen_reg_rtx (SImode);
+  scratch_string = gen_reg_rtx (Pmode);
+  loop_label = gen_label_rtx ();
+  end_label = gen_label_rtx ();
+  addr = force_reg (Pmode, XEXP (src, 0));
+  emit_move_insn (scratch_string, addr);
+  emit_label (loop_label);
+  mem = change_address (src, SImode, scratch_string);
+  emit_move_insn (word1, mem);
+  emit_move_insn (word2, adjust_address (mem, SImode, 4));
+  cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
+  emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
+  cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
+  emit_jump_insn (gen_rtx_SET (VOIDmode,
+                               pc_rtx,
+                               gen_rtx_IF_THEN_ELSE (VOIDmode,
+                                                     cond,
+                                                     gen_rtx_LABEL_REF
+                                                       (VOIDmode,
+                                                        end_label),
+                                                     pc_rtx)));
+  emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
+  emit_jump_insn (gen_rtx_SET (VOIDmode,
+                               pc_rtx,
+                               gen_rtx_LABEL_REF (VOIDmode, loop_label)));
+  emit_label (end_label);
+  emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
+  emit_insn (gen_subsi3 (result, scratch_string, addr));
+  emit_insn (gen_subsi3 (result, result, const1_rtx));
+  DONE;
+})
+
 (define_split
   [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
 	(compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
@@ -4790,7 +5207,7 @@
   "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
    && ! HONOR_SIGNED_ZEROS (SFmode)"
   "{fnms|fnmsub} %0,%1,%2,%3"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "dmul")])
 
 (define_expand "sqrtsf2"
   [(set (match_operand:SF 0 "gpc_reg_operand" "")
@@ -4823,7 +5240,7 @@
 			 (match_dup 3)
 			 (match_dup 4)))]
   "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
-   && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)" 
+   && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
   {
      operands[3] = gen_reg_rtx (SFmode);
      operands[4] = gen_reg_rtx (SFmode);
@@ -5438,6 +5855,62 @@
   "{fcirz|fctiwz} %0,%1"
   [(set_attr "type" "fp")])
 
+(define_insn "btruncdf2"
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
+  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+  "friz %0,%1"
+  [(set_attr "type" "fp")])
+
+(define_insn "btruncsf2"
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
+  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+  "friz %0,%1"
+  [(set_attr "type" "fp")])
+
+(define_insn "ceildf2"
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
+  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+  "frip %0,%1"
+  [(set_attr "type" "fp")])
+
+(define_insn "ceilsf2"
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
+  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+  "frip %0,%1"
+  [(set_attr "type" "fp")])
+
+(define_insn "floordf2"
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
+  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+  "frim %0,%1"
+  [(set_attr "type" "fp")])
+
+(define_insn "floorsf2"
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
+  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+  "frim %0,%1"
+  [(set_attr "type" "fp")])
+
+(define_insn "rounddf2"
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
+  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+  "frin %0,%1"
+  [(set_attr "type" "fp")])
+
+(define_insn "roundsf2"
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
+  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+  "frin %0,%1"
+  [(set_attr "type" "fp")])
+
 ; An UNSPEC is used so we don't have to support SImode in FP registers.
 (define_insn "stfiwx"
   [(set (match_operand:SI 0 "memory_operand" "=Z")
@@ -5546,7 +6019,7 @@
    (set (match_dup 0) (plus:DI (match_dup 0)
 			       (const_int 2047)))
    (set (match_dup 4) (compare:CCUNS (match_dup 3)
-				     (const_int 3)))
+				     (const_int 2)))
    (set (match_dup 0) (ior:DI (match_dup 0)
 			      (match_dup 1)))
    (parallel [(set (match_dup 0) (and:DI (match_dup 0)
@@ -5946,12 +6419,19 @@
   "")
 
 (define_insn "muldi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
-		 (match_operand:DI 2 "gpc_reg_operand" "r")))]
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+        (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
+                 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
   "TARGET_POWERPC64"
-  "mulld %0,%1,%2"
-   [(set_attr "type" "lmul")])
+  "@
+   mulld %0,%1,%2
+   mulli %0,%1,%2"
+   [(set (attr "type")
+      (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
+		(const_string "imul3")
+	     (match_operand:SI 2 "short_cint_operand" "")
+		(const_string "imul2")]
+	(const_string "lmul")))])
 
 (define_insn "*muldi3_internal1"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -6100,7 +6580,7 @@
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
 			   (match_operand:DI 2 "reg_or_cint_operand" "ri"))
-		(match_operand:DI 3 "mask_operand" "n")))]
+		(match_operand:DI 3 "mask64_operand" "n")))]
   "TARGET_POWERPC64"
   "rld%I2c%B3 %0,%1,%H2,%S3")
 
@@ -6109,7 +6589,7 @@
 	(compare:CC (and:DI
 		     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 				(match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
-		     (match_operand:DI 3 "mask_operand" "n,n"))
+		     (match_operand:DI 3 "mask64_operand" "n,n"))
 		    (const_int 0)))
    (clobber (match_scratch:DI 4 "=r,r"))]
   "TARGET_64BIT"
@@ -6124,7 +6604,7 @@
 	(compare:CC (and:DI
 		     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
 				(match_operand:DI 2 "reg_or_cint_operand" ""))
-		     (match_operand:DI 3 "mask_operand" ""))
+		     (match_operand:DI 3 "mask64_operand" ""))
 		    (const_int 0)))
    (clobber (match_scratch:DI 4 ""))]
   "TARGET_POWERPC64 && reload_completed"
@@ -6142,7 +6622,7 @@
 	(compare:CC (and:DI
 		     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 				(match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
-		     (match_operand:DI 3 "mask_operand" "n,n"))
+		     (match_operand:DI 3 "mask64_operand" "n,n"))
 		    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
 	(and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
@@ -6158,7 +6638,7 @@
 	(compare:CC (and:DI
 		     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
 				(match_operand:DI 2 "reg_or_cint_operand" ""))
-		     (match_operand:DI 3 "mask_operand" ""))
+		     (match_operand:DI 3 "mask64_operand" ""))
 		    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "")
 	(and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
@@ -6496,7 +6976,7 @@
   "@
    rldic. %4,%1,%H2,%W3
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "compare")
    (set_attr "length" "4,8")])
 
 (define_split
@@ -6530,7 +7010,7 @@
   "@
    rldic. %0,%1,%H2,%W3
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "compare")
    (set_attr "length" "4,8")])
 
 (define_split
@@ -6556,7 +7036,7 @@
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
 			   (match_operand:SI 2 "const_int_operand" "i"))
-		(match_operand:DI 3 "mask_operand" "n")))]
+		(match_operand:DI 3 "mask64_operand" "n")))]
   "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
   "rldicr %0,%1,%H2,%S3")
 
@@ -6565,14 +7045,14 @@
 	(compare:CC
 	 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 			    (match_operand:SI 2 "const_int_operand" "i,i"))
-		 (match_operand:DI 3 "mask_operand" "n,n"))
+		 (match_operand:DI 3 "mask64_operand" "n,n"))
 	 (const_int 0)))
    (clobber (match_scratch:DI 4 "=r,r"))]
   "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
   "@
    rldicr. %4,%1,%H2,%S3
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "compare")
    (set_attr "length" "4,8")])
 
 (define_split
@@ -6580,7 +7060,7 @@
 	(compare:CC
 	 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
 			    (match_operand:SI 2 "const_int_operand" ""))
-		 (match_operand:DI 3 "mask_operand" ""))
+		 (match_operand:DI 3 "mask64_operand" ""))
 	 (const_int 0)))
    (clobber (match_scratch:DI 4 ""))]
   "TARGET_POWERPC64 && reload_completed
@@ -6598,7 +7078,7 @@
 	(compare:CC
 	 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 			    (match_operand:SI 2 "const_int_operand" "i,i"))
-		    (match_operand:DI 3 "mask_operand" "n,n"))
+		    (match_operand:DI 3 "mask64_operand" "n,n"))
 	 (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
 	(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
@@ -6606,7 +7086,7 @@
   "@
    rldicr. %0,%1,%H2,%S3
    #"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "compare")
    (set_attr "length" "4,8")])
 
 (define_split
@@ -6614,7 +7094,7 @@
 	(compare:CC
 	 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
 			    (match_operand:SI 2 "const_int_operand" ""))
-		 (match_operand:DI 3 "mask_operand" ""))
+		 (match_operand:DI 3 "mask64_operand" ""))
 	 (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "")
 	(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
@@ -6819,7 +7299,8 @@
    (clobber (match_scratch:CC 3 ""))]
   "TARGET_POWERPC64
     && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
-    && !mask_operand (operands[2], DImode)"
+    && !mask_operand (operands[2], DImode)
+    && !mask64_operand (operands[2], DImode)"
   [(set (match_dup 0)
 	(and:DI (rotate:DI (match_dup 1)
 			   (match_dup 4))
@@ -6833,16 +7314,17 @@
 })
 
 (define_insn "*anddi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
-	(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
-			    (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
+	(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
+			    (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
 		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
-   (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
+   (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
+   (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
   "TARGET_64BIT"
   "@
    and. %3,%1,%2
    rldic%B2. %3,%1,0,%S2
+   rlwinm. %3,%1,0,%m2,%M2
    andi. %3,%1,%b2
    andis. %3,%1,%u2
    #
@@ -6850,9 +7332,10 @@
    #
    #
    #
+   #
    #"
-  [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
-   (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
+  [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
+   (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
 
 (define_split
   [(set (match_operand:CC 0 "cc_reg_operand" "")
@@ -6861,9 +7344,10 @@
                     (const_int 0)))
    (clobber (match_scratch:DI 3 ""))
    (clobber (match_scratch:CC 4 ""))]
-  "TARGET_POWERPC64 && reload_completed
+  "TARGET_64BIT && reload_completed
     && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
-    && !mask_operand (operands[2], DImode)"
+    && !mask_operand (operands[2], DImode)
+    && !mask64_operand (operands[2], DImode)"
   [(set (match_dup 3)
 	(and:DI (rotate:DI (match_dup 1)
 			   (match_dup 5))
@@ -6880,17 +7364,18 @@
 }")
 
 (define_insn "*anddi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
-	(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
-			    (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
+	(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
+			    (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
 		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
 	(and:DI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
+   (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
   "TARGET_64BIT"
   "@
    and. %0,%1,%2
    rldic%B2. %0,%1,0,%S2
+   rlwinm. %0,%1,0,%m2,%M2
    andi. %0,%1,%b2
    andis. %0,%1,%u2
    #
@@ -6898,19 +7383,20 @@
    #
    #
    #
+   #
    #"
-  [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
-   (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
+  [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
+   (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
 
 (define_split
   [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
 	(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			    (match_operand:DI 2 "and_operand" ""))
+			    (match_operand:DI 2 "and64_2_operand" ""))
 		    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "")
 	(and:DI (match_dup 1) (match_dup 2)))
    (clobber (match_scratch:CC 4 ""))]
-  "TARGET_POWERPC64 && reload_completed"
+  "TARGET_64BIT && reload_completed"
   [(parallel [(set (match_dup 0)
 		    (and:DI (match_dup 1) (match_dup 2)))
 	       (clobber (match_dup 4))])
@@ -6927,9 +7413,10 @@
    (set (match_operand:DI 0 "gpc_reg_operand" "")
 	(and:DI (match_dup 1) (match_dup 2)))
    (clobber (match_scratch:CC 4 ""))]
-  "TARGET_POWERPC64 && reload_completed
+  "TARGET_64BIT && reload_completed
     && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
-    && !mask_operand (operands[2], DImode)"
+    && !mask_operand (operands[2], DImode)
+    && !mask64_operand (operands[2], DImode)"
   [(set (match_dup 0)
 	(and:DI (rotate:DI (match_dup 1)
 			   (match_dup 5))
@@ -7507,7 +7994,7 @@
 }")
 
 (define_insn "*movsf_hardfloat"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
 	(match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
   "(gpc_reg_operand (operands[0], SFmode)
    || gpc_reg_operand (operands[1], SFmode))
@@ -7525,7 +8012,7 @@
    {cror 0,0,0|nop}
    #
    #"
-  [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
+  [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
    (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
 
 (define_insn "*movsf_softfloat"
@@ -7547,7 +8034,7 @@
    #
    #
    {cror 0,0,0|nop}"
-  [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
+  [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
    (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
 
 
@@ -7609,7 +8096,7 @@
 
 (define_split
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
-	(match_operand:DF 1 "easy_fp_constant" ""))]
+	(match_operand:DF 1 "const_double_operand" ""))]
   "TARGET_POWERPC64 && reload_completed
    && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
        || (GET_CODE (operands[0]) == SUBREG
@@ -7670,9 +8157,10 @@
       if (GET_CODE (operands[1]) == MEM
 	  && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
 			reload_completed || reload_in_progress)
+	      || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[1], 0))
 	      || GET_CODE (XEXP (operands[1], 0)) == REG
 	      || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
-		  || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
+	      || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
 	      || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
 	{
 	  /* If the low-address word is used in the address, we must load
@@ -7712,9 +8200,10 @@
       if (GET_CODE (operands[0]) == MEM
           && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
 		    reload_completed || reload_in_progress)
+	      || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[0], 0))
 	      || GET_CODE (XEXP (operands[0], 0)) == REG
     	      || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
-		  || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
+	      || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
 	      || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
 	return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
       else
@@ -7787,7 +8276,7 @@
 ; ld/std require word-aligned displacements -> 'Y' constraint.
 ; List Y->r and r->Y before r->r for reload.
 (define_insn "*movdf_hardfloat64"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
 	(match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
   "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
    && (gpc_reg_operand (operands[0], DFmode)
@@ -7805,7 +8294,7 @@
    #
    #
    #"
-  [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
+  [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
    (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
 
 (define_insn "*movdf_softfloat64"
@@ -7824,13 +8313,13 @@
    #
    #
    {cror 0,0,0|nop}"
-  [(set_attr "type" "load,store,*,*,*,*,*,*,*")
+  [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
    (set_attr "length" "4,4,4,4,4,8,12,16,4")])
 
 (define_expand "movtf"
   [(set (match_operand:TF 0 "general_operand" "")
 	(match_operand:TF 1 "any_operand" ""))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
+  "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
   "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
 
@@ -7840,7 +8329,7 @@
 (define_insn_and_split "*movtf_internal"
   [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
 	(match_operand:TF 1 "input_operand"         "f,o,f,YGHF,r,r"))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
+  "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
    && (gpc_reg_operand (operands[0], TFmode)
        || gpc_reg_operand (operands[1], TFmode))"
@@ -7854,17 +8343,20 @@
   [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
 		   (float_extend:TF (match_operand:DF 1 "input_operand" "")))
 	      (use (match_dup 2))])]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
+  "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
 {
   operands[2] = CONST0_RTX (DFmode);
+  /* Generate GOT reference early for SVR4 PIC.  */
+  if (DEFAULT_ABI == ABI_V4 && flag_pic)
+    operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
 })
 
 (define_insn_and_split "*extenddftf2_internal"
   [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
        (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
    (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
+  "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
   "#"
   "&& reload_completed"
@@ -7882,7 +8374,7 @@
 (define_expand "extendsftf2"
   [(set (match_operand:TF 0 "nonimmediate_operand" "")
 	(float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
+  "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
 {
   rtx tmp = gen_reg_rtx (DFmode);
@@ -7894,14 +8386,14 @@
 (define_expand "trunctfdf2"
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
 	(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
+  "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
   "")
 
 (define_insn_and_split "trunctfdf2_internal1"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
 	(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
+  "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
   "@
    #
@@ -7917,7 +8409,7 @@
 (define_insn "trunctfdf2_internal2"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
 	(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
+  "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
   "fadd %0,%1,%L1"
   [(set_attr "type" "fp")])
@@ -7926,7 +8418,7 @@
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
 	(float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
    (clobber (match_scratch:DF 2 "=f"))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
+  "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
   "#"
   "&& reload_completed"
@@ -7939,7 +8431,7 @@
 (define_expand "floatsitf2"
   [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
         (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
+  "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
 {
   rtx tmp = gen_reg_rtx (DFmode);
@@ -7967,7 +8459,7 @@
 	      (clobber (match_dup 3))
 	      (clobber (match_dup 4))
 	      (clobber (match_dup 5))])]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
+  "!TARGET_IEEEQUAD
    && (TARGET_POWER2 || TARGET_POWERPC)
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
 {
@@ -7984,7 +8476,7 @@
    (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
    (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
    (clobber (match_operand:DI 5 "memory_operand" "=o"))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
+  "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
   "#"
   "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
@@ -8005,7 +8497,7 @@
 (define_insn "negtf2"
   [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
 	(neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
+  "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
   "*
 {
@@ -8020,7 +8512,7 @@
 (define_expand "abstf2"
   [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
 	(abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
+  "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
   "
 {
@@ -8040,7 +8532,7 @@
 			   (label_ref (match_operand 2 "" ""))
 			   (pc)))
    (set (match_dup 6) (neg:DF (match_dup 6)))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
+  "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
   "
 {
@@ -8143,7 +8635,7 @@
 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
 (define_split
   [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(match_operand:DI 1 "mask_operand" ""))]
+	(match_operand:DI 1 "mask64_operand" ""))]
   "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
   [(set (match_dup 0) (const_int -1))
    (set (match_dup 0)
@@ -8258,7 +8750,7 @@
       return \"#\";
     }
 }"
-  [(set_attr "type" "store,store,*,load,load,*")])
+  [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
 
 (define_insn "*movti_ppc64"
   [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
@@ -8359,7 +8851,7 @@
   "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
   "*
 { return rs6000_output_load_multiple (operands); }"
-  [(set_attr "type" "load")
+  [(set_attr "type" "load_ux")
    (set_attr "length" "32")])
 
 (define_insn "*ldmsi7"
@@ -8381,7 +8873,7 @@
   "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
   "*
 { return rs6000_output_load_multiple (operands); }"
-  [(set_attr "type" "load")
+  [(set_attr "type" "load_ux")
    (set_attr "length" "32")])
 
 (define_insn "*ldmsi6"
@@ -8401,7 +8893,7 @@
   "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
   "*
 { return rs6000_output_load_multiple (operands); }"
-  [(set_attr "type" "load")
+  [(set_attr "type" "load_ux")
    (set_attr "length" "32")])
 
 (define_insn "*ldmsi5"
@@ -8419,7 +8911,7 @@
   "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
   "*
 { return rs6000_output_load_multiple (operands); }"
-  [(set_attr "type" "load")
+  [(set_attr "type" "load_ux")
    (set_attr "length" "32")])
 
 (define_insn "*ldmsi4"
@@ -8435,7 +8927,7 @@
   "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
   "*
 { return rs6000_output_load_multiple (operands); }"
-  [(set_attr "type" "load")
+  [(set_attr "type" "load_ux")
    (set_attr "length" "32")])
 
 (define_insn "*ldmsi3"
@@ -8449,7 +8941,7 @@
   "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
   "*
 { return rs6000_output_load_multiple (operands); }"
-  [(set_attr "type" "load")
+  [(set_attr "type" "load_ux")
    (set_attr "length" "32")])
 
 (define_expand "store_multiple"
@@ -8526,7 +9018,7 @@
 	  (match_operand:SI 10 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store")])
+  [(set_attr "type" "store_ux")])
 
 (define_insn "*stmsi7"
   [(match_parallel 0 "store_multiple_operation"
@@ -8547,7 +9039,7 @@
 	  (match_operand:SI 9 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store")])
+  [(set_attr "type" "store_ux")])
 
 (define_insn "*stmsi6"
   [(match_parallel 0 "store_multiple_operation"
@@ -8566,7 +9058,7 @@
 	  (match_operand:SI 8 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store")])
+  [(set_attr "type" "store_ux")])
 
 (define_insn "*stmsi5"
   [(match_parallel 0 "store_multiple_operation"
@@ -8583,7 +9075,7 @@
 	  (match_operand:SI 7 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store")])
+  [(set_attr "type" "store_ux")])
 
 (define_insn "*stmsi4"
   [(match_parallel 0 "store_multiple_operation"
@@ -8598,7 +9090,7 @@
 	  (match_operand:SI 6 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store")])
+  [(set_attr "type" "store_ux")])
 
 (define_insn "*stmsi3"
   [(match_parallel 0 "store_multiple_operation"
@@ -8611,7 +9103,7 @@
 	  (match_operand:SI 5 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store")])
+  [(set_attr "type" "store_ux")])
 
 (define_expand "setmemsi"
   [(parallel [(set (match_operand:BLK 0 "" "")
@@ -8622,7 +9114,7 @@
   "
 {
   /* If value to set is not zero, use the library routine.  */
-  if (operand[2] != const0_rtx)
+  if (operands[2] != const0_rtx)
     FAIL;
 
   if (expand_block_clear (operands))
@@ -8692,7 +9184,7 @@
    && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
    && REGNO (operands[4]) == 5"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
+  [(set_attr "type" "store_ux")
    (set_attr "length" "8")])
 
 (define_insn ""
@@ -8716,7 +9208,7 @@
    && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
    && REGNO (operands[4]) == 5"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
+  [(set_attr "type" "store_ux")
    (set_attr "length" "8")])
 
 ;; Move up to 24 bytes at a time.  The fixed registers are needed because the
@@ -8755,7 +9247,7 @@
    && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
    && REGNO (operands[4]) == 5"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
+  [(set_attr "type" "store_ux")
    (set_attr "length" "8")])
 
 (define_insn ""
@@ -8776,7 +9268,7 @@
    && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
    && REGNO (operands[4]) == 5"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
+  [(set_attr "type" "store_ux")
    (set_attr "length" "8")])
 
 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
@@ -8811,7 +9303,7 @@
    && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
    && REGNO (operands[4]) == 5"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
+  [(set_attr "type" "store_ux")
    (set_attr "length" "8")])
 
 (define_insn ""
@@ -8830,7 +9322,7 @@
    && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
    && REGNO (operands[4]) == 5"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
+  [(set_attr "type" "store_ux")
    (set_attr "length" "8")])
 
 ;; Move up to 8 bytes at a time.
@@ -8854,7 +9346,7 @@
   "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
    && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
+  [(set_attr "type" "store_ux")
    (set_attr "length" "8")])
 
 (define_insn ""
@@ -8867,7 +9359,7 @@
   "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
    && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
+  [(set_attr "type" "store_ux")
    (set_attr "length" "8")])
 
 ;; Move up to 4 bytes at a time.
@@ -8891,7 +9383,7 @@
   "TARGET_STRING && TARGET_POWER
    && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
+  [(set_attr "type" "store_ux")
    (set_attr "length" "8")])
 
 (define_insn ""
@@ -8904,7 +9396,7 @@
   "TARGET_STRING && ! TARGET_POWER
    && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
+  [(set_attr "type" "store_ux")
    (set_attr "length" "8")])
 
 ;; Define insns that do load or store with update.  Some of these we can
@@ -9137,11 +9629,11 @@
 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
 
 (define_insn "*lfq_power2"
-  [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
-	(match_operand:TF 1 "memory_operand" ""))]
+  [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
+	(match_operand:V2DF 1 "memory_operand" ""))]
   "TARGET_POWER2
    && TARGET_HARD_FLOAT && TARGET_FPRS"
-   "lfq%U1%X1 %0,%1")
+  "lfq%U1%X1 %0,%1")
 
 (define_peephole2
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
@@ -9153,13 +9645,13 @@
    && registers_ok_for_quad_peep (operands[0], operands[2])
    && mems_ok_for_quad_peep (operands[1], operands[3])"
   [(set (match_dup 0)
-        (match_dup 1))]
-  "operands[1] = widen_memory_access (operands[1], TFmode, 0);
-   operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));")
+	(match_dup 1))]
+  "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
+   operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
 
 (define_insn "*stfq_power2"
-  [(set (match_operand:TF 0 "memory_operand" "")
-	(match_operand:TF 1 "gpc_reg_operand" "f"))]
+  [(set (match_operand:V2DF 0 "memory_operand" "")
+	(match_operand:V2DF 1 "gpc_reg_operand" "f"))]
   "TARGET_POWER2
    && TARGET_HARD_FLOAT && TARGET_FPRS"
   "stfq%U0%X0 %1,%0")
@@ -9176,8 +9668,8 @@
    && mems_ok_for_quad_peep (operands[0], operands[2])"
   [(set (match_dup 0)
 	(match_dup 1))]
-  "operands[0] = widen_memory_access (operands[0], TFmode, 0);
-   operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));")
+  "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
+   operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
 
 ;; after inserting conditional returns we can sometimes have
 ;; unnecessary register moves.  Unfortunately we cannot have a
@@ -9459,51 +9951,58 @@
   ""
   "DONE;")
 
+;; Adjust stack pointer (op0) to a new value (op1).
+;; First copy old stack backchain to new location, and ensure that the
+;; scheduler won't reorder the sp assignment before the backchain write.
 (define_expand "restore_stack_block"
-  [(use (match_operand 0 "register_operand" ""))
-   (set (match_dup 2) (match_dup 3))
-   (set (match_dup 0) (match_operand 1 "register_operand" ""))
-   (set (match_dup 3) (match_dup 2))]
+  [(set (match_dup 2) (match_dup 3))
+   (set (match_dup 4) (match_dup 2))
+   (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
+   (set (match_operand 0 "register_operand" "")
+	(match_operand 1 "register_operand" ""))]
   ""
   "
 {
   operands[2] = gen_reg_rtx (Pmode);
-  operands[3] = gen_rtx_MEM (Pmode, operands[0]);
+  operands[3] = gen_frame_mem (Pmode, operands[0]);
+  operands[4] = gen_frame_mem (Pmode, operands[1]);
+  operands[5] = gen_frame_mem (BLKmode, operands[0]);
 }")
 
 (define_expand "save_stack_nonlocal"
-  [(match_operand 0 "memory_operand" "")
-   (match_operand 1 "register_operand" "")]
+  [(set (match_dup 3) (match_dup 4))
+   (set (match_operand 0 "memory_operand" "") (match_dup 3))
+   (set (match_dup 2) (match_operand 1 "register_operand" ""))]
   ""
   "
 {
-  rtx temp = gen_reg_rtx (Pmode);
   int units_per_word = (TARGET_32BIT) ? 4 : 8;
 
   /* Copy the backchain to the first word, sp to the second.  */
-  emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
-  emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
-  emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
-		  operands[1]);
-  DONE;
+  operands[0] = adjust_address_nv (operands[0], Pmode, 0);
+  operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
+  operands[3] = gen_reg_rtx (Pmode);
+  operands[4] = gen_frame_mem (Pmode, operands[1]);
 }")
 
 (define_expand "restore_stack_nonlocal"
-  [(match_operand 0 "register_operand" "")
-   (match_operand 1 "memory_operand" "")]
+  [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
+   (set (match_dup 3) (match_dup 4))
+   (set (match_dup 5) (match_dup 2))
+   (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
+   (set (match_operand 0 "register_operand" "") (match_dup 3))]
   ""
   "
 {
-  rtx temp = gen_reg_rtx (Pmode);
   int units_per_word = (TARGET_32BIT) ? 4 : 8;
 
   /* Restore the backchain from the first word, sp from the second.  */
-  emit_move_insn (temp,
-		  adjust_address_nv (operands[1], Pmode, 0));
-  emit_move_insn (operands[0],
-		  adjust_address_nv (operands[1], Pmode, units_per_word));
-  emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
-  DONE;
+  operands[2] = gen_reg_rtx (Pmode);
+  operands[3] = gen_reg_rtx (Pmode);
+  operands[1] = adjust_address_nv (operands[1], Pmode, 0);
+  operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
+  operands[5] = gen_frame_mem (Pmode, operands[3]);
+  operands[6] = gen_frame_mem (BLKmode, operands[0]);
 }")
 
 ;; TOC register handling.
@@ -10757,7 +11256,87 @@
   ""
   "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
 
-
+(define_expand "stack_protect_set"
+  [(match_operand 0 "memory_operand" "")
+   (match_operand 1 "memory_operand" "")]
+  ""
+{
+#ifdef TARGET_THREAD_SSP_OFFSET
+  rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
+  rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
+  operands[1] = gen_rtx_MEM (Pmode, addr);
+#endif
+  if (TARGET_64BIT)
+    emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
+  else
+    emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
+  DONE;
+})
+
+(define_insn "stack_protect_setsi"
+  [(set (match_operand:SI 0 "memory_operand" "=m")
+	(unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
+   (set (match_scratch:SI 2 "=&r") (const_int 0))]
+  "TARGET_32BIT"
+  "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
+  [(set_attr "type" "three")
+   (set_attr "length" "12")])
+
+(define_insn "stack_protect_setdi"
+  [(set (match_operand:DI 0 "memory_operand" "=m")
+	(unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
+   (set (match_scratch:DI 2 "=&r") (const_int 0))]
+  "TARGET_64BIT"
+  "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
+  [(set_attr "type" "three")
+   (set_attr "length" "12")])
+
+(define_expand "stack_protect_test"
+  [(match_operand 0 "memory_operand" "")
+   (match_operand 1 "memory_operand" "")
+   (match_operand 2 "" "")]
+  ""
+{
+#ifdef TARGET_THREAD_SSP_OFFSET
+  rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
+  rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
+  operands[1] = gen_rtx_MEM (Pmode, addr);
+#endif
+  rs6000_compare_op0 = operands[0];
+  rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
+				       UNSPEC_SP_TEST);
+  rs6000_compare_fp_p = 0;
+  emit_jump_insn (gen_beq (operands[2]));
+  DONE;
+})
+
+(define_insn "stack_protect_testsi"
+  [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
+        (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
+		      (match_operand:SI 2 "memory_operand" "m,m")]
+		     UNSPEC_SP_TEST))
+   (set (match_scratch:SI 4 "=r,r") (const_int 0))
+   (clobber (match_scratch:SI 3 "=&r,&r"))]
+  "TARGET_32BIT"
+  "@
+   {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
+   {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
+  [(set_attr "length" "16,20")])
+
+(define_insn "stack_protect_testdi"
+  [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
+        (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
+		      (match_operand:DI 2 "memory_operand" "m,m")]
+		     UNSPEC_SP_TEST))
+   (set (match_scratch:DI 4 "=r,r") (const_int 0))
+   (clobber (match_scratch:DI 3 "=&r,&r"))]
+  "TARGET_64BIT"
+  "@
+   ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
+   ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
+  [(set_attr "length" "16,20")])
+
+
 ;; Here are the actual compare insns.
 (define_insn "*cmp<mode>_internal1"
   [(set (match_operand:CC 0 "cc_reg_operand" "=y")
@@ -10768,32 +11347,47 @@
   [(set_attr "type" "cmp")])
 
 ;; If we are comparing a register for equality with a large constant,
-;; we can do this with an XOR followed by a compare.  But we need a scratch
-;; register for the result of the XOR.
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_operand" "")
-	(compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
-		    (match_operand:SI 2 "non_short_cint_operand" "")))
-   (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
-  "find_single_use (operands[0], insn, 0)
-   && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
-       || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
-  [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
-   (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
-  "
-{
-  /* Get the constant we are comparing against, C,  and see what it looks like
-     sign-extended to 16 bits.  Then see what constant could be XOR'ed
-     with C to get the sign-extended value.  */
+;; we can do this with an XOR followed by a compare.  But this is profitable
+;; only if the large constant is only used for the comparison (and in this
+;; case we already have a register to reuse as scratch).
+;;
+;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
+;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
 
-  HOST_WIDE_INT c = INTVAL (operands[2]);
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand")
+        (match_operand:SI 1 "logical_const_operand" ""))
+   (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
+		       [(match_dup 0)
+			(match_operand:SI 2 "logical_const_operand" "")]))
+   (set (match_operand:CC 4 "cc_reg_operand" "")
+        (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
+                    (match_dup 0)))
+   (set (pc)
+        (if_then_else (match_operator 6 "equality_operator"
+                       [(match_dup 4) (const_int 0)])
+                      (match_operand 7 "" "")
+                      (match_operand 8 "" "")))]
+  "peep2_reg_dead_p (3, operands[0])
+   && peep2_reg_dead_p (4, operands[4])"
+ [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
+  (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
+  (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
+ 
+{
+  /* Get the constant we are comparing against, and see what it looks like
+     when sign-extended from 16 to 32 bits.  Then see what constant we could
+     XOR with SEXTC to get the sign-extended value.  */
+  rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
+					      SImode,
+					      operands[1], operands[2]);
+  HOST_WIDE_INT c = INTVAL (cnst);
   HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
   HOST_WIDE_INT xorv = c ^ sextc;
 
-  operands[4] = GEN_INT (xorv);
-  operands[5] = GEN_INT (sextc);
-}")
+  operands[9] = GEN_INT (xorv);
+  operands[10] = GEN_INT (sextc);
+})
 
 (define_insn "*cmpsi_internal2"
   [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
@@ -10877,7 +11471,7 @@
   [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
 	(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
 		      (match_operand:TF 2 "gpc_reg_operand" "f")))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
+  "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
   "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
   [(set_attr "type" "fpcompare")
@@ -10895,7 +11489,7 @@
     (clobber (match_scratch:DF 8 "=f"))
     (clobber (match_scratch:DF 9 "=f"))
     (clobber (match_scratch:DF 10 "=f"))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
+  "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
   "#"
   "&& reload_completed"
@@ -11162,58 +11756,60 @@
 (define_insn_and_split "*eq<mode>"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
 	(eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
-		(match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))
-   (clobber (match_scratch:GPR 3 "=r"))
-   (clobber (match_scratch:GPR 4 "=r"))]
-  ""
+		(match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
+  "!TARGET_POWER"
   "#"
-  "reload_completed"
-  [(set (match_dup 3)
-	(clz:GPR (match_dup 4)))
+  "!TARGET_POWER"
+  [(set (match_dup 0)
+	(clz:GPR (match_dup 3)))
    (set (match_dup 0)
-	(lshiftrt:GPR (match_dup 3) (match_dup 5)))]
+	(lshiftrt:GPR (match_dup 0) (match_dup 4)))]
   {
     if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
       {
+	/* Use output operand as intermediate.  */
+	operands[3] = operands[0];
+
 	if (logical_operand (operands[2], <MODE>mode))
-	  emit_insn (gen_rtx_SET (VOIDmode, operands[4],
+	  emit_insn (gen_rtx_SET (VOIDmode, operands[3],
 				  gen_rtx_XOR (<MODE>mode,
 					       operands[1], operands[2])));
 	else
-	  emit_insn (gen_rtx_SET (VOIDmode, operands[4],
+	  emit_insn (gen_rtx_SET (VOIDmode, operands[3],
 				  gen_rtx_PLUS (<MODE>mode, operands[1],
 						negate_rtx (<MODE>mode,
 							    operands[2]))));
       }
     else
-      operands[4] = operands[1];
+      operands[3] = operands[1];
 
-    operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
+    operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
   })
 
 (define_insn_and_split "*eq<mode>_compare"
-  [(set (match_operand:CC 5 "cc_reg_operand" "=y")
+  [(set (match_operand:CC 3 "cc_reg_operand" "=y")
 	(compare:CC
 	 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
 	       (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
 	 (const_int 0)))
    (set (match_operand:P 0 "gpc_reg_operand" "=r")
-	(eq:P (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:P 3 "=r"))
-   (clobber (match_scratch:P 4 "=r"))]
-  ""
+	(eq:P (match_dup 1) (match_dup 2)))]
+  "!TARGET_POWER && optimize_size"
   "#"
-  "reload_completed"
-  [(set (match_dup 3)
+  "!TARGET_POWER && optimize_size"
+  [(set (match_dup 0)
 	(clz:P (match_dup 4)))
-   (parallel [(set (match_dup 5)
-		   (compare:CC (lshiftrt:P (match_dup 3) (match_dup 6))
+   (parallel [(set (match_dup 3)
+		   (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
 			       (const_int 0)))
 	      (set (match_dup 0)
-		   (lshiftrt:P (match_dup 3) (match_dup 6)))])]
+		   (lshiftrt:P (match_dup 0) (match_dup 5)))])]
   {
     if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
       {
+	/* Use output operand as intermediate.  */
+	operands[4] = operands[0];
+
 	if (logical_operand (operands[2], <MODE>mode))
 	  emit_insn (gen_rtx_SET (VOIDmode, operands[4],
 				  gen_rtx_XOR (<MODE>mode,
@@ -11227,9 +11823,24 @@
     else
       operands[4] = operands[1];
 
-    operands[6] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
+    operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
   })
 
+(define_insn "*eqsi_power"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
+	(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
+	       (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
+   (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
+  "TARGET_POWER"
+  "@
+   xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
+   {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
+   {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
+   {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
+   {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
+  [(set_attr "type" "three,two,three,three,three")
+   (set_attr "length" "12,8,12,12,12")])
+
 ;; We have insns of the form shown by the first define_insn below.  If
 ;; there is something inside the comparison operation, we must split it.
 (define_split
@@ -11245,7 +11856,7 @@
    (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
 			       (match_dup 4)))])
 
-(define_insn ""
+(define_insn "*plus_eqsi"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
 	(plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
 			(match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
@@ -11260,7 +11871,7 @@
   [(set_attr "type" "three,two,three,three,three")
    (set_attr "length" "12,8,12,12,12")])
 
-(define_insn ""
+(define_insn "*compare_plus_eqsi"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
 	(compare:CC
 	 (plus:SI
@@ -11269,7 +11880,7 @@
 	  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
-  "TARGET_32BIT"
+  "TARGET_32BIT && optimize_size"
   "@
    xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
    {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
@@ -11293,7 +11904,7 @@
 	  (match_operand:SI 3 "gpc_reg_operand" ""))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 ""))]
-  "TARGET_32BIT && reload_completed"
+  "TARGET_32BIT && optimize_size && reload_completed"
   [(set (match_dup 4)
 	(plus:SI (eq:SI (match_dup 1)
 		 (match_dup 2))
@@ -11303,7 +11914,7 @@
 		    (const_int 0)))]
   "")
 
-(define_insn ""
+(define_insn "*plus_eqsi_compare"
   [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
 	(compare:CC
 	 (plus:SI
@@ -11313,7 +11924,7 @@
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
 	(plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "TARGET_32BIT"
+  "TARGET_32BIT && optimize_size"
   "@
    xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
    {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
@@ -11338,7 +11949,7 @@
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "TARGET_32BIT && reload_completed"
+  "TARGET_32BIT && optimize_size && reload_completed"
   [(set (match_dup 0)
 	(plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (set (match_dup 4)
@@ -11346,23 +11957,46 @@
 		    (const_int 0)))]
   "")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
-	(neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
-		       (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))))]
-  "TARGET_32BIT"
-  "@
-   xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
-   {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
-   {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
-   {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
-   {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
-   [(set_attr "type" "three,two,three,three,three")
-    (set_attr "length" "12,8,12,12,12")])
+(define_insn "*neg_eq0<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
+	(neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
+		     (const_int 0))))]
+  ""
+  "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
+  [(set_attr "type" "two")
+   (set_attr "length" "8")])
+
+(define_insn_and_split "*neg_eq<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
+	(neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
+		     (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
+  ""
+  "#"
+  ""
+  [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
+  {
+    if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
+      {
+	/* Use output operand as intermediate.  */
+	operands[3] = operands[0];
+
+	if (logical_operand (operands[2], <MODE>mode))
+	  emit_insn (gen_rtx_SET (VOIDmode, operands[3],
+				  gen_rtx_XOR (<MODE>mode,
+					       operands[1], operands[2])));
+	else
+	  emit_insn (gen_rtx_SET (VOIDmode, operands[3],
+				  gen_rtx_PLUS (<MODE>mode, operands[1],
+						negate_rtx (<MODE>mode,
+							    operands[2]))));
+      }
+    else
+      operands[3] = operands[1];
+  })
 
 ;; Simplify (ne X (const_int 0)) on the PowerPC.  No need to on the Power,
 ;; since it nabs/sr is just as fast.
-(define_insn "*ne0"
+(define_insn "*ne0si"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
 	(lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
 		     (const_int 31)))
@@ -11372,7 +12006,7 @@
   [(set_attr "type" "two")
    (set_attr "length" "8")])
 
-(define_insn ""
+(define_insn "*ne0di"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
 		     (const_int 63)))
@@ -11383,7 +12017,7 @@
    (set_attr "length" "8")])
 
 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
-(define_insn ""
+(define_insn "*plus_ne0si"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (lshiftrt:SI
 		  (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
@@ -11395,7 +12029,7 @@
   [(set_attr "type" "two")
    (set_attr "length" "8")])
 
-(define_insn ""
+(define_insn "*plus_ne0di"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(plus:DI (lshiftrt:DI
 		  (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
@@ -11407,7 +12041,7 @@
   [(set_attr "type" "two")
    (set_attr "length" "8")])
 
-(define_insn ""
+(define_insn "*compare_plus_ne0si"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
 	(compare:CC
 	 (plus:SI (lshiftrt:SI
@@ -11445,7 +12079,7 @@
 		    (const_int 0)))]
   "")
 
-(define_insn ""
+(define_insn "*compare_plus_ne0di"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
 	(compare:CC
 	 (plus:DI (lshiftrt:DI
@@ -11480,7 +12114,7 @@
 		    (const_int 0)))]
   "")
 
-(define_insn ""
+(define_insn "*plus_ne0si_compare"
   [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
 	(compare:CC
 	 (plus:SI (lshiftrt:SI
@@ -11521,7 +12155,7 @@
 		    (const_int 0)))]
   "")
 
-(define_insn ""
+(define_insn "*plus_ne0di_compare"
   [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
 	(compare:CC
 	 (plus:DI (lshiftrt:DI
@@ -11699,64 +12333,24 @@
    {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
   [(set_attr "length" "12")])
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		(match_operand:SI 2 "reg_or_short_operand" "rI")))]
-  "TARGET_32BIT"
+(define_insn "*leu<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
+	(leu:P (match_operand:P 1 "gpc_reg_operand" "r")
+	       (match_operand:P 2 "reg_or_short_operand" "rI")))]
+  ""
   "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
   [(set_attr "type" "three")
    (set_attr "length" "12")])
 
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-		(match_operand:DI 2 "reg_or_short_operand" "rI")))]
-  "TARGET_64BIT"
-  "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
-  [(set_attr "type" "three")
-   (set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-		 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
-	 (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(leu:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_64BIT"
-  "@
-   subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
-		 (match_operand:DI 2 "reg_or_short_operand" ""))
-	 (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(leu:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_64BIT && reload_completed"
-  [(set (match_dup 0)
-	(leu:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
+(define_insn "*leu<mode>_compare"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
 	(compare:CC
-	 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
+	 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
+		(match_operand:P 2 "reg_or_short_operand" "rI,rI"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(leu:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_32BIT"
+   (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
+	(leu:P (match_dup 1) (match_dup 2)))]
+  ""
   "@
    {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
    #"
@@ -11766,25 +12360,25 @@
 (define_split
   [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
 	(compare:CC
-	 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		 (match_operand:SI 2 "reg_or_short_operand" ""))
+	 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
+		(match_operand:P 2 "reg_or_short_operand" ""))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(leu:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_32BIT && reload_completed"
+   (set (match_operand:P 0 "gpc_reg_operand" "")
+	(leu:P (match_dup 1) (match_dup 2)))]
+  "reload_completed"
   [(set (match_dup 0)
-	(leu:SI (match_dup 1) (match_dup 2)))
+	(leu:P (match_dup 1) (match_dup 2)))
    (set (match_dup 3)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
   "")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
-	(plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			 (match_operand:SI 2 "reg_or_short_operand" "rI"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r")))]
-  "TARGET_32BIT"
+(define_insn "*plus_leu<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
+	(plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
+		       (match_operand:P 2 "reg_or_short_operand" "rI"))
+		(match_operand:P 3 "gpc_reg_operand" "r")))]
+  ""
   "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
   [(set_attr "type" "two")
    (set_attr "length" "8")])
@@ -11854,22 +12448,22 @@
 		    (const_int 0)))]
   "")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
-  "TARGET_32BIT"
+(define_insn "*neg_leu<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
+	(neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
+		      (match_operand:P 2 "reg_or_short_operand" "rI"))))]
+  ""
   "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
    [(set_attr "type" "three")
     (set_attr "length" "12")])
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
-	(and:SI (neg:SI
-		 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			 (match_operand:SI 2 "reg_or_short_operand" "rI")))
-		(match_operand:SI 3 "gpc_reg_operand" "r")))]
-  "TARGET_32BIT"
+(define_insn "*and_neg_leu<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
+	(and:P (neg:P
+		 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
+			(match_operand:P 2 "reg_or_short_operand" "rI")))
+		(match_operand:P 3 "gpc_reg_operand" "r")))]
+  ""
   "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
   [(set_attr "type" "three")
    (set_attr "length" "12")])
@@ -12065,206 +12659,106 @@
   "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
   [(set_attr "length" "12")])
 
-(define_insn_and_split ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
-  "TARGET_32BIT"
-  "#"
-  "TARGET_32BIT"
-  [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
-   (set (match_dup 0) (neg:SI (match_dup 0)))]
-  "")
-
-(define_insn_and_split ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-		(match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
-  "TARGET_64BIT"
+(define_insn_and_split "*ltu<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
+	(ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
+	       (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
+  ""
   "#"
-  "TARGET_64BIT"
-  [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
-   (set (match_dup 0) (neg:DI (match_dup 0)))]
+  ""
+  [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
+   (set (match_dup 0) (neg:P (match_dup 0)))]
   "")
 
-(define_insn ""
+(define_insn_and_split "*ltu<mode>_compare"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
 	(compare:CC
-	 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-		 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(ltu:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_32BIT"
-  "@
-   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
-   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
-   #
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,12,16,16")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
+	 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
+		(match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ltu:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_32BIT && reload_completed"
-  [(set (match_dup 0)
-	(ltu:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
+   (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
+	(ltu:P (match_dup 1) (match_dup 2)))]
+  ""
+  "#"
+  ""
+  [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
+   (parallel [(set (match_dup 3)
+		   (compare:CC (neg:P (match_dup 0)) (const_int 0)))
+	      (set (match_dup 0) (neg:P (match_dup 0)))])]
   "")
 
-(define_insn_and_split ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
-	(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
-		 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
-  "TARGET_32BIT"
+(define_insn_and_split "*plus_ltu<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
+	(plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
+		       (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
+		(match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
+  ""
   "#"
   "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
-  [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
-   (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
+  [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
+   (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
   "")
 
-(define_insn_and_split ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
-	(plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
-		 (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))]
-  "TARGET_64BIT"
+(define_insn_and_split "*plus_ltu<mode>_compare"
+  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
+	(compare:CC
+	 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
+			(match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
+		 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
+	 (const_int 0)))
+   (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
+	(plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
+  ""
   "#"
   "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
-  [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
-   (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
+  [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
+   (parallel [(set (match_dup 4)
+		   (compare:CC (minus:P (match_dup 3) (match_dup 0))
+			       (const_int 0)))
+	      (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
   "")
 
+(define_insn "*neg_ltu<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
+	(neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
+		      (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
+  ""
+  "@
+   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
+   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
+  [(set_attr "type" "two")
+   (set_attr "length" "8")])
+
 (define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+	       (match_operand:SI 2 "reg_or_short_operand" "rI")))
+   (clobber (match_scratch:SI 3 "=r"))]
+  "TARGET_POWER"
+  "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
+   [(set_attr "length" "12")])
+
+(define_insn ""
+  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
 	(compare:CC
-	 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			  (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
+	 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
+		(match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
 	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
-  "TARGET_32BIT"
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(ge:SI (match_dup 1) (match_dup 2)))
+   (clobber (match_scratch:SI 3 "=r,r"))]
+  "TARGET_POWER"
   "@
-   {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
-   {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
-   #
+   doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
    #"
   [(set_attr "type" "compare")
-   (set_attr "length" "12,12,16,16")])
+   (set_attr "length" "12,16")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
 	(compare:CC
-	 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			  (match_operand:SI 2 "reg_or_neg_short_operand" ""))
-		  (match_operand:SI 3 "gpc_reg_operand" ""))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_32BIT && reload_completed"
-  [(set (match_dup 4)
-	(plus:SI (ltu:SI (match_dup 1) (match_dup 2))
-		 (match_dup 3)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 4)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			  (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
-	(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "TARGET_32BIT"
-  "@
-   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
-   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
-   #
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,12,16,16")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			  (match_operand:SI 2 "reg_or_neg_short_operand" ""))
-		  (match_operand:SI 3 "gpc_reg_operand" ""))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "TARGET_32BIT && reload_completed"
-  [(set (match_dup 0)
-	(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
-  "TARGET_32BIT"
-  "@
-   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
-   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
-  [(set_attr "type" "two")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			(match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))]
-  "TARGET_64BIT"
-  "@
-   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
-   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
-  [(set_attr "type" "two")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-	       (match_operand:SI 2 "reg_or_short_operand" "rI")))
-   (clobber (match_scratch:SI 3 "=r"))]
-  "TARGET_POWER"
-  "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
-   [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		(match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ge:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  "TARGET_POWER"
-  "@
-   doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		(match_operand:SI 2 "reg_or_short_operand" ""))
+	 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
+		(match_operand:SI 2 "reg_or_short_operand" ""))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(ge:SI (match_dup 1) (match_dup 2)))
@@ -12360,37 +12854,26 @@
   "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
   [(set_attr "length" "12")])
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
-  "TARGET_32BIT"
+(define_insn "*geu<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
+	(geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
+	       (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
+  ""
   "@
    {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
    {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
   [(set_attr "type" "three")
    (set_attr "length" "12")])
 
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-		(match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
-  "TARGET_64BIT"
-  "@
-   subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
-   addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
-  [(set_attr "type" "three")
-   (set_attr "length" "12")])
-
-(define_insn ""
+(define_insn "*geu<mode>_compare"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
 	(compare:CC
-	 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-		 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
+	 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
+		(match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(geu:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_32BIT"
+   (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
+	(geu:P (match_dup 1) (match_dup 2)))]
+  ""
   "@
    {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
    {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
@@ -12402,58 +12885,25 @@
 (define_split
   [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
 	(compare:CC
-	 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
+	 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
+		(match_operand:P 2 "reg_or_neg_short_operand" ""))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(geu:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_32BIT && reload_completed"
-  [(set (match_dup 0)
-	(geu:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
-		 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
-	 (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
-	(geu:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_64BIT"
-  "@
-   subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
-   addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
-   #
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,12,16,16")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
-		 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
-	 (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(geu:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_64BIT && reload_completed"
+   (set (match_operand:P 0 "gpc_reg_operand" "")
+	(geu:P (match_dup 1) (match_dup 2)))]
+  "reload_completed"
   [(set (match_dup 0)
-	(geu:DI (match_dup 1) (match_dup 2)))
+	(geu:P (match_dup 1) (match_dup 2)))
    (set (match_dup 3)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
   "")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
-	(plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
-  "TARGET_32BIT"
+(define_insn "*plus_geu<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
+	(plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
+		       (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
+		(match_operand:P 3 "gpc_reg_operand" "r,r")))]
+  ""
   "@
    {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
    {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
@@ -12529,24 +12979,24 @@
 		    (const_int 0)))]
   "")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			(match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
-  "TARGET_32BIT"
+(define_insn "*neg_geu<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
+	(neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
+		      (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
+  ""
   "@
    {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
    {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
   [(set_attr "type" "three")
    (set_attr "length" "12")])
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
-	(and:SI (neg:SI
-		 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
-		(match_operand:SI 3 "gpc_reg_operand" "r,r")))]
-  "TARGET_32BIT"
+(define_insn "*and_neg_geu<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
+	(and:P (neg:P
+		 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
+			(match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
+		(match_operand:P 3 "gpc_reg_operand" "r,r")))]
+  ""
   "@
    {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
    {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
@@ -12629,86 +13079,6 @@
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-	       (const_int 0)))]
-  "TARGET_32BIT"
-  "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
-  [(set_attr "type" "three")
-   (set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-	       (const_int 0)))]
-  "TARGET_64BIT"
-  "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
-  [(set_attr "type" "three")
-   (set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		(const_int 0))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(gt:SI (match_dup 1) (const_int 0)))]
-  "TARGET_32BIT"
-  "@
-   {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "12,16")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		(const_int 0))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(gt:SI (match_dup 1) (const_int 0)))]
-  "TARGET_32BIT && reload_completed"
-  [(set (match_dup 0)
-	(gt:SI (match_dup 1) (const_int 0)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-		(const_int 0))
-	 (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(gt:DI (match_dup 1) (const_int 0)))]
-  "TARGET_64BIT"
-  "@
-   subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "12,16")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
-		(const_int 0))
-	 (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(gt:DI (match_dup 1) (const_int 0)))]
-  "TARGET_64BIT && reload_completed"
-  [(set (match_dup 0)
-	(gt:DI (match_dup 1) (const_int 0)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 	       (match_operand:SI 2 "reg_or_short_operand" "r")))]
   "TARGET_POWER"
   "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
@@ -12745,27 +13115,17 @@
 		    (const_int 0)))]
   "")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
-	(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			(const_int 0))
-		 (match_operand:SI 2 "gpc_reg_operand" "r")))]
-  "TARGET_32BIT"
+(define_insn "*plus_gt0<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
+	(plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
+		      (const_int 0))
+		 (match_operand:P 2 "gpc_reg_operand" "r")))]
+  ""
   "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
   [(set_attr "type" "three")
    (set_attr "length" "12")])
 
 (define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
-	(plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-			(const_int 0))
-		 (match_operand:DI 2 "gpc_reg_operand" "r")))]
-  "TARGET_64BIT"
-  "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
-  [(set_attr "type" "three")
-   (set_attr "length" "12")])
-
-(define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
 	(compare:CC
 	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
@@ -12971,292 +13331,79 @@
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		       (const_int 0))))]
-  "TARGET_32BIT"
-  "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
-  [(set_attr "type" "three")
-   (set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-		       (const_int 0))))]
-  "TARGET_64BIT"
-  "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
-  [(set_attr "type" "three")
-   (set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (match_operand:SI 2 "reg_or_short_operand" "r"))))]
   "TARGET_POWER"
   "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
   [(set_attr "length" "12")])
 
-(define_insn_and_split ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-        (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-                (match_operand:SI 2 "reg_or_short_operand" "rI")))]
-  "TARGET_32BIT"
-  "#"
-  "TARGET_32BIT"
-  [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
-   (set (match_dup 0) (neg:SI (match_dup 0)))]
-  "")
-
-(define_insn_and_split ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-        (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-                (match_operand:DI 2 "reg_or_short_operand" "rI")))]
-  "TARGET_64BIT"
+(define_insn_and_split "*gtu<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
+	(gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
+	       (match_operand:P 2 "reg_or_short_operand" "rI")))]
+  ""
   "#"
-  "TARGET_64BIT"
-  [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
-   (set (match_dup 0) (neg:DI (match_dup 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(gtu:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_32BIT"
-  "@
-   {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		 (match_operand:SI 2 "reg_or_short_operand" ""))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(gtu:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_32BIT && reload_completed"
-  [(set (match_dup 0)
-	(gtu:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
+  ""
+  [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
+   (set (match_dup 0) (neg:P (match_dup 0)))]
   "")
 
-(define_insn ""
+(define_insn_and_split "*gtu<mode>_compare"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
 	(compare:CC
-	 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-		 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
+	 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
+		 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
 	 (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(gtu:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_64BIT"
-  "@
-   subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
-		 (match_operand:DI 2 "reg_or_short_operand" ""))
-	 (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(gtu:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_64BIT && reload_completed"
-  [(set (match_dup 0)
-	(gtu:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn_and_split ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
-        (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-                         (match_operand:SI 2 "reg_or_short_operand" "rI"))
-                 (match_operand:SI 3 "reg_or_short_operand" "rI")))]
-  "TARGET_32BIT"
+   (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
+	(gtu:P (match_dup 1) (match_dup 2)))]
+  ""
   "#"
-  "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
-  [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
-   (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
+  ""
+  [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
+   (parallel [(set (match_dup 3)
+		   (compare:CC (neg:P (match_dup 0)) (const_int 0)))
+	      (set (match_dup 0) (neg:P (match_dup 0)))])]
   "")
 
-(define_insn_and_split ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
-        (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-                         (match_operand:DI 2 "reg_or_short_operand" "rI"))
-                 (match_operand:DI 3 "reg_or_short_operand" "rI")))]
-  "TARGET_64BIT"
+(define_insn_and_split "*plus_gtu<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
+        (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
+		       (match_operand:P 2 "reg_or_short_operand" "rI"))
+		(match_operand:P 3 "reg_or_short_operand" "rI")))]
+  ""
   "#"
   "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
-  [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
-   (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
+  [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
+   (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
   "")
 
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			  (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
-  "TARGET_32BIT"
-  "@
-   {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
-   {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
-   #
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12,12,16")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			  (match_operand:SI 2 "reg_or_short_operand" ""))
-		  (match_operand:SI 3 "gpc_reg_operand" ""))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_32BIT && reload_completed"
-  [(set (match_dup 4)
-	(plus:SI (gtu:SI (match_dup 1) (match_dup 2))
-		 (match_dup 3)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 4)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
-			  (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
-		  (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
-  "TARGET_64BIT"
-  "@
-   addic %4,%1,%k2\;addze. %4,%3
-   subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3
-   #
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12,12,16")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			  (match_operand:DI 2 "reg_or_short_operand" ""))
-		  (match_operand:DI 3 "gpc_reg_operand" ""))
-	 (const_int 0)))
-   (clobber (match_scratch:DI 4 ""))]
-  "TARGET_64BIT && reload_completed"
-  [(set (match_dup 4)
-	(plus:DI (gtu:DI (match_dup 1) (match_dup 2))
-		  (match_dup 3)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 4)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			  (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
-	(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "TARGET_32BIT"
-  "@
-   {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
-   {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
-   #
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12,12,16")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			  (match_operand:SI 2 "reg_or_short_operand" ""))
-		  (match_operand:SI 3 "gpc_reg_operand" ""))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "TARGET_32BIT && reload_completed"
-  [(set (match_dup 0)
-	(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
+(define_insn_and_split "*plus_gtu<mode>_compare"
   [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
 	(compare:CC
-	 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
-			  (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
-		  (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
-	 (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
-	(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "TARGET_64BIT"
-  "@
-   addic %0,%1,%k2\;addze. %0,%3
-   subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3
-   #
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12,12,16")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			  (match_operand:DI 2 "reg_or_short_operand" ""))
-		  (match_operand:DI 3 "gpc_reg_operand" ""))
+	 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
+			(match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
+		 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
 	 (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "TARGET_64BIT && reload_completed"
-  [(set (match_dup 0)
-	(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
+   (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
+	(plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
+  ""
+  "#"
+  "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
+  [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
+   (parallel [(set (match_dup 4)
+		   (compare:CC (minus:P (match_dup 3) (match_dup 0))
+			       (const_int 0)))
+	      (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
   "")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
-  "TARGET_32BIT"
+(define_insn "*neg_gtu<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
+	(neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
+		      (match_operand:P 2 "reg_or_short_operand" "rI"))))]
+  ""
   "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
   [(set_attr "type" "two")
    (set_attr "length" "8")])
 
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-			(match_operand:DI 2 "reg_or_short_operand" "rI"))))]
-  "TARGET_64BIT"
-  "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
-  [(set_attr "type" "two")
-   (set_attr "length" "8")])
 
 ;; Define both directions of branch and return.  If we need a reload
 ;; register, we'd rather use CR0 since it is much easier to copy a
@@ -13290,7 +13437,7 @@
 {
   return output_cbranch (operands[0], NULL, 0, insn);
 }"
-  [(set_attr "type" "branch")
+  [(set_attr "type" "jmpreg")
    (set_attr "length" "4")])
 
 (define_insn ""
@@ -13321,7 +13468,7 @@
 {
   return output_cbranch (operands[0], NULL, 1, insn);
 }"
-  [(set_attr "type" "branch")
+  [(set_attr "type" "jmpreg")
    (set_attr "length" "4")])
 
 ;; Logic on condition register values.
@@ -13505,7 +13652,7 @@
   operands[4] = gen_reg_rtx (DImode);
 }")
 
-(define_insn ""
+(define_insn "*tablejump<mode>_internal1"
   [(set (pc)
 	(match_operand:P 0 "register_operand" "c,*l"))
    (use (label_ref (match_operand 1 "" "")))]
@@ -13792,7 +13939,8 @@
 		   [(set (match_operand:SI 1 "memory_operand" "=m")
        			 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
   "TARGET_MULTIPLE"
-  "{stm|stmw} %2,%1")
+  "{stm|stmw} %2,%1"
+  [(set_attr "type" "store_ux")])
 
 (define_insn "*save_fpregs_<mode>"
   [(match_parallel 0 "any_parallel_operand"
@@ -13867,14 +14015,15 @@
 
 ; The load-multiple instructions have similar properties.
 ; Note that "load_multiple" is a name known to the machine-independent
-; code that actually corresponds to the powerpc load-string.
+; code that actually corresponds to the PowerPC load-string.
 
 (define_insn "*lmw"
   [(match_parallel 0 "lmw_operation"
 		   [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
        			 (match_operand:SI 2 "memory_operand" "m"))])]
   "TARGET_MULTIPLE"
-  "{lm|lmw} %1,%2")
+  "{lm|lmw} %1,%2"
+  [(set_attr "type" "load_ux")])
 
 (define_insn "*return_internal_<mode>"
   [(return)
@@ -13929,7 +14078,7 @@
 }")
 
 (define_insn "prefetch"
-  [(prefetch (match_operand:V4SI 0 "address_operand" "p")
+  [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
 	     (match_operand:SI 1 "const_int_operand" "n")
 	     (match_operand:SI 2 "const_int_operand" "n"))]
   "TARGET_POWERPC"