X-Git-Url: http://git.sourceforge.jp/view?p=pf3gnuchains%2Fgcc-fork.git;a=blobdiff_plain;f=gcc%2Fconfig%2Fm32c%2Fm32c.h;h=78e3115c291efdf9b8f7674747e82de02d9f08c9;hp=1b1d357c2b78f7b95ba2b380de7964941b531e19;hb=181dd1c5a49707a7901562f374fecf94973cadcf;hpb=c238c203159902905b6de2d47c004cfbf7d0f297 diff --git a/gcc/config/m32c/m32c.h b/gcc/config/m32c/m32c.h index 1b1d357c2b7..78e3115c291 100644 --- a/gcc/config/m32c/m32c.h +++ b/gcc/config/m32c/m32c.h @@ -1,5 +1,5 @@ /* Target Definitions for R8C/M16C/M32C - Copyright (C) 2005 + Copyright (C) 2005, 2007, 2008, 2009 Free Software Foundation, Inc. Contributed by Red Hat. @@ -7,7 +7,7 @@ GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 2, or (at your + by the Free Software Foundation; either version 3, or (at your option) any later version. GCC is distributed in the hope that it will be useful, but WITHOUT @@ -16,9 +16,8 @@ License for more details. You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING. If not, write to the Free - Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA - 02110-1301, USA. */ + along with GCC; see the file COPYING3. If not see + . */ #ifndef GCC_M32C_H #define GCC_M32C_H @@ -29,9 +28,9 @@ #define STARTFILE_SPEC "crt0.o%s crtbegin.o%s" /* There are four CPU series we support, but they basically break down - into two families - the R8C/M16C families, with 16 bit address - registers and one set of opcodes, and the M32CM/M32C group, with 24 - bit address registers and a different set of opcodes. The + into two families - the R8C/M16C families, with 16-bit address + registers and one set of opcodes, and the M32CM/M32C group, with + 24-bit address registers and a different set of opcodes. The assembler doesn't care except for which opcode set is needed; the big difference is in the memory maps, which we cover in LIB_SPEC. */ @@ -49,12 +48,12 @@ thing when no CPU is specified, which defaults to R8C. */ #undef LIB_SPEC #define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \ -%{msim*:%{!T*: %{mcpu=m32cm:-Tsim24.ld}%{mcpu=m32c:-Tsim24.ld} \ - %{!mcpu=m32cm:%{!mcpu=m32c:-Tsim16.ld}}}} \ -%{!T*:%{!msim*: %{mcpu=m16c:-Tm16c.ld} \ - %{mcpu=m32cm:-Tm32cm.ld} \ - %{mcpu=m32c:-Tm32c.ld} \ - %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:-Tr8c.ld}}}}} \ +%{msim*:%{!T*: %{mcpu=m32cm:%Tsim24.ld}%{mcpu=m32c:%Tsim24.ld} \ + %{!mcpu=m32cm:%{!mcpu=m32c:%Tsim16.ld}}}} \ +%{!T*:%{!msim*: %{mcpu=m16c:%Tm16c.ld} \ + %{mcpu=m32cm:%Tm32cm.ld} \ + %{mcpu=m32c:%Tm32c.ld} \ + %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:%Tr8c.ld}}}}} \ " /* Run-time Target Specification */ @@ -97,11 +96,11 @@ extern int target_memregs; #define TARGET_VERSION fprintf (stderr, " (m32c)"); -#define OVERRIDE_OPTIONS m32c_override_options (); +#define OVERRIDE_OPTIONS m32c_override_options () /* Defining data structures for per-function information */ -typedef struct machine_function GTY (()) +typedef struct GTY (()) machine_function { /* How much we adjust the stack when returning from an exception handler. */ @@ -139,22 +138,38 @@ machine_function; GCC expects us to have a "native" format, so we pick the one that matches "int". Pointers are 16 bits for R8C/M16C (when TARGET_A16 is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but - 24 bit pointers are stored in 32 bit words. */ + 24-bit pointers are stored in 32-bit words. */ #define BITS_PER_UNIT 8 #define UNITS_PER_WORD 2 #define POINTER_SIZE (TARGET_A16 ? 16 : 32) #define POINTERS_EXTEND_UNSIGNED 1 +/* We have a problem with libgcc2. It only defines two versions of + each function, one for "int" and one for "long long". Ie it assumes + that "sizeof (int) == sizeof (long)". For the M32C this is not true + and we need a third set of functions. We explicitly define + LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting + to get the SI and DI versions from the libgcc2.c sources, and we + provide our own set of HI functions in m32c-lib2.c, which is why this + definition is surrounded by #ifndef..#endif. */ +#ifndef LIBGCC2_UNITS_PER_WORD +#define LIBGCC2_UNITS_PER_WORD 4 +#endif /* These match the alignment enforced by the two types of stack operations. */ #define PARM_BOUNDARY (TARGET_A16 ? 8 : 16) #define STACK_BOUNDARY (TARGET_A16 ? 8 : 16) /* We do this because we care more about space than about speed. For - the chips with 16 bit busses, we could set these to 16 if + the chips with 16-bit busses, we could set these to 16 if desired. */ #define FUNCTION_BOUNDARY 8 #define BIGGEST_ALIGNMENT 8 +/* Since we have a maximum structure alignment of 8 there + is no need to enforce any alignment of bitfield types. */ +#undef PCC_BITFIELD_TYPE_MATTERS +#define PCC_BITFIELD_TYPE_MATTERS 0 + #define STRICT_ALIGNMENT 0 #define SLOW_BYTE_ACCESS 1 @@ -174,15 +189,18 @@ machine_function; #undef PTRDIFF_TYPE #define PTRDIFF_TYPE (TARGET_A16 ? "int" : "long int") +#undef UINTPTR_TYPE +#define UINTPTR_TYPE (TARGET_A16 ? "unsigned int" : "long unsigned int") + /* REGISTER USAGE */ /* Register Basics */ /* Register layout: - [r0h][r0l] $r0 (16 bits, or two 8 bit halves) + [r0h][r0l] $r0 (16 bits, or two 8-bit halves) [--------] $r2 (16 bits) - [r1h][r1l] $r1 (16 bits, or two 8 bit halves) + [r1h][r1l] $r1 (16 bits, or two 8-bit halves) [--------] $r3 (16 bits) [---][--------] $a0 (might be 24 bits) [---][--------] $a1 (might be 24 bits) @@ -225,7 +243,7 @@ machine_function; #define REG_ALLOC_ORDER { \ 0, 1, 2, 3, 4, 5, /* r0..r3, a0, a1 */ \ - 12, 13, 14, 15, 16, 17, 18, /* mem0..mem7 */ \ + 12, 13, 14, 15, 16, 17, 18, 19, /* mem0..mem7 */ \ 6, 7, 8, 9, 10, 11 /* sb, fb, sp, pc, flg, ap */ } /* How Values Fit in Registers */ @@ -259,6 +277,7 @@ machine_function; { 0x00000002 }, /* R2 - r2 */\ { 0x00000008 }, /* R3 - r3 */\ { 0x00000003 }, /* R02 - r0r2 */\ + { 0x0000000c }, /* R13 - r1r3 */\ { 0x00000005 }, /* HL - r0 r1 */\ { 0x00000005 }, /* QI - r0 r1 */\ { 0x0000000a }, /* R23 - r2 r3 */\ @@ -271,6 +290,7 @@ machine_function; { 0x000001f0 }, /* PS - a0 a1 sb fp sp */\ { 0x0000000f }, /* SI - r0r2 r1r3 a0a1 */\ { 0x0000003f }, /* HI - r0 r1 r2 r3 a0 a1 */\ + { 0x00000033 }, /* R02A - r0r2 a0 a1 */ \ { 0x0000003f }, /* RA - r0..r3 a0 a1 */\ { 0x0000007f }, /* GENERAL */\ { 0x00000400 }, /* FLG */\ @@ -297,6 +317,7 @@ enum reg_class R2_REGS, R3_REGS, R02_REGS, + R13_REGS, HL_REGS, QI_REGS, R23_REGS, @@ -309,6 +330,7 @@ enum reg_class PS_REGS, SI_REGS, HI_REGS, + R02A_REGS, RA_REGS, GENERAL_REGS, FLG_REGS, @@ -337,6 +359,7 @@ enum reg_class "R2_REGS", \ "R3_REGS", \ "R02_REGS", \ +"R13_REGS", \ "HL_REGS", \ "QI_REGS", \ "R23_REGS", \ @@ -349,6 +372,7 @@ enum reg_class "PS_REGS", \ "SI_REGS", \ "HI_REGS", \ +"R02A_REGS", \ "RA_REGS", \ "GENERAL_REGS", \ "FLG_REGS", \ @@ -459,19 +483,19 @@ enum reg_class #define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N) #define DBX_REGISTER_NUMBER(N) m32c_dwarf_frame_regnum (N) -/* Eliminating Frame Pointer and Arg Pointer */ +#undef ASM_PREFERRED_EH_DATA_FORMAT +/* This is the same as the default in practice, except that by making + it explicit we tell binutils what size pointers to use. */ +#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ + (TARGET_A16 ? DW_EH_PE_udata2 : DW_EH_PE_udata4) -/* If the frame pointer isn't used, we detect it manually. But the - stack pointer doesn't have as flexible addressing as the frame - pointer, so we always assume we have it. */ -#define FRAME_POINTER_REQUIRED 1 +/* Eliminating Frame Pointer and Arg Pointer */ #define ELIMINABLE_REGS \ {{AP_REGNO, SP_REGNO}, \ {AP_REGNO, FB_REGNO}, \ {FB_REGNO, SP_REGNO}} -#define CAN_ELIMINATE(FROM,TO) 1 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \ (VAR) = m32c_initial_elimination_offset(FROM,TO) @@ -509,10 +533,7 @@ typedef struct m32c_cumulative_args /* How Scalar Function Values Are Returned */ -#define FUNCTION_VALUE(VT,F) m32c_function_value (VT, F) -#define LIBCALL_VALUE(MODE) m32c_libcall_value (MODE) - -#define FUNCTION_VALUE_REGNO_P(r) ((r) == R0_REGNO || (r) == MEM0_REGNO) +#define FUNCTION_VALUE_REGNO_P(r) m32c_function_value_regno_p (r) /* How Large Values Are Returned */ @@ -534,13 +555,11 @@ typedef struct m32c_cumulative_args #define TRAMPOLINE_SIZE m32c_trampoline_size () #define TRAMPOLINE_ALIGNMENT m32c_trampoline_alignment () -#define INITIALIZE_TRAMPOLINE(a,fn,sc) m32c_initialize_trampoline (a, fn, sc) /* Addressing Modes */ #define HAVE_PRE_DECREMENT 1 #define HAVE_POST_INCREMENT 1 -#define CONSTANT_ADDRESS_P(X) CONSTANT_P(X) #define MAX_REGS_PER_ADDRESS 1 /* This is passed to the macros below, so that they can be implemented @@ -551,26 +570,14 @@ typedef struct m32c_cumulative_args #define REG_OK_STRICT_V 0 #endif -#define GO_IF_LEGITIMATE_ADDRESS(MODE,X,LABEL) \ - if (m32c_legitimate_address_p (MODE, X, REG_OK_STRICT_V)) \ - goto LABEL; - #define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V) #define REG_OK_FOR_INDEX_P(X) 0 /* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */ -#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ - if (m32c_legitimize_address(&(X),OLDX,MODE)) \ - goto win; - #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ if (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \ - goto win; - -#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ - if (m32c_mode_dependent_address (ADDR)) \ - goto LABEL; + goto WIN; #define LEGITIMATE_CONSTANT_P(X) m32c_legitimate_constant_p (X) @@ -667,7 +674,7 @@ typedef struct m32c_cumulative_args #define STORE_FLAG_VALUE 1 -/* 16 or 24 bit pointers */ +/* 16- or 24-bit pointers */ #define Pmode (TARGET_A16 ? HImode : PSImode) #define FUNCTION_MODE QImode