X-Git-Url: http://git.sourceforge.jp/view?p=pf3gnuchains%2Fgcc-fork.git;a=blobdiff_plain;f=gcc%2Fconfig%2F1750a%2F1750a.md;h=1ebd02e213fff4c6ea6167173945a76faa71dd08;hp=e2d4f2644c69311ee950bb0b251c277f0176e18c;hb=f380450bdceb4c8294e2d54b4925645385935520;hpb=ba986dfc6937ada0c47951b06010726a02e00d00 diff --git a/gcc/config/1750a/1750a.md b/gcc/config/1750a/1750a.md index e2d4f2644c6..1ebd02e213f 100644 --- a/gcc/config/1750a/1750a.md +++ b/gcc/config/1750a/1750a.md @@ -1,13 +1,14 @@ ;;- Machine description for GNU compiler ;;- MIL-STD-1750A version. -;; Copyright (C) 1994, 1995 Free Software Foundation, Inc. -;; Contributed by O.M.Kellogg, DASA (kellogg@space.otn.dasa.de). +;; Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, +;; 2000 Free Software Foundation, Inc. +;; Contributed by O.M.Kellogg, DASA (oliver.kellogg@space.otn.dasa.de). ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by -;; the Free Software Foundation; either version 1, or (at your option) +;; the Free Software Foundation; either version 2, or (at your option) ;; any later version. ;; GNU CC is distributed in the hope that it will be useful, @@ -55,49 +56,25 @@ [(set (match_operand:QI 0 "push_operand" "=<") (match_operand:QI 1 "general_operand" "r"))] "" - "pshm r%1,r%1 ; stackptr = R%0") + "pshm r%1,r%1") (define_insn "" [(set (match_operand:HI 0 "push_operand" "=<") (match_operand:HI 1 "general_operand" "r"))] "" - "* - { - rtx new_operands[3]; - new_operands[2] = operands[0]; - new_operands[0] = operands[1]; - new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1); - output_asm_insn(\"pshm r%0,r%1 ; stackptr = r%2\",new_operands); - return \";\"; - } ") + "pshm r%1,r%d1") (define_insn "" [(set (match_operand:HF 0 "push_operand" "=<") (match_operand:HF 1 "general_operand" "r"))] "" - "* - { - rtx new_operands[3]; - new_operands[2] = operands[0]; - new_operands[0] = operands[1]; - new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1); - output_asm_insn(\"pshm r%0,r%1 ; stackptr = r%2\",new_operands); - return \";\"; - } ") + "pshm r%1,r%d1") (define_insn "" [(set (match_operand:TQF 0 "push_operand" "=<") (match_operand:TQF 1 "general_operand" "r"))] "" - "* - { - rtx new_operands[3]; - new_operands[2] = operands[0]; - new_operands[0] = operands[1]; - new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+2); - output_asm_insn(\"pshm r%0,r%1 ; stackptr = r%2\",new_operands); - return \";\"; - } ") + "pshm r%1,r%t1") ;; stackpop (define_insn "" @@ -110,43 +87,22 @@ [(set (match_operand:HI 0 "general_operand" "=r") (match_operand:HI 1 "push_operand" ">"))] "" - "* - { - rtx new_operands[2]; - new_operands[0] = operands[0]; - new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1); - output_asm_insn(\"popm r%0,r%1\",new_operands); - return \";\"; - } ") + "popm r%1,r%d1") (define_insn "" [(set (match_operand:HF 0 "general_operand" "=r") (match_operand:HF 1 "push_operand" ">"))] "" - "* - { - rtx new_operands[2]; - new_operands[0] = operands[0]; - new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1); - output_asm_insn(\"popm r%0,r%1\",new_operands); - return \";\"; - } ") - + "popm r%1,r%d1") + (define_insn "" [(set (match_operand:TQF 0 "general_operand" "=r") (match_operand:TQF 1 "push_operand" ">"))] "" - "* - { - rtx new_operands[2]; - new_operands[0] = operands[0]; - new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+2); - output_asm_insn(\"popm r%0,r%1\",new_operands); - return \";\"; - } ") + "popm r%1,r%t1") -;; Test operations. These shouldn't really occur for 1750: -;; all important instructions set the cc's (see NOTICE_UPDATE_CC) + +;; Test operations. (define_insn "tstqi" [(set (cc0) @@ -160,35 +116,42 @@ "" "dlr r%0,r%0 ; from tsthi") +; With 1750A floats, testing the most significant word suffices. + (define_insn "tsthf" [(set (cc0) (match_operand:HF 0 "register_operand" "r"))] "" - "dlr r%0,r%0 ; from tsthf") + "lr r%0,r%0 ; tsthf") -;; This one is happy with "roughly zero" :-) (should be improved) (define_insn "tsttqf" [(set (cc0) (match_operand:TQF 0 "register_operand" "r"))] "" - "dlr r%0,r%0 ; from tsttqf") + "lr r%0,r%0 ; tsttqf") ;; block move. -; there is a problem with this insn in gcc-2.2.3 -; (clobber (match_dup 2)) does not prevent use of this operand later -; (define_insn "movstrqi" - [(set (mem:BLK (match_operand:QI 0 "register_operand" "r")) - (mem:BLK (match_operand:QI 1 "register_operand" "r"))) - (use (match_operand:QI 2 "register_operand" "r")) - (use (match_operand:QI 3 "immediate_operand" "")) + [(set (match_operand:BLK 0 "mov_memory_operand" "=m") + (match_operand:BLK 1 "mov_memory_operand" "m")) + (use (match_operand:QI 2 "general_operand" "r")) + (match_operand 3 "" "") (clobber (match_dup 0)) (clobber (match_dup 1)) (clobber (match_dup 2))] "" - "* return (char *)movcnt_regno_adjust(operands); ") + "* + { + rtx regops[3]; + + regops[0] = XEXP (operands[0], 0); + regops[1] = XEXP (operands[1], 0); + regops[2] = operands[2]; + + return movcnt_regno_adjust (regops); + } ") ;; compare instructions. @@ -211,6 +174,8 @@ return \"ucr.m %0,%1\"; case 4: return \"uc.m %0,%1\"; + default: + abort(); } else switch (which_alternative) @@ -225,6 +190,8 @@ return \"cr r%0,r%1\"; case 4: return \"c r%0,%1\"; + default: + abort(); } } ") @@ -233,18 +200,29 @@ (compare (match_operand:HI 0 "general_operand" "r,r") (match_operand:HI 1 "general_operand" "r,m")))] "" - "@ - dcr r%0,r%1 - dc r%0,%1 ") + "* + { + if (next_cc_user_is_unsigned (insn)) + { + if (which_alternative == 0) + return \"ducr.m %0,%1\"; + return \"duc.m %0,%1\"; + } + else + { + if (which_alternative == 0) + return \"dcr r%0,r%1\"; + return \"dc r%0,%1\"; + } + } ") (define_insn "cmphf" [(set (cc0) - (compare (match_operand:HF 0 "general_operand" "r,z,r") - (match_operand:HF 1 "general_operand" "r,Q,m")))] + (compare (match_operand:HF 0 "general_operand" "r,r") + (match_operand:HF 1 "general_operand" "r,m")))] "" "@ fcr r%0,r%1 - fcb %Q1 fc r%0,%1 ") (define_insn "cmptqf" @@ -262,55 +240,29 @@ (define_insn "trunchiqi2" [(set (match_operand:QI 0 "register_operand" "=r") - (truncate:QI - (match_operand:HI 1 "register_operand" "r")))] + (truncate:QI (match_operand:HI 1 "register_operand" "r")))] "" - "* - { - rtx new_operands[2]; - new_operands[0] = operands[0]; - new_operands[1] = gen_rtx (REG, HImode, REGNO(operands[1]) + 1); - output_asm_insn(\"lr r%0,r%1 ;trunchiqi2\",new_operands); - return \";\"; - } ") + "lr r%0,r%d1") -;; zero extension instructions -(define_insn "zero_extendqihi2" - [(set (match_operand:HI 0 "register_operand" "=r,r,r") - (zero_extend:HI (match_operand:QI 1 "general_operand" "r,m,i")))] - "" - "* - { - rtx new_opnds[2]; - output_asm_insn(\"xorr r%0,r%0 ;zero_extendqihi2\",operands); - new_opnds[0] = gen_rtx (REG, HImode, REGNO(operands[0]) + 1); - new_opnds[1] = operands[1]; - switch (which_alternative) - { - case 0: - output_asm_insn(\"lr r%0,r%1\",new_opnds); - break; - case 1: - output_asm_insn(\"l r%0,%1\",new_opnds); - break; - case 2: - output_asm_insn(\"lim r%0,%1\",new_opnds); - break; - } - return \";\"; - } ") +;; zero extension instructions: not defined, GCC can synthesize ;; sign extension instructions (define_insn "extendqihi2" - [(set (match_operand:HI 0 "register_operand" "=r,r,r") - (sign_extend:HI (match_operand:QI 1 "general_operand" "r,m,i")) )] + [(set (match_operand:HI 0 "register_operand" "=r,r") + (sign_extend:HI (match_operand:QI 1 "general_operand" "r,m")) )] "" - "@ - lr r%0,r%1 ;extendqihi2\;dsra r%0,16 - l r%0,%1 ;extendqihi2\;dsra r%0,16 - lim r%0,%1 ;extendqihi2\;dsra r%0,16 ") + "* + if (which_alternative == 0) + { + if (REGNO (operands [0]) != REGNO (operands [1])) + output_asm_insn (\"lr r%0,r%1\", operands); + } + else + output_asm_insn (\"l r%0,%1\", operands); + return \"dsra r%0,16 ;extendqihi2\"; + ") ;; Conversions between float and double. @@ -321,16 +273,17 @@ (float_extend:TQF (match_operand:HF 1 "general_operand" "r,m")))] "" "* + output_asm_insn(\"xorr r%t0,r%t0 ;extendhftqf2\", operands); + if (which_alternative == 0) { - rtx new_opnds[2]; - new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0]) + 2); - new_opnds[1] = operands[1]; - output_asm_insn(\"xorr r%0,r%0 ;extendhftqf2\",new_opnds); - if (which_alternative == 0) - return \"dlr r%0,r%1 ; put condition codes back on track\"; + if (REGNO (operands[1]) != REGNO (operands[0])) + return \"dlr r%0,r%1\"; else - return \"dl r%0,%1 ; put condition codes back on track\"; - } ") + return \";\"; + } + else + return \"dl r%0,%1\"; + ") ; 1750 TQF-to-HF truncate is a no-op: just leave away the least signif. 16 bits (define_insn "trunctqfhf2" @@ -381,112 +334,120 @@ ;; 16-bit moves +; memory indirect to reg +(define_insn "" + [(set (match_operand:QI 0 "register_operand" "=r") + (mem:QI (match_operand 1 "memory_operand" "m")))] + "" + "li r%0,%1") + +; reg/const to memory indirect +(define_insn "" + [(set (mem:QI (match_operand 0 "memory_operand" "=m,m")) + (match_operand:QI 1 "nonmemory_operand" "r,K"))] + "" + "@ + sti r%1,%0 + stci %1,%0") + +; general case (define_insn "movqi" - [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,t,r,Q,m,m") - (match_operand:QI 1 "general_operand" "O,I,J,M,i,r,Q,m,t,r,K"))] + [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,m,m") + (match_operand:QI 1 "general_operand" "O,I,J,i,r,m,r,K"))] "" "@ xorr r%0,r%0 lisp r%0,%1 lisn r%0,%J1 - lim r%0,%1 ; 'M' constraint - lim r%0,%1 ; 'i' constraint + lim r%0,%1 lr r%0,r%1 - lb %Q1 l r%0,%1 - stb %Q0 st r%1,%0 stc %1,%0 ") ;; 32-bit moves -; Set HIreg to constant +; memory indirect to reg (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") - (match_operand:HI 1 "immediate_operand" "i"))] + (mem:HI (match_operand 1 "memory_operand" "m")))] "" - "* - { - rtx new_opnds[2]; - int val = INTVAL(operands[1]); - if (val >= 0) - { - if (val <= 65535) - { - new_opnds[0] = gen_rtx(REG,QImode,REGNO(operands[0])); - new_opnds[1] = operands[1]; - output_asm_insn(\"xorr r%0,r%0 ;movhi cst->reg\",new_opnds); - REGNO(new_opnds[0]) += 1; - if (val == 0) - output_asm_insn(\"xorr r%0,r%0\",new_opnds); - else if (val <= 16) - output_asm_insn(\"lisp r%0,%1\",new_opnds); - else - output_asm_insn(\"lim r%0,%1\",new_opnds); - return \";\"; - } - } - else if (val >= -16) - return \"lisn r%0,%J1\;dsra r%0,16 ;movhi cst\"; - new_opnds[0] = gen_rtx(REG, QImode, REGNO(operands[0])); - new_opnds[1] = gen_rtx(CONST_INT,VOIDmode,(INTVAL(operands[1])) >> 16); - output_asm_insn(\"lim r%0,%1 ;movhi cst->reg\",new_opnds); - INTVAL(new_opnds[1]) = val & 0xFFFF; - REGNO(new_opnds[0]) += 1; - output_asm_insn(\"lim r%0,%1\",new_opnds); - return \";\"; - } - ") + "dli r%0,%1") + +; reg to memory indirect +(define_insn "" + [(set (mem:HI (match_operand 0 "memory_operand" "=m")) + (match_operand:HI 1 "register_operand" "r"))] + "" + "dsti r%1,%0") -(define_insn "movhi" - [(set (match_operand:HI 0 "general_operand" "=r,z,r,Q,m") - (match_operand:HI 1 "general_operand" "r,Q,m,z,r"))] +; general case +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=r,r,r,r,r,m,m") + (match_operand:HI 1 "general_operand" "O,I,J,r,m,r,K"))] "" "@ + xorr r%0,r%0\;xorr r%d0,r%d0 + xorr r%0,r%0\;lisp r%d0,%1 + lisn r%0,1 \;lisn r%d0,%J1 dlr r%0,r%1 - dlb %Q1 dl r%0,%1 - dstb %Q0 - dst r%1,%0 ") + dst r%1,%0 + stc 0,%0 \;stc %1,%A0 ") +(define_expand "movhi" + [(set (match_operand:HI 0 "general_operand" "=g") + (match_operand:HI 1 "general_operand" "g"))] + "" + " + { + rtx op1 = operands[1]; + if (GET_CODE (operands[0]) == MEM) + { + if (GET_CODE (op1) == MEM + || (GET_CODE (op1) == CONST_INT + && (INTVAL (op1) < 0 || INTVAL (op1) > 15))) + operands[1] = force_reg (HImode, operands[1]); + } + else if (GET_CODE (op1) == CONST_INT + && (INTVAL (op1) < -16 || INTVAL (op1) > 16)) + operands[1] = force_const_mem (HImode, operands[1]); + }") -;; Single-Float moves are *same* as HImode moves: -;(define_insn "movhf" -; [(set (match_operand:HF 0 "general_operand" "=r,r,r,m") -; (match_operand:HF 1 "general_operand" "F,r,m,r"))] -; "" -; "@ -; %D1\;dl r%0,%F1 -; dlr r%0,r%1 -; dl r%0,%1 -; dst r%1,%0 ") +;; Single-Float moves -(define_insn "movhf" - [(set (match_operand:HF 0 "general_operand" "=r,z,r,Q,m") - (match_operand:HF 1 "general_operand" "r,Q,m,z,r"))] +(define_insn "" + [(set (match_operand:HF 0 "general_operand" "=r,r,m,m") + (match_operand:HF 1 "general_operand" "r,m,r,G"))] "" "@ dlr r%0,r%1 - dlb %Q1 dl r%0,%1 - dstb %Q0 - dst r%1,%0 ") + dst r%1,%0 + stc 0,%0 \;stc 0,%A0 ") +(define_expand "movhf" + [(set (match_operand:HF 0 "general_operand" "") + (match_operand:HF 1 "general_operand" ""))] + "" + " + { + enum rtx_code op1code = GET_CODE (operands[1]); + if (GET_CODE (operands[0]) == MEM) + { + if (op1code == MEM || (op1code == CONST_DOUBLE + && !rtx_equal_p (operands[1], CONST0_RTX (HFmode)))) + operands[1] = force_reg (HFmode, operands[1]); + } + else if (op1code == CONST_DOUBLE) + operands[1] = force_const_mem (HFmode, operands[1]); + }") -;; Longfloat moves -;(define_insn "movtqf" -; [(set (match_operand:TQF 0 "general_operand" "=r,r,r,m") -; (match_operand:TQF 1 "general_operand" "F,r,m,r"))] -; "" -; "@ -; %E1\;efl r%0,%G1 -; eflr.m %0,%1 -; efl r%0,%1 -; efst r%1,%0 ") +;; Longfloat moves -(define_insn "movtqf" +(define_insn "" [(set (match_operand:TQF 0 "general_operand" "=r,r,m") (match_operand:TQF 1 "general_operand" "r,m,r"))] "" @@ -495,15 +456,31 @@ efl r%0,%1 efst r%1,%0 ") +(define_expand "movtqf" + [(set (match_operand:TQF 0 "general_operand" "") + (match_operand:TQF 1 "general_operand" ""))] + "" + " + { + enum rtx_code op1code = GET_CODE (operands[1]); + if (GET_CODE (operands[0]) == MEM) + { + if (op1code == MEM || op1code == CONST_DOUBLE) + operands[1] = force_reg (TQFmode, operands[1]); + } + else if (op1code == CONST_DOUBLE) + operands[1] = force_const_mem (TQFmode, operands[1]); + }") + ;; add instructions ;; single integer (define_insn "addqi3" - [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,t,r,m,m") - (plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0,0,0") - (match_operand:QI 2 "general_operand" "I,J,i,r,Q,m,I,J")))] + [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,m,m") + (plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0,0") + (match_operand:QI 2 "general_operand" "I,J,i,r,m,I,J")))] "" "* switch (which_alternative) @@ -520,13 +497,13 @@ case 3: return \"ar r%0,r%2\"; case 4: - return \"ab %Q2\"; - case 5: return \"a r%0,%2\"; - case 6: + case 5: return \"incm %2,%0\"; - case 7: + case 6: return \"decm %J2,%0\"; + default: + abort(); } ") ;; double integer @@ -540,13 +517,12 @@ da r%0,%2 ") (define_insn "addhf3" - [(set (match_operand:HF 0 "register_operand" "=r,z,r") - (plus:HF (match_operand:HF 1 "register_operand" "%0,0,0") - (match_operand:HF 2 "general_operand" "r,Q,m")))] + [(set (match_operand:HF 0 "register_operand" "=r,r") + (plus:HF (match_operand:HF 1 "register_operand" "%0,0") + (match_operand:HF 2 "general_operand" "r,m")))] "" "@ far r%0,r%2 - fab %Q2 fa r%0,%2 ") (define_insn "addtqf3" @@ -563,15 +539,14 @@ ;; single integer (define_insn "subqi3" - [(set (match_operand:QI 0 "general_operand" "=r,r,r,t,r,m") - (minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0,0,0") - (match_operand:QI 2 "general_operand" "I,i,r,Q,m,I")))] + [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,m") + (minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0,0") + (match_operand:QI 2 "general_operand" "I,i,r,m,I")))] "" "@ sisp r%0,%2 sim r%0,%2 sr r%0,r%2 - sbb %Q2 s r%0,%2 decm %2,%0 ") @@ -586,13 +561,12 @@ ds r%0,%2 ") (define_insn "subhf3" - [(set (match_operand:HF 0 "register_operand" "=r,z,r") - (minus:HF (match_operand:HF 1 "register_operand" "0,0,0") - (match_operand:HF 2 "general_operand" "r,Q,m")))] + [(set (match_operand:HF 0 "register_operand" "=r,r") + (minus:HF (match_operand:HF 1 "register_operand" "0,0") + (match_operand:HF 2 "general_operand" "r,m")))] "" "@ fsr r%0,r%2 - fsb %Q2 fs r%0,%2 ") (define_insn "subtqf3" @@ -622,15 +596,27 @@ ; 32-bit product (define_insn "mulqihi3" - [(set (match_operand:HI 0 "register_operand" "=r,r,t,r") - (mult:HI (match_operand:QI 1 "register_operand" "%0,0,0,0") - (match_operand:QI 2 "general_operand" "M,r,Q,m")))] + [(set (match_operand:HI 0 "register_operand" "=r,r,r") + (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%r,r,r")) + (sign_extend:HI (match_operand:QI 2 "general_operand" "r,m,i"))))] "" - "@ - mim r%0,%1 - mr r%0,r%2 - mb %Q2 - m r%0,%2 ") + "* + if (REGNO (operands[1]) != REGNO (operands[0])) + output_asm_insn (\"lr r%0,r%1\", operands); + + switch (which_alternative) + { + case 0: + return \"mr r%0,r%2\"; + case 1: + return \"m r%0,%2\"; + case 2: + return \"mim r%0,%2\"; + default: + abort(); + } + ") + (define_insn "mulhi3" [(set (match_operand:HI 0 "register_operand" "=r,r") @@ -644,13 +630,12 @@ ; not available on 1750: "umulhi3","umulhisi3","umulsi3" (unsigned multiply's) (define_insn "mulhf3" - [(set (match_operand:HF 0 "register_operand" "=r,z,r") - (mult:HF (match_operand:HF 1 "register_operand" "%0,0,0") - (match_operand:HF 2 "general_operand" "r,Q,m")))] + [(set (match_operand:HF 0 "register_operand" "=r,r") + (mult:HF (match_operand:HF 1 "register_operand" "%0,0") + (match_operand:HF 2 "general_operand" "r,m")))] "" "@ fmr r%0,r%2 - fmb %Q2 fm r%0,%2 ") (define_insn "multqf3" @@ -682,7 +667,7 @@ "" "* { - char *istr; + const char *istr; switch(which_alternative) { case 0: @@ -693,10 +678,10 @@ rtx new_opnds[4]; new_opnds[0] = operands[0]; new_opnds[1] = operands[1]; - new_opnds[2] = gen_rtx (CONST_INT, VOIDmode, -INTVAL(operands[2])); + new_opnds[2] = GEN_INT (-INTVAL(operands[2])); new_opnds[3] = operands[3]; istr = \"disn\"; - return (char *)mod_regno_adjust(istr,new_opnds); + return mod_regno_adjust (istr, new_opnds); } break; case 2: @@ -709,7 +694,7 @@ istr = \"dv \"; break; } - return (char *)mod_regno_adjust(istr,operands); + return mod_regno_adjust (istr, operands); }") ;; Division for other types is straightforward. @@ -724,13 +709,12 @@ dd r%0,%2 ") (define_insn "divhf3" - [(set (match_operand:HF 0 "register_operand" "=r,z,r") - (div:HF (match_operand:HF 1 "register_operand" "0,0,0") - (match_operand:HF 2 "general_operand" "r,Q,m")))] + [(set (match_operand:HF 0 "register_operand" "=r,r") + (div:HF (match_operand:HF 1 "register_operand" "0,0") + (match_operand:HF 2 "general_operand" "r,m")))] "" "@ fdr r%0,r%2 - fdb %Q2 fd r%0,%2 ") (define_insn "divtqf3" @@ -792,26 +776,64 @@ (neg:TQF (match_operand:TQF 1 "register_operand" "r")))] "" " - emit_insn(gen_rtx(SET,VOIDmode,operands[0],CONST0_RTX(TQFmode))); - emit_insn(gen_rtx(SET,VOIDmode,operands[0], - gen_rtx(MINUS,TQFmode,operands[0],operands[1]))); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], CONST0_RTX (TQFmode))); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], + gen_rtx_MINUS (TQFmode, operands[0], operands[1]))); DONE; ") ;; bit-logical instructions +;; Set Bit +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=r,m") + (ior:QI (match_operand:QI 1 "general_operand" "0,0") + (match_operand:QI 2 "const_int_operand" "i,i")))] + "one_bit_set_p (INTVAL (operands [2]))" + "@ + sbr %b2,r%0 + sb %b2,%0") + +;; Reset Bit +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=r,m") + (and:QI (match_operand:QI 1 "general_operand" "0,0") + (match_operand:QI 2 "const_int_operand" "i,i")))] + "one_bit_set_p ((~INTVAL (operands [2])) & 0xffff)" + "@ + rbr %B2,r%0 + rb %B2,%0") + +;; Set Variable Bit +(define_insn "" + [(set (match_operand:QI 0 "register_operand" "=r") + (ior:QI (match_operand:QI 1 "register_operand" "0") + (lshiftrt:QI (const_int 32768) + (match_operand:QI 2 "register_operand" "r"))))] + "" + "svbr r%2,%r0") + +;; Reset Variable Bit +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=r") + (and:QI (match_operand:QI 1 "general_operand" "0") + (not:QI (lshiftrt:QI (const_int 32768) + (match_operand:QI 2 "register_operand" "r")))))] + "" + "rvbr r%2,%r0") + + ;; AND (define_insn "andqi3" - [(set (match_operand:QI 0 "general_operand" "=r,r,t,r") - (and:QI (match_operand:QI 1 "general_operand" "%0,0,0,0") - (match_operand:QI 2 "general_operand" "M,r,Q,m")))] + [(set (match_operand:QI 0 "general_operand" "=r,r,r") + (and:QI (match_operand:QI 1 "general_operand" "%0,0,0") + (match_operand:QI 2 "general_operand" "M,r,m")))] "" "@ andm r%0,%2 andr r%0,r%2 - andb %Q2 and r%0,%2 ") ; This sets incorrect condition codes. See notice_update_cc() @@ -825,14 +847,13 @@ ;; OR (define_insn "iorqi3" - [(set (match_operand:QI 0 "general_operand" "=r,r,t,r") - (ior:QI (match_operand:QI 1 "general_operand" "%0,0,0,0") - (match_operand:QI 2 "general_operand" "M,r,Q,m")))] + [(set (match_operand:QI 0 "general_operand" "=r,r,r") + (ior:QI (match_operand:QI 1 "general_operand" "%0,0,0") + (match_operand:QI 2 "general_operand" "M,r,m")))] "" "@ orim r%0,%2 orr r%0,r%2 - orb %Q2 or r%0,%2 ") ; This sets incorrect condition codes. See notice_update_cc() @@ -917,20 +938,16 @@ (match_operand:QI 2 "nonmemory_operand" "L,r")))] "" ; the 'L' constraint is a slight imprecise... "* - if (which_alternative == 1) - return \"dslr r%0,r%2\"; - else if (INTVAL(operands[2]) <= 16) - return \"dsll r%0,%2\"; - else - { - rtx new_opnds[2]; - new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0])); - new_opnds[1] = gen_rtx (REG, QImode, REGNO(operands[0]) + 1); - output_asm_insn(\"lr r%0,r%1 ; ashlhi3 shiftcount > 16\",new_opnds); - new_opnds[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL(operands[2]) - 16); - output_asm_insn(\"sll r%0,%1\",new_opnds); - return \";\"; - } ") + if (which_alternative == 1) + return \"dslr r%0,r%2\"; + else if (INTVAL(operands[2]) <= 16) + return \"dsll r%0,%2\"; + else + { + output_asm_insn (\"dsll r%0,16 ; ashlhi3 shiftcnt > 16\", operands); + return \"sll r%0,%w2\"; + } + ") ;; Right shift by a variable shiftcount works by negating the shift count, @@ -939,14 +956,14 @@ ;; prevents converting shifts to ZERO_EXTRACTs with negative positions, ;; which isn't valid. (define_expand "lshrqi3" - [(set (match_operand:QI 0 "general_operand" "=r") - (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") + [(set (match_operand:QI 0 "register_operand" "=r") + (lshiftrt:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "g")))] "" " { if (GET_CODE (operands[2]) != CONST_INT) - operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2])); + operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2])); }") (define_insn "" @@ -973,7 +990,7 @@ " { if (GET_CODE (operands[2]) != CONST_INT) - operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2])); + operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2])); }") (define_insn "" @@ -982,17 +999,11 @@ (match_operand:QI 2 "immediate_operand" "L")))] "" "* - { - rtx new_opnds[2]; - int amount = INTVAL(operands[2]); - if (amount <= 16) + if (INTVAL (operands[2]) <= 16) return \"dsrl r%0,%2\"; - output_asm_insn(\"dsrl r%0,16 ; lshrhi3 shiftcount > 16\",operands); - new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0]) + 1); - new_opnds[1] = gen_rtx (CONST_INT, VOIDmode, amount - 16); - output_asm_insn(\"srl r%0,%1\",new_opnds); - return \";\"; - } ") + output_asm_insn (\"dsrl r%0,16 ; lshrhi3 shiftcount > 16\", operands); + return \"srl r%d0,%w2\"; + ") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") @@ -1003,14 +1014,14 @@ ;; Same applies for arithmetic shift right. (define_expand "ashrqi3" - [(set (match_operand:QI 0 "general_operand" "=r") - (ashiftrt:QI (match_operand:QI 1 "general_operand" "0") + [(set (match_operand:QI 0 "register_operand" "=r") + (ashiftrt:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "g")))] "" " { if (GET_CODE (operands[2]) != CONST_INT) - operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2])); + operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2])); }") (define_insn "" @@ -1029,14 +1040,14 @@ ;; HImode arithmetic shift right. (define_expand "ashrhi3" - [(set (match_operand:HI 0 "general_operand" "=r") - (ashiftrt:HI (match_operand:HI 1 "general_operand" "0") + [(set (match_operand:HI 0 "register_operand" "=r") + (ashiftrt:HI (match_operand:HI 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "g")))] "" " { if (GET_CODE (operands[2]) != CONST_INT) - operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2])); + operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2])); }") (define_insn "" @@ -1045,17 +1056,11 @@ (match_operand:QI 2 "immediate_operand" "L")))] "" "* - { - rtx new_opnds[2]; - int amount = INTVAL(operands[2]); - if (amount <= 16) + if (INTVAL (operands[2]) <= 16) return \"dsra r%0,%2\"; - output_asm_insn(\"dsra r%0,16 ; ashrhi3 shiftcount > 16\",operands); - new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0]) + 1); - new_opnds[1] = gen_rtx (CONST_INT, VOIDmode, amount - 16); - output_asm_insn(\"sra r%0,%1\",new_opnds); - return \";\"; - } ") + output_asm_insn (\"dsra r%0,16 ; ashrhi3 shiftcount > 16\", operands); + return \"sra r%d0,%w2\"; + ") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") @@ -1109,7 +1114,7 @@ ;******************** ;; Bit field instructions, general cases. -;; "o,d" constraint causes a nonoffsetable memref to match the "o" +;; "o,d" constraint causes a nonoffsettable memref to match the "o" ;; so that its address is reloaded. ;; (define_insn "extv" ... @@ -1142,7 +1147,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "* return (char *)branch_or_jump(\"ez\",CODE_LABEL_NUMBER(operands[0])); + "* return branch_or_jump (\"ez\", CODE_LABEL_NUMBER (operands[0])); ") (define_insn "bne" @@ -1152,7 +1157,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "* return (char *)branch_or_jump(\"nz\",CODE_LABEL_NUMBER(operands[0])); + "* return branch_or_jump (\"nz\", CODE_LABEL_NUMBER (operands[0])); ") (define_insn "bgt" @@ -1162,7 +1167,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "* return (char *)branch_or_jump(\"gt\",CODE_LABEL_NUMBER(operands[0])); + "* return branch_or_jump (\"gt\", CODE_LABEL_NUMBER (operands[0])); ") (define_insn "blt" @@ -1172,7 +1177,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "* return (char *)branch_or_jump(\"lt\",CODE_LABEL_NUMBER(operands[0])); + "* return branch_or_jump (\"lt\", CODE_LABEL_NUMBER (operands[0])); ") (define_insn "bge" @@ -1182,7 +1187,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "* return (char *)branch_or_jump(\"ge\",CODE_LABEL_NUMBER(operands[0])); + "* return branch_or_jump (\"ge\", CODE_LABEL_NUMBER (operands[0])); ") (define_insn "ble" @@ -1192,7 +1197,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "* return (char *)branch_or_jump(\"le\",CODE_LABEL_NUMBER(operands[0])); + "* return branch_or_jump (\"le\", CODE_LABEL_NUMBER (operands[0])); ") @@ -1244,7 +1249,7 @@ (pc) (label_ref (match_operand 0 "" ""))))] "" - "* return (char *)branch_or_jump(\"nz\",CODE_LABEL_NUMBER(operands[0])); + "* return branch_or_jump (\"nz\", CODE_LABEL_NUMBER (operands[0])); ") (define_insn "" @@ -1254,7 +1259,7 @@ (pc) (label_ref (match_operand 0 "" ""))))] "" - "* return (char *)branch_or_jump(\"ez\",CODE_LABEL_NUMBER(operands[0])); + "* return branch_or_jump (\"ez\", CODE_LABEL_NUMBER (operands[0])); ") (define_insn "" @@ -1264,7 +1269,7 @@ (pc) (label_ref (match_operand 0 "" ""))))] "" - "* return (char *)branch_or_jump(\"le\",CODE_LABEL_NUMBER(operands[0])); + "* return branch_or_jump (\"le\", CODE_LABEL_NUMBER (operands[0])); ") (define_insn "" @@ -1274,7 +1279,7 @@ (pc) (label_ref (match_operand 0 "" ""))))] "" - "* return (char *)branch_or_jump(\"ge\",CODE_LABEL_NUMBER(operands[0])); + "* return branch_or_jump (\"ge\", CODE_LABEL_NUMBER (operands[0])); ") (define_insn "" @@ -1284,7 +1289,7 @@ (pc) (label_ref (match_operand 0 "" ""))))] "" - "* return (char *)branch_or_jump(\"lt\",CODE_LABEL_NUMBER(operands[0])); + "* return branch_or_jump (\"lt\", CODE_LABEL_NUMBER (operands[0])); ") (define_insn "" @@ -1294,7 +1299,7 @@ (pc) (label_ref (match_operand 0 "" ""))))] "" - "* return (char *)branch_or_jump(\"gt\",CODE_LABEL_NUMBER(operands[0])); + "* return branch_or_jump (\"gt\", CODE_LABEL_NUMBER (operands[0])); ") @@ -1356,7 +1361,7 @@ ;; Call subroutine, returning value in operand 0 ;; (which must be a hard register). (define_insn "call_value" - [(set (match_operand 0 "register_operand" "r") + [(set (match_operand 0 "register_operand" "=r") (call (match_operand:QI 1 "memory_operand" "m") (match_operand:QI 2 "general_operand" "g")))] ;; Operand 2 not really used for 1750. @@ -1379,17 +1384,6 @@ "" "ANYCALL %0") - -; (define_insn "return" -; [(return)] -; "" -; "* -; { -; rtx oprnd = gen_rtx(CONST_INT,VOIDmode,get_frame_size()); -; output_asm_insn(\"ret.m %0\",&oprnd); -; return \"\;\"; -; } ") - (define_insn "indirect_jump" [(set (pc) (match_operand:QI 0 "address_operand" "p"))] ""