"*// C++*" { set src ${basename}[pid].cc }
default { set src ${basename}[pid].c }
}
- switch $type {
+ set compile_type $type
+ switch -glob $type {
assembly { set output ${basename}[pid].s }
object { set output ${basename}[pid].o }
executable { set output ${basename}[pid].exe }
+ "rtl-*" {
+ set output ${basename}[pid].s
+ lappend options "additional_flags=-fdump-$type"
+ set compile_type assembly
+ }
}
set f [open $src "w"]
puts $f $contents
close $f
- set lines [${tool}_target_compile $src $output $type "$options"]
+ set lines [${tool}_target_compile $src $output $compile_type "$options"]
file delete $src
- return [list $lines $output]
+ set scan_output $output
+ # Don't try folding this into the switch above; calling "glob" before the
+ # file is created won't work.
+ if [regexp "rtl-(.*)" $type dummy rtl_type] {
+ set scan_output "[glob $src.\[0-9\]\[0-9\]\[0-9\]r.$rtl_type]"
+ file delete $output
+ }
+
+ return [list $lines $scan_output]
}
proc current_target_name { } {
return $gc_sections_available_saved
}
+# Return 1 if according to target_info struct and explicit target list
+# target is supposed to support trampolines.
+
+proc check_effective_target_trampolines { } {
+ if [target_info exists no_trampolines] {
+ return 0
+ }
+ if { [istarget avr-*-*]
+ || [istarget hppa2.0w-hp-hpux11.23]
+ || [istarget hppa64-hp-hpux11.23] } {
+ return 0;
+ }
+ return 1
+}
+
+# Return 1 if according to target_info struct and explicit target list
+# target is supposed to keep null pointer checks. This could be due to
+# use of option fno-delete-null-pointer-checks or hardwired in target.
+
+proc check_effective_target_keeps_null_pointer_checks { } {
+ if [target_info exists keeps_null_pointer_checks] {
+ return 1
+ }
+ if { [istarget avr-*-*] } {
+ return 1;
+ }
+ return 0
+}
+
# Return true if profiling is supported on the target.
proc check_profiling_available { test_what } {
return 0
}
+ # We don't yet support profiling for MIPS16.
+ if { [istarget mips*-*-*]
+ && ![check_effective_target_nomips16]
+ && ([lindex $test_what 1] == "-p"
+ || [lindex $test_what 1] == "-pg") } {
+ return 0
+ }
+
+ # MinGW does not support -p.
+ if { [istarget *-*-mingw*] && [lindex $test_what 1] == "-p" } {
+ return 0
+ }
+
# At present, there is no profiling support on NetWare.
if { [istarget *-*-netware*] } {
return 0
|| [istarget arm*-*-eabi*]
|| [istarget arm*-*-elf]
|| [istarget arm*-*-symbianelf*]
+ || [istarget avr-*-*]
|| [istarget bfin-*-*]
|| [istarget powerpc-*-eabi*]
- || [istarget strongarm*-*-elf]
- || [istarget xscale*-*-elf]
|| [istarget cris-*-*]
|| [istarget crisv32-*-*]
|| [istarget fido-*-elf]
|| [istarget m68k-*-uclinux*]
|| [istarget mips*-*-elf*]
|| [istarget xstormy16-*]
- || [istarget xtensa-*-elf]
- || [istarget *-*-vxworks*]
- || [istarget *-*-windiss] } {
+ || [istarget xtensa*-*-elf]
+ || [istarget *-*-vxworks*] } {
set profiling_available_saved 0
} else {
set profiling_available_saved 1
# This won't change for different subtargets so cache the result.
proc check_effective_target_tls_native {} {
+ # VxWorks uses emulated TLS machinery, but with non-standard helper
+ # functions, so we fail to automatically detect it.
+ global target_triplet
+ if { [regexp ".*-.*-vxworks.*" $target_triplet] } {
+ return 0
+ }
+
return [check_no_messages_and_pattern tls_native "!emutls" assembly {
__thread int i;
int f (void) { return i; }
}]
}
+# Return 1 if compilation with -fgraphite is error-free for trivial
+# code, 0 otherwise.
+
+proc check_effective_target_fgraphite {} {
+ return [check_no_compiler_messages fgraphite object {
+ void foo (void) { }
+ } "-O1 -fgraphite"]
+}
+
# Return 1 if compilation with -fopenmp is error-free for trivial
# code, 0 otherwise.
# Return true if the target has access to FPU instructions.
proc check_effective_target_hard_float { } {
- return [check_no_compiler_messages hard_float assembly {
- #if ((defined __mips \
- && (defined __mips_soft_float || defined __mips16)) \
- || (defined __xtensa__ && defined __XTENSA_SOFT_FLOAT__))
- #error FOO
- #endif
+ if { [istarget mips*-*-*] } {
+ return [check_no_compiler_messages hard_float assembly {
+ #if (defined __mips_soft_float || defined __mips16)
+ #error FOO
+ #endif
+ }]
+ }
+
+ # The generic test equates hard_float with "no call for adding doubles".
+ return [check_no_messages_and_pattern hard_float "!\\(call" rtl-expand {
+ double a (double b, double c) { return b + c; }
}]
}
# we don't support MIPS16 PIC.
proc add_options_for_mips16_attribute { flags } {
- return "$flags -mno-abicalls -fno-pic"
+ return "$flags -mno-abicalls -fno-pic -DMIPS16=__attribute__((mips16))"
}
# Return true if we can force a mode that allows MIPS16 code generation.
}]
}
+# Return 1 if the target supports Fortran integer(16), 0 otherwise.
+#
+# When the target name changes, replace the cached result.
+
+proc check_effective_target_fortran_integer_16 { } {
+ return [check_no_compiler_messages fortran_integer_16 executable {
+ ! Fortran
+ integer(16) :: i
+ end
+ }]
+}
+
# Return 1 if we can statically link libgfortran, 0 otherwise.
#
# When the target name changes, replace the cached result.
}]
}
+# Return 1 if the target supports executing SSE2 instructions, 0
+# otherwise. Cache the result.
+
+proc check_sse2_hw_available { } {
+ return [check_cached_effective_target sse2_hw_available {
+ # If this is not the right target then we can skip the test.
+ if { !([istarget x86_64-*-*] || [istarget i?86-*-*]) } {
+ expr 0
+ } else {
+ check_runtime_nocache sse2_hw_available {
+ #include "cpuid.h"
+ int main ()
+ {
+ unsigned int eax, ebx, ecx, edx = 0;
+ if (__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+ return !(edx & bit_SSE2);
+ return 1;
+ }
+ } ""
+ }
+ }]
+}
+
# Return 1 if the target supports executing AltiVec instructions, 0
# otherwise. Cache the result.
&& [check_effective_target_lp64])
|| ([istarget powerpc*-*-*]
&& ([check_effective_target_powerpc_spe]
- || [check_effective_target_powerpc_altivec]))} {
+ || [check_effective_target_powerpc_altivec]))
+ || [istarget spu-*-*]
+ || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) } {
set et_vect_cmdline_needed_saved 0
}
}
|| [istarget x86_64-*-*]
|| [istarget sparc*-*-*]
|| [istarget alpha*-*-*]
- || [istarget ia64-*-*] } {
+ || [istarget ia64-*-*]
+ || [check_effective_target_arm32] } {
set et_vect_int_saved 1
}
}
} else {
set et_vect_floatint_cvt_saved 0
if { [istarget i?86-*-*]
+ || ([istarget powerpc*-*-*]
+ && ![istarget powerpc-*-linux*paired*])
|| [istarget x86_64-*-*] } {
set et_vect_floatint_cvt_saved 1
}
}
}
+# Return 1 is this is an ARM target where -mthumb causes Thumb-1 to be
+# used.
+
+proc check_effective_target_arm_thumb1_ok { } {
+ return [check_no_compiler_messages arm_thumb1_ok assembly {
+ #if !defined(__arm__) || !defined(__thumb__) || defined(__thumb2__)
+ #error FOO
+ #endif
+ } "-mthumb"]
+}
+
# Return 1 if the target supports executing NEON instructions, 0
# otherwise. Cache the result.
} "-mfpu=neon -mfloat-abi=softfp"]
}
+# Return 1 if this is a ARM target with NEON enabled.
+
+proc check_effective_target_arm_neon { } {
+ if { [check_effective_target_arm32] } {
+ return [check_no_compiler_messages arm_neon object {
+ #ifndef __ARM_NEON__
+ #error not NEON
+ #else
+ int dummy;
+ #endif
+ }]
+ } else {
+ return 0
+ }
+}
+
+# Return 1 if this a Loongson-2E or -2F target using an ABI that supports
+# the Loongson vector modes.
+
+proc check_effective_target_mips_loongson { } {
+ return [check_no_compiler_messages loongson assembly {
+ #if !defined(__mips_loongson_vector_rev)
+ #error FOO
+ #endif
+ }]
+}
+
# Return 1 if this is a PowerPC target with floating-point registers.
proc check_effective_target_powerpc_fprs { } {
}
}
+# Return 1 if this is a PowerPC target with hardware double-precision
+# floating point.
+
+proc check_effective_target_powerpc_hard_double { } {
+ if { [istarget powerpc*-*-*]
+ || [istarget rs6000-*-*] } {
+ return [check_no_compiler_messages powerpc_hard_double object {
+ #ifdef _SOFT_DOUBLE
+ #error soft double
+ #else
+ int dummy;
+ #endif
+ }]
+ } else {
+ return 0
+ }
+}
+
# Return 1 if this is a PowerPC target supporting -maltivec.
proc check_effective_target_powerpc_altivec_ok { } {
# Return 1 if this is a PowerPC target that supports SPU.
proc check_effective_target_powerpc_spu { } {
- return [istarget powerpc*-*-linux*]
+ if [istarget powerpc*-*-linux*] {
+ return [check_effective_target_powerpc_altivec_ok]
+ } else {
+ return 0
+ }
}
# Return 1 if this is a PowerPC target with SPE enabled.
}
}
+# Return 1 if this is a SPU target with a toolchain that
+# supports automatic overlay generation.
+
+proc check_effective_target_spu_auto_overlay { } {
+ if { [istarget spu*-*-elf*] } {
+ return [check_no_compiler_messages spu_auto_overlay executable {
+ int main (void) { }
+ } "-Wl,--auto-overlay" ]
+ } else {
+ return 0
+ }
+}
+
# The VxWorks SPARC simulator accepts only EM_SPARC executables and
# chokes on EM_SPARC32PLUS or EM_SPARCV9 executables. Return 1 if the
# test environment appears to run executables on such a simulator.
&& ![istarget powerpc-*-linux*paired*])
|| [istarget ia64-*-*]
|| [istarget i?86-*-*]
- || [istarget x86_64-*-*] } {
+ || [istarget x86_64-*-*]
+ || [check_effective_target_arm32] } {
set et_vect_shift_saved 1
}
}
&& ![istarget powerpc-*-linux*paired*])
&& [check_effective_target_ilp32])
|| [istarget x86_64-*-*]
+ || [check_effective_target_arm32]
|| ([istarget sparc*-*-*] && [check_effective_target_ilp32]) } {
set answer 1
} else {
|| [istarget spu-*-*]
|| [istarget mipsisa64*-*-*]
|| [istarget x86_64-*-*]
- || [istarget ia64-*-*] } {
+ || [istarget ia64-*-*]
+ || [check_effective_target_arm32] } {
set et_vect_float_saved 1
}
}
return $et_vect_double_saved
}
+# Return 1 if the target supports hardware vectors of long long, 0 otherwise.
+#
+# This won't change for different subtargets so cache the result.
+
+proc check_effective_target_vect_long_long { } {
+ global et_vect_long_long_saved
+
+ if [info exists et_vect_long_long_saved] {
+ verbose "check_effective_target_vect_long_long: using cached result" 2
+ } else {
+ set et_vect_long_long_saved 0
+ if { [istarget i?86-*-*]
+ || [istarget x86_64-*-*] } {
+ set et_vect_long_long_saved 1
+ }
+ }
+
+ verbose "check_effective_target_vect_long_long: returning $et_vect_long_long_saved" 2
+ return $et_vect_long_long_saved
+}
+
+
# Return 1 if the target plus current options does not support a vector
# max instruction on "int", 0 otherwise.
#
return $et_vect_no_bitwise_saved
}
+# Return 1 if the target plus current options supports vector permutation,
+# 0 otherwise.
+#
+# This won't change for different subtargets so cache the result.
+
+proc check_effective_target_vect_perm { } {
+ global et_vect_perm
+
+ if [info exists et_vect_perm_saved] {
+ verbose "check_effective_target_vect_perm: using cached result" 2
+ } else {
+ set et_vect_perm_saved 0
+ if { [istarget powerpc*-*-*]
+ || [istarget spu-*-*] } {
+ set et_vect_perm_saved 1
+ }
+ }
+ verbose "check_effective_target_vect_perm: returning $et_vect_perm_saved" 2
+ return $et_vect_perm_saved
+}
+
+
# Return 1 if the target plus current options supports a vector
# widening summation of *short* args into *int* result, 0 otherwise.
# A target can also support this widening summation if it can support
set et_vect_pack_trunc_saved 0
if { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
|| [istarget i?86-*-*]
- || [istarget x86_64-*-*] } {
+ || [istarget x86_64-*-*]
+ || [istarget spu-*-*] } {
set et_vect_pack_trunc_saved 1
}
}
set et_vect_unpack_saved 0
if { ([istarget powerpc*-*-*] && ![istarget powerpc-*paired*])
|| [istarget i?86-*-*]
- || [istarget x86_64-*-*] } {
+ || [istarget x86_64-*-*]
+ || [istarget spu-*-*] } {
set et_vect_unpack_saved 1
}
}
verbose "check_effective_target_unaligned_stack: using cached result" 2
} else {
set et_unaligned_stack_saved 0
- if { ( [istarget i?86-*-*] || [istarget x86_64-*-*] )
- && (! [istarget *-*-darwin*] ) } {
- set et_unaligned_stack_saved 1
- }
}
verbose "check_effective_target_unaligned_stack: returning $et_unaligned_stack_saved" 2
return $et_unaligned_stack_saved
set et_vect_no_align_saved 0
if { [istarget mipsisa64*-*-*]
|| [istarget sparc*-*-*]
- || [istarget ia64-*-*] } {
+ || [istarget ia64-*-*]
+ || [check_effective_target_arm32] } {
set et_vect_no_align_saved 1
}
}
} else {
set et_vect_short_mult_saved 0
if { [istarget ia64-*-*]
+ || [istarget spu-*-*]
|| [istarget i?86-*-*]
|| [istarget x86_64-*-*] } {
set et_vect_short_mult_saved 1
if { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
|| [istarget spu-*-*]
|| [istarget i?86-*-*]
- || [istarget x86_64-*-*] } {
+ || [istarget x86_64-*-*]
+ || [check_effective_target_arm32] } {
set et_vect_int_mult_saved 1
}
}
verbose "check_effective_target_vect_extract_even_odd: using cached result" 2
} else {
set et_vect_extract_even_odd_saved 0
- if { [istarget powerpc*-*-*] } {
+ if { [istarget powerpc*-*-*]
+ || [istarget spu-*-*] } {
set et_vect_extract_even_odd_saved 1
}
}
return $et_vect_extract_even_odd_saved
}
+# Return 1 if the target supports vector even/odd elements extraction of
+# vectors with SImode elements or larger, 0 otherwise.
+
+proc check_effective_target_vect_extract_even_odd_wide { } {
+ global et_vect_extract_even_odd_wide_saved
+
+ if [info exists et_vect_extract_even_odd_wide_saved] {
+ verbose "check_effective_target_vect_extract_even_odd_wide: using cached result" 2
+ } else {
+ set et_vect_extract_even_odd_wide_saved 0
+ if { [istarget powerpc*-*-*]
+ || [istarget i?86-*-*]
+ || [istarget x86_64-*-*]
+ || [istarget spu-*-*] } {
+ set et_vect_extract_even_odd_wide_saved 1
+ }
+ }
+
+ verbose "check_effective_target_vect_extract_even_wide_odd: returning $et_vect_extract_even_odd_wide_saved" 2
+ return $et_vect_extract_even_odd_wide_saved
+}
+
# Return 1 if the target supports vector interleaving, 0 otherwise.
proc check_effective_target_vect_interleave { } {
set et_vect_interleave_saved 0
if { [istarget powerpc*-*-*]
|| [istarget i?86-*-*]
- || [istarget x86_64-*-*] } {
+ || [istarget x86_64-*-*]
+ || [istarget spu-*-*] } {
set et_vect_interleave_saved 1
}
}
return $et_vect_strided_saved
}
+# Return 1 if the target supports vector interleaving and extract even/odd
+# for wide element types, 0 otherwise.
+proc check_effective_target_vect_strided_wide { } {
+ global et_vect_strided_wide_saved
+
+ if [info exists et_vect_strided_wide_saved] {
+ verbose "check_effective_target_vect_strided_wide: using cached result" 2
+ } else {
+ set et_vect_strided_wide_saved 0
+ if { [check_effective_target_vect_interleave]
+ && [check_effective_target_vect_extract_even_odd_wide] } {
+ set et_vect_strided_wide_saved 1
+ }
+ }
+
+ verbose "check_effective_target_vect_strided_wide: returning $et_vect_strided_wide_saved" 2
+ return $et_vect_strided_wide_saved
+}
+
# Return 1 if the target supports section-anchors
proc check_effective_target_section_anchors { } {
|| [istarget s390*-*-*]
|| [istarget powerpc*-*-*]
|| [istarget sparc64-*-*]
- || [istarget sparcv9-*-*] } {
+ || [istarget sparcv9-*-*]
+ || [istarget mips*-*-*] } {
set et_sync_int_long_saved 1
}
}
|| [istarget s390*-*-*]
|| [istarget powerpc*-*-*]
|| [istarget sparc64-*-*]
- || [istarget sparcv9-*-*] } {
+ || [istarget sparcv9-*-*]
+ || [istarget mips*-*-*] } {
set et_sync_char_short_saved 1
}
}
return 0
}
-# Return 1 if the target is a VxWorks RTP.
+# Return 1 if the target is a VxWorks kernel.
proc check_effective_target_vxworks_kernel { } {
return [check_no_compiler_messages vxworks_kernel assembly {
}]
}
+# Return 1 if the target is a VxWorks RTP.
+
+proc check_effective_target_vxworks_rtp { } {
+ return [check_no_compiler_messages vxworks_rtp assembly {
+ #if !defined __vxworks || !defined __RTP__
+ #error NO
+ #endif
+ }]
+}
+
# Return 1 if the target is expected to provide wide character support.
proc check_effective_target_wchar { } {
}]
}
+# Return 1 if the target has <pthread.h>.
+
+proc check_effective_target_pthread_h { } {
+ return [check_no_compiler_messages pthread_h assembly {
+ #include <pthread.h>
+ }]
+}
+
+# Return 1 if the target can truncate a file from a file-descriptor,
+# as used by libgfortran/io/unix.c:fd_truncate; i.e. ftruncate or
+# chsize. We test for a trivially functional truncation; no stubs.
+# As libgfortran uses _FILE_OFFSET_BITS 64, we do too; it'll cause a
+# different function to be used.
+
+proc check_effective_target_fd_truncate { } {
+ set prog {
+ #define _FILE_OFFSET_BITS 64
+ #include <unistd.h>
+ #include <stdio.h>
+ #include <stdlib.h>
+ int main ()
+ {
+ FILE *f = fopen ("tst.tmp", "wb");
+ int fd;
+ const char t[] = "test writing more than ten characters";
+ char s[11];
+ fd = fileno (f);
+ write (fd, t, sizeof (t) - 1);
+ lseek (fd, 0, 0);
+ if (ftruncate (fd, 10) != 0)
+ exit (1);
+ close (fd);
+ f = fopen ("tst.tmp", "rb");
+ if (fread (s, 1, sizeof (s), f) != 10 || strncmp (s, t, 10) != 0)
+ exit (1);
+ exit (0);
+ }
+ }
+
+ if { [check_runtime ftruncate $prog] } {
+ return 1;
+ }
+
+ regsub "ftruncate" $prog "chsize" prog
+ return [check_runtime chsize $prog]
+}
+
# Add to FLAGS all the target-specific flags needed to access the c99 runtime.
proc add_options_for_c99_runtime { flags } {
$contents [add_options_for_c99_runtime ""]
}]
}
+
+# Return 1 if target wchar_t is at least 4 bytes.
+
+proc check_effective_target_4byte_wchar_t { } {
+ return [check_no_compiler_messages 4byte_wchar_t object {
+ int dummy[sizeof (__WCHAR_TYPE__) >= 4 ? 1 : -1];
+ }]
+}
+
+# Return 1 if the target supports automatic stack alignment.
+
+proc check_effective_target_automatic_stack_alignment { } {
+ if { [istarget i?86*-*-*]
+ || [istarget x86_64-*-*] } then {
+ return 1
+ } else {
+ return 0
+ }
+}
+
+# Return 1 if avx instructions can be compiled.
+
+proc check_effective_target_avx { } {
+ return [check_no_compiler_messages avx object {
+ void _mm256_zeroall (void)
+ {
+ __builtin_ia32_vzeroall ();
+ }
+ } "-O2 -mavx" ]
+}
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