GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
-Software Foundation; either version 2, or (at your option) any later
+Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
for more details.
You should have received a copy of the GNU General Public License
-along with GCC; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
-02110-1301, USA. */
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
#include "config.h"
};
/* Forward declarations */
-static void set_of_1 (rtx, rtx, void *);
-static bool covers_regno_p (rtx, unsigned int);
-static bool covers_regno_no_parallel_p (rtx, unsigned int);
+static void set_of_1 (rtx, const_rtx, void *);
+static bool covers_regno_p (const_rtx, unsigned int);
+static bool covers_regno_no_parallel_p (const_rtx, unsigned int);
static int rtx_referenced_p_1 (rtx *, void *);
-static int computed_jump_p_1 (rtx);
-static void parms_set (rtx, rtx, void *);
+static int computed_jump_p_1 (const_rtx);
+static void parms_set (rtx, const_rtx, void *);
static void subreg_get_info (unsigned int, enum machine_mode,
unsigned int, enum machine_mode,
struct subreg_info *);
-static unsigned HOST_WIDE_INT cached_nonzero_bits (rtx, enum machine_mode,
- rtx, enum machine_mode,
+static unsigned HOST_WIDE_INT cached_nonzero_bits (const_rtx, enum machine_mode,
+ const_rtx, enum machine_mode,
unsigned HOST_WIDE_INT);
-static unsigned HOST_WIDE_INT nonzero_bits1 (rtx, enum machine_mode, rtx,
- enum machine_mode,
+static unsigned HOST_WIDE_INT nonzero_bits1 (const_rtx, enum machine_mode,
+ const_rtx, enum machine_mode,
unsigned HOST_WIDE_INT);
-static unsigned int cached_num_sign_bit_copies (rtx, enum machine_mode, rtx,
+static unsigned int cached_num_sign_bit_copies (const_rtx, enum machine_mode, const_rtx,
enum machine_mode,
unsigned int);
-static unsigned int num_sign_bit_copies1 (rtx, enum machine_mode, rtx,
+static unsigned int num_sign_bit_copies1 (const_rtx, enum machine_mode, const_rtx,
enum machine_mode, unsigned int);
/* Offset of the first 'e', 'E' or 'V' operand for each rtx code, or
(within one function) and so is anything marked `unchanging'. */
int
-rtx_unstable_p (rtx x)
+rtx_unstable_p (const_rtx x)
{
- RTX_CODE code = GET_CODE (x);
+ const RTX_CODE code = GET_CODE (x);
int i;
const char *fmt;
case CONST:
case CONST_INT:
case CONST_DOUBLE:
+ case CONST_FIXED:
case CONST_VECTOR:
case SYMBOL_REF:
case LABEL_REF:
zero, we are slightly more conservative.
The frame pointer and the arg pointer are considered constant. */
-int
-rtx_varies_p (rtx x, int for_alias)
+bool
+rtx_varies_p (const_rtx x, bool for_alias)
{
RTX_CODE code;
int i;
case CONST:
case CONST_INT:
case CONST_DOUBLE:
+ case CONST_FIXED:
case CONST_VECTOR:
case SYMBOL_REF:
case LABEL_REF:
alignment machines. */
static int
-rtx_addr_can_trap_p_1 (rtx x, enum machine_mode mode, bool unaligned_mems)
+rtx_addr_can_trap_p_1 (const_rtx x, enum machine_mode mode, bool unaligned_mems)
{
enum rtx_code code = GET_CODE (x);
/* Return nonzero if the use of X as an address in a MEM can cause a trap. */
int
-rtx_addr_can_trap_p (rtx x)
+rtx_addr_can_trap_p (const_rtx x)
{
return rtx_addr_can_trap_p_1 (x, VOIDmode, false);
}
/* Return true if X is an address that is known to not be zero. */
bool
-nonzero_address_p (rtx x)
+nonzero_address_p (const_rtx x)
{
- enum rtx_code code = GET_CODE (x);
+ const enum rtx_code code = GET_CODE (x);
switch (code)
{
FOR_ALIAS is nonzero if we are called from alias analysis; if it is
zero, we are slightly more conservative. */
-int
-rtx_addr_varies_p (rtx x, int for_alias)
+bool
+rtx_addr_varies_p (const_rtx x, bool for_alias)
{
enum rtx_code code;
int i;
This is used in cse.c with the `related_value' field. */
HOST_WIDE_INT
-get_integer_term (rtx x)
+get_integer_term (const_rtx x)
{
if (GET_CODE (x) == CONST)
x = XEXP (x, 0);
Only obvious integer terms are detected. */
rtx
-get_related_value (rtx x)
+get_related_value (const_rtx x)
{
if (GET_CODE (x) != CONST)
return 0;
to somewhere in the same object or object_block as SYMBOL. */
bool
-offset_within_block_p (rtx symbol, HOST_WIDE_INT offset)
+offset_within_block_p (const_rtx symbol, HOST_WIDE_INT offset)
{
tree decl;
zero, we do not count occurrences inside the destination of a SET. */
int
-count_occurrences (rtx x, rtx find, int count_dest)
+count_occurrences (const_rtx x, const_rtx find, int count_dest)
{
int i, j;
enum rtx_code code;
case REG:
case CONST_INT:
case CONST_DOUBLE:
+ case CONST_FIXED:
case CONST_VECTOR:
case SYMBOL_REF:
case CODE_LABEL:
for a subexpression of IN that is Lisp "equal" to REG. */
int
-reg_mentioned_p (rtx reg, rtx in)
+reg_mentioned_p (const_rtx reg, const_rtx in)
{
const char *fmt;
int i;
case CONST_INT:
case CONST_VECTOR:
case CONST_DOUBLE:
+ case CONST_FIXED:
/* These are kept unique for a given value. */
return 0;
no CODE_LABEL insn. */
int
-no_labels_between_p (rtx beg, rtx end)
+no_labels_between_p (const_rtx beg, const_rtx end)
{
rtx p;
if (beg == end)
FROM_INSN and TO_INSN (exclusive of those two). */
int
-reg_used_between_p (rtx reg, rtx from_insn, rtx to_insn)
+reg_used_between_p (const_rtx reg, const_rtx from_insn, const_rtx to_insn)
{
rtx insn;
we do not consider it a reference. */
int
-reg_referenced_p (rtx x, rtx body)
+reg_referenced_p (const_rtx x, const_rtx body)
{
int i;
FROM_INSN and TO_INSN (exclusive of those two). */
int
-reg_set_between_p (rtx reg, rtx from_insn, rtx to_insn)
+reg_set_between_p (const_rtx reg, const_rtx from_insn, const_rtx to_insn)
{
- rtx insn;
+ const_rtx insn;
if (from_insn == to_insn)
return 0;
/* Internals of reg_set_between_p. */
int
-reg_set_p (rtx reg, rtx insn)
+reg_set_p (const_rtx reg, const_rtx insn)
{
/* We can be passed an insn or part of one. If we are passed an insn,
check if a side-effect of the insn clobbers REG. */
X contains a MEM; this routine does usememory aliasing. */
int
-modified_between_p (rtx x, rtx start, rtx end)
+modified_between_p (const_rtx x, const_rtx start, const_rtx end)
{
- enum rtx_code code = GET_CODE (x);
+ const enum rtx_code code = GET_CODE (x);
const char *fmt;
int i, j;
rtx insn;
{
case CONST_INT:
case CONST_DOUBLE:
+ case CONST_FIXED:
case CONST_VECTOR:
case CONST:
case SYMBOL_REF:
does use memory aliasing. */
int
-modified_in_p (rtx x, rtx insn)
+modified_in_p (const_rtx x, const_rtx insn)
{
- enum rtx_code code = GET_CODE (x);
+ const enum rtx_code code = GET_CODE (x);
const char *fmt;
int i, j;
{
case CONST_INT:
case CONST_DOUBLE:
+ case CONST_FIXED:
case CONST_VECTOR:
case CONST:
case SYMBOL_REF:
/* Helper function for set_of. */
struct set_of_data
{
- rtx found;
- rtx pat;
+ const_rtx found;
+ const_rtx pat;
};
static void
-set_of_1 (rtx x, rtx pat, void *data1)
+set_of_1 (rtx x, const_rtx pat, void *data1)
{
- struct set_of_data *data = (struct set_of_data *) (data1);
- if (rtx_equal_p (x, data->pat)
- || (!MEM_P (x) && reg_overlap_mentioned_p (data->pat, x)))
- data->found = pat;
+ struct set_of_data *const data = (struct set_of_data *) (data1);
+ if (rtx_equal_p (x, data->pat)
+ || (!MEM_P (x) && reg_overlap_mentioned_p (data->pat, x)))
+ data->found = pat;
}
/* Give an INSN, return a SET or CLOBBER expression that does modify PAT
(either directly or via STRICT_LOW_PART and similar modifiers). */
-rtx
-set_of (rtx pat, rtx insn)
+const_rtx
+set_of (const_rtx pat, const_rtx insn)
{
struct set_of_data data;
data.found = NULL_RTX;
will not be used, which we ignore. */
rtx
-single_set_2 (rtx insn, rtx pat)
+single_set_2 (const_rtx insn, const_rtx pat)
{
rtx set = NULL;
int set_verified = 1;
zero. */
int
-multiple_sets (rtx insn)
+multiple_sets (const_rtx insn)
{
int found;
int i;
and there are no side effects. */
int
-set_noop_p (rtx set)
+set_noop_p (const_rtx set)
{
rtx src = SET_SRC (set);
rtx dst = SET_DEST (set);
value to itself. */
int
-noop_move_p (rtx insn)
+noop_move_p (const_rtx insn)
{
rtx pat = PATTERN (insn);
LOC may be zero, meaning don't ignore anything. */
int
-refers_to_regno_p (unsigned int regno, unsigned int endregno, rtx x,
+refers_to_regno_p (unsigned int regno, unsigned int endregno, const_rtx x,
rtx *loc)
{
int i;
conflict because we expect this to be a rare case. */
int
-reg_overlap_mentioned_p (rtx x, rtx in)
+reg_overlap_mentioned_p (const_rtx x, const_rtx in)
{
unsigned int regno, endregno;
the SUBREG will be passed. */
void
-note_stores (rtx x, void (*fun) (rtx, rtx, void *), void *data)
+note_stores (const_rtx x, void (*fun) (rtx, const_rtx, void *), void *data)
{
int i;
by INSN. */
int
-dead_or_set_p (rtx insn, rtx x)
+dead_or_set_p (const_rtx insn, const_rtx x)
{
unsigned int regno, end_regno;
unsigned int i;
part of the register is TEST_REGNO. */
static bool
-covers_regno_no_parallel_p (rtx dest, unsigned int test_regno)
+covers_regno_no_parallel_p (const_rtx dest, unsigned int test_regno)
{
unsigned int regno, endregno;
any member matches the covers_regno_no_parallel_p criteria. */
static bool
-covers_regno_p (rtx dest, unsigned int test_regno)
+covers_regno_p (const_rtx dest, unsigned int test_regno)
{
if (GET_CODE (dest) == PARALLEL)
{
/* Utility function for dead_or_set_p to check an individual register. */
int
-dead_or_set_regno_p (rtx insn, unsigned int test_regno)
+dead_or_set_regno_p (const_rtx insn, unsigned int test_regno)
{
- rtx pattern;
+ const_rtx pattern;
/* See if there is a death note for something that includes TEST_REGNO. */
if (find_regno_note (insn, REG_DEAD, test_regno))
If DATUM is nonzero, look for one whose datum is DATUM. */
rtx
-find_reg_note (rtx insn, enum reg_note kind, rtx datum)
+find_reg_note (const_rtx insn, enum reg_note kind, const_rtx datum)
{
rtx link;
it might be the case that the note overlaps REGNO. */
rtx
-find_regno_note (rtx insn, enum reg_note kind, unsigned int regno)
+find_regno_note (const_rtx insn, enum reg_note kind, unsigned int regno)
{
rtx link;
has such a note. */
rtx
-find_reg_equal_equiv_note (rtx insn)
+find_reg_equal_equiv_note (const_rtx insn)
{
rtx link;
return null. */
rtx
-find_constant_src (rtx insn)
+find_constant_src (const_rtx insn)
{
rtx note, set, x;
in the CALL_INSN_FUNCTION_USAGE information of INSN. */
int
-find_reg_fusage (rtx insn, enum rtx_code code, rtx datum)
+find_reg_fusage (const_rtx insn, enum rtx_code code, const_rtx datum)
{
/* If it's not a CALL_INSN, it can't possibly have a
CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
in the CALL_INSN_FUNCTION_USAGE information of INSN. */
int
-find_regno_fusage (rtx insn, enum rtx_code code, unsigned int regno)
+find_regno_fusage (const_rtx insn, enum rtx_code code, unsigned int regno)
{
rtx link;
/* Return true if INSN is a call to a pure function. */
int
-pure_call_p (rtx insn)
+pure_call_p (const_rtx insn)
{
- rtx link;
+ const_rtx link;
if (!CALL_P (insn) || ! CONST_OR_PURE_CALL_P (insn))
return 0;
/* Remove register note NOTE from the REG_NOTES of INSN. */
void
-remove_note (rtx insn, rtx note)
+remove_note (rtx insn, const_rtx note)
{
rtx link;
NODE matches. */
int
-in_expr_list_p (rtx listp, rtx node)
+in_expr_list_p (const_rtx listp, const_rtx node)
{
- rtx x;
+ const_rtx x;
for (x = listp; x; x = XEXP (x, 1))
if (node == XEXP (x, 0))
A simple equality test is used to determine if NODE matches. */
void
-remove_node_from_expr_list (rtx node, rtx *listp)
+remove_node_from_expr_list (const_rtx node, rtx *listp)
{
rtx temp = *listp;
rtx prev = NULL_RTX;
only volatile asms and UNSPEC_VOLATILE instructions. */
int
-volatile_insn_p (rtx x)
+volatile_insn_p (const_rtx x)
{
- RTX_CODE code;
-
- code = GET_CODE (x);
+ const RTX_CODE code = GET_CODE (x);
switch (code)
{
case LABEL_REF:
case CONST_INT:
case CONST:
case CONST_DOUBLE:
+ case CONST_FIXED:
case CONST_VECTOR:
case CC0:
case PC:
/* Recursively scan the operands of this expression. */
{
- const char *fmt = GET_RTX_FORMAT (code);
+ const char *const fmt = GET_RTX_FORMAT (code);
int i;
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
int
-volatile_refs_p (rtx x)
+volatile_refs_p (const_rtx x)
{
- RTX_CODE code;
-
- code = GET_CODE (x);
+ const RTX_CODE code = GET_CODE (x);
switch (code)
{
case LABEL_REF:
case CONST_INT:
case CONST:
case CONST_DOUBLE:
+ case CONST_FIXED:
case CONST_VECTOR:
case CC0:
case PC:
/* Recursively scan the operands of this expression. */
{
- const char *fmt = GET_RTX_FORMAT (code);
+ const char *const fmt = GET_RTX_FORMAT (code);
int i;
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
incrementing. */
int
-side_effects_p (rtx x)
+side_effects_p (const_rtx x)
{
- RTX_CODE code;
-
- code = GET_CODE (x);
+ const RTX_CODE code = GET_CODE (x);
switch (code)
{
case LABEL_REF:
case CONST_INT:
case CONST:
case CONST_DOUBLE:
+ case CONST_FIXED:
case CONST_VECTOR:
case CC0:
case PC:
cannot trap at its current location, but it might become trapping if moved
elsewhere. */
-static int
-may_trap_p_1 (rtx x, unsigned flags)
+int
+may_trap_p_1 (const_rtx x, unsigned flags)
{
int i;
enum rtx_code code;
/* Handle these cases quickly. */
case CONST_INT:
case CONST_DOUBLE:
+ case CONST_FIXED:
case CONST_VECTOR:
case SYMBOL_REF:
case LABEL_REF:
case SCRATCH:
return 0;
- case ASM_INPUT:
+ case UNSPEC:
case UNSPEC_VOLATILE:
+ return targetm.unspec_may_trap_p (x, flags);
+
+ case ASM_INPUT:
case TRAP_IF:
return 1;
/* Return nonzero if evaluating rtx X might cause a trap. */
int
-may_trap_p (rtx x)
+may_trap_p (const_rtx x)
{
return may_trap_p_1 (x, 0);
}
is moved from its current location by some optimization. */
int
-may_trap_after_code_motion_p (rtx x)
+may_trap_after_code_motion_p (const_rtx x)
{
return may_trap_p_1 (x, MTP_AFTER_MOVE);
}
on a strict alignment machine. */
int
-may_trap_or_fault_p (rtx x)
+may_trap_or_fault_p (const_rtx x)
{
return may_trap_p_1 (x, MTP_UNALIGNED_MEMS);
}
i.e., an inequality. */
int
-inequality_comparisons_p (rtx x)
+inequality_comparisons_p (const_rtx x)
{
const char *fmt;
int len, i;
- enum rtx_code code = GET_CODE (x);
+ const enum rtx_code code = GET_CODE (x);
switch (code)
{
case CC0:
case CONST_INT:
case CONST_DOUBLE:
+ case CONST_FIXED:
case CONST_VECTOR:
case CONST:
case LABEL_REF:
*LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
bool
-tablejump_p (rtx insn, rtx *labelp, rtx *tablep)
+tablejump_p (const_rtx insn, rtx *labelp, rtx *tablep)
{
rtx label, table;
of an IF_THEN_ELSE. */
static int
-computed_jump_p_1 (rtx x)
+computed_jump_p_1 (const_rtx x)
{
- enum rtx_code code = GET_CODE (x);
+ const enum rtx_code code = GET_CODE (x);
int i, j;
const char *fmt;
case CONST:
case CONST_INT:
case CONST_DOUBLE:
+ case CONST_FIXED:
case CONST_VECTOR:
case SYMBOL_REF:
case REG:
we can recognize them by a (use (label_ref)). */
int
-computed_jump_p (rtx insn)
+computed_jump_p (const_rtx insn)
{
int i;
if (JUMP_P (insn))
{
rtx pat = PATTERN (insn);
- if (find_reg_note (insn, REG_LABEL, NULL_RTX))
+ /* If we have a JUMP_LABEL set, we're not a computed jump. */
+ if (JUMP_LABEL (insn) != NULL)
return 0;
- else if (GET_CODE (pat) == PARALLEL)
+
+ if (GET_CODE (pat) == PARALLEL)
{
int len = XVECLEN (pat, 0);
int has_use_labelref = 0;
/* Constants always come the second operand. Prefer "nice" constants. */
if (code == CONST_INT)
- return -7;
+ return -8;
if (code == CONST_DOUBLE)
- return -6;
+ return -7;
+ if (code == CONST_FIXED)
+ return -7;
op = avoid_constant_pool_reference (op);
code = GET_CODE (op);
{
case RTX_CONST_OBJ:
if (code == CONST_INT)
- return -5;
+ return -6;
if (code == CONST_DOUBLE)
- return -4;
- return -3;
+ return -5;
+ if (code == CONST_FIXED)
+ return -5;
+ return -4;
case RTX_EXTRA:
/* SUBREGs of objects should come second. */
if (code == SUBREG && OBJECT_P (SUBREG_REG (op)))
- return -2;
-
+ return -3;
return 0;
case RTX_OBJ:
/* Complex expressions should be the first, so decrease priority
- of objects. */
- return -1;
+ of objects. Prefer pointer objects over non pointer objects. */
+ if ((REG_P (op) && REG_POINTER (op))
+ || (MEM_P (op) && MEM_POINTER (op)))
+ return -1;
+ return -2;
case RTX_COMM_ARITH:
/* Prefer operands that are themselves commutative to be first.
/* Return 1 iff it is necessary to swap operands of commutative operation
in order to canonicalize expression. */
-int
+bool
swap_commutative_operands_p (rtx x, rtx y)
{
return (commutative_operand_precedence (x)
/* Return 1 if X is an autoincrement side effect and the register is
not the stack pointer. */
int
-auto_inc_p (rtx x)
+auto_inc_p (const_rtx x)
{
switch (GET_CODE (x))
{
/* Return nonzero if IN contains a piece of rtl that has the address LOC. */
int
-loc_mentioned_in_p (rtx *loc, rtx in)
+loc_mentioned_in_p (rtx *loc, const_rtx in)
{
enum rtx_code code;
const char *fmt;
fmt = GET_RTX_FORMAT (code);
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
{
- if (loc == &in->u.fld[i].rt_rtx)
- return 1;
if (fmt[i] == 'e')
{
- if (loc_mentioned_in_p (loc, XEXP (in, i)))
+ if (loc == &XEXP (in, i) || loc_mentioned_in_p (loc, XEXP (in, i)))
return 1;
}
else if (fmt[i] == 'E')
for (j = XVECLEN (in, i) - 1; j >= 0; j--)
- if (loc_mentioned_in_p (loc, XVECEXP (in, i, j)))
+ if (loc == &XVECEXP (in, i, j)
+ || loc_mentioned_in_p (loc, XVECEXP (in, i, j)))
return 1;
}
return 0;
(counting from the least significant bit of the reg). */
unsigned int
-subreg_lsb (rtx x)
+subreg_lsb (const_rtx x)
{
return subreg_lsb_1 (GET_MODE (x), GET_MODE (SUBREG_REG (x)),
SUBREG_BYTE (x));
/* Return the final regno that a subreg expression refers to. */
unsigned int
-subreg_regno (rtx x)
+subreg_regno (const_rtx x)
{
unsigned int ret;
rtx subreg = SUBREG_REG (x);
/* Return the number of registers that a subreg expression refers
to. */
unsigned int
-subreg_nregs (rtx x)
+subreg_nregs (const_rtx x)
+{
+ return subreg_nregs_with_regno (REGNO (SUBREG_REG (x)), x);
+}
+
+/* Return the number of registers that a subreg REG with REGNO
+ expression refers to. This is a copy of the rtlanal.c:subreg_nregs
+ changed so that the regno can be passed in. */
+
+unsigned int
+subreg_nregs_with_regno (unsigned int regno, const_rtx x)
{
struct subreg_info info;
rtx subreg = SUBREG_REG (x);
- int regno = REGNO (subreg);
subreg_get_info (regno, GET_MODE (subreg), SUBREG_BYTE (x), GET_MODE (x),
&info);
return info.nregs;
}
+
struct parms_set_data
{
int nregs;
/* Helper function for noticing stores to parameter registers. */
static void
-parms_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
+parms_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
{
struct parms_set_data *d = data;
if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER
call instruction. */
bool
-keep_with_call_p (rtx insn)
+keep_with_call_p (const_rtx insn)
{
rtx set;
if we can break or not. */
if (SET_DEST (set) == stack_pointer_rtx)
{
- rtx i2 = next_nonnote_insn (insn);
+ /* This CONST_CAST is okay because next_nonnote_insn just
+ returns it's argument and we assign it to a const_rtx
+ variable. */
+ const_rtx i2 = next_nonnote_insn (CONST_CAST_RTX(insn));
if (i2 && keep_with_call_p (i2))
return true;
}
not apply to the fallthru case of a conditional jump. */
bool
-label_is_jump_target_p (rtx label, rtx jump_insn)
+label_is_jump_target_p (const_rtx label, const_rtx jump_insn)
{
rtx tmp = JUMP_LABEL (jump_insn);
return true;
}
+ if (find_reg_note (jump_insn, REG_LABEL_TARGET, label))
+ return true;
+
return false;
}
\f
unsigned HOST_WIDE_INT
-nonzero_bits (rtx x, enum machine_mode mode)
+nonzero_bits (const_rtx x, enum machine_mode mode)
{
return cached_nonzero_bits (x, mode, NULL_RTX, VOIDmode, 0);
}
unsigned int
-num_sign_bit_copies (rtx x, enum machine_mode mode)
+num_sign_bit_copies (const_rtx x, enum machine_mode mode)
{
return cached_num_sign_bit_copies (x, mode, NULL_RTX, VOIDmode, 0);
}
identical subexpressions on the first or the second level. */
static unsigned HOST_WIDE_INT
-cached_nonzero_bits (rtx x, enum machine_mode mode, rtx known_x,
+cached_nonzero_bits (const_rtx x, enum machine_mode mode, const_rtx known_x,
enum machine_mode known_mode,
unsigned HOST_WIDE_INT known_ret)
{
an arithmetic operation, we can do better. */
static unsigned HOST_WIDE_INT
-nonzero_bits1 (rtx x, enum machine_mode mode, rtx known_x,
+nonzero_bits1 (const_rtx x, enum machine_mode mode, const_rtx known_x,
enum machine_mode known_mode,
unsigned HOST_WIDE_INT known_ret)
{
first or the second level. */
static unsigned int
-cached_num_sign_bit_copies (rtx x, enum machine_mode mode, rtx known_x,
+cached_num_sign_bit_copies (const_rtx x, enum machine_mode mode, const_rtx known_x,
enum machine_mode known_mode,
unsigned int known_ret)
{
be between 1 and the number of bits in MODE. */
static unsigned int
-num_sign_bit_copies1 (rtx x, enum machine_mode mode, rtx known_x,
+num_sign_bit_copies1 (const_rtx x, enum machine_mode mode, const_rtx known_x,
enum machine_mode known_mode,
unsigned int known_ret)
{
known_x, known_mode, known_ret);
num1 = cached_num_sign_bit_copies (XEXP (x, 1), mode,
known_x, known_mode, known_ret);
+
+ /* If num1 is clearing some of the top bits then regardless of
+ the other term, we are guaranteed to have at least that many
+ high-order zero bits. */
+ if (code == AND
+ && num1 > 1
+ && bitwidth <= HOST_BITS_PER_WIDE_INT
+ && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && !(INTVAL (XEXP (x, 1)) & ((HOST_WIDE_INT) 1 << (bitwidth - 1))))
+ return num1;
+
+ /* Similarly for IOR when setting high-order bits. */
+ if (code == IOR
+ && num1 > 1
+ && bitwidth <= HOST_BITS_PER_WIDE_INT
+ && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && (INTVAL (XEXP (x, 1)) & ((HOST_WIDE_INT) 1 << (bitwidth - 1))))
+ return num1;
+
return MIN (num0, num1);
case PLUS: case MINUS:
{
enum rtx_code code;
rtx prev = insn;
- rtx set;
+ const_rtx set;
rtx tem;
rtx op0, op1;
int reverse_code = 0;
assume it already contains a truncated value of MODE. */
bool
-truncated_to_mode (enum machine_mode mode, rtx x)
+truncated_to_mode (enum machine_mode mode, const_rtx x)
{
/* This register has already been used in MODE without explicit
truncation. */
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