/* This file contains the definitions and documentation for the
Register Transfer Expressions (rtx's) that make up the
Register Transfer Language (rtl) used in the Back End of the GNU compiler.
- Copyright (C) 1987, 88, 92, 94, 95, 97, 1998 Free Software Foundation, Inc.
+ Copyright (C) 1987, 88, 92, 94, 95, 97, 98, 1999, 2000
+ Free Software Foundation, Inc.
-This file is part of GNU CC.
+This file is part of GCC.
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 2, or (at your option) any later
+version.
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
+along with GCC; see the file COPYING. If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
/* Expression definitions and descriptions for all targets are in this file.
These names are stored in rtx_name[].
By convention these are the internal (field 1) names in lower_case.
- 3. The print format, and type of each rtx->fld[] (field) in this rtx.
+ 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
These formats are stored in rtx_format[].
The meaning of the formats is documented in front of this array in rtl.c
"i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
"m" an rtx code for something that matches in insns (e.g, MATCH_DUP)
"g" an rtx code for grouping insns together (e.g, GROUP_PARALLEL)
+ "a" an rtx code for autoincrement addressing modes (e.g. POST_DEC)
"x" everything else
*/
DEF_RTL_EXPR(NIL, "nil", "*", 'x')
+
+/* include a file */
+
+DEF_RTL_EXPR(INCLUDE, "include", "s", 'x')
+
/* ---------------------------------------------------------------------
Expressions used in constructing lists.
--------------------------------------------------------------------- */
DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm')
/* Appears only in machine descriptions.
- Should be used only in attribute tests.
- The predicate in operand 0 is applied to the whole insn being checked. */
-DEF_RTL_EXPR(MATCH_INSN, "match_insn", "s", 'm')
-
-/* Appears only in machine descriptions.
Operand 0 is the operand number, as in match_operand.
Operand 1 is the predicate to apply to the insn. */
-DEF_RTL_EXPR(MATCH_INSN2, "match_insn2", "is", 'm')
+DEF_RTL_EXPR(MATCH_INSN, "match_insn", "is", 'm')
/* Appears only in machine descriptions.
Defines the pattern for one kind of instruction.
template to use.
4: optionally, a vector of attributes for this insn.
*/
-DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEssV", 'x')
+DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", 'x')
/* Definition of a peephole optimization.
1st operand: vector of insn patterns to match
3rd operand: template or C code to produce assembler output.
4: optionally, a vector of attributes for this insn.
*/
-DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EssV", 'x')
+DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", 'x')
/* Definition of a split operation.
1st operand: insn pattern to match
3rd operand: vector of insn patterns to place into a SEQUENCE
4th operand: optionally, some C code to execute before generating the
insns. This might, for example, create some RTX's and store them in
- elements of `recog_operand' for use by the vector of insn-patterns.
- (`operands' is an alias here for `recog_operand'). */
+ elements of `recog_data.operand' for use by the vector of
+ insn-patterns.
+ (`operands' is an alias here for `recog_data.operand'). */
DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x')
+/* Definition of an insn and associated split.
+ This is the concatenation, with a few modifications, of a define_insn
+ and a define_split which share the same pattern.
+ Operand:
+ 0: names this instruction.
+ If the name is the null string, the instruction is in the
+ machine description just to be recognized, and will never be emitted by
+ the tree to rtl expander.
+ 1: is the pattern.
+ 2: is a string which is a C expression
+ giving an additional condition for recognizing this pattern.
+ A null string means no extra condition.
+ 3: is the action to execute if this pattern is matched.
+ If this assembler code template starts with a * then it is a fragment of
+ C code to run to decide on a template to use. Otherwise, it is the
+ template to use.
+ 4: C expression that must be true for split. This may start with "&&"
+ in which case the split condition is the logical and of the insn
+ condition and what follows the "&&" of this operand.
+ 5: vector of insn patterns to place into a SEQUENCE
+ 6: optionally, some C code to execute before generating the
+ insns. This might, for example, create some RTX's and store them in
+ elements of `recog_data.operand' for use by the vector of
+ insn-patterns.
+ (`operands' is an alias here for `recog_data.operand').
+ 7: optionally, a vector of attributes for this insn. */
+DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", 'x')
+
+/* Definition of an RTL peephole operation.
+ Follows the same arguments as define_split. */
+DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", 'x')
+
/* Definition of a combiner pattern.
Operands not defined yet. */
DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x')
/* Define how to generate multiple insns for a standard insn name.
1st operand: the insn name.
2nd operand: vector of insn-patterns.
- Use match_operand to substitute an element of `recog_operand'.
+ Use match_operand to substitute an element of `recog_data.operand'.
3rd operand: C expression that must be true for this to be available.
This may not test any operands.
4th operand: Extra C code to execute before generating the insns.
This might, for example, create some RTX's and store them in
- elements of `recog_operand' for use by the vector of insn-patterns.
- (`operands' is an alias here for `recog_operand'). */
+ elements of `recog_data.operand' for use by the vector of
+ insn-patterns.
+ (`operands' is an alias here for `recog_data.operand'). */
DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x')
/* Define a requirement for delay slots.
/* Define attribute computation for `asm' instructions. */
DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' )
+/* Definition of a conditional execution meta operation. Automatically
+ generates new instances of DEFINE_INSN, selected by having attribute
+ "predicable" true. The new pattern will contain a COND_EXEC and the
+ predicate at top-level.
+
+ Operand:
+ 0: The predicate pattern. The top-level form should match a
+ relational operator. Operands should have only one alternative.
+ 1: A C expression giving an additional condition for recognizing
+ the generated pattern.
+ 2: A template or C code to produce assembler output. */
+DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", 'x')
+
/* SEQUENCE appears in the result of a `gen_...' function
for a DEFINE_EXPAND that wants to make several insns.
Its elements are the bodies of the insns that should be made.
`emit_insn' takes the SEQUENCE apart and makes separate insns. */
DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x')
-/* Refers to the address of its argument.
- This appears only in machine descriptions, indicating that
- any expression that would be acceptable as the operand of MEM
- should be matched. */
+/* Refers to the address of its argument. This is only used in alias.c. */
DEF_RTL_EXPR(ADDRESS, "address", "e", 'm')
/* ----------------------------------------------------------------------
+ Constructions for CPU pipeline description described by NDFAs.
+ These do not appear in actual rtl code in the compiler.
+ ---------------------------------------------------------------------- */
+
+/* (define_cpu_unit string [string]) describes cpu functional
+ units (separated by comma).
+
+ 1st operand: Names of cpu functional units.
+ 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
+
+ All define_reservations, define_cpu_units, and
+ define_query_cpu_units should have unique names which may not be
+ "nothing". */
+DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", 'x')
+
+/* (define_query_cpu_unit string [string]) describes cpu functional
+ units analogously to define_cpu_unit. The reservation of such
+ units can be queried for automaton state. */
+DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", 'x')
+
+/* (exclusion_set string string) means that each CPU functional unit
+ in the first string can not be reserved simultaneously with any
+ unit whose name is in the second string and vise versa. CPU units
+ in the string are separated by commas. For example, it is useful
+ for description CPU with fully pipelined floating point functional
+ unit which can execute simultaneously only single floating point
+ insns or only double floating point insns. All CPU functional
+ units in a set should belong to the same automaton. */
+DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", 'x')
+
+/* (presence_set string string) means that each CPU functional unit in
+ the first string can not be reserved unless at least one of pattern
+ of units whose names are in the second string is reserved. This is
+ an asymmetric relation. CPU units or unit patterns in the strings
+ are separated by commas. Pattern is one unit name or unit names
+ separated by white-spaces.
+
+ For example, it is useful for description that slot1 is reserved
+ after slot0 reservation for a VLIW processor. We could describe it
+ by the following construction
+
+ (presence_set "slot1" "slot0")
+
+ Or slot1 is reserved only after slot0 and unit b0 reservation. In
+ this case we could write
+
+ (presence_set "slot1" "slot0 b0")
+
+ All CPU functional units in a set should belong to the same
+ automaton. */
+DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", 'x')
+
+/* (final_presence_set string string) is analogous to `presence_set'.
+ The difference between them is when checking is done. When an
+ instruction is issued in given automaton state reflecting all
+ current and planned unit reservations, the automaton state is
+ changed. The first state is a source state, the second one is a
+ result state. Checking for `presence_set' is done on the source
+ state reservation, checking for `final_presence_set' is done on the
+ result reservation. This construction is useful to describe a
+ reservation which is actually two subsequent reservations. For
+ example, if we use
+
+ (presence_set "slot1" "slot0")
+
+ the following insn will be never issued (because slot1 requires
+ slot0 which is absent in the source state).
+
+ (define_reservation "insn_and_nop" "slot0 + slot1")
+
+ but it can be issued if we use analogous `final_presence_set'. */
+DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", 'x')
+
+/* (absence_set string string) means that each CPU functional unit in
+ the first string can be reserved only if each pattern of units
+ whose names are in the second string is not reserved. This is an
+ asymmetric relation (actually exclusion set is analogous to this
+ one but it is symmetric). CPU units or unit patterns in the string
+ are separated by commas. Pattern is one unit name or unit names
+ separated by white-spaces.
+
+ For example, it is useful for description that slot0 can not be
+ reserved after slot1 or slot2 reservation for a VLIW processor. We
+ could describe it by the following construction
+
+ (absence_set "slot2" "slot0, slot1")
+
+ Or slot2 can not be reserved if slot0 and unit b0 are reserved or
+ slot1 and unit b1 are reserved . In this case we could write
+
+ (absence_set "slot2" "slot0 b0, slot1 b1")
+
+ All CPU functional units in a set should to belong the same
+ automaton. */
+DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", 'x')
+
+/* (final_absence_set string string) is analogous to `absence_set' but
+ checking is done on the result (state) reservation. See comments
+ for `final_presence_set'. */
+DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", 'x')
+
+/* (define_bypass number out_insn_names in_insn_names) names bypass
+ with given latency (the first number) from insns given by the first
+ string (see define_insn_reservation) into insns given by the second
+ string. Insn names in the strings are separated by commas. The
+ third operand is optional name of function which is additional
+ guard for the bypass. The function will get the two insns as
+ parameters. If the function returns zero the bypass will be
+ ignored for this case. Additional guard is necessary to recognize
+ complicated bypasses, e.g. when consumer is load address. */
+DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", 'x')
+
+/* (define_automaton string) describes names of automata generated and
+ used for pipeline hazards recognition. The names are separated by
+ comma. Actually it is possibly to generate the single automaton
+ but unfortunately it can be very large. If we use more one
+ automata, the summary size of the automata usually is less than the
+ single one. The automaton name is used in define_cpu_unit and
+ define_query_cpu_unit. All automata should have unique names. */
+DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", 'x')
+
+/* (automata_option string) describes option for generation of
+ automata. Currently there are the following options:
+
+ o "no-minimization" which makes no minimization of automata. This
+ is only worth to do when we are debugging the description and
+ need to look more accurately at reservations of states.
+
+ o "time" which means printing additional time statistics about
+ generation of automata.
+
+ o "v" which means generation of file describing the result
+ automata. The file has suffix `.dfa' and can be used for the
+ description verification and debugging.
+
+ o "w" which means generation of warning instead of error for
+ non-critical errors.
+
+ o "ndfa" which makes nondeterministic finite state automata. */
+DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", 'x')
+
+/* (define_reservation string string) names reservation (the first
+ string) of cpu functional units (the 2nd string). Sometimes unit
+ reservations for different insns contain common parts. In such
+ case, you can describe common part and use its name (the 1st
+ parameter) in regular expression in define_insn_reservation. All
+ define_reservations, define_cpu_units, and define_query_cpu_units
+ should have unique names which may not be "nothing". */
+DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", 'x')
+
+/* (define_insn_reservation name default_latency condition regexpr)
+ describes reservation of cpu functional units (the 3nd operand) for
+ instruction which is selected by the condition (the 2nd parameter).
+ The first parameter is used for output of debugging information.
+ The reservations are described by a regular expression according
+ the following syntax:
+
+ regexp = regexp "," oneof
+ | oneof
+
+ oneof = oneof "|" allof
+ | allof
+
+ allof = allof "+" repeat
+ | repeat
+
+ repeat = element "*" number
+ | element
+
+ element = cpu_function_unit_name
+ | reservation_name
+ | result_name
+ | "nothing"
+ | "(" regexp ")"
+
+ 1. "," is used for describing start of the next cycle in
+ reservation.
+
+ 2. "|" is used for describing the reservation described by the
+ first regular expression *or* the reservation described by the
+ second regular expression *or* etc.
+
+ 3. "+" is used for describing the reservation described by the
+ first regular expression *and* the reservation described by the
+ second regular expression *and* etc.
+
+ 4. "*" is used for convenience and simply means sequence in
+ which the regular expression are repeated NUMBER times with
+ cycle advancing (see ",").
+
+ 5. cpu functional unit name which means its reservation.
+
+ 6. reservation name -- see define_reservation.
+
+ 7. string "nothing" means no units reservation. */
+
+DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", 'x')
+
+/* ----------------------------------------------------------------------
Expressions used for insn attributes. These also do not appear in
actual rtl code in the compiler.
---------------------------------------------------------------------- */
/* Definition of an insn attribute.
1st operand: name of the attribute
2nd operand: comma-separated list of possible attribute values
- 3rd operand: expression for the default value of the attribute. */
+ 3rd operand: expression for the default value of the attribute. */
DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x')
-/* Marker for the name of an attribute. */
+/* Marker for the name of an attribute. */
DEF_RTL_EXPR(ATTR, "attr", "s", 'x')
/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
attribute name and the second is the comparison value. */
DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x')
+/* A special case of the above representing a set of alternatives. The first
+ operand is bitmap of the set, the second one is the default value. */
+DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", 'x')
+
/* A conditional expression which is true if the specified flag is
true for the insn being scheduled in reorg.
All formats must start with "iuu" to handle the chain.
Each insn expression holds an rtl instruction and its semantics
during back-end processing.
- See macros's in "rtl.h" for the meaning of each rtx->fld[].
+ See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
---------------------------------------------------------------------- */
/* An instruction that cannot jump. */
-DEF_RTL_EXPR(INSN, "insn", "iuueiee", 'i')
+DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", 'i')
/* An instruction that can possibly jump.
- Fields ( rtx->fld[] ) have exact same meaning as INSN's. */
-DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuueiee0", 'i')
+ Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
+DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", 'i')
/* An instruction that can possibly call a subroutine
but which will not change which instruction comes next
in the current function.
- Field ( rtx->fld[7] ) is CALL_INSN_FUNCTION_USAGE.
- All other fields ( rtx->fld[] ) have exact same meaning as INSN's. */
-DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuueieee", 'i')
+ Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE.
+ All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
+DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", 'i')
/* A marker that indicates that control will not flow through. */
-DEF_RTL_EXPR(BARRIER, "barrier", "iuu", 'x')
+DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", 'x')
/* Holds a label that is followed by instructions.
Operand:
- 3: is a number that is unique in the entire compilation.
- 4: is the user-given name of the label, if any.
- 5: is used in jump.c for the use-count of the label.
- 6: is used in flow.c to point to the chain of label_ref's to this label. */
-DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuis00", 'x')
-
-/* Say where in the code a source line starts, for symbol table's sake.
- Contains a filename and a line number. Line numbers <= 0 are special:
- 0 is used in a dummy placed at the front of every function
- just so there will never be a need to delete the first insn;
- -1 indicates a dummy; insns to be deleted by flow analysis and combining
- are really changed to NOTEs with a number of -1.
- -2 means beginning of a name binding contour; output N_LBRAC.
- -3 means end of a contour; output N_RBRAC. */
-DEF_RTL_EXPR(NOTE, "note", "iuusn", 'x')
+ 4: is used in jump.c for the use-count of the label.
+ 5: is used in flow.c to point to the chain of label_ref's to this label.
+ 6: is a number that is unique in the entire compilation.
+ 7: is the user-given name of the label, if any. */
+DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", 'x')
-/* INLINE_HEADER is use by inline function machinery. The information
- it contains helps to build the mapping function between the rtx's of
- the function to be inlined and the current function being expanded. */
-
-DEF_RTL_EXPR(INLINE_HEADER, "inline_header", "iuuuiiiiiieeiiEeEssE", 'x')
+/* Say where in the code a source line starts, for symbol table's sake.
+ Operand:
+ 4: filename, if line number > 0, note-specific data otherwise.
+ 5: line number if > 0, enum note_insn otherwise.
+ 6: unique number if line number == note_insn_deleted_label. */
+DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", 'x')
/* ----------------------------------------------------------------------
Top level constituents of INSN, JUMP_INSN and CALL_INSN.
---------------------------------------------------------------------- */
-/* Several operations to be done in parallel. */
+/* Conditionally execute code.
+ Operand 0 is the condition that if true, the code is executed.
+ Operand 1 is the code to be executed (typically a SET).
+
+ Semantics are that there are no side effects if the condition
+ is false. This pattern is created automatically by the if_convert
+ pass run after reload or by target-specific splitters. */
+DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", 'x')
+
+/* Several operations to be done in parallel (perhaps under COND_EXEC). */
DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x')
/* A string that is passed through to the assembler as input.
CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
compilations. */
-DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEeei", 'x')
+DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", 'x')
+
+/* Memory prefetch, with attributes supported on some targets.
+ Operand 1 is the address of the memory to fetch.
+ Operand 2 is 1 for a write access, 0 otherwise.
+ Operand 3 is the level of temporal locality; 0 means there is no
+ temporal locality and 1, 2, and 3 are for increasing levels of temporal
+ locality.
+
+ The attributes specified by operands 2 and 3 are ignored for targets
+ whose prefetch instructions do not support them. */
+DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", 'x')
/* ----------------------------------------------------------------------
At the top level of an instruction (perhaps under PARALLEL).
For an unconditional trap, make the condition (const_int 1). */
DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", 'x')
+/* Placeholder for _Unwind_Resume before we know if a function call
+ or a branch is needed. Operand 1 is the exception region from
+ which control is flowing. */
+DEF_RTL_EXPR(RESX, "resx", "i", 'x')
+
/* ----------------------------------------------------------------------
Primitive values for use in expressions.
---------------------------------------------------------------------- */
/* numeric integer constant */
DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o')
-/* numeric double constant.
- Operand 0 is the MEM that stores this constant in memory,
- or various other things (see comments at immed_double_const in varasm.c).
- Operand 1 is a chain of all CONST_DOUBLEs in use in the current function.
- Remaining operands hold the actual value.
- The number of operands may be more than 2 if cross-compiling;
- see init_rtl. */
-DEF_RTL_EXPR(CONST_DOUBLE, "const_double", "e0ww", 'o')
+/* numeric floating point constant.
+ Operands hold the value. They are all 'w' and there may be from 2 to 6;
+ see real.h. */
+DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, 'o')
+
+/* Describes a vector constant. */
+DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", 'x')
/* String constant. Used only for attributes right now. */
DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o')
by a SET whose first operand is (PC). */
DEF_RTL_EXPR(PC, "pc", "", 'o')
-/* A register. The "operand" is the register number, accessed
- with the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
- than a hardware register is being referred to. */
-DEF_RTL_EXPR(REG, "reg", "i", 'o')
+/* Used in the cselib routines to describe a value. */
+DEF_RTL_EXPR(VALUE, "value", "0", 'o')
+
+/* A register. The "operand" is the register number, accessed with
+ the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
+ than a hardware register is being referred to. The second operand
+ holds the original register number - this will be different for a
+ pseudo register that got turned into a hard register.
+ This rtx needs to have as many (or more) fields as a MEM, since we
+ can change REG rtx's into MEMs during reload. */
+DEF_RTL_EXPR(REG, "reg", "i00", 'o')
/* A scratch register. This represents a register used only within a
single insn. It will be turned into a REG during register allocation
in DECL_RTLs and during RTL generation, but not in the insn chain. */
DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o')
-/* A memory location; operand is the address.
- Can be nested inside a VOLATILE. */
-DEF_RTL_EXPR(MEM, "mem", "e", 'o')
+/* A memory location; operand is the address. The second operand is the
+ alias set to which this MEM belongs. We use `0' instead of `w' for this
+ field so that the field need not be specified in machine descriptions. */
+DEF_RTL_EXPR(MEM, "mem", "e0", 'o')
/* Reference to an assembler label in the code for this function.
The operand is a CODE_LABEL found in the insn chain.
LABEL_NEXTREF and CONTAINING_INSN. */
DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o')
-/* Reference to a named label: the string that is the first operand,
- with `_' added implicitly in front.
- Exception: if the first character explicitly given is `*',
- to give it to the assembler, remove the `*' and do not add `_'. */
-DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s", 'o')
+/* Reference to a named label:
+ Operand 0: label name
+ Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
+ Operand 2: tree from which this symbol is derived, or null.
+ This is either a DECL node, or some kind of constant. */
+DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", 'o')
/* The condition code register is represented, in our imagination,
as a register holding a value that can be compared to zero.
3rd operand: the decl for the object in the register, for
put_reg_in_stack. */
-DEF_RTL_EXPR(ADDRESSOF, "addressof", "ei0", 'o')
+DEF_RTL_EXPR(ADDRESSOF, "addressof", "eit", 'o')
/* =====================================================================
A QUEUED expression really points to a member of the queue of instructions
/* General conditional. The first operand is a vector composed of pairs of
expressions. The first element of each pair is evaluated, in turn.
The value of the conditional is the second expression of the first pair
- whose first expression evaluates non-zero. If none of the expressions is
+ whose first expression evaluates nonzero. If none of the expressions is
true, the second operand will be used as the value of the conditional.
This should be replaced with use of IF_THEN_ELSE. */
/* Operand:
0: value to be shifted.
1: number of bits. */
-DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2')
-DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2')
-
-/* Right shift operations, for machines where these are not the same
- as left shifting with a negative argument. */
-
-DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2')
-DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2')
-DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2')
+DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2') /* shift left */
+DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2') /* rotate left */
+DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2') /* arithmetic shift right */
+DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2') /* logical shift right */
+DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2') /* rotate right */
/* Minimum and maximum values of two operands. We need both signed and
unsigned forms. (We cannot use MIN for SMIN because it conflicts
containing MEM. These operations exist in only two cases:
1. pushes onto the stack.
2. created automatically by the life_analysis pass in flow.c. */
-DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'x')
-DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'x')
-DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'x')
-DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'x')
+DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'a')
+DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'a')
+DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'a')
+DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'a')
+
+/* These binary operations are used to represent generic address
+ side-effects in memory addresses, except for simple incrementation
+ or decrementation which use the above operations. They are
+ created automatically by the life_analysis pass in flow.c.
+ The first operand is a REG which is used as the address.
+ The second operand is an expression that is assigned to the
+ register, either before (PRE_MODIFY) or after (POST_MODIFY)
+ evaluating the address.
+ Currently, the compiler can only handle second operands of the
+ form (plus (reg) (reg)) and (plus (reg) (const_int)), where
+ the first operand of the PLUS has to be the same register as
+ the first operand of the *_MODIFY. */
+DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'a')
+DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'a')
/* Comparison operations. The ordered comparisons exist in two
flavors, signed and unsigned. */
DEF_RTL_EXPR(LEU, "leu", "ee", '<')
DEF_RTL_EXPR(LTU, "ltu", "ee", '<')
+/* Additional floating point unordered comparison flavors. */
+DEF_RTL_EXPR(UNORDERED, "unordered", "ee", '<')
+DEF_RTL_EXPR(ORDERED, "ordered", "ee", '<')
+
+/* These are equivalent to unordered or ... */
+DEF_RTL_EXPR(UNEQ, "uneq", "ee", '<')
+DEF_RTL_EXPR(UNGE, "unge", "ee", '<')
+DEF_RTL_EXPR(UNGT, "ungt", "ee", '<')
+DEF_RTL_EXPR(UNLE, "unle", "ee", '<')
+DEF_RTL_EXPR(UNLT, "unlt", "ee", '<')
+
+/* This is an ordered NE, ie !UNEQ, ie false for NaN. */
+DEF_RTL_EXPR(LTGT, "ltgt", "ee", '<')
+
/* Represents the result of sign-extending the sole operand.
The machine modes of the operand and of the SIGN_EXTEND expression
determine how much sign-extension is going on. */
or 0 if arg is 0. */
DEF_RTL_EXPR(FFS, "ffs", "e", '1')
+/* Count leading zeros. */
+DEF_RTL_EXPR(CLZ, "clz", "e", '1')
+
+/* Count trailing zeros. */
+DEF_RTL_EXPR(CTZ, "ctz", "e", '1')
+
+/* Population count (number of 1 bits). */
+DEF_RTL_EXPR(POPCOUNT, "popcount", "e", '1')
+
+/* Population parity (number of 1 bits modulo 2). */
+DEF_RTL_EXPR(PARITY, "parity", "e", '1')
+
/* Reference to a signed bit-field of specified size and position.
Operand 0 is the memory unit (usually SImode or QImode) which
contains the field's first bit. Operand 1 is the width, in bits.
of a constant expression. */
DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o')
-/* Header for range information. Operand 0 is the NOTE_INSN_RANGE_START insn.
+/* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn.
Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of
the registers that can be substituted within this range. Operand 3 is the
number of calls in the range. Operand 4 is the number of insns in the
live length. Operand 7 is the number of calls that this register is live
across. Operand 8 is the symbol node of the variable if the register is a
user variable. Operand 9 is the block node that the variable is declared
- in if the register is a user variable. */
+ in if the register is a user variable. */
DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", 'x')
/* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of
0 is the live bitmap. Operand 1 is the original block number. */
DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", 'x')
+/* A unary `__builtin_constant_p' expression. These are only emitted
+ during RTL generation, and then only if optimize > 0. They are
+ eliminated by the first CSE pass. */
+DEF_RTL_EXPR(CONSTANT_P_RTX, "constant_p_rtx", "e", 'x')
+
+/* A placeholder for a CALL_INSN which may be turned into a normal call,
+ a sibling (tail) call or tail recursion.
+
+ Immediately after RTL generation, this placeholder will be replaced
+ by the insns to perform the call, sibcall or tail recursion.
+
+ This RTX has 4 operands. The first three are lists of instructions to
+ perform the call as a normal call, sibling call and tail recursion
+ respectively. The latter two lists may be NULL, the first may never
+ be NULL.
+
+ The last operand is the tail recursion CODE_LABEL, which may be NULL if no
+ potential tail recursive calls were found.
+
+ The tail recursion label is needed so that we can clear LABEL_PRESERVE_P
+ after we select a call method.
+
+ This method of tail-call elimination is intended to be replaced by
+ tree-based optimizations once front-end conversions are complete. */
+DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x')
+
+/* Describes a merge operation between two vector values.
+ Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
+ that specifies where the parts of the result are taken from. Set bits
+ indicate operand 0, clear bits indicate operand 1. The parts are defined
+ by the mode of the vectors. */
+DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", '3')
+
+/* Describes an operation that selects parts of a vector.
+ Operands 0 is the source vector, operand 1 is a PARALLEL that contains
+ a CONST_INT for each of the subparts of the result vector, giving the
+ number of the source subpart that should be stored into it. */
+DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", '2')
+
+/* Describes a vector concat operation. Operands 0 and 1 are the source
+ vectors, the result is a vector that is as long as operands 0 and 1
+ combined and is the concatenation of the two source vectors. */
+DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", '2')
+
+/* Describes an operation that converts a small vector into a larger one by
+ duplicating the input values. The output vector mode must have the same
+ submodes as the input vector mode, and the number of output parts must be
+ an integer multiple of the number of input parts. */
+DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", '1')
+
+/* Addition with signed saturation */
+DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", 'c')
+
+/* Addition with unsigned saturation */
+DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", 'c')
+
+/* Operand 0 minus operand 1, with signed saturation. */
+DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", '2')
+
+/* Operand 0 minus operand 1, with unsigned saturation. */
+DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", '2')
+
+/* Signed saturating truncate. */
+DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", '1')
+
+/* Unsigned saturating truncate. */
+DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", '1')
+
+
/*
Local variables:
mode:c
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