-fcompare-elim -fcprop-registers -fcrossjumping @gol
-fcse-follow-jumps -fcse-skip-blocks -fcx-fortran-rules @gol
-fcx-limited-range @gol
--fdata-sections -fdce -fdce -fdelayed-branch @gol
--fdelete-null-pointer-checks -fdse -fdevirtualize -fdse @gol
+-fdata-sections -fdce -fdelayed-branch @gol
+-fdelete-null-pointer-checks -fdevirtualize -fdse @gol
-fearly-inlining -fipa-sra -fexpensive-optimizations -ffat-lto-objects @gol
-ffast-math -ffinite-math-only -ffloat-store -fexcess-precision=@var{style} @gol
-fforward-propagate -ffp-contract=@var{style} -ffunction-sections @gol
-mprefergot -musermode -multcost=@var{number} -mdiv=@var{strategy} @gol
-mdivsi3_libfunc=@var{name} -mfixed-range=@var{register-range} @gol
-madjust-unroll -mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol
--maccumulate-outgoing-args -minvalid-symbols -msoft-atomic}
+-maccumulate-outgoing-args -minvalid-symbols -msoft-atomic @gol
+-mbranch-cost=@var{num} -mcbranchdi -mcmpeqdi -mfused-madd -mpretend-cmove}
@emph{Solaris 2 Options}
@gccoptlist{-mimpure-text -mno-impure-text @gol
@itemx iso9899:1999
@itemx iso9899:199x
ISO C99. Note that this standard is not yet fully supported; see
-@w{@uref{http://gcc.gnu.org/c99status.html}} for more information. The
+@w{@uref{http://gcc.gnu.org/gcc-4.7/c99status.html}} for more information. The
names @samp{c9x} and @samp{iso9899:199x} are deprecated.
@item c11
@item -fstrict-enums
@opindex fstrict-enums
Allow the compiler to optimize using the assumption that a value of
-enumeration type can only be one of the values of the enumeration (as
+enumerated type can only be one of the values of the enumeration (as
defined in the C++ standard; basically, a value that can be
represented in the minimum number of bits needed to represent all the
enumerators). This assumption may not be valid if the program uses a
-cast to convert an arbitrary integer value to the enumeration type.
+cast to convert an arbitrary integer value to the enumerated type.
@item -ftemplate-depth=@var{n}
@opindex ftemplate-depth
do not warn but -fstrict-aliasing still breaks the code, as it has very few
false negatives. However, it has many false positives.
Warns for all pointer conversions between possibly incompatible types,
-even if never dereferenced. Runs in the frontend only.
+even if never dereferenced. Runs in the front end only.
Level 2: Aggressive, quick, not too precise.
May still have many false positives (not as many as level 1 though),
and few false negatives (but possibly more than level 1).
Unlike level 1, it only warns when an address is taken. Warns about
-incomplete types. Runs in the frontend only.
+incomplete types. Runs in the front end only.
Level 3 (default for @option{-Wstrict-aliasing}):
Should have very few false positives and few false
negatives. Slightly slower than levels 1 or 2 when optimization is enabled.
-Takes care of the common pun+dereference pattern in the frontend:
+Takes care of the common pun+dereference pattern in the front end:
@code{*(int*)&some_float}.
-If optimization is enabled, it also runs in the backend, where it deals
+If optimization is enabled, it also runs in the back end, where it deals
with multiple statement cases using flow-sensitive points-to information.
Only warns when the converted pointer is dereferenced.
Does not warn about incomplete types.
@item -Wenum-compare
@opindex Wenum-compare
@opindex Wno-enum-compare
-Warn about a comparison between values of different enum types. In C++
-this warning is enabled by default. In C this warning is enabled by
-@option{-Wall}.
+Warn about a comparison between values of different enumerated types.
+In C++ enumeral mismatches in conditional expressions are also
+diagnosed and the warning is enabled by default. In C this warning is
+enabled by @option{-Wall}.
@item -Wjump-misses-init @r{(C, Objective-C only)}
@opindex Wjump-misses-init
forward across the initialization of a variable, or jumps backward to a
label after the variable has been initialized. This only warns about
variables that are initialized when they are declared. This warning is
-only supported for C and Objective C; in C++ this sort of branch is an
+only supported for C and Objective-C; in C++ this sort of branch is an
error in any case.
@option{-Wjump-misses-init} is included in @option{-Wc++-compat}. It
@itemx -fdump-rtl-pro_and_epilogue
@opindex fdump-rtl-pro_and_epilogue
-Dump after generating the function pro and epilogues.
+Dump after generating the function prologues and epilogues.
@item -fdump-rtl-regmove
@opindex fdump-rtl-regmove
Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}.
@item -fira-algorithm=@var{algorithm}
-Use specified coloring algorithm for the integrated register
-allocator. The @var{algorithm} argument should be @code{priority} or
-@code{CB}. The first algorithm specifies Chow's priority coloring,
-the second one specifies Chaitin-Briggs coloring. The second
-algorithm can be unimplemented for some architectures. If it is
-implemented, it is the default because Chaitin-Briggs coloring as a
-rule generates a better code.
+Use the specified coloring algorithm for the integrated register
+allocator. The @var{algorithm} argument can be @samp{priority}, which
+specifies Chow's priority coloring, or @samp{CB}, which specifies
+Chaitin-Briggs coloring. Chaitin-Briggs coloring is not implemented
+for all architectures, but for those targets that do support it, it is
+the default because it generates better code.
@item -fira-region=@var{region}
Use specified regions for the integrated register allocator. The
-@var{region} argument should be one of @code{all}, @code{mixed}, or
-@code{one}. The first value means using all loops as register
-allocation regions, the second value which is enabled by default when
-compiling with optimization for speed (@option{-O}, @option{-O2},
-@dots{}) means using all loops except for loops with small register
-pressure as the regions, and third one which is enabled by default for
-@option{-Os} or @option{-O0} means using all function as a single
-region. The first value can give best result for machines with small
-size and irregular register set, the third one results in faster and
-generates decent code and the smallest size code, and the second value
-usually give the best results in most cases and for most
-architectures.
+@var{region} argument should be one of the following:
+
+@table @samp
+
+@item all
+Use all loops as register allocation regions.
+This can give the best results for machines with a small and/or
+irregular register set.
+
+@item mixed
+Use all loops except for loops with small register pressure
+as the regions. This value usually gives
+the best results in most cases and for most architectures,
+and is enabled by default when compiling with optimization for speed
+(@option{-O}, @option{-O2}, @dots{}).
+
+@item one
+Use all functions as a single region.
+This typically results in the smallest code size, and is enabled by default for
+@option{-Os} or @option{-O0}.
+
+@end table
@item -fira-loop-pressure
@opindex fira-loop-pressure
-Use IRA to evaluate register pressure in loops for decision to move
-loop invariants. Usage of this option usually results in generation
-of faster and smaller code on machines with big register files (>= 32
-registers) but it can slow compiler down.
+Use IRA to evaluate register pressure in loops for decisions to move
+loop invariants. This option usually results in generation
+of faster and smaller code on machines with large register files (>= 32
+registers), but it can slow the compiler down.
This option is enabled at level @option{-O3} for some targets.
@item -fno-ira-share-save-slots
@opindex fno-ira-share-save-slots
-Switch off sharing stack slots used for saving call used hard
-registers living through a call. Each hard register will get a
-separate stack slot and as a result function stack frame will be
-bigger.
+Disable sharing of stack slots used for saving call-used hard
+registers living through a call. Each hard register gets a
+separate stack slot, and as a result function stack frames are
+larger.
@item -fno-ira-share-spill-slots
@opindex fno-ira-share-spill-slots
-Switch off sharing stack slots allocated for pseudo-registers. Each
-pseudo-register that did not get a hard register will get a separate
-stack slot and as a result function stack frame will be bigger.
+Disable sharing of stack slots allocated for pseudo-registers. Each
+pseudo-register that does not get a hard register gets a separate
+stack slot, and as a result function stack frames are larger.
@item -fira-verbose=@var{n}
@opindex fira-verbose
-Set up how verbose dump file for the integrated register allocator
-will be. Default value is 5. If the value is greater or equal to 10,
-the dump file will be stderr as if the value were @var{n} minus 10.
+Control the verbosity of the dump file for the integrated register allocator.
+The default value is 5. If the value @var{n} is greater or equal to 10,
+the dump output is sent to stderr using the same format as @var{n} minus 10.
@item -fdelayed-branch
@opindex fdelayed-branch
@item -floop-flatten
@opindex floop-flatten
Removes the loop nesting structure: transforms the loop nest into a
-single loop. This transformation can be useful to vectorize all the
-levels of the loop nest.
+single loop. This transformation can be useful as an enablement
+transform for vectorization and parallelization. This feature
+is experimental.
+To use this code transformation, GCC has to be configured
+with @option{--with-ppl} and @option{--with-cloog} to enable the
+Graphite loop transformation infrastructure.
@item -floop-parallelize-all
@opindex floop-parallelize-all
limit after inlining, inlining is constrained by
@option{--param large-function-growth}. This parameter is useful primarily
to avoid extreme compilation time caused by non-linear algorithms used by the
-backend.
+back end.
The default value is 2700.
@item large-function-growth
@item max-tail-merge-comparisons
The maximum amount of similar bbs to compare a bb with. This is used to
-avoid quadratic behaviour in tree tail merging. The default value is 10.
+avoid quadratic behavior in tree tail merging. The default value is 10.
@item max-tail-merge-iterations
The maximum amount of iterations of the pass over the function. This is used to
be disabled. The default maximum SCC size is 10000.
@item ira-max-loops-num
-IRA uses a regional register allocation by default. If a function
-contains loops more than number given by the parameter, only at most
-given number of the most frequently executed loops will form regions
-for the regional register allocation. The default value of the
+IRA uses regional register allocation by default. If a function
+contains more loops than the number given by this parameter, only at most
+the given number of the most frequently-executed loops form regions
+for regional register allocation. The default value of the
parameter is 100.
-@item ira-max-conflict-table-size
-Although IRA uses a sophisticated algorithm of compression conflict
-table, the table can be still big for huge functions. If the conflict
-table for a function could be more than size in MB given by the
-parameter, the conflict table is not built and faster, simpler, and
-lower quality register allocation algorithm will be used. The
-algorithm do not use pseudo-register conflicts. The default value of
-the parameter is 2000.
+@item ira-max-conflict-table-size
+Although IRA uses a sophisticated algorithm to compress the conflict
+table, the table can still require excessive amounts of memory for
+huge functions. If the conflict table for a function could be more
+than the size in MB given by this parameter, the register allocator
+instead uses a faster, simpler, and lower-quality
+algorithm that does not require building a pseudo-register conflict table.
+The default value of the parameter is 2000.
@item ira-loop-reserved-regs
IRA can be used to evaluate more accurate register pressure in loops
-for decision to move loop invariants (see @option{-O3}). The number
-of available registers reserved for some other purposes is described
-by this parameter. The default value of the parameter is 2 which is
-minimal number of registers needed for execution of typical
-instruction. This value is the best found from numerous experiments.
+for decisions to move loop invariants (see @option{-O3}). The number
+of available registers reserved for some other purposes is given
+by this parameter. The default value of the parameter is 2, which is
+the minimal number of registers needed by typical instructions.
+This value is the best found from numerous experiments.
@item loop-invariant-max-bbs-in-loop
Loop invariant motion can be very expensive, both in compilation time and
@item -mno-sched-prolog
@opindex mno-sched-prolog
-Prevent the reordering of instructions in the function prolog, or the
+Prevent the reordering of instructions in the function prologue, or the
merging of those instruction with the instructions in the function's
body. This means that all functions will start with a recognizable set
of instructions (or in fact one of a choice from a small set of
@option{-mcpu=native} causes the compiler to auto-detect the CPU
of the build computer. At present, this feature is only supported on
-Linux, and not all architectures are recognised. If the auto-detect is
+Linux, and not all architectures are recognized. If the auto-detect is
unsuccessful the option has no effect.
@item -mtune=@var{name}
@option{-mtune=native} causes the compiler to auto-detect the CPU
of the build computer. At present, this feature is only supported on
-Linux, and not all architectures are recognised. If the auto-detect is
+Linux, and not all architectures are recognized. If the auto-detect is
unsuccessful the option has no effect.
@item -march=@var{name}
@option{-march=native} causes the compiler to auto-detect the architecture
of the build computer. At present, this feature is only supported on
-Linux, and not all architectures are recognised. If the auto-detect is
+Linux, and not all architectures are recognized. If the auto-detect is
unsuccessful the option has no effect.
@item -mfpu=@var{name}
@subsection AVR Options
@cindex AVR Options
-These options are defined for AVR implementations:
-
@table @gcctabopt
@item -mmcu=@var{mcu}
@opindex mmcu
Specify Atmel AVR instruction set architectures (ISA) or MCU type.
-For a complete list of @var{mcu} values that are supported by avr-gcc,
-see the compiler output when called with the @code{--help=target}
+For a complete list of @var{mcu} values that are supported by @command{avr-gcc},
+see the compiler output when called with the @option{--help=target}
command line option.
The default for this option is@tie{}@code{avr2}.
-avr-gcc supports the following AVR devices and ISAs:
+GCC supports the following AVR devices and ISAs:
@table @code
-@item avr1
-This ISA is implemented by the minimal AVR core and supported
-for assembler only.
-@*@var{mcu}@tie{}= @code{at90s1200},
-@code{attiny10}, @code{attiny11}, @code{attiny12}, @code{attiny15},
-@code{attiny28}.
-
@item avr2
``Classic'' devices with up to 8@tie{}KiB of program memory.
-@*@var{mcu}@tie{}= @code{at90s2313}, @code{attiny26}, @code{at90c8534},
-@dots{}
+@*@var{mcu}@tie{}= @code{at90c8534}, @code{at90s2313},
+@code{at90s2323}, @code{at90s2333}, @code{at90s2343},
+@code{at90s4414}, @code{at90s4433}, @code{at90s4434},
+@code{at90s8515}, @code{at90s8535}, @code{attiny22}, @code{attiny26}.
@item avr25
``Classic'' devices with up to 8@tie{}KiB of program memory and with
the @code{MOVW} instruction.
-@*@var{mcu}@tie{}= @code{attiny2313}, @code{attiny261}, @code{attiny24},
-@dots{}
+@*@var{mcu}@tie{}= @code{at86rf401}, @code{ata6289}, @code{attiny13},
+@code{attiny13a}, @code{attiny2313}, @code{attiny2313a},
+@code{attiny24}, @code{attiny24a}, @code{attiny25}, @code{attiny261},
+@code{attiny261a}, @code{attiny4313}, @code{attiny43u},
+@code{attiny44}, @code{attiny44a}, @code{attiny45}, @code{attiny461},
+@code{attiny461a}, @code{attiny48}, @code{attiny84}, @code{attiny84a},
+@code{attiny85}, @code{attiny861}, @code{attiny861a}, @code{attiny87},
+@code{attiny88}.
@item avr3
-``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of program memory.
+``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of program memory.
@*@var{mcu}@tie{}= @code{at43usb355}, @code{at76c711}.
@item avr31
``Classic'' devices with 128@tie{}KiB of program memory.
-@*@var{mcu}@tie{}= @code{atmega103}, @code{at43usb320}.
+@*@var{mcu}@tie{}= @code{at43usb320}, @code{atmega103}.
@item avr35
``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of program
memory and with the @code{MOVW} instruction.
-@*@var{mcu}@tie{}= @code{at90usb162}, @code{atmega8u2},
-@code{attiny167}, @dots{}
+@*@var{mcu}@tie{}= @code{at90usb162}, @code{at90usb82},
+@code{atmega16u2}, @code{atmega32u2}, @code{atmega8u2},
+@code{attiny167}.
@item avr4
``Enhanced'' devices with up to 8@tie{}KiB of program memory.
-@*@var{mcu}@tie{}= @code{atmega8}, @code{atmega88}, @code{at90pwm81},
-@dots{}
+@*@var{mcu}@tie{}= @code{at90pwm1}, @code{at90pwm2}, @code{at90pwm2b},
+@code{at90pwm3}, @code{at90pwm3b}, @code{at90pwm81}, @code{atmega48},
+@code{atmega48a}, @code{atmega48p}, @code{atmega8}, @code{atmega8515},
+@code{atmega8535}, @code{atmega88}, @code{atmega88a},
+@code{atmega88p}, @code{atmega88pa}, @code{atmega8hva}.
@item avr5
``Enhanced'' devices with 16@tie{}KiB up to 64@tie{}KiB of program memory.
-@*@var{mcu}@tie{}= @code{atmega16}, @code{atmega6490}, @code{at90can64},
-@dots{}
+@*@var{mcu}@tie{}= @code{at90can32}, @code{at90can64},
+@code{at90pwm216}, @code{at90pwm316}, @code{at90scr100},
+@code{at90usb646}, @code{at90usb647}, @code{at94k}, @code{atmega16},
+@code{atmega161}, @code{atmega162}, @code{atmega163},
+@code{atmega164a}, @code{atmega164p}, @code{atmega165},
+@code{atmega165a}, @code{atmega165p}, @code{atmega168},
+@code{atmega168a}, @code{atmega168p}, @code{atmega169},
+@code{atmega169a}, @code{atmega169p}, @code{atmega169pa},
+@code{atmega16a}, @code{atmega16hva}, @code{atmega16hva2},
+@code{atmega16hvb}, @code{atmega16m1}, @code{atmega16u4},
+@code{atmega32}, @code{atmega323}, @code{atmega324a},
+@code{atmega324p}, @code{atmega324pa}, @code{atmega325},
+@code{atmega3250}, @code{atmega3250a}, @code{atmega3250p},
+@code{atmega325a}, @code{atmega325p}, @code{atmega328},
+@code{atmega328p}, @code{atmega329}, @code{atmega3290},
+@code{atmega3290a}, @code{atmega3290p}, @code{atmega329a},
+@code{atmega329p}, @code{atmega329pa}, @code{atmega32c1},
+@code{atmega32hvb}, @code{atmega32m1}, @code{atmega32u4},
+@code{atmega32u6}, @code{atmega406}, @code{atmega64},
+@code{atmega640}, @code{atmega644}, @code{atmega644a},
+@code{atmega644p}, @code{atmega644pa}, @code{atmega645},
+@code{atmega6450}, @code{atmega6450a}, @code{atmega6450p},
+@code{atmega645a}, @code{atmega645p}, @code{atmega649},
+@code{atmega6490}, @code{atmega649a}, @code{atmega649p},
+@code{atmega64c1}, @code{atmega64hve}, @code{atmega64m1},
+@code{m3000}.
@item avr51
``Enhanced'' devices with 128@tie{}KiB of program memory.
-@*@var{mcu}@tie{}= @code{atmega128}, @code{at90can128}, @code{at90usb1287},
-@dots{}
+@*@var{mcu}@tie{}= @code{at90can128}, @code{at90usb1286},
+@code{at90usb1287}, @code{atmega128}, @code{atmega1280},
+@code{atmega1281}, @code{atmega1284p}, @code{atmega128rfa1}.
@item avr6
-``Enhanced'' devices with 3-byte PC, i.e.@: with at least 256@tie{}KiB
-of program memory.
+``Enhanced'' devices with 3-byte PC, i.e.@: with more than
+128@tie{}KiB of program memory.
@*@var{mcu}@tie{}= @code{atmega2560}, @code{atmega2561}.
-@end table
+@item avrxmega2
+``XMEGA'' devices with more than 8@tie{}KiB and up to 64@tie{}KiB of
+program memory.
+@*@var{mcu}@tie{}= @code{atxmega16a4}, @code{atxmega16d4},
+@code{atxmega16x1}, @code{atxmega32a4}, @code{atxmega32d4},
+@code{atxmega32x1}.
+
+@item avrxmega4
+``XMEGA'' devices with more than 64@tie{}KiB and up to 128@tie{}KiB of
+program memory.
+@*@var{mcu}@tie{}= @code{atxmega64a3}, @code{atxmega64d3}.
+
+@item avrxmega5
+``XMEGA'' devices with more than 64@tie{}KiB and up to 128@tie{}KiB of
+program memory and more than 64@tie{}KiB of RAM.
+@*@var{mcu}@tie{}= @code{atxmega64a1}, @code{atxmega64a1u}.
+
+@item avrxmega6
+``XMEGA'' devices with more than 128@tie{}KiB of program memory.
+@*@var{mcu}@tie{}= @code{atxmega128a3}, @code{atxmega128d3},
+@code{atxmega192a3}, @code{atxmega192d3}, @code{atxmega256a3},
+@code{atxmega256a3b}, @code{atxmega256a3bu}, @code{atxmega256d3}.
+
+@item avrxmega7
+``XMEGA'' devices with more than 128@tie{}KiB of program memory and
+more than 64@tie{}KiB of RAM.
+@*@var{mcu}@tie{}= @code{atxmega128a1}, @code{atxmega128a1u}.
+
+@item avr1
+This ISA is implemented by the minimal AVR core and supported for
+assembler only.
+@*@var{mcu}@tie{}= @code{at90s1200}, @code{attiny11}, @code{attiny12},
+@code{attiny15}, @code{attiny28}.
+@end table
@item -maccumulate-args
@opindex maccumulate-args
@item -mcall-prologues
@opindex mcall-prologues
-Functions prologues/epilogues expanded as call to appropriate
-subroutines. Code size will be smaller.
+Functions prologues/epilogues are expanded as calls to appropriate
+subroutines. Code size is smaller.
@item -mint8
@opindex mint8
-Assume int to be 8-bit integer. This affects the sizes of all types: a
-char will be 1 byte, an int will be 1 byte, a long will be 2 bytes
-and long long will be 4 bytes. Please note that this option does not
-comply to the C standards, but it will provide you with smaller code
+Assume @code{int} to be 8-bit integer. This affects the sizes of all types: a
+@code{char} is 1 byte, an @code{int} is 1 byte, a @code{long} is 2 bytes,
+and @code{long long} is 4 bytes. Please note that this option does not
+conform to the C standards, but it results in smaller code
size.
@item -mno-interrupts
@opindex mno-interrupts
Generated code is not compatible with hardware interrupts.
-Code size will be smaller.
+Code size is smaller.
@item -mrelax
@opindex mrelax
Jump relaxing is performed by the linker because jump offsets are not
known before code is located. Therefore, the assembler code generated by the
-compiler will be the same, but the instructions in the executable may
+compiler is the same, but the instructions in the executable may
differ from instructions in the assembler code.
+Relaxing must be turned on if linker stubs are needed, see the
+section on @code{EIND} and linker stubs below.
+
@item -mshort-calls
@opindex mshort-calls
Use @code{RCALL}/@code{RJMP} instructions even on devices with
have the @code{CALL} and @code{JMP} instructions.
See also the @code{-mrelax} command line option.
+@item -msp8
+@opindex msp8
+Treat the stack pointer register as an 8-bit register,
+i.e.@: assume the high byte of the stack pointer is zero.
+In general, you don't need to set this option by hand.
+
+This option is used internally by the compiler to select and
+build multilibs for architectures @code{avr2} and @code{avr25}.
+These architectures mix devices with and without @code{SPH}.
+For any setting other than @code{-mmcu=avr2} or @code{-mmcu=avr25}
+the compiler driver will add or remove this option from the compiler
+proper's command line, because the compiler then knows if the device
+or architecture has an 8-bit stack pointer and thus no @code{SPH}
+register or not.
+
@item -mstrict-X
@opindex mstrict-X
Use address register @code{X} in a way proposed by the hardware. This means
-that @code{X} will only be used in indirect, post-increment or
+that @code{X} is only used in indirect, post-increment or
pre-decrement addressing.
Without this option, the @code{X} register may be used in the same way
as @code{Y} or @code{Z} which then is emulated by additional
instructions.
For example, loading a value with @code{X+const} addressing with a
-small non-negative @code{const < 64} to a register @var{Rn} will be
+small non-negative @code{const < 64} to a register @var{Rn} is
performed as
@example
@item -mtiny-stack
@opindex mtiny-stack
-Only use the lower 8@tie{}bits of the stack pointer and assume that the high
-byte of SP is always zero.
+Only change the lower 8@tie{}bits of the stack pointer.
@end table
@subsubsection @code{EIND} and Devices with more than 128 Ki Bytes of Flash
-
+@cindex @code{EIND}
Pointers in the implementation are 16@tie{}bits wide.
The address of a function or label is represented as word address so
that indirect jumps and calls can target any code address in the
The compiler never sets @code{EIND}.
@item
-The startup code from libgcc never sets @code{EIND}.
-Notice that startup code is a blend of code from libgcc and avr-libc.
-For the impact of avr-libc on @code{EIND}, see the
-@w{@uref{http://nongnu.org/avr-libc/user-manual,avr-libc user manual}}.
-
-@item
The compiler uses @code{EIND} implicitely in @code{EICALL}/@code{EIJMP}
instructions or might read @code{EIND} directly in order to emulate an
indirect call/jump by means of a @code{RET} instruction.
prologue/epilogue.
@item
+For indirect calls to functions and computed goto, the linker
+generates @emph{stubs}. Stubs are jump pads sometimes also called
+@emph{trampolines}. Thus, the indirect call/jump jumps to such a stub.
+The stub contains a direct jump to the desired address.
+
+@item
+Linker relaxation must be turned on so that the linker will generate
+the stubs correctly an all situaltion. See the compiler option
+@code{-mrelax} and the linler option @code{--relax}.
+There are corner cases where the linker is supposed to generate stubs
+but aborts without relaxation and without a helpful error message.
+
+@item
+The default linker script is arranged for code with @code{EIND = 0}.
+If code is supposed to work for a setup with @code{EIND != 0}, a custom
+linker script has to be used in order to place the sections whose
+name start with @code{.trampolines} into the segment where @code{EIND}
+points to.
+
+@item
+The startup code from libgcc never sets @code{EIND}.
+Notice that startup code is a blend of code from libgcc and AVR-LibC.
+For the impact of AVR-LibC on @code{EIND}, see the
+@w{@uref{http://nongnu.org/avr-libc/user-manual,AVR-LibC user manual}}.
+
+@item
It is legitimate for user-specific startup code to set up @code{EIND}
early, for example by means of initialization code located in
section @code{.init3}. Such code runs prior to general startup code
-that initializes RAM and calls constructors.
+that initializes RAM and calls constructors, but after the bit
+of startup code from AVR-LibC that sets @code{EIND} to the segment
+where the vector table is located.
+@example
+#include <avr/io.h>
-@item
-For indirect calls to functions and computed goto, the linker will
-generate @emph{stubs}. Stubs are jump pads sometimes also called
-@emph{trampolines}. Thus, the indirect call/jump will jump to such a stub.
-The stub contains a direct jump to the desired address.
+static void
+__attribute__((section(".init3"),naked,used,no_instrument_function))
+init3_set_eind (void)
+@{
+ __asm volatile ("ldi r24,pm_hh8(__trampolines_start)\n\t"
+ "out %i0,r24" :: "n" (&EIND) : "r24","memory");
+@}
+@end example
+
+@noindent
+The @code{__trampolines_start} symbol is defined in the linker script.
@item
-Stubs will be generated automatically by the linker if
+Stubs are generated automatically by the linker if
the following two conditions are met:
@itemize @minus
@end itemize
@item
-The compiler will emit such @code{gs} modifiers for code labels in the
+The compiler emits such @code{gs} modifiers for code labels in the
following situations:
@itemize @minus
@item Taking address of a function or code label.
@end itemize
@item
-The default linker script is arranged for code with @code{EIND = 0}.
-If code is supposed to work for a setup with @code{EIND != 0}, a custom
-linker script has to be used in order to place the sections whose
-name start with @code{.trampolines} into the segment where @code{EIND}
-points to.
-
-@item
Jumping to non-symbolic addresses like so is @emph{not} supported:
@example
Alternatively, @code{func_4} can be defined in the linker script.
@end itemize
+@subsubsection Handling of the @code{RAMPD}, @code{RAMPX}, @code{RAMPY} and @code{RAMPZ} Special Function Registers
+@cindex @code{RAMPD}
+@cindex @code{RAMPX}
+@cindex @code{RAMPY}
+@cindex @code{RAMPZ}
+Some AVR devices support memories larger than the 64@tie{}KiB range
+that can be accessed with 16-bit pointers. To access memory locations
+outside this 64@tie{}KiB range, the contentent of a @code{RAMP}
+register is used as high part of the address:
+The @code{X}, @code{Y}, @code{Z} address register is concatenated
+with the @code{RAMPX}, @code{RAMPY}, @code{RAMPZ} special function
+register, respectively, to get a wide address. Similarly,
+@code{RAMPD} is used together with direct addressing.
+
+@itemize
+@item
+The startup code initializes the @code{RAMP} special function
+registers with zero.
+
+@item
+If a @ref{AVR Named Address Spaces,named address space} other than
+generic or @code{__flash} is used, then @code{RAMPZ} is set
+as needed before the operation.
+
+@item
+If the device supports RAM larger than 64@tie{KiB} and the compiler
+needs to change @code{RAMPZ} to accomplish an operation, @code{RAMPZ}
+is reset to zero after the operation.
+
+@item
+If the device comes with a specific @code{RAMP} register, the ISR
+prologue/epilogue saves/restores that SFR and initializes it with
+zero in case the ISR code might (implicitly) use it.
+
+@item
+RAM larger than 64@tie{KiB} is not supported by GCC for AVR targets.
+If you use inline assembler to read from locations outside the
+16-bit address range and change one of the @code{RAMP} registers,
+you must reset it to zero after the access.
+
+@end itemize
+
@subsubsection AVR Built-in Macros
-avr-gcc defines several built-in macros so that the user code can test
-for presence of absence of features. Almost any of the following
+GCC defines several built-in macros so that the user code can test
+for the presence or absence of features. Almost any of the following
built-in macros are deduced from device capabilities and thus
triggered by the @code{-mmcu=} command-line option.
@item __AVR_@var{Device}__
Setting @code{-mmcu=@var{device}} defines this built-in macro which reflects
-the device's name. For example, @code{-mmcu=atmega8} will define the
+the device's name. For example, @code{-mmcu=atmega8} defines the
built-in macro @code{__AVR_ATmega8__}, @code{-mmcu=attiny261a} defines
@code{__AVR_ATtiny261A__}, etc.
the scheme @code{__AVR_@var{Device}__} where @var{Device} is
the device name as from the AVR user manual. The difference between
@var{Device} in the built-in macro and @var{device} in
-@code{-mmcu=@var{device}} is that the latter is always lower case.
+@code{-mmcu=@var{device}} is that the latter is always lowercase.
-@item __AVR_HAVE_RAMPZ__
@item __AVR_HAVE_ELPM__
-The device has the @code{RAMPZ} special function register and thus the
-@code{ELPM} instruction.
+The device has the the @code{ELPM} instruction.
@item __AVR_HAVE_ELPMX__
The device has the @code{ELPM R@var{n},Z} and @code{ELPM
register-register moves.
@item __AVR_HAVE_LPMX__
-The device has the @code{LPM R@var{n},Z} and @code{LPM
-R@var{n},Z+} instructions.
+The device has the @code{LPM R@var{n},Z} and
+@code{LPM R@var{n},Z+} instructions.
@item __AVR_HAVE_MUL__
The device has a hardware multiplier.
@item __AVR_HAVE_EIJMP_EICALL__
@item __AVR_3_BYTE_PC__
The device has the @code{EIJMP} and @code{EICALL} instructions.
-This is the case for devices with at least 256@tie{}KiB of program memory.
+This is the case for devices with more than 128@tie{}KiB of program memory.
This also means that the program counter
(PC) is 3@tie{}bytes wide.
@item __AVR_HAVE_8BIT_SP__
@item __AVR_HAVE_16BIT_SP__
-The stack pointer (SP) is respectively 8 or 16 bits wide.
+The stack pointer (SP) register is treated as 8-bit respectively
+16-bit register by the compiler.
The definition of these macros is affected by @code{-mtiny-stack}.
+@item __AVR_HAVE_SPH__
+@item __AVR_SP8__
+The device has the SPH (high part of stack pointer) special function
+register or has an 8-bit stack pointer, respectively.
+The definition of these macros is affected by @code{-mmcu=} and
+in the cases of @code{-mmcu=avr2} and @code{-mmcu=avr25} also
+by @code{-msp8}.
+
+@item __AVR_HAVE_RAMPD__
+@item __AVR_HAVE_RAMPX__
+@item __AVR_HAVE_RAMPY__
+@item __AVR_HAVE_RAMPZ__
+The device has the @code{RAMPD}, @code{RAMPX}, @code{RAMPY},
+@code{RAMPZ} special function register, respectively.
+
@item __NO_INTERRUPTS__
This macro reflects the @code{-mno-interrupts} command line option.
@item -mbig-endian
@opindex mbig-endian
-Generate code for a big endian target.
+Generate code for a big-endian target.
@item -mlittle-endian
@opindex mlittle-endian
-Generate code for a little endian target. This is the default.
+Generate code for a little-endian target. This is the default.
@item -msim
@opindex msim
@item bdver1
AMD Family 15h core based CPUs with x86-64 instruction set support. (This
supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A,
-SSSE3, SSE4.1, SSE4.2, 3DNow!, enhanced 3DNow!, ABM and 64-bit
-instruction set extensions.)
+SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)
+@item bdver2
+AMD Family 15h core based CPUs with x86-64 instruction set support. (This
+supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE,
+SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set
+extensions.)
@item btver1
AMD Family 14h core based CPUs with x86-64 instruction set support. (This
supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit
@table @gcctabopt
@item -mbig-endian
@opindex mbig-endian
-Generate code for a big endian target. This is the default for HP-UX@.
+Generate code for a big-endian target. This is the default for HP-UX@.
@item -mlittle-endian
@opindex mlittle-endian
-Generate code for a little endian target. This is the default for AIX5
+Generate code for a little-endian target. This is the default for AIX5
and GNU/Linux.
@item -mgnu-as
@itemx -mbig-endian
@opindex mlittle-endian
@opindex mbig-endian
-Generate code for a little endian target.
+Generate code for a little-endian target.
@item -m210
@itemx -m340
Generate code that uses (does not use) the load multiple word
instructions and the store multiple word instructions. These
instructions are generated by default on POWER systems, and not
-generated on PowerPC systems. Do not use @option{-mmultiple} on little
-endian PowerPC systems, since those instructions do not work when the
-processor is in little endian mode. The exceptions are PPC740 and
-PPC750 which permit the instructions usage in little endian mode.
+generated on PowerPC systems. Do not use @option{-mmultiple} on little-endian
+PowerPC systems, since those instructions do not work when the
+processor is in little-endian mode. The exceptions are PPC740 and
+PPC750 which permit these instructions in little-endian mode.
@item -mstring
@itemx -mno-string
and the store string word instructions to save multiple registers and
do small block moves. These instructions are generated by default on
POWER systems, and not generated on PowerPC systems. Do not use
-@option{-mstring} on little endian PowerPC systems, since those
-instructions do not work when the processor is in little endian mode.
-The exceptions are PPC740 and PPC750 which permit the instructions
-usage in little endian mode.
+@option{-mstring} on little-endian PowerPC systems, since those
+instructions do not work when the processor is in little-endian mode.
+The exceptions are PPC740 and PPC750 which permit these instructions
+in little-endian mode.
@item -mupdate
@itemx -mno-update
@opindex mlittle
@opindex mlittle-endian
On System V.4 and embedded PowerPC systems compile code for the
-processor in little endian mode. The @option{-mlittle-endian} option is
+processor in little-endian mode. The @option{-mlittle-endian} option is
the same as @option{-mlittle}.
@item -mbig
@opindex mbig
@opindex mbig-endian
On System V.4 and embedded PowerPC systems compile code for the
-processor in big endian mode. The @option{-mbig-endian} option is
+processor in big-endian mode. The @option{-mbig-endian} option is
the same as @option{-mbig}.
@item -mdynamic-no-pic
@opindex mbig-endian-data
@opindex mlittle-endian-data
Store data (but not code) in the big-endian format. The default is
-@option{-mlittle-endian-data}, i.e.@: to store data in the little endian
+@option{-mlittle-endian-data}, i.e.@: to store data in the little-endian
format.
@item -msmall-data-limit=@var{N}
could have been held in the reserved register are now pushed onto the
stack.
-Note, common variables (variables that have not been initialised) and
+Note, common variables (variables that have not been initialized) and
constants are not placed into the small data area as they are assigned
to other sections in the output executable.
@table @gcctabopt
@item -meb
@opindex meb
-Compile code for big endian mode. This is the default.
+Compile code for big-endian mode. This is the default.
@item -mel
@opindex mel
-Compile code for little endian mode.
+Compile code for little-endian mode.
@item -mnhwloop
@opindex mnhwloop
@item -mb
@opindex mb
-Compile code for the processor in big endian mode.
+Compile code for the processor in big-endian mode.
@item -ml
@opindex ml
-Compile code for the processor in little endian mode.
+Compile code for the processor in little-endian mode.
@item -mdalign
@opindex mdalign
@item -msoft-atomic
@opindex msoft-atomic
-Generate software atomic sequences for the atomic operations.
-This is the default when the target is @code{sh-*-linux*}.
+Generate GNU/Linux compatible gUSA software atomic sequences for the atomic
+built-in functions. The generated atomic sequences require support from the
+interrupt / exception handling code of the system and are only suitable for
+single-core systems. They will not perform correctly on multi-core systems.
+This option is enabled by default when the target is @code{sh-*-linux*}.
+For details on the atomic built-in functions see @ref{__atomic Builtins}.
@item -mspace
@opindex mspace
This option is only meaningful when @option{-mno-pt-fixed} is in effect.
It will then prevent cross-basic-block cse, hoisting and most scheduling
of symbol loads. The default is @option{-mno-invalid-symbols}.
+
+@item -mbranch-cost=@var{num}
+@opindex mbranch-cost=@var{num}
+Assume @var{num} to be the cost for a branch instruction. Higher numbers
+will make the compiler try to generate more branch-free code if possible.
+If not specified the value is selected depending on the processor type that
+is being compiled for.
+
+@item -mcbranchdi
+@opindex mcbranchdi
+Enable the @code{cbranchdi4} instruction pattern.
+
+@item -mcmpeqdi
+@opindex mcmpeqdi
+Emit the @code{cmpeqdi_t} instruction pattern even when @option{-mcbranchdi}
+is in effect.
+
+@item -mfused-madd
+@opindex mfused-madd
+Allow the usage of the @code{fmac} instruction (floating-point
+multiply-accumulate) if the processor type supports it. Enabling this
+option might generate code that produces different numeric floating-point
+results compared to strict IEEE 754 arithmetic.
+
+@item -mpretend-cmove
+@opindex mpretend-cmove
+Prefer zero-displacement conditional branches for conditional move instruction
+patterns. This can result in faster code on the SH4 processor.
+
@end table
@node Solaris 2 Options
@table @gcctabopt
@item -fbounds-check
@opindex fbounds-check
-For front-ends that support it, generate additional code to check that
+For front ends that support it, generate additional code to check that
indices used to access arrays are within the declared range. This is
-currently only supported by the Java and Fortran front-ends, where
+currently only supported by the Java and Fortran front ends, where
this option defaults to true and false respectively.
@item -ftrapv
overflow of addition, subtraction and multiplication wraps around
using twos-complement representation. This flag enables some optimizations
and disables others. This option is enabled by default for the Java
-front-end, as required by the Java language specification.
+front end, as required by the Java language specification.
@item -fexceptions
@opindex fexceptions
overflow if the program is unable to allocate any more memory. This
is most useful when running threaded programs, as it is no longer
necessary to calculate a good stack size to use for each thread. This
-is currently only implemented for the i386 and x86_64 backends running
+is currently only implemented for the i386 and x86_64 back ends running
GNU/Linux.
When code compiled with @option{-fsplit-stack} calls code compiled
@item -fstrict-volatile-bitfields
@opindex fstrict-volatile-bitfields
-This option should be used if accesses to volatile bitfields (or other
+This option should be used if accesses to volatile bit-fields (or other
structure fields, although the compiler usually honors those types
anyway) should use a single access of the width of the
field's type, aligned to a natural alignment if possible. For
example, targets with memory-mapped peripheral registers might require
all such accesses to be 16 bits wide; with this flag the user could
-declare all peripheral bitfields as ``unsigned short'' (assuming short
+declare all peripheral bit-fields as ``unsigned short'' (assuming short
is 16 bits on these targets) to force GCC to use 16-bit accesses
instead of, perhaps, a more efficient 32-bit access.
If this option is disabled, the compiler will use the most efficient
instruction. In the previous example, that might be a 32-bit load
instruction, even though that will access bytes that do not contain
-any portion of the bitfield, or memory-mapped registers unrelated to
+any portion of the bit-field, or memory-mapped registers unrelated to
the one being updated.
If the target requires strict alignment, and honoring the field
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