@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-@c 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+@c 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
@c Free Software Foundation, Inc.
@c This is part of the GCC manual.
@c For copying conditions, see the file gcc.texi.
@c man begin COPYRIGHT
Copyright @copyright{} 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
-Wstrict-overflow -Wstrict-overflow=@var{n} @gol
-Wswitch -Wswitch-default -Wswitch-enum -Wsync-nand @gol
-Wsystem-headers -Wtrigraphs -Wtype-limits -Wundef -Wuninitialized @gol
--Wunknown-pragmas -Wno-pragmas -Wunreachable-code @gol
+-Wunknown-pragmas -Wno-pragmas @gol
-Wunsuffixed-float-constants -Wunused -Wunused-function @gol
-Wunused-label -Wunused-parameter -Wno-unused-result -Wunused-value -Wunused-variable @gol
-Wvariadic-macros -Wvla @gol
-fcompare-debug@r{[}=@var{opts}@r{]} -fcompare-debug-second @gol
-feliminate-dwarf2-dups -feliminate-unused-debug-types @gol
-feliminate-unused-debug-symbols -femit-class-debug-always @gol
+-fenable-icf-debug @gol
-fmem-report -fpre-ipa-mem-report -fpost-ipa-mem-report -fprofile-arcs @gol
-frandom-seed=@var{string} -fsched-verbose=@var{n} @gol
-fsel-sched-verbose -fsel-sched-dump-cfg -fsel-sched-pipelining-verbose @gol
-femit-struct-debug-baseonly -femit-struct-debug-reduced @gol
-femit-struct-debug-detailed@r{[}=@var{spec-list}@r{]} @gol
-p -pg -print-file-name=@var{library} -print-libgcc-file-name @gol
--print-multi-directory -print-multi-lib @gol
+-print-multi-directory -print-multi-lib -print-multi-os-directory @gol
-print-prog-name=@var{program} -print-search-dirs -Q @gol
-print-sysroot -print-sysroot-headers-suffix @gol
-save-temps -save-temps=cwd -save-temps=obj -time@r{[}=@var{file}@r{]}}
-finline-small-functions -fipa-cp -fipa-cp-clone -fipa-matrix-reorg -fipa-pta @gol
-fipa-pure-const -fipa-reference -fipa-struct-reorg @gol
-fipa-type-escape -fira-algorithm=@var{algorithm} @gol
--fira-region=@var{region} -fira-coalesce -fno-ira-share-save-slots @gol
+-fira-region=@var{region} -fira-coalesce @gol
+-fira-loop-pressure -fno-ira-share-save-slots @gol
-fno-ira-share-spill-slots -fira-verbose=@var{n} @gol
-fivopts -fkeep-inline-functions -fkeep-static-consts @gol
-floop-block -floop-interchange -floop-strip-mine -fgraphite-identity @gol
--floop-parallelize-all @gol
--fmerge-all-constants -fmerge-constants -fmodulo-sched @gol
+-floop-parallelize-all -flto -flto-compression-level -flto-report -fltrans @gol
+-fltrans-output-list -fmerge-all-constants -fmerge-constants -fmodulo-sched @gol
-fmodulo-sched-allow-regmoves -fmove-loop-invariants -fmudflap @gol
-fmudflapir -fmudflapth -fno-branch-count-reg -fno-default-inline @gol
-fno-defer-pop -fno-function-cse -fno-guess-branch-probability @gol
-funit-at-a-time -funroll-all-loops -funroll-loops @gol
-funsafe-loop-optimizations -funsafe-math-optimizations -funswitch-loops @gol
-fvariable-expansion-in-unroller -fvect-cost-model -fvpt -fweb @gol
--fwhole-program @gol
+-fwhole-program -fwhopr -fwpa -fuse-linker-plugin @gol
--param @var{name}=@var{value}
-O -O0 -O1 -O2 -O3 -Os}
-mfix-cortex-m3-ldrd}
@emph{AVR Options}
-@gccoptlist{-mmcu=@var{mcu} -msize -mno-interrupts @gol
+@gccoptlist{-mmcu=@var{mcu} -mno-interrupts @gol
-mcall-prologues -mtiny-stack -mint8}
@emph{Blackfin Options}
-mincoming-stack-boundary=@var{num}
-mcld -mcx16 -msahf -mmovbe -mcrc32 -mrecip @gol
-mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol
--maes -mpclmul @gol
--msse4a -m3dnow -mpopcnt -mabm @gol
+-maes -mpclmul -mfused-madd @gol
+-msse4a -m3dnow -mpopcnt -mabm -mfma4 -mxop -mlwp @gol
-mthreads -mno-align-stringops -minline-all-stringops @gol
-minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol
-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
@emph{IA-64/VMS Options}
@gccoptlist{-mvms-return-codes -mdebug-main=@var{prefix} -mmalloc64}
+@emph{LM32 Options}
+@gccoptlist{-mbarrel-shift-enabled -mdivide-enabled -mmultiply-enabled @gol
+-msign-extend-enabled -muser-enabled}
+
@emph{M32R/D Options}
@gccoptlist{-m32r2 -m32rx -m32r @gol
-mdebug @gol
-mbranch-cost=@var{num} -mbranch-likely -mno-branch-likely @gol
-mfp-exceptions -mno-fp-exceptions @gol
-mvr4130-align -mno-vr4130-align -msynci -mno-synci @gol
--mrelax-pic-calls -mno-relax-pic-calls}
+-mrelax-pic-calls -mno-relax-pic-calls -mmcount-ra-address}
@emph{MMIX Options}
@gccoptlist{-mlibfuncs -mno-libfuncs -mepsilon -mno-epsilon -mabi=gnu @gol
-msim -mmvme -mads -myellowknife -memb -msdata @gol
-msdata=@var{opt} -mvxworks -G @var{num} -pthread}
+@emph{RX Options}
+@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol
+-mcpu= -patch=@gol
+-mbig-endian-data -mlittle-endian-data @gol
+-msmall-data @gol
+-msim -mno-sim@gol
+-mas100-syntax -mno-as100-syntax@gol
+-mrelax@gol
+-mmax-constant-size=@gol
+-mint-register=@gol
+-msave-acc-in-interrupts}
+
@emph{S/390 and zSeries Options}
@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol
-mhard-float -msoft-float -mhard-dfp -mno-hard-dfp @gol
-msafe-dma -munsafe-dma @gol
-mbranch-hints @gol
-msmall-mem -mlarge-mem -mstdmain @gol
--mfixed-range=@var{register-range}}
+-mfixed-range=@var{register-range} @gol
+-mea32 -mea64 @gol
+-maddress-space-conversion -mno-address-space-conversion @gol
+-mcache-size=@var{cache-size} @gol
+-matomic-updates -mno-atomic-updates}
@emph{System V Options}
@gccoptlist{-Qy -Qn -YP,@var{paths} -Ym,@var{dir}}
@emph{i386 and x86-64 Windows Options}
@gccoptlist{-mconsole -mcygwin -mno-cygwin -mdll
--mnop-fun-dllimport -mthread -municode -mwin32 -mwindows}
+-mnop-fun-dllimport -mthread -municode -mwin32 -mwindows
+-fno-set-stack-executable}
@emph{Xstormy16 Options}
@gccoptlist{-msim}
@opindex Wno-nested-externs
Warn if an @code{extern} declaration is encountered within a function.
-@item -Wunreachable-code
-@opindex Wunreachable-code
-@opindex Wno-unreachable-code
-Warn if the compiler detects that code will never be executed.
-
-This option is intended to warn when the compiler detects that at
-least a whole line of source code will never be executed, because
-some condition is never satisfied or because it is after a
-procedure that never returns.
-
-It is possible for this option to produce a warning even though there
-are circumstances under which part of the affected line can be executed,
-so care should be taken when removing apparently-unreachable code.
-
-For instance, when a function is inlined, a warning may mean that the
-line is unreachable in only one inlined copy of the function.
-
-This option is not made part of @option{-Wall} because in a debugging
-version of a program there is often substantial code which checks
-correct functioning of the program and is, hopefully, unreachable
-because the program does work. Another common use of unreachable
-code is to provide behavior which is selectable at compile-time.
-
@item -Winline
@opindex Winline
@opindex Wno-inline
This option is implied by @option{-pedantic}, and can be disabled with
@option{-Wno-overlength-strings}.
-@item -Wunsuffixed-float-constants
+@item -Wunsuffixed-float-constants @r{(C and Objective-C only)}
@opindex Wunsuffixed-float-constants
GCC will issue a warning for any floating constant that does not have
This option works only with DWARF 2.
+@item -fenable-icf-debug
+@opindex fenable-icf-debug
+Generate additional debug information to support identical code folding (ICF).
+This option only works with DWARF version 2 or higher.
+
@item -fno-merge-debug-strings
@opindex fmerge-debug-strings
@opindex fno-merge-debug-strings
Dump each function after applying vectorization of loops. The file name is
made by appending @file{.vect} to the source file name.
+@item slp
+@opindex fdump-tree-slp
+Dump each function after applying vectorization of basic blocks. The file name
+is made by appending @file{.slp} to the source file name.
+
@item vrp
@opindex fdump-tree-vrp
Dump each function after Value Range Propagation (VRP). The file name
level that @option{-fdump-tree-vect-stats} uses.
Higher verbosity levels mean either more information dumped for each
reported loop, or same amount of information reported for more loops:
-If @var{n}=3, alignment related information is added to the reports.
-If @var{n}=4, data-references related information (e.g.@: memory dependences,
+if @var{n}=3, vectorizer cost model information is reported.
+If @var{n}=4, alignment related information is added to the reports.
+If @var{n}=5, data-references related information (e.g.@: memory dependences,
memory access-patterns) is added to the reports.
-If @var{n}=5, the vectorizer reports also non-vectorized inner-most loops
+If @var{n}=6, the vectorizer reports also non-vectorized inner-most loops
that did not pass the first analysis phase (i.e., may not be countable, or
may have complicated control-flow).
-If @var{n}=6, the vectorizer reports also non-vectorized nested loops.
-For @var{n}=7, all the information the vectorizer generates during its
+If @var{n}=7, the vectorizer reports also non-vectorized nested loops.
+If @var{n}=8, SLP related information is added to the reports.
+For @var{n}=9, all the information the vectorizer generates during its
analysis and transformation is reported. This is the same verbosity level
that @option{-fdump-tree-vect-details} uses.
amount of debugging output the scheduler prints. This information is
written to standard error, unless @option{-fdump-rtl-sched1} or
@option{-fdump-rtl-sched2} is specified, in which case it is output
-to the usual dump listing file, @file{.sched} or @file{.sched2}
+to the usual dump listing file, @file{.sched1} or @file{.sched2}
respectively. However for @var{n} greater than nine, the output is
always printed to standard error.
@samp{-}, without spaces between multiple switches. This is supposed to
ease shell-processing.
+@item -print-multi-os-directory
+@opindex print-multi-os-directory
+Print the path to OS libraries for the selected
+multilib, relative to some @file{lib} subdirectory. If OS libraries are
+present in the @file{lib} subdirectory and no multilibs are used, this is
+usually just @file{.}, if OS libraries are present in @file{lib@var{suffix}}
+sibling directories this prints e.g.@: @file{../lib64}, @file{../lib} or
+@file{../lib32}, or if OS libraries are present in @file{lib/@var{subdir}}
+subdirectories it prints e.g.@: @file{amd64}, @file{sparcv9} or @file{ev6}.
+
@item -print-prog-name=@var{program}
@opindex print-prog-name
Like @option{-print-file-name}, but searches for a program such as @samp{cpp}.
Not all optimizations are controlled directly by a flag. Only
optimizations that have a flag are listed in this section.
+Most optimizations are only enabled if an @option{-O} level is set on
+the command line. Otherwise they are disabled, even if individual
+optimization flags are specified.
+
Depending on the target and how GCC was configured, a slightly different
set of optimizations may be enabled at each @option{-O} level than
those listed here. You can invoke GCC with @samp{-Q --help=optimizers}
Do optimistic register coalescing. This option might be profitable for
architectures with big regular register files.
+@item -fira-loop-pressure
+@opindex fira-loop-pressure
+Use IRA to evaluate register pressure in loops for decision to move
+loop invariants. Usage of this option usually results in generation
+of faster and smaller code on machines with big register files (>= 32
+registers) but it can slow compiler down.
+
+This option is enabled at level @option{-O3} for some targets.
+
@item -fno-ira-share-save-slots
@opindex fno-ira-share-save-slots
Switch off sharing stack slots used for saving call used hard
by allowing other instructions to be issued until the result of the load
or floating point instruction is required.
-Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}.
+Enabled at levels @option{-O2}, @option{-O3}.
@item -fschedule-insns2
@opindex fschedule-insns2
Perform loop vectorization on trees. This flag is enabled by default at
@option{-O3}.
+@item -ftree-slp-vectorize
+@opindex ftree-slp-vectorize
+Perform basic block vectorization on trees. This flag is enabled by default at
+@option{-O3} and when @option{-ftree-vectorize} is enabled.
+
@item -ftree-vect-loop-version
@opindex ftree-vect-loop-version
Perform loop versioning when doing loop vectorization on trees. When a loop
and in effect are optimized more aggressively by interprocedural optimizers.
While this option is equivalent to proper use of the @code{static} keyword for
programs consisting of a single file, in combination with option
-@option{--combine} this flag can be used to compile many smaller scale C
-programs since the functions and variables become local for the whole combined
-compilation unit, not for the single source file itself.
+@option{-combine}, @option{-flto} or @option{-fwhopr} this flag can be used to
+compile many smaller scale programs since the functions and variables become
+local for the whole combined compilation unit, not for the single source file
+itself.
This option implies @option{-fwhole-file} for Fortran programs.
+@item -flto
+@opindex flto
+This option runs the standard link-time optimizer. When invoked
+with source code, it generates GIMPLE (one of GCC's internal
+representations) and writes it to special ELF sections in the object
+file. When the object files are linked together, all the function
+bodies are read from these ELF sections and instantiated as if they
+had been part of the same translation unit.
+
+To use the link-timer optimizer, @option{-flto} needs to be specified at
+compile time and during the final link. For example,
+
+@smallexample
+gcc -c -O2 -flto foo.c
+gcc -c -O2 -flto bar.c
+gcc -o myprog -flto -O2 foo.o bar.o
+@end smallexample
+
+The first two invocations to GCC will save a bytecode representation
+of GIMPLE into special ELF sections inside @file{foo.o} and
+@file{bar.o}. The final invocation will read the GIMPLE bytecode from
+@file{foo.o} and @file{bar.o}, merge the two files into a single
+internal image, and compile the result as usual. Since both
+@file{foo.o} and @file{bar.o} are merged into a single image, this
+causes all the inter-procedural analyses and optimizations in GCC to
+work across the two files as if they were a single one. This means,
+for example, that the inliner will be able to inline functions in
+@file{bar.o} into functions in @file{foo.o} and vice-versa.
+
+Another (simpler) way to enable link-time optimization is,
+
+@smallexample
+gcc -o myprog -flto -O2 foo.c bar.c
+@end smallexample
+
+The above will generate bytecode for @file{foo.c} and @file{bar.c},
+merge them together into a single GIMPLE representation and optimize
+them as usual to produce @file{myprog}.
+
+The only important thing to keep in mind is that to enable link-time
+optimizations the @option{-flto} flag needs to be passed to both the
+compile and the link commands.
+
+Note that when a file is compiled with @option{-flto}, the generated
+object file will be larger than a regular object file because it will
+contain GIMPLE bytecodes and the usual final code. This means that
+object files with LTO information can be linked as a normal object
+file. So, in the previous example, if the final link is done with
+
+@smallexample
+gcc -o myprog foo.o bar.o
+@end smallexample
+
+The only difference will be that no inter-procedural optimizations
+will be applied to produce @file{myprog}. The two object files
+@file{foo.o} and @file{bar.o} will be simply sent to the regular
+linker.
+
+Additionally, the optimization flags used to compile individual files
+are not necessarily related to those used at link-time. For instance,
+
+@smallexample
+gcc -c -O0 -flto foo.c
+gcc -c -O0 -flto bar.c
+gcc -o myprog -flto -O3 foo.o bar.o
+@end smallexample
+
+This will produce individual object files with unoptimized assembler
+code, but the resulting binary @file{myprog} will be optimized at
+@option{-O3}. Now, if the final binary is generated without
+@option{-flto}, then @file{myprog} will not be optimized.
+
+When producing the final binary with @option{-flto}, GCC will only
+apply link-time optimizations to those files that contain bytecode.
+Therefore, you can mix and match object files and libraries with
+GIMPLE bytecodes and final object code. GCC will automatically select
+which files to optimize in LTO mode and which files to link without
+further processing.
+
+There are some code generation flags that GCC will preserve when
+generating bytecodes, as they need to be used during the final link
+stage. Currently, the following options are saved into the GIMPLE
+bytecode files: @option{-fPIC}, @option{-fcommon} and all the
+@option{-m} target flags.
+
+At link time, these options are read-in and reapplied. Note that the
+current implementation makes no attempt at recognizing conflicting
+values for these options. If two or more files have a conflicting
+value (e.g., one file is compiled with @option{-fPIC} and another
+isn't), the compiler will simply use the last value read from the
+bytecode files. It is recommended, then, that all the files
+participating in the same link be compiled with the same options.
+
+Another feature of LTO is that it is possible to apply interprocedural
+optimizations on files written in different languages. This requires
+some support in the language front end. Currently, the C, C++ and
+Fortran front ends are capable of emitting GIMPLE bytecodes, so
+something like this should work
+
+@smallexample
+gcc -c -flto foo.c
+g++ -c -flto bar.cc
+gfortran -c -flto baz.f90
+g++ -o myprog -flto -O3 foo.o bar.o baz.o -lgfortran
+@end smallexample
+
+Notice that the final link is done with @command{g++} to get the C++
+runtime libraries and @option{-lgfortran} is added to get the Fortran
+runtime libraries. In general, when mixing languages in LTO mode, you
+should use the same link command used when mixing languages in a
+regular (non-LTO) compilation. This means that if your build process
+was mixing languages before, all you need to add is @option{-flto} to
+all the compile and link commands.
+
+If object files containing GIMPLE bytecode are stored in a library
+archive, say @file{libfoo.a}, it is possible to extract and use them
+in an LTO link if you are using @command{gold} as the linker (which,
+in turn requires GCC to be configured with @option{--enable-gold}).
+To enable this feature, use the flag @option{-fuse-linker-plugin} at
+link-time:
+
+@smallexample
+gcc -o myprog -O2 -flto -fuse-linker-plugin a.o b.o -lfoo
+@end smallexample
+
+With the linker plugin enabled, @command{gold} will extract the needed
+GIMPLE files from @file{libfoo.a} and pass them on to the running GCC
+to make them part of the aggregated GIMPLE image to be optimized.
+
+If you are not using @command{gold} and/or do not specify
+@option{-fuse-linker-plugin} then the objects inside @file{libfoo.a}
+will be extracted and linked as usual, but they will not participate
+in the LTO optimization process.
+
+Link time optimizations do not require the presence of the whole
+program to operate. If the program does not require any symbols to
+be exported, it is possible to combine @option{-flto} and
+@option{-fwhopr} with @option{-fwhole-program} to allow the
+interprocedural optimizers to use more aggressive assumptions which
+may lead to improved optimization opportunities.
+
+Regarding portability: the current implementation of LTO makes no
+attempt at generating bytecode that can be ported between different
+types of hosts. The bytecode files are versioned and there is a
+strict version check, so bytecode files generated in one version of
+GCC will not work with an older/newer version of GCC.
+
+Link time optimization does not play well with generating debugging
+information. Combining @option{-flto} or @option{-fwhopr} with
+@option{-g} is experimental.
+
+This option is disabled by default.
+
+@item -fwhopr
+@opindex fwhopr
+This option is identical in functionality to @option{-flto} but it
+differs in how the final link stage is executed. Instead of loading
+all the function bodies in memory, the callgraph is analyzed and
+optimization decisions are made (whole program analysis or WPA). Once
+optimization decisions are made, the callgraph is partitioned and the
+different sections are compiled separately (local transformations or
+LTRANS)@. This process allows optimizations on very large programs
+that otherwise would not fit in memory. This option enables
+@option{-fwpa} and @option{-fltrans} automatically.
+
+Disabled by default.
+
+This option is experimental.
+
+@item -fwpa
+@opindex fwpa
+This is an internal option used by GCC when compiling with
+@option{-fwhopr}. You should never need to use it.
+
+This option runs the link-time optimizer in the whole-program-analysis
+(WPA) mode, which reads in summary information from all inputs and
+performs a whole-program analysis based on summary information only.
+It generates object files for subsequent runs of the link-time
+optimizer where individual object files are optimized using both
+summary information from the WPA mode and the actual function bodies.
+It then drives the LTRANS phase.
+
+Disabled by default.
+
+@item -fltrans
+@opindex fltrans
+This is an internal option used by GCC when compiling with
+@option{-fwhopr}. You should never need to use it.
+
+This option runs the link-time optimizer in the local-transformation (LTRANS)
+mode, which reads in output from a previous run of the LTO in WPA mode.
+In the LTRANS mode, LTO optimizes an object and produces the final assembly.
+
+Disabled by default.
+
+@item -fltrans-output-list=@var{file}
+@opindex fltrans-output-list
+This is an internal option used by GCC when compiling with
+@option{-fwhopr}. You should never need to use it.
+
+This option specifies a file to which the names of LTRANS output files are
+written. This option is only meaningful in conjunction with @option{-fwpa}.
+
+Disabled by default.
+
+@item -flto-compression-level=@var{n}
+This option specifies the level of compression used for intermediate
+language written to LTO object files, and is only meaningful in
+conjunction with LTO mode (@option{-fwhopr}, @option{-flto}). Valid
+values are 0 (no compression) to 9 (maximum compression). Values
+outside this range are clamped to either 0 or 9. If the option is not
+given, a default balanced compression setting is used.
+
+@item -flto-report
+Prints a report with internal details on the workings of the link-time
+optimizer. The contents of this report vary from version to version,
+it is meant to be useful to GCC developers when processing object
+files in LTO mode (via @option{-fwhopr} or @option{-flto}).
+
+Disabled by default.
+
+@item -fuse-linker-plugin
+Enables the extraction of objects with GIMPLE bytecode information
+from library archives. This option relies on features available only
+in @command{gold}, so to use this you must configure GCC with
+@option{--enable-gold}. See @option{-flto} for a description on the
+effect of this flag and how to use it.
+
+Disabled by default.
+
@item -fcprop-registers
@opindex fcprop-registers
After register allocation and post-register allocation instruction splitting,
make debugging impossible, since variables will no longer stay in
a ``home register''.
-Enabled by default with @option{-funroll-loops}.
+Enabled by default with @option{-funroll-loops} and @option{-fpeel-loops}.
@item -ftracer
@opindex ftracer
parameter, then structure reorganization is not applied to this structure.
The default is 10.
-@item predictable-branch-cost-outcome
+@item predictable-branch-outcome
When branch is predicted to be taken with probability lower than this threshold
(in percent), then it is considered well predictable. The default is 10.
algorithm do not use pseudo-register conflicts. The default value of
the parameter is 2000.
+@item ira-loop-reserved-regs
+IRA can be used to evaluate more accurate register pressure in loops
+for decision to move loop invariants (see @option{-O3}). The number
+of available registers reserved for some other purposes is described
+by this parameter. The default value of the parameter is 2 which is
+minimal number of registers needed for execution of typical
+instruction. This value is the best found from numerous experiments.
+
@item loop-invariant-max-bbs-in-loop
Loop invariant motion can be very expensive, both in compile time and
in amount of needed compile time memory, with very large loops. Loops
* i386 and x86-64 Windows Options::
* IA-64 Options::
* IA-64/VMS Options::
+* LM32 Options::
* M32C Options::
* M32R/D Options::
* M680x0 Options::
* picoChip Options::
* PowerPC Options::
* RS/6000 and PowerPC Options::
+* RX Options::
* S/390 and zSeries Options::
* Score Options::
* SH Options::
@samp{arm10e}, @samp{arm1020e}, @samp{arm1022e},
@samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
@samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
-@samp{cortex-a8}, @samp{cortex-a9},
+@samp{cortex-a5}, @samp{cortex-a8}, @samp{cortex-a9},
@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m3},
@samp{cortex-m1},
@samp{cortex-m0},
@opindex mfp
This specifies what floating point hardware (or hardware emulation) is
available on the target. Permissible names are: @samp{fpa}, @samp{fpe2},
-@samp{fpe3}, @samp{maverick}, @samp{vfp}, @samp{vfpv3}, @samp{vfpv3-d16},
-@samp{neon}, and @samp{neon-fp16}. @option{-mfp} and @option{-mfpe}
-are synonyms for @option{-mfpu}=@samp{fpe}@var{number}, for compatibility
-with older versions of GCC@.
+@samp{fpe3}, @samp{maverick}, @samp{vfp}, @samp{vfpv3}, @samp{vfpv3-fp16},
+@samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd}, @samp{vfpv3xd-fp16},
+@samp{neon}, @samp{neon-fp16}, @samp{vfpv4}, @samp{vfpv4-d16},
+@samp{fpv4-sp-d16} and @samp{neon-vfpv4}.
+@option{-mfp} and @option{-mfpe} are synonyms for
+@option{-mfpu}=@samp{fpe}@var{number}, for compatibility with older versions
+of GCC@.
If @option{-msoft-float} is specified this specifies the format of
floating point values.
memory space (MCU types: atmega16, atmega161, atmega163, atmega32, atmega323,
atmega64, atmega128, at43usb355, at94k).
-@item -msize
-@opindex msize
-Output instruction sizes to the asm file.
-
@item -mno-interrupts
@opindex mno-interrupts
Generated code is not compatible with hardware interrupts.
@table @gcctabopt
@item -mvms-return-codes
@opindex mvms-return-codes
-Return VMS condition codes from main. The default is to return POSIX
+Return VMS condition codes from main. The default is to return POSIX
style condition (e.g.@: error) codes.
@item -mdebug-main=@var{prefix}
@itemx -mno-pclmul
@itemx -msse4a
@itemx -mno-sse4a
+@itemx -mfma4
+@itemx -mno-fma4
+@itemx -mxop
+@itemx -mno-xop
+@itemx -mlwp
+@itemx -mno-lwp
@itemx -m3dnow
@itemx -mno-3dnow
@itemx -mpopcnt
@opindex m3dnow
@opindex mno-3dnow
These switches enable or disable the use of instructions in the MMX,
-SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AES, PCLMUL, SSE4A, ABM or
-3DNow!@: extended instruction sets.
+SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AES, PCLMUL, SSE4A, FMA4, XOP,
+LWP, ABM or 3DNow!@: extended instruction sets.
These extensions are also available as built-in functions: see
@ref{X86 Built-in Functions}, for details of the functions enabled and
disabled by these switches.
the file containing the CPU detection code should be compiled without
these options.
+@item -mfused-madd
+@itemx -mno-fused-madd
+@opindex mfused-madd
+@opindex mno-fused-madd
+Do (don't) generate code that uses the fused multiply/add or multiply/subtract
+instructions. The default is to use these instructions.
+
@item -mcld
@opindex mcld
This option instructs GCC to emit a @code{cld} instruction in the prologue
of the non-reciprocal instruction, the precision of the sequence can be
decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994).
+Note that GCC implements 1.0f/sqrtf(x) in terms of RSQRTSS (or RSQRTPS)
+already with @option{-ffast-math} (or the above option combination), and
+doesn't need @option{-mrecip}.
+
@item -mveclibabi=@var{type}
@opindex mveclibabi
Specifies the ABI type to use for vectorizing intrinsics using an
@opindex mfused-madd
@opindex mno-fused-madd
Do (don't) generate code that uses the fused multiply/add or multiply/subtract
-instructions. The default is to use these instructions.
+instructions. The default is to use these instructions.
@item -mno-dwarf2-asm
@itemx -mdwarf2-asm
Default to 64bit memory allocation routines.
@end table
+@node LM32 Options
+@subsection LM32 Options
+@cindex LM32 options
+
+These @option{-m} options are defined for the Lattice Mico32 architecture:
+
+@table @gcctabopt
+@item -mbarrel-shift-enabled
+@opindex mbarrel-shift-enabled
+Enable barrel-shift instructions.
+
+@item -mdivide-enabled
+@opindex mdivide-enabled
+Enable divide and modulus instructions.
+
+@item -mmultiply-enabled
+@opindex multiply-enabled
+Enable multiply instructions.
+
+@item -msign-extend-enabled
+@opindex msign-extend-enabled
+Enable sign extend instructions.
+
+@item -muser-enabled
+@opindex muser-enabled
+Enable user-defined instructions.
+
+@end table
+
@node M32C Options
@subsection M32C Options
@cindex M32C options
directive and @code{-mexplicit-relocs} is in effect. With
@code{-mno-explicit-relocs}, this optimization can be performed by the
assembler and the linker alone without help from the compiler.
+
+@item -mmcount-ra-address
+@itemx -mno-mcount-ra-address
+@opindex mmcount-ra-address
+@opindex mno-mcount-ra-address
+Emit (do not emit) code that allows @code{_mcount} to modify the
+calling function's return address. When enabled, this option extends
+the usual @code{_mcount} interface with a new @var{ra-address}
+parameter, which has type @code{intptr_t *} and is passed in register
+@code{$12}. @code{_mcount} can then modify the return address by
+doing both of the following:
+@itemize
+@item
+Returning the new address in register @code{$31}.
+@item
+Storing the new address in @code{*@var{ra-address}},
+if @var{ra-address} is nonnull.
+@end itemize
+
+The default is @option{-mno-mcount-ra-address}.
+
@end table
@node MMIX Options
instruction scheduling parameters for machine type @var{cpu_type}.
Supported values for @var{cpu_type} are @samp{401}, @samp{403},
@samp{405}, @samp{405fp}, @samp{440}, @samp{440fp}, @samp{464}, @samp{464fp},
-@samp{505}, @samp{601}, @samp{602}, @samp{603}, @samp{603e}, @samp{604},
-@samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400},
-@samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
-@samp{860}, @samp{970}, @samp{8540}, @samp{e300c2}, @samp{e300c3},
-@samp{e500mc}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
-@samp{power}, @samp{power2}, @samp{power3}, @samp{power4},
-@samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, @samp{power7},
-@samp{common}, @samp{powerpc}, @samp{powerpc64}, @samp{rios},
+@samp{476}, @samp{476fp}, @samp{505}, @samp{601}, @samp{602}, @samp{603},
+@samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{630}, @samp{740},
+@samp{7400}, @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
+@samp{860}, @samp{970}, @samp{8540}, @samp{a2}, @samp{e300c2},
+@samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{ec603e}, @samp{G3},
+@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
+@samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x},
+@samp{power7}, @samp{common}, @samp{powerpc}, @samp{powerpc64}, @samp{rios},
@samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}.
@option{-mcpu=common} selects a completely generic processor. Code
signals may get corrupted data.
@item -mavoid-indexed-addresses
-@item -mno-avoid-indexed-addresses
+@itemx -mno-avoid-indexed-addresses
@opindex mavoid-indexed-addresses
@opindex mno-avoid-indexed-addresses
Generate code that tries to avoid (not avoid) the use of indexed load
@opindex mmulhw
@opindex mno-mulhw
Generate code that uses (does not use) the half-word multiply and
-multiply-accumulate instructions on the IBM 405, 440 and 464 processors.
+multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors.
These instructions are generated by default when targetting those
processors.
@opindex mdlmzb
@opindex mno-dlmzb
Generate code that uses (does not use) the string-search @samp{dlmzb}
-instruction on the IBM 405, 440 and 464 processors. This instruction is
+instruction on the IBM 405, 440, 464 and 476 processors. This instruction is
generated by default when targetting those processors.
@item -mno-bit-align
@end table
+@node RX Options
+@subsection RX Options
+@cindex RX Options
+
+These command line options are defined for RX targets:
+
+@table @gcctabopt
+@item -m64bit-doubles
+@itemx -m32bit-doubles
+@opindex m64bit-doubles
+@opindex m32bit-doubles
+Make the @code{double} data type be 64-bits (@option{-m64bit-doubles})
+or 32-bits (@option{-m32bit-doubles}) in size. The default is
+@option{-m32bit-doubles}. @emph{Note} RX floating point hardware only
+works on 32-bit values, which is why the default is
+@option{-m32bit-doubles}.
+
+@item -fpu
+@itemx -nofpu
+@opindex fpu
+@opindex nofpu
+Enables (@option{-fpu}) or disables (@option{-nofpu}) the use of RX
+floating point hardware. The default is enabled for the @var{RX600}
+series and disabled for the @var{RX200} series.
+
+Floating point instructions will only be generated for 32-bit floating
+point values however, so if the @option{-m64bit-doubles} option is in
+use then the FPU hardware will not be used for doubles.
+
+@emph{Note} If the @option{-fpu} option is enabled then
+@option{-funsafe-math-optimizations} is also enabled automatically.
+This is because the RX FPU instructions are themselves unsafe.
+
+@item -mcpu=@var{name}
+@itemx -patch=@var{name}
+@opindex -mcpu
+@opindex -patch
+Selects the type of RX CPU to be targeted. Currently three types are
+supported, the generic @var{RX600} and @var{RX200} series hardware and
+the specific @var{RX610} cpu. The default is @var{RX600}.
+
+The only difference between @var{RX600} and @var{RX610} is that the
+@var{RX610} does not support the @code{MVTIPL} instruction.
+
+The @var{RX200} series does not have a hardware floating point unit
+and so @option{-nofpu} is enabled by default when this type is
+selected.
+
+@item -mbig-endian-data
+@itemx -mlittle-endian-data
+@opindex mbig-endian-data
+@opindex mlittle-endian-data
+Store data (but not code) in the big-endian format. The default is
+@option{-mlittle-endian-data}, ie to store data in the little endian
+format.
+
+@item -msmall-data-limit=@var{N}
+@opindex msmall-data-limit
+Specifies the maximum size in bytes of global and static variables
+which can be placed into the small data area. Using the small data
+area can lead to smaller and faster code, but the size of area is
+limited and it is up to the programmer to ensure that the area does
+not overflow. Also when the small data area is used one of the RX's
+registers (@code{r13}) is reserved for use pointing to this area, so
+it is no longer available for use by the compiler. This could result
+in slower and/or larger code if variables which once could have been
+held in @code{r13} are now pushed onto the stack.
+
+Note, common variables (variables which have not been initialised) and
+constants are not placed into the small data area as they are assigned
+to other sections in the output executable.
+
+The default value is zero, which disables this feature. Note, this
+feature is not enabled by default with higher optimization levels
+(@option{-O2} etc) because of the potentially detrimental effects of
+reserving register @code{r13}. It is up to the programmer to
+experiment and discover whether this feature is of benefit to their
+program.
+
+@item -msim
+@itemx -mno-sim
+@opindex msim
+@opindex mno-sim
+Use the simulator runtime. The default is to use the libgloss board
+specific runtime.
+
+@item -mas100-syntax
+@itemx -mno-as100-syntax
+@opindex mas100-syntax
+@opindex mno-as100-syntax
+When generating assembler output use a syntax that is compatible with
+Renesas's AS100 assembler. This syntax can also be handled by the GAS
+assembler but it has some restrictions so generating it is not the
+default option.
+
+@item -mmax-constant-size=@var{N}
+@opindex mmax-constant-size
+Specifies the maxium size, in bytes, of a constant that can be used as
+an operand in a RX instruction. Although the RX instruction set does
+allow constants of up to 4 bytes in length to be used in instructions,
+a longer value equates to a longer instruction. Thus in some
+circumstances it can be beneficial to restrict the size of constants
+that are used in instructions. Constants that are too big are instead
+placed into a constant pool and referenced via register indirection.
+
+The value @var{N} can be between 0 and 4. A value of 0 (the default)
+or 4 means that constants of any size are allowed.
+
+@item -mrelax
+@opindex mrelax
+Enable linker relaxation. Linker relaxation is a process whereby the
+linker will attempt to reduce the size of a program by finding shorter
+versions of various instructions. Disabled by default.
+
+@item -mint-register=@var{N}
+@opindex mint-register
+Specify the number of registers to reserve for fast interrupt handler
+functions. The value @var{N} can be between 0 and 4. A value of 1
+means that register @code{r13} will be reserved for ther exclusive use
+of fast interrupt handlers. A value of 2 reserves @code{r13} and
+@code{r12}. A value of 3 reserves @code{r13}, @code{r12} and
+@code{r11}, and a value of 4 reserves @code{r13} through @code{r10}.
+A value of 0, the default, does not reserve any registers.
+
+@item -msave-acc-in-interrupts
+@opindex msave-acc-in-interrupts
+Specifies that interrupt handler functions should preserve the
+accumulator register. This is only necessary if normal code might use
+the accumulator register, for example because it performs 64-bit
+multiplications. The default is to ignore the accumulator as this
+makes the interrupt handlers faster.
+
+@end table
+
+@emph{Note:} The generic GCC command line @option{-ffixed-@var{reg}}
+has special significance to the RX port when used with the
+@code{interrupt} function attribute. This attribute indicates a
+function intended to process fast interrupts. GCC will will ensure
+that it only uses the registers @code{r10}, @code{r11}, @code{r12}
+and/or @code{r13} and only provided that the normal use of the
+corresponding registers have been restricted via the
+@option{-ffixed-@var{reg}} or @option{-mint-register} command line
+options.
+
@node S/390 and zSeries Options
@subsection S/390 and zSeries Options
@cindex S/390 and zSeries Options
two registers separated by a dash. Multiple register ranges can be
specified separated by a comma.
+@item -mea32
+@itemx -mea64
+@opindex mea32
+@opindex mea64
+Compile code assuming that pointers to the PPU address space accessed
+via the @code{__ea} named address space qualifier are either 32 or 64
+bits wide. The default is 32 bits. As this is an ABI changing option,
+all object code in an executable must be compiled with the same setting.
+
+@item -maddress-space-conversion
+@itemx -mno-address-space-conversion
+@opindex maddress-space-conversion
+@opindex mno-address-space-conversion
+Allow/disallow treating the @code{__ea} address space as superset
+of the generic address space. This enables explicit type casts
+between @code{__ea} and generic pointer as well as implicit
+conversions of generic pointers to @code{__ea} pointers. The
+default is to allow address space pointer conversions.
+
+@item -mcache-size=@var{cache-size}
+@opindex mcache-size
+This option controls the version of libgcc that the compiler links to an
+executable and selects a software-managed cache for accessing variables
+in the @code{__ea} address space with a particular cache size. Possible
+options for @var{cache-size} are @samp{8}, @samp{16}, @samp{32}, @samp{64}
+and @samp{128}. The default cache size is 64KB.
+
+@item -matomic-updates
+@itemx -mno-atomic-updates
+@opindex matomic-updates
+@opindex mno-atomic-updates
+This option controls the version of libgcc that the compiler links to an
+executable and selects whether atomic updates to the software-managed
+cache of PPU-side variables are used. If you use atomic updates, changes
+to a PPU variable from SPU code using the @code{__ea} named address space
+qualifier will not interfere with changes to other PPU variables residing
+in the same cache line from PPU code. If you do not use atomic updates,
+such interference may occur; however, writing back cache lines will be
+more efficient. The default behavior is to use atomic updates.
+
@item -mdual-nops
@itemx -mdual-nops=@var{n}
@opindex mdual-nops
@opindex municode
This option is available for mingw-w64 targets. It specifies
that the UNICODE macro is getting pre-defined and that the
-unicode capable runtime startup code is choosen.
+unicode capable runtime startup code is chosen.
@item -mwin32
@opindex mwin32
instructing the linker to set the PE header subsystem type
appropriately.
+@item -fno-set-stack-executable
+@opindex fno-set-stack-executable
+This option is available for MinGW targets. It specifies that
+the executable flag for stack used by nested functions isn't
+set. This is necessary for binaries running in kernel mode of
+Windows, as there the user32 API, which is used to set executable
+privileges, isn't available.
+
@item -mpe-aligned-commons
@opindex mpe-aligned-commons
This option is available for Cygwin and MinGW targets. It
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