-fprofile-correction -fprofile-dir=@var{path} -fprofile-generate @gol
-fprofile-generate=@var{path} @gol
-fprofile-use -fprofile-use=@var{path} -fprofile-values @gol
--freciprocal-math -fregmove -frename-registers -freorder-blocks @gol
+-freciprocal-math -free -fregmove -frename-registers -freorder-blocks @gol
-freorder-blocks-and-partition -freorder-functions @gol
-frerun-cse-after-loop -freschedule-modulo-scheduled-loops @gol
-frounding-math -fsched2-use-superblocks -fsched-pressure @gol
@emph{PowerPC Options}
See RS/6000 and PowerPC Options.
+@emph{RL78 Options}
+@gccoptlist{-msim -mmul=none -mmul=g13 -mmul=rl78}
+
@emph{RS/6000 and PowerPC Options}
@gccoptlist{-mcpu=@var{cpu-type} @gol
-mtune=@var{cpu-type} @gol
-mprefergot -musermode -multcost=@var{number} -mdiv=@var{strategy} @gol
-mdivsi3_libfunc=@var{name} -mfixed-range=@var{register-range} @gol
-madjust-unroll -mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol
--maccumulate-outgoing-args -minvalid-symbols}
+-maccumulate-outgoing-args -minvalid-symbols -msoft-atomic}
@emph{Solaris 2 Options}
@gccoptlist{-mimpure-text -mno-impure-text @gol
@gccoptlist{-mcpu=@var{cpu-type} @gol
-mtune=@var{cpu-type} @gol
-mcmodel=@var{code-model} @gol
+-mmemory-model=@var{mem-model} @gol
-m32 -m64 -mapp-regs -mno-app-regs @gol
-mfaster-structs -mno-faster-structs -mflat -mno-flat @gol
-mfpu -mno-fpu -mhard-float -msoft-float @gol
@w{@uref{http://gcc.gnu.org/c99status.html}} for more information. The
names @samp{c9x} and @samp{iso9899:199x} are deprecated.
-@item c1x
-ISO C1X, the draft of the next revision of the ISO C standard.
-Support is limited and experimental and features enabled by this
-option may be changed or removed if changed in or removed from the
-standard draft.
+@item c11
+@itemx c1x
+@itemx iso9899:2011
+ISO C11, the 2011 revision of the ISO C standard.
+Support is incomplete and experimental. The name @samp{c1x} is
+deprecated.
@item gnu90
@itemx gnu89
GNU dialect of ISO C99. When ISO C99 is fully implemented in GCC,
this will become the default. The name @samp{gnu9x} is deprecated.
+@item gnu11
@item gnu1x
-GNU dialect of ISO C1X. Support is limited and experimental and
-features enabled by this option may be changed or removed if changed
-in or removed from the standard draft.
+GNU dialect of ISO C11. Support is incomplete and experimental. The
+name @samp{gnu1x} is deprecated.
@item c++98
The 1998 ISO C++ standard plus amendments. Same as @option{-ansi} for
Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}.
+@item -free
+@opindex free
+Attempt to remove redundant extension instructions. This is especially
+helpful for the x86-64 architecture which implicitly zero-extends in 64-bit
+registers after writing to their lower 32-bit half.
+
+Enabled for x86 at levels @option{-O2}, @option{-O3}.
+
@item -foptimize-register-move
@itemx -fregmove
@opindex foptimize-register-move
Use specified regions for the integrated register allocator. The
@var{region} argument should be one of @code{all}, @code{mixed}, or
@code{one}. The first value means using all loops as register
-allocation regions, the second value which is the default means using
-all loops except for loops with small register pressure as the
-regions, and third one means using all function as a single region.
-The first value can give best result for machines with small size and
-irregular register set, the third one results in faster and generates
-decent code and the smallest size code, and the default value usually
-give the best results in most cases and for most architectures.
+allocation regions, the second value which is enabled by default when
+compiling with optimization for speed (@option{-O}, @option{-O2},
+@dots{}) means using all loops except for loops with small register
+pressure as the regions, and third one which is enabled by default for
+@option{-Os} or @option{-O0} means using all function as a single
+region. The first value can give best result for machines with small
+size and irregular register set, the third one results in faster and
+generates decent code and the smallest size code, and the second value
+usually give the best results in most cases and for most
+architectures.
@item -fira-loop-pressure
@opindex fira-loop-pressure
* PDP-11 Options::
* picoChip Options::
* PowerPC Options::
+* RL78 Options::
* RS/6000 and PowerPC Options::
* RX Options::
* S/390 and zSeries Options::
AMD Family 10h core based CPUs with x86-64 instruction set support. (This
supersets MMX, SSE, SSE2, SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bit
instruction set extensions.)
+@item bdver1
+AMD Family 15h core based CPUs with x86-64 instruction set support. (This
+supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A,
+SSSE3, SSE4.1, SSE4.2, 3DNow!, enhanced 3DNow!, ABM and 64-bit
+instruction set extensions.)
+@item btver1
+AMD Family 14h core based CPUs with x86-64 instruction set support. (This
+supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit
+instruction set extensions.)
@item winchip-c6
IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction
set support.
While picking a specific @var{cpu-type} will schedule things appropriately
for that particular chip, the compiler will not generate any code that
-does not run on the i386 without the @option{-march=@var{cpu-type}} option
-being used.
+does not run on the default machine type without the @option{-march=@var{cpu-type}}
+option being used. For example, if GCC is configured for i686-pc-linux-gnu
+then @option{-mtune=pentium4} will generate code that is tuned for Pentium4
+but will still run on i686 machines.
@item -march=@var{cpu-type}
@opindex march
These are listed under @xref{RS/6000 and PowerPC Options}.
+@node RL78 Options
+@subsection RL78 Options
+@cindex RL78 Options
+
+@table @gcctabopt
+
+@item -msim
+@opindex msim
+Links in additional target libraries to support operation within a
+simulator.
+
+@item -mmul=none
+@itemx -mmul=g13
+@itemx -mmul=rl78
+@opindex mmul
+Specifies the type of hardware multiplication support to be used. The
+default is @code{none}, which uses software multiplication functions.
+The @code{g13} option is for the hardware multiply/divide peripheral
+only on the RL78/G13 targets. The @code{rl78} option is for the
+standard hardware multiplication defined in the RL78 software manual.
+
+@end table
+
@node RS/6000 and PowerPC Options
@subsection IBM RS/6000 and PowerPC Options
@cindex RS/6000 and PowerPC Options
This option is deprecated. It pads structures to multiple of 4 bytes,
which is incompatible with the SH ABI@.
+@item -msoft-atomic
+@opindex msoft-atomic
+Generate software atomic sequences for the atomic operations.
+This is the default when the target is @code{sh-*-linux*}.
+
@item -mspace
@opindex mspace
Optimize for space instead of speed. Implied by @option{-Os}.
Here is a list of each supported architecture and their supported
implementations.
-@smallexample
- v7: cypress
- v8: supersparc, hypersparc, leon
- sparclite: f930, f934, sparclite86x
- sparclet: tsc701
- v9: ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4
-@end smallexample
+@table @asis
+@item v7
+cypress
+
+@item v8
+supersparc, hypersparc, leon
+
+@item sparclite
+f930, f934, sparclite86x
+
+@item sparclet
+tsc701
+
+@item v9
+ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4
+@end table
By default (unless configured otherwise), GCC generates code for the V7
variant of the SPARC architecture. With @option{-mcpu=cypress}, the compiler
The 64-bit environment sets int to 32 bits and long and pointer
to 64 bits.
-@item -mcmodel=medlow
-@opindex mcmodel=medlow
-Generate code for the Medium/Low code model: 64-bit addresses, programs
+@item -mcmodel=@var{which}
+@opindex mcmodel
+Set the code model to one of
+
+@table @samp
+@item medlow
+The Medium/Low code model: 64-bit addresses, programs
must be linked in the low 32 bits of memory. Programs can be statically
or dynamically linked.
-@item -mcmodel=medmid
-@opindex mcmodel=medmid
-Generate code for the Medium/Middle code model: 64-bit addresses, programs
+@item medmid
+The Medium/Middle code model: 64-bit addresses, programs
must be linked in the low 44 bits of memory, the text and data segments must
be less than 2GB in size and the data segment must be located within 2GB of
the text segment.
-@item -mcmodel=medany
-@opindex mcmodel=medany
-Generate code for the Medium/Anywhere code model: 64-bit addresses, programs
+@item medany
+The Medium/Anywhere code model: 64-bit addresses, programs
may be linked anywhere in memory, the text and data segments must be less
than 2GB in size and the data segment must be located within 2GB of the
text segment.
-@item -mcmodel=embmedany
-@opindex mcmodel=embmedany
-Generate code for the Medium/Anywhere code model for embedded systems:
+@item embmedany
+The Medium/Anywhere code model for embedded systems:
64-bit addresses, the text and data segments must be less than 2GB in
size, both starting anywhere in memory (determined at link time). The
global register %g4 points to the base of the data segment. Programs
are statically linked and PIC is not supported.
+@end table
+
+@item -mmemory-model=@var{mem-model}
+@opindex mmemory-model
+Set the memory model in force on the processor to one of
+
+@table @samp
+@item default
+The default memory model for the processor and operating system.
+
+@item rmo
+Relaxed Memory Order
+
+@item pso
+Partial Store Order
+
+@item tso
+Total Store Order
+
+@item sc
+Sequential Consistency
+@end table
+
+These memory models are formally defined in Appendix D of the Sparc V9
+architecture manual, as set in the processor's @code{PSTATE.MM} field.
@item -mstack-bias
@itemx -mno-stack-bias