@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-@c 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
+@c 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
@c Free Software Foundation, Inc.
@c This is part of the GCC manual.
@c For copying conditions, see the file gcc.texi.
@c man begin COPYRIGHT
Copyright @copyright{} 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
+1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
+2012
Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
documented here, since you rarely need to use any of them.
@cindex C compilation options
-Most of the command line options that you can use with GCC are useful
+Most of the command-line options that you can use with GCC are useful
for C programs; when an option is only useful with another language
(usually C++), the explanation says so explicitly. If the description
for a particular option does not mention a source language, you can use
-fno-default-inline -fvisibility-inlines-hidden @gol
-fvisibility-ms-compat @gol
-Wabi -Wconversion-null -Wctor-dtor-privacy @gol
--Wnoexcept -Wnon-virtual-dtor -Wreorder @gol
+-Wdelete-non-virtual-dtor -Wnarrowing -Wnoexcept @gol
+-Wnon-virtual-dtor -Wreorder @gol
-Weffc++ -Wstrict-null-sentinel @gol
-Wno-non-template-friend -Wold-style-cast @gol
-Woverloaded-virtual -Wno-pmf-conversions @gol
-pedantic-errors @gol
-w -Wextra -Wall -Waddress -Waggregate-return -Warray-bounds @gol
-Wno-attributes -Wno-builtin-macro-redefined @gol
--Wc++-compat -Wc++0x-compat -Wcast-align -Wcast-qual @gol
+-Wc++-compat -Wc++11-compat -Wcast-align -Wcast-qual @gol
-Wchar-subscripts -Wclobbered -Wcomment @gol
-Wconversion -Wcoverage-mismatch -Wno-cpp -Wno-deprecated @gol
-Wno-deprecated-declarations -Wdisabled-optimization @gol
-Wno-unused-result -Wunused-value @gol -Wunused-variable @gol
-Wunused-but-set-parameter -Wunused-but-set-variable @gol
-Wvariadic-macros -Wvector-operation-performance -Wvla
--Wvolatile-register-var -Wwrite-strings}
+-Wvolatile-register-var -Wwrite-strings -Wzero-as-null-pointer-constant}
@item C and Objective-C-only Warning Options
@gccoptlist{-Wbad-function-cast -Wmissing-declarations @gol
-fprofile-correction -fprofile-dir=@var{path} -fprofile-generate @gol
-fprofile-generate=@var{path} @gol
-fprofile-use -fprofile-use=@var{path} -fprofile-values @gol
--freciprocal-math -fregmove -frename-registers -freorder-blocks @gol
+-freciprocal-math -free -fregmove -frename-registers -freorder-blocks @gol
-freorder-blocks-and-partition -freorder-functions @gol
-frerun-cse-after-loop -freschedule-modulo-scheduled-loops @gol
-frounding-math -fsched2-use-superblocks -fsched-pressure @gol
-iwithprefixbefore @var{dir} -isystem @var{dir} @gol
-imultilib @var{dir} -isysroot @var{dir} @gol
-M -MM -MF -MG -MP -MQ -MT -nostdinc @gol
--P -fworking-directory -remap @gol
--trigraphs -undef -U@var{macro} -Wp,@var{option} @gol
--Xpreprocessor @var{option}}
+-P -fdebug-cpp -ftrack-macro-expansion -fworking-directory @gol
+-remap -trigraphs -undef -U@var{macro} @gol
+-Wp,@var{option} -Xpreprocessor @var{option}}
@item Assembler Option
@xref{Assembler Options,,Passing Options to the Assembler}.
@c Try and put the significant identifier (CPU or system) first,
@c so users have a clue at guessing where the ones they want will be.
+@emph{Adapteva Epiphany Options}
+@gccoptlist{-mhalf-reg-file -mprefer-short-insn-regs @gol
+-mbranch-cost=@var{num} -mcmove -mnops=@var{num} -msoft-cmpsf @gol
+-msplit-lohi -mpost-inc -mpost-modify -mstack-offset=@var{num} @gol
+-mround-nearest -mlong-calls -mshort-calls -msmall16 @gol
+-mfp-mode=@var{mode} -mvect-double -max-vect-align=@var{num} @gol
+-msplit-vecmove-early -m1reg-@var{reg}}
+
@emph{ARM Options}
@gccoptlist{-mapcs-frame -mno-apcs-frame @gol
-mabi=@var{name} @gol
-mfix-cortex-m3-ldrd}
@emph{AVR Options}
-@gccoptlist{-mmcu=@var{mcu} -mno-interrupts @gol
--mcall-prologues -mtiny-stack -mint8}
+@gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol
+-mcall-prologues -mint8 -mno-interrupts -mrelax -mshort-calls @gol
+-mstrict-X -mtiny-stack}
@emph{Blackfin Options}
@gccoptlist{-mcpu=@var{cpu}@r{[}-@var{sirevision}@r{]} @gol
@emph{PowerPC Options}
See RS/6000 and PowerPC Options.
+@emph{RL78 Options}
+@gccoptlist{-msim -mmul=none -mmul=g13 -mmul=rl78}
+
@emph{RS/6000 and PowerPC Options}
@gccoptlist{-mcpu=@var{cpu-type} @gol
-mtune=@var{cpu-type} @gol
-mprefergot -musermode -multcost=@var{number} -mdiv=@var{strategy} @gol
-mdivsi3_libfunc=@var{name} -mfixed-range=@var{register-range} @gol
-madjust-unroll -mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol
--maccumulate-outgoing-args -minvalid-symbols}
+-maccumulate-outgoing-args -minvalid-symbols -msoft-atomic}
@emph{Solaris 2 Options}
@gccoptlist{-mimpure-text -mno-impure-text @gol
@gccoptlist{-mcpu=@var{cpu-type} @gol
-mtune=@var{cpu-type} @gol
-mcmodel=@var{code-model} @gol
+-mmemory-model=@var{mem-model} @gol
-m32 -m64 -mapp-regs -mno-app-regs @gol
-mfaster-structs -mno-faster-structs -mflat -mno-flat @gol
-mfpu -mno-fpu -mhard-float -msoft-float @gol
@item --help
@opindex help
-Print (on the standard output) a description of the command line options
+Print (on the standard output) a description of the command-line options
understood by @command{gcc}. If the @option{-v} option is also specified
then @option{--help} will also be passed on to the various processes
-invoked by @command{gcc}, so that they can display the command line options
+invoked by @command{gcc}, so that they can display the command-line options
they accept. If the @option{-Wextra} option has also been specified
-(prior to the @option{--help} option), then command line options which
+(prior to the @option{--help} option), then command-line options which
have no documentation associated with them will also be displayed.
@item --target-help
@opindex target-help
-Print (on the standard output) a description of target-specific command
-line options for each tool. For some targets extra target-specific
+Print (on the standard output) a description of target-specific command-line
+options for each tool. For some targets extra target-specific
information may also be printed.
@item --help=@{@var{class}@r{|[}^@r{]}@var{qualifier}@}@r{[},@dots{}@r{]}
-Print (on the standard output) a description of the command line
+Print (on the standard output) a description of the command-line
options understood by the compiler that fit into all specified classes
and qualifiers. These are the supported classes:
-mapcs [disabled]
@end smallexample
-The output is sensitive to the effects of previous command line
+The output is sensitive to the effects of previous command-line
options, so for example it is possible to find out which optimizations
are enabled at @option{-O2} by using:
@w{@uref{http://gcc.gnu.org/c99status.html}} for more information. The
names @samp{c9x} and @samp{iso9899:199x} are deprecated.
-@item c1x
-ISO C1X, the draft of the next revision of the ISO C standard.
-Support is limited and experimental and features enabled by this
-option may be changed or removed if changed in or removed from the
-standard draft.
+@item c11
+@itemx c1x
+@itemx iso9899:2011
+ISO C11, the 2011 revision of the ISO C standard.
+Support is incomplete and experimental. The name @samp{c1x} is
+deprecated.
@item gnu90
@itemx gnu89
GNU dialect of ISO C99. When ISO C99 is fully implemented in GCC,
this will become the default. The name @samp{gnu9x} is deprecated.
+@item gnu11
@item gnu1x
-GNU dialect of ISO C1X. Support is limited and experimental and
-features enabled by this option may be changed or removed if changed
-in or removed from the standard draft.
+GNU dialect of ISO C11. Support is incomplete and experimental. The
+name @samp{gnu1x} is deprecated.
@item c++98
The 1998 ISO C++ standard plus amendments. Same as @option{-ansi} for
GNU dialect of @option{-std=c++98}. This is the default for
C++ code.
-@item c++0x
-The working draft of the upcoming ISO C++0x standard. This option
-enables experimental features that are likely to be included in
-C++0x. The working draft is constantly changing, and any feature that is
-enabled by this flag may be removed from future versions of GCC if it is
-not part of the C++0x standard.
+@item c++11
+The 2011 ISO C++ standard plus amendments. Support for C++11 is still
+experimental, and may change in incompatible ways in future releases.
-@item gnu++0x
-GNU dialect of @option{-std=c++0x}. This option enables
-experimental features that may be removed in future versions of GCC.
+@item gnu++11
+GNU dialect of @option{-std=c++11}. Support for C++11 is still
+experimental, and may change in incompatible ways in future releases.
@end table
@item -fgnu89-inline
implies @option{-pthread}, and thus is only supported on targets that
have support for @option{-pthread}.
+@item -fgnu-tm
+@opindex fgnu-tm
+When the option @option{-fgnu-tm} is specified, the compiler will
+generate code for the Linux variant of Intel's current Transactional
+Memory ABI specification document (Revision 1.1, May 6 2009). This is
+an experimental feature whose interface may change in future versions
+of GCC, as the official specification changes. Please note that not
+all architectures are supported for this feature.
+
+For more information on GCC's support for transactional memory,
+@xref{Enabling libitm,,The GNU Transactional Memory Library,libitm,GNU
+Transactional Memory Library}.
+
+Note that the transactional memory feature is not supported with
+non-call exceptions (@option{-fnon-call-exceptions}).
+
@item -fms-extensions
@opindex fms-extensions
Accept some non-standard constructs used in Microsoft header files.
@section Options Controlling C++ Dialect
@cindex compiler options, C++
-@cindex C++ options, command line
+@cindex C++ options, command-line
@cindex options, C++
This section describes the command-line options that are only meaningful
for C++ programs; but you can also use most of the GNU compiler options
Version 3 corrects an error in mangling a constant address as a
template argument.
-Version 4 implements a standard mangling for vector types.
+Version 4, which first appeared in G++ 4.5, implements a standard
+mangling for vector types.
-Version 5 corrects the mangling of attribute const/volatile on
-function pointer types, decltype of a plain decl, and use of a
-function parameter in the declaration of another parameter.
+Version 5, which first appeared in G++ 4.6, corrects the mangling of
+attribute const/volatile on function pointer types, decltype of a
+plain decl, and use of a function parameter in the declaration of
+another parameter.
-Version 6 corrects the promotion behavior of C++0x scoped enums.
+Version 6, which first appeared in G++ 4.7, corrects the promotion
+behavior of C++11 scoped enums and the mangling of template argument
+packs, const/static_cast, prefix ++ and --, and a class scope function
+used as a template argument.
See also @option{-Wabi}.
@item -fconserve-space
@opindex fconserve-space
-Put uninitialized or runtime-initialized global variables into the
+Put uninitialized or run-time-initialized global variables into the
common segment, as C does. This saves space in the executable at the
cost of not diagnosing duplicate definitions. If you compile with this
flag and your program mysteriously crashes after @code{main()} has
@item -fconstexpr-depth=@var{n}
@opindex fconstexpr-depth
-Set the maximum nested evaluation depth for C++0x constexpr functions
+Set the maximum nested evaluation depth for C++11 constexpr functions
to @var{n}. A limit is needed to detect endless recursion during
constant expression evaluation. The minimum specified by the standard
is 512.
-@item -fno-deduce-init-list
-@opindex fno-deduce-init-list
-Disable deduction of a template type parameter as
+@item -fdeduce-init-list
+@opindex fdeduce-init-list
+Enable deduction of a template type parameter as
std::initializer_list from a brace-enclosed initializer list, i.e.
@smallexample
@}
@end smallexample
-This option is present because this deduction is an extension to the
-current specification in the C++0x working draft, and there was
-some concern about potential overload resolution problems.
+This deduction was implemented as a possible extension to the
+originally proposed semantics for the C++11 standard, but was not part
+of the final standard, so it is disabled by default. This option is
+deprecated, and may be removed in a future version of G++.
@item -ffriend-injection
@opindex ffriend-injection
@item -fno-enforce-eh-specs
@opindex fno-enforce-eh-specs
Don't generate code to check for violation of exception specifications
-at runtime. This option violates the C++ standard, but may be useful
+at run time. This option violates the C++ standard, but may be useful
for reducing code size in production builds, much like defining
@samp{NDEBUG}. This does not give user code permission to throw
exceptions in violation of the exception specifications; the compiler
@item -fno-rtti
@opindex fno-rtti
Disable generation of information about every class with virtual
-functions for use by the C++ runtime type identification features
+functions for use by the C++ run-time type identification features
(@samp{dynamic_cast} and @samp{typeid}). If you don't use those parts
of the language, you can save some space by using this flag. Note that
exception handling uses the same information, but it will generate it as
needed. The @samp{dynamic_cast} operator can still be used for casts that
-do not require runtime type information, i.e.@: casts to @code{void *} or to
+do not require run-time type information, i.e.@: casts to @code{void *} or to
unambiguous base classes.
@item -fstats
A limit on the template instantiation depth is needed to detect
endless recursions during template class instantiation. ANSI/ISO C++
conforming programs must not rely on a maximum depth greater than 17
-(changed to 1024 in C++0x). The default value is 900, as the compiler
+(changed to 1024 in C++11). The default value is 900, as the compiler
can run out of stack space before hitting 1024 in some situations.
@item -fno-threadsafe-statics
@item -fvisibility-inlines-hidden
@opindex fvisibility-inlines-hidden
This switch declares that the user does not attempt to compare
-pointers to inline methods where the addresses of the two functions
+pointers to inline functions or methods where the addresses of the two functions
were taken in different shared objects.
The effect of this is that GCC may, effectively, mark inline methods with
base class does not have a virtual destructor. This warning is enabled
by @option{-Wall}.
-@item -Wno-narrowing @r{(C++ and Objective-C++ only)}
+@item -Wnarrowing @r{(C++ and Objective-C++ only)}
@opindex Wnarrowing
@opindex Wno-narrowing
-With -std=c++0x, suppress the diagnostic required by the standard for
-narrowing conversions within @samp{@{ @}}, e.g.
+Warn when a narrowing conversion prohibited by C++11 occurs within
+@samp{@{ @}}, e.g.
@smallexample
int i = @{ 2.2 @}; // error: narrowing from double to int
@end smallexample
-This flag can be useful for compiling valid C++98 code in C++0x mode.
+This flag is included in @option{-Wall} and @option{-Wc++11-compat}.
+
+With -std=c++11, @option{-Wno-narrowing} suppresses the diagnostic
+required by the standard. Note that this does not affect the meaning
+of well-formed code; narrowing conversions are still considered
+ill-formed in SFINAE context.
@item -Wnoexcept @r{(C++ and Objective-C++ only)}
@opindex Wnoexcept
@section Options Controlling Objective-C and Objective-C++ Dialects
@cindex compiler options, Objective-C and Objective-C++
-@cindex Objective-C and Objective-C++ options, command line
+@cindex Objective-C and Objective-C++ options, command-line
@cindex options, Objective-C and Objective-C++
(NOTE: This manual does not describe the Objective-C and Objective-C++
languages themselves. @xref{Standards,,Language Standards
to be retained. This is useful in Zero-Link debugging mode, since it allows
for individual class implementations to be modified during program execution.
The GNU runtime currently always retains calls to @code{objc_get_class("@dots{}")}
-regardless of command line options.
+regardless of command-line options.
@item -gen-decls
@opindex gen-decls
@opindex fno-diagnostics-show-option
@opindex fdiagnostics-show-option
By default, each diagnostic emitted includes text which indicates the
-command line option that directly controls the diagnostic (if such an
+command-line option that directly controls the diagnostic (if such an
option is known to the diagnostic machinery). Specifying the
@option{-fno-diagnostics-show-option} flag suppresses that behavior.
-@item -Wcoverage-mismatch
-@opindex Wcoverage-mismatch
-Warn if feedback profiles do not match when using the
-@option{-fprofile-use} option.
-If a source file was changed between @option{-fprofile-gen} and
-@option{-fprofile-use}, the files with the profile feedback can fail
-to match the source file and GCC can not use the profile feedback
-information. By default, this warning is enabled and is treated as an
-error. @option{-Wno-coverage-mismatch} can be used to disable the
-warning or @option{-Wno-error=coverage-mismatch} can be used to
-disable the error. Disable the error for this warning can result in
-poorly optimized code, so disabling the error is useful only in the
-case of very minor changes such as bug fixes to an existing code-base.
-Completely disabling the warning is not recommended.
-
@end table
@node Warning Options
@gccoptlist{-Waddress @gol
-Warray-bounds @r{(only with} @option{-O2}@r{)} @gol
--Wc++0x-compat @gol
+-Wc++11-compat @gol
-Wchar-subscripts @gol
-Wenum-compare @r{(in C/Objc; this is on by default in C++)} @gol
-Wimplicit-int @r{(C and Objective-C only)} @gol
comment, or whenever a Backslash-Newline appears in a @samp{//} comment.
This warning is enabled by @option{-Wall}.
+@item -Wno-coverage-mismatch
+@opindex Wno-coverage-mismatch
+Warn if feedback profiles do not match when using the
+@option{-fprofile-use} option.
+If a source file was changed between @option{-fprofile-gen} and
+@option{-fprofile-use}, the files with the profile feedback can fail
+to match the source file and GCC cannot use the profile feedback
+information. By default, this warning is enabled and is treated as an
+error. @option{-Wno-coverage-mismatch} can be used to disable the
+warning or @option{-Wno-error=coverage-mismatch} can be used to
+disable the error. Disabling the error for this warning can result in
+poorly optimized code and is useful only in the
+case of very minor changes such as bug fixes to an existing code-base.
+Completely disabling the warning is not recommended.
+
@item -Wno-cpp
@r{(C, Objective-C, C++, Objective-C++ and Fortran only)}
@option{-Wformat}. Currently equivalent to @samp{-Wformat
-Wformat-nonliteral -Wformat-security -Wformat-y2k}.
-@item -Wnonnull @r{(C and Objective-C only)}
+@item -Wnonnull
@opindex Wnonnull
@opindex Wno-nonnull
Warn about passing a null pointer for arguments marked as
@opindex Wunused-result
@opindex Wno-unused-result
Do not warn if a caller of a function marked with attribute
-@code{warn_unused_result} (@pxref{Variable Attributes}) does not use
+@code{warn_unused_result} (@pxref{Function Attributes}) does not use
its return value. The default is @option{-Wunused-result}.
@item -Wunused-variable
entry to a use of the variable that is initialized, but there exist
some other paths the variable is not initialized, the compiler will
emit a warning if it can not prove the uninitialized paths do not
-happen at runtime. These warnings are made optional because GCC is
+happen at run time. These warnings are made optional because GCC is
not smart enough to see all the reasons why the code might be correct
despite appearing to have an error. Here is one example of how
this can happen:
@cindex unknown pragmas, warning
@cindex pragmas, warning of unknown
Warn when a #pragma directive is encountered which is not understood by
-GCC@. If this command line option is used, warnings will even be issued
+GCC@. If this command-line option is used, warnings will even be issued
for unknown pragmas in system header files. This is not the case if
-the warnings were only enabled by the @option{-Wall} command line option.
+the warnings were only enabled by the @option{-Wall} command-line option.
@item -Wno-pragmas
@opindex Wno-pragmas
@item -Wno-div-by-zero
@opindex Wno-div-by-zero
@opindex Wdiv-by-zero
-Do not warn about compile-time integer division by zero. Floating point
+Do not warn about compile-time integer division by zero. Floating-point
division by zero is not warned about, as it can be a legitimate way of
obtaining infinities and NaNs.
Print warning messages for constructs found in system header files.
Warnings from system headers are normally suppressed, on the assumption
that they usually do not indicate real problems and would only make the
-compiler output harder to read. Using this command line option tells
+compiler output harder to read. Using this command-line option tells
GCC to emit warnings from system headers as if they occurred in user
code. However, note that using @option{-Wall} in conjunction with this
option will @emph{not} warn about unknown pragmas in system
@item -Wfloat-equal
@opindex Wfloat-equal
@opindex Wno-float-equal
-Warn if floating point values are used in equality comparisons.
+Warn if floating-point values are used in equality comparisons.
The idea behind this is that sometimes it is convenient (for the
programmer) to consider floating-point values as approximations to
The unary plus operator.
@item
-The @samp{U} integer constant suffix, or the @samp{F} or @samp{L} floating point
+The @samp{U} integer constant suffix, or the @samp{F} or @samp{L} floating-point
constant suffixes. (Traditional C does support the @samp{L} suffix on integer
constants.) Note, these suffixes appear in macros defined in the system
headers of most modern systems, e.g.@: the @samp{_MIN}/@samp{_MAX} macros in @code{<limits.h>}.
traditional C case.
@item
-Conversions by prototypes between fixed/floating point values and vice
+Conversions by prototypes between fixed/floating-point values and vice
versa. The absence of these prototypes when compiling with traditional
C would cause serious problems. This is a subset of the possible
conversion warnings, for the full set use @option{-Wtraditional-conversion}.
Warn if a prototype causes a type conversion that is different from what
would happen to the same argument in the absence of a prototype. This
includes conversions of fixed point to floating and vice versa, and
-conversions changing the width or signedness of a fixed point argument
+conversions changing the width or signedness of a fixed-point argument
except when the same as the default promotion.
@item -Wdeclaration-after-statement @r{(C and Objective-C only)}
ISO C and ISO C++, e.g.@: request for implicit conversion from
@code{void *} to a pointer to non-@code{void} type.
-@item -Wc++0x-compat @r{(C++ and Objective-C++ only)}
-Warn about C++ constructs whose meaning differs between ISO C++ 1998 and
-ISO C++ 200x, e.g., identifiers in ISO C++ 1998 that will become keywords
-in ISO C++ 200x. This warning is enabled by @option{-Wall}.
+@item -Wc++11-compat @r{(C++ and Objective-C++ only)}
+Warn about C++ constructs whose meaning differs between ISO C++ 1998
+and ISO C++ 2011, e.g., identifiers in ISO C++ 1998 that are keywords
+in ISO C++ 2011. This warning turns on @option{-Wnarrowing} and is
+enabled by @option{-Wall}.
@item -Wcast-qual
@opindex Wcast-qual
Do not warn for conversions between @code{NULL} and non-pointer
types. @option{-Wconversion-null} is enabled by default.
+@item -Wzero-as-null-pointer-constant @r{(C++ and Objective-C++ only)}
+@opindex Wzero-as-null-pointer-constant
+@opindex Wno-zero-as-null-pointer-constant
+Warn when a literal '0' is used as null pointer constant. This can
+be useful to facilitate the conversion to @code{nullptr} in C++11.
+
@item -Wempty-body
@opindex Wempty-body
@opindex Wno-empty-body
@item -grecord-gcc-switches
@opindex grecord-gcc-switches
-This switch causes the command line options, that were used to invoke the
+This switch causes the command-line options, that were used to invoke the
compiler and may affect code generation, to be appended to the
DW_AT_producer attribute in DWARF debugging information. The options
are concatenated with spaces separating them from each other and from
@item -gno-record-gcc-switches
@opindex gno-record-gcc-switches
-Disallow appending command line options to the DW_AT_producer attribute
+Disallow appending command-line options to the DW_AT_producer attribute
in DWARF debugging information. This is the default.
@item -gstrict-dwarf
dynamically: in addition to the static allocation described above, stack
adjustments are made in the body of the function, for example to push/pop
arguments around function calls. If the qualifier @code{bounded} is also
-present, the amount of these adjustments is bounded at compile-time and
+present, the amount of these adjustments is bounded at compile time and
the second field is an upper bound of the total amount of stack used by
the function. If it is not present, the amount of these adjustments is
-not bounded at compile-time and the second field only represents the
+not bounded at compile time and the second field only represents the
bounded part.
@item -fprofile-arcs
@item -fdump-passes
@opindex fdump-passes
Dump the list of optimization passes that are turned on and off by
-the current command line options.
+the current command-line options.
@item -fdump-statistics-@var{option}
@opindex fdump-statistics
preprocessed @file{foo.i} output file even though the compiler now
normally uses an integrated preprocessor.
-When used in combination with the @option{-x} command line option,
+When used in combination with the @option{-x} command-line option,
@option{-save-temps} is sensible enough to avoid over writing an
input source file with the same extension as an intermediate file.
The corresponding intermediate file may be obtained by renaming the
@item -fno-inline
@opindex fno-inline
-Don't pay attention to the @code{inline} keyword. Normally this option
-is used to keep the compiler from expanding any functions inline.
-Note that if you are not optimizing, no functions can be expanded inline.
+Do not expand any functions inline apart from those marked with
+the @code{always_inline} attribute. This is the default when not
+optimizing.
+
+Single functions can be exempted from inlining by marking them
+with the @code{noinline} attribute.
@item -finline-small-functions
@opindex finline-small-functions
Integrate functions into their callers when their body is smaller than expected
function call code (so overall size of program gets smaller). The compiler
heuristically decides which functions are simple enough to be worth integrating
-in this way.
+in this way. This inlining applies to all functions, even those not declared
+inline.
Enabled at level @option{-O2}.
@item -finline-functions
@opindex finline-functions
-Integrate all simple functions into their callers. The compiler
-heuristically decides which functions are simple enough to be worth
-integrating in this way.
+Consider all functions for inlining, even if they are not declared inline.
+The compiler heuristically decides which functions are worth integrating
+in this way.
If all calls to a given function are integrated, and the function is
declared @code{static}, then the function is normally not output as
@item -fmerge-constants
@opindex fmerge-constants
-Attempt to merge identical constants (string constants and floating point
+Attempt to merge identical constants (string constants and floating-point
constants) across compilation units.
This option is the default for optimized compilation if the assembler and
This option implies @option{-fmerge-constants}. In addition to
@option{-fmerge-constants} this considers e.g.@: even constant initialized
-arrays or initialized constant variables with integral or floating point
+arrays or initialized constant variables with integral or floating-point
types. Languages like C or C++ require each variable, including multiple
instances of the same variable in recursive calls, to have distinct locations,
so using this option will result in non-conforming
This pass also performs global constant and copy propagation.
@emph{Note:} When compiling a program using computed gotos, a GCC
-extension, you may get better runtime performance if you disable
+extension, you may get better run-time performance if you disable
the global common subexpression elimination pass by adding
@option{-fno-gcse} to the command line.
Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}.
+@item -free
+@opindex free
+Attempt to remove redundant extension instructions. This is especially
+helpful for the x86-64 architecture which implicitly zero-extends in 64-bit
+registers after writing to their lower 32-bit half.
+
+Enabled for x86 at levels @option{-O2}, @option{-O3}.
+
@item -foptimize-register-move
@itemx -fregmove
@opindex foptimize-register-move
Use specified regions for the integrated register allocator. The
@var{region} argument should be one of @code{all}, @code{mixed}, or
@code{one}. The first value means using all loops as register
-allocation regions, the second value which is the default means using
-all loops except for loops with small register pressure as the
-regions, and third one means using all function as a single region.
-The first value can give best result for machines with small size and
-irregular register set, the third one results in faster and generates
-decent code and the smallest size code, and the default value usually
-give the best results in most cases and for most architectures.
+allocation regions, the second value which is enabled by default when
+compiling with optimization for speed (@option{-O}, @option{-O2},
+@dots{}) means using all loops except for loops with small register
+pressure as the regions, and third one which is enabled by default for
+@option{-Os} or @option{-O0} means using all function as a single
+region. The first value can give best result for machines with small
+size and irregular register set, the third one results in faster and
+generates decent code and the smallest size code, and the second value
+usually give the best results in most cases and for most
+architectures.
@item -fira-loop-pressure
@opindex fira-loop-pressure
eliminate execution stalls due to required data being unavailable. This
helps machines that have slow floating point or memory load instructions
by allowing other instructions to be issued until the result of the load
-or floating point instruction is required.
+or floating-point instruction is required.
Enabled at levels @option{-O2}, @option{-O3}.
@item -ftree-tail-merge
Look for identical code sequences. When found, replace one with a jump to the
other. This optimization is known as tail merging or cross jumping. This flag
-is enabled by default at @option{-O2} and higher. The run time of this pass can
+is enabled by default at @option{-O2} and higher. The compilation time
+in this pass can
be limited using @option{max-tail-merge-comparisons} parameter and
@option{max-tail-merge-iterations} parameter.
@opindex ftree-vect-loop-version
Perform loop versioning when doing loop vectorization on trees. When a loop
appears to be vectorizable except that data alignment or data dependence cannot
-be determined at compile time then vectorized and non-vectorized versions of
-the loop are generated along with runtime checks for alignment or dependence
+be determined at compile time, then vectorized and non-vectorized versions of
+the loop are generated along with run-time checks for alignment or dependence
to control which version is executed. This option is enabled by default
except at level @option{-Os} where it is disabled.
bodies are read from these ELF sections and instantiated as if they
had been part of the same translation unit.
-To use the link-timer optimizer, @option{-flto} needs to be specified at
-compile time and during the final link. For example,
+To use the link-time optimizer, @option{-flto} needs to be specified at
+compile time and during the final link. For example:
@smallexample
gcc -c -O2 -flto foo.c
gcc -o myprog -flto -O2 foo.o bar.o
@end smallexample
-The first two invocations to GCC will save a bytecode representation
+The first two invocations to GCC save a bytecode representation
of GIMPLE into special ELF sections inside @file{foo.o} and
-@file{bar.o}. The final invocation will read the GIMPLE bytecode from
-@file{foo.o} and @file{bar.o}, merge the two files into a single
-internal image, and compile the result as usual. Since both
+@file{bar.o}. The final invocation reads the GIMPLE bytecode from
+@file{foo.o} and @file{bar.o}, merges the two files into a single
+internal image, and compiles the result as usual. Since both
@file{foo.o} and @file{bar.o} are merged into a single image, this
-causes all the inter-procedural analyses and optimizations in GCC to
+causes all the interprocedural analyses and optimizations in GCC to
work across the two files as if they were a single one. This means,
-for example, that the inliner will be able to inline functions in
+for example, that the inliner is able to inline functions in
@file{bar.o} into functions in @file{foo.o} and vice-versa.
-Another (simpler) way to enable link-time optimization is,
+Another (simpler) way to enable link-time optimization is:
@smallexample
gcc -o myprog -flto -O2 foo.c bar.c
@end smallexample
-The above will generate bytecode for @file{foo.c} and @file{bar.c},
-merge them together into a single GIMPLE representation and optimize
+The above generates bytecode for @file{foo.c} and @file{bar.c},
+merges them together into a single GIMPLE representation and optimizes
them as usual to produce @file{myprog}.
The only important thing to keep in mind is that to enable link-time
To make whole program optimization effective, it is necessary to make
certain whole program assumptions. The compiler needs to know
what functions and variables can be accessed by libraries and runtime
-outside of the link time optimized unit. When supported by the linker,
-the linker plugin (see @option{-fuse-linker-plugin}) passes to the
-compiler information about used and externally visible symbols. When
+outside of the link-time optimized unit. When supported by the linker,
+the linker plugin (see @option{-fuse-linker-plugin}) passes information
+to the compiler about used and externally visible symbols. When
the linker plugin is not available, @option{-fwhole-program} should be
-used to allow the compiler to make these assumptions, which will lead
+used to allow the compiler to make these assumptions, which leads
to more aggressive optimization decisions.
Note that when a file is compiled with @option{-flto}, the generated
-object file will be larger than a regular object file because it will
-contain GIMPLE bytecodes and the usual final code. This means that
-object files with LTO information can be linked as a normal object
-file. So, in the previous example, if the final link is done with
-
-@smallexample
-gcc -o myprog foo.o bar.o
-@end smallexample
-
-The only difference will be that no inter-procedural optimizations
-will be applied to produce @file{myprog}. The two object files
-@file{foo.o} and @file{bar.o} will be simply sent to the regular
-linker.
+object file is larger than a regular object file because it
+contains GIMPLE bytecodes and the usual final code. This means that
+object files with LTO information can be linked as normal object
+files; if @option{-flto} is not passed to the linker, no
+interprocedural optimizations are applied.
Additionally, the optimization flags used to compile individual files
-are not necessarily related to those used at link-time. For instance,
+are not necessarily related to those used at link time. For instance,
@smallexample
gcc -c -O0 -flto foo.c
gcc -o myprog -flto -O3 foo.o bar.o
@end smallexample
-This will produce individual object files with unoptimized assembler
-code, but the resulting binary @file{myprog} will be optimized at
-@option{-O3}. Now, if the final binary is generated without
-@option{-flto}, then @file{myprog} will not be optimized.
+This produces individual object files with unoptimized assembler
+code, but the resulting binary @file{myprog} is optimized at
+@option{-O3}. If, instead, the final binary is generated without
+@option{-flto}, then @file{myprog} is not optimized.
-When producing the final binary with @option{-flto}, GCC will only
-apply link-time optimizations to those files that contain bytecode.
+When producing the final binary with @option{-flto}, GCC only
+applies link-time optimizations to those files that contain bytecode.
Therefore, you can mix and match object files and libraries with
-GIMPLE bytecodes and final object code. GCC will automatically select
+GIMPLE bytecodes and final object code. GCC automatically selects
which files to optimize in LTO mode and which files to link without
further processing.
-There are some code generation flags that GCC will preserve when
+There are some code generation flags that GCC preserves when
generating bytecodes, as they need to be used during the final link
stage. Currently, the following options are saved into the GIMPLE
bytecode files: @option{-fPIC}, @option{-fcommon} and all the
@option{-m} target flags.
-At link time, these options are read-in and reapplied. Note that the
-current implementation makes no attempt at recognizing conflicting
-values for these options. If two or more files have a conflicting
-value (e.g., one file is compiled with @option{-fPIC} and another
-isn't), the compiler will simply use the last value read from the
-bytecode files. It is recommended, then, that all the files
-participating in the same link be compiled with the same options.
+At link time, these options are read in and reapplied. Note that the
+current implementation makes no attempt to recognize conflicting
+values for these options. If different files have conflicting option
+values (e.g., one file is compiled with @option{-fPIC} and another
+isn't), the compiler simply uses the last value read from the
+bytecode files. It is recommended, then, that you compile all the files
+participating in the same link with the same options.
+
+If LTO encounters objects with C linkage declared with incompatible
+types in separate translation units to be linked together (undefined
+behavior according to ISO C99 6.2.7), a non-fatal diagnostic may be
+issued. The behavior is still undefined at run time.
Another feature of LTO is that it is possible to apply interprocedural
optimizations on files written in different languages. This requires
-some support in the language front end. Currently, the C, C++ and
+support in the language front end. Currently, the C, C++ and
Fortran front ends are capable of emitting GIMPLE bytecodes, so
-something like this should work
+something like this should work:
@smallexample
gcc -c -flto foo.c
Notice that the final link is done with @command{g++} to get the C++
runtime libraries and @option{-lgfortran} is added to get the Fortran
runtime libraries. In general, when mixing languages in LTO mode, you
-should use the same link command used when mixing languages in a
-regular (non-LTO) compilation. This means that if your build process
-was mixing languages before, all you need to add is @option{-flto} to
+should use the same link command options as when mixing languages in a
+regular (non-LTO) compilation; all you need to add is @option{-flto} to
all the compile and link commands.
-If LTO encounters objects with C linkage declared with incompatible
-types in separate translation units to be linked together (undefined
-behavior according to ISO C99 6.2.7), a non-fatal diagnostic may be
-issued. The behavior is still undefined at runtime.
-
If object files containing GIMPLE bytecode are stored in a library archive, say
@file{libfoo.a}, it is possible to extract and use them in an LTO link if you
-are using a linker with linker plugin support. To enable this feature, use
-the flag @option{-fuse-linker-plugin} at link-time:
+are using a linker with plugin support. To enable this feature, use
+the flag @option{-fuse-linker-plugin} at link time:
@smallexample
gcc -o myprog -O2 -flto -fuse-linker-plugin a.o b.o -lfoo
@end smallexample
-With the linker plugin enabled, the linker will extract the needed
-GIMPLE files from @file{libfoo.a} and pass them on to the running GCC
+With the linker plugin enabled, the linker extracts the needed
+GIMPLE files from @file{libfoo.a} and passes them on to the running GCC
to make them part of the aggregated GIMPLE image to be optimized.
-If you are not using a linker with linker plugin support and/or do not
-enable linker plugin then the objects inside @file{libfoo.a}
-will be extracted and linked as usual, but they will not participate
+If you are not using a linker with plugin support and/or do not
+enable the linker plugin, then the objects inside @file{libfoo.a}
+are extracted and linked as usual, but they do not participate
in the LTO optimization process.
-Link time optimizations do not require the presence of the whole program to
+Link-time optimizations do not require the presence of the whole program to
operate. If the program does not require any symbols to be exported, it is
-possible to combine @option{-flto} and with @option{-fwhole-program} to allow
+possible to combine @option{-flto} and @option{-fwhole-program} to allow
the interprocedural optimizers to use more aggressive assumptions which may
lead to improved optimization opportunities.
Use of @option{-fwhole-program} is not needed when linker plugin is
active (see @option{-fuse-linker-plugin}).
-Regarding portability: the current implementation of LTO makes no
-attempt at generating bytecode that can be ported between different
+The current implementation of LTO makes no
+attempt to generate bytecode that is portable between different
types of hosts. The bytecode files are versioned and there is a
strict version check, so bytecode files generated in one version of
GCC will not work with an older/newer version of GCC.
-Link time optimization does not play well with generating debugging
+Link-time optimization does not work well with generation of debugging
information. Combining @option{-flto} with
@option{-g} is currently experimental and expected to produce wrong
results.
You can also specify @option{-flto=jobserver} to use GNU make's
job server mode to determine the number of parallel jobs. This
is useful when the Makefile calling GCC is already executing in parallel.
-The parent Makefile will need a @samp{+} prepended to the command recipe
-for this to work. This will likely only work if @env{MAKE} is
+You must prepend a @samp{+} to the command recipe in the parent Makefile
+for this to work. This option likely only works if @env{MAKE} is
GNU make.
-This option is disabled by default.
+This option is disabled by default
@item -flto-partition=@var{alg}
@opindex flto-partition
-Specify the partitioning algorithm used by the link time optimizer.
+Specify the partitioning algorithm used by the link-time optimizer.
The value is either @code{1to1} to specify a partitioning mirroring
the original source files or @code{balanced} to specify partitioning
into equally sized chunks (whenever possible). Specifying @code{none}
@item -flto-report
Prints a report with internal details on the workings of the link-time
-optimizer. The contents of this report vary from version to version,
-it is meant to be useful to GCC developers when processing object
+optimizer. The contents of this report vary from version to version.
+It is meant to be useful to GCC developers when processing object
files in LTO mode (via @option{-flto}).
Disabled by default.
@item -fuse-linker-plugin
-Enables the use of a linker plugin during link time optimization. This
+Enables the use of a linker plugin during link-time optimization. This
option relies on plugin support in the linker, which is available in gold
or in GNU ld 2.21 or newer.
This option enables the extraction of object files with GIMPLE bytecode out
of library archives. This improves the quality of optimization by exposing
-more code to the link time optimizer. This information specifies what
+more code to the link-time optimizer. This information specifies what
symbols can be accessed externally (by non-LTO object or during dynamic
linking). Resulting code quality improvements on binaries (and shared
libraries that use hidden visibility) are similar to @code{-fwhole-program}.
See @option{-flto} for a description of the effect of this flag and how to
use it.
-Enabled by default when LTO support in GCC is enabled and GCC was compiled
-with a linker supporting plugins (GNU ld 2.21 or newer or gold).
+This option is enabled by default when LTO support in GCC is enabled
+and GCC was configured for use with
+a linker supporting plugins (GNU ld 2.21 or newer or gold).
@item -ffat-lto-objects
@opindex ffat-lto-objects
Fat LTO objects are object files that contain both the intermediate language
-and the object code. This makes them useable for both LTO linking and normal
-linking. This option makes effect only with @option{-flto} and is ignored
-at linktime.
+and the object code. This makes them usable for both LTO linking and normal
+linking. This option is effective only when compiling with @option{-flto}
+and is ignored at link time.
@option{-fno-fat-lto-objects} improves compilation time over plain LTO, but
requires the complete toolchain to be aware of LTO. It requires a linker with
The default is @option{-ffat-lto-objects} but this default is intended to
change in future releases when linker plugin enabled environments become more
common.
+
@item -fcompare-elim
@opindex fcompare-elim
After register allocation and post-register allocation instruction splitting,
the profile feedback data files. See @option{-fprofile-dir}.
@end table
-The following options control compiler behavior regarding floating
-point arithmetic. These options trade off between speed and
+The following options control compiler behavior regarding floating-point
+arithmetic. These options trade off between speed and
correctness. All must be specifically enabled.
@table @gcctabopt
@item -ffloat-store
@opindex ffloat-store
-Do not store floating point variables in registers, and inhibit other
-options that might change whether a floating point value is taken from a
+Do not store floating-point variables in registers, and inhibit other
+options that might change whether a floating-point value is taken from a
register or memory.
-@cindex floating point precision
+@cindex floating-point precision
This option prevents undesirable excess precision on machines such as
the 68000 where the floating registers (of the 68881) keep more
precision than a @code{double} is supposed to have. Similarly for the
computation result. NOTE: re-ordering may change the sign of zero as
well as ignore NaNs and inhibit or create underflow or overflow (and
thus cannot be used on a code which relies on rounding behavior like
-@code{(x + 2**52) - 2**52)}. May also reorder floating-point comparisons
+@code{(x + 2**52) - 2**52}. May also reorder floating-point comparisons
and thus may not be used when ordered comparisons are required.
This option requires that both @option{-fno-signed-zeros} and
@option{-fno-trapping-math} be in effect. Moreover, it doesn't make
@item -fno-signed-zeros
@opindex fno-signed-zeros
-Allow optimizations for floating point arithmetic that ignore the
+Allow optimizations for floating-point arithmetic that ignore the
signedness of zero. IEEE arithmetic specifies the behavior of
distinct +0.0 and @minus{}0.0 values, which then prohibits simplification
of expressions such as x+0.0 or 0.0*x (even with @option{-ffinite-math-only}).
@item -frounding-math
@opindex frounding-math
-Disable transformations and optimizations that assume default floating
-point rounding behavior. This is round-to-zero for all floating point
+Disable transformations and optimizations that assume default floating-point
+rounding behavior. This is round-to-zero for all floating point
to integer conversions, and round-to-nearest for all other arithmetic
truncations. This option should be specified for programs that change
the FP rounding mode dynamically, or that may be executed with a
non-default rounding mode. This option disables constant folding of
-floating point expressions at compile-time (which may be affected by
+floating-point expressions at compile time (which may be affected by
rounding mode) and arithmetic transformations that are unsafe in the
presence of sign-dependent rounding modes.
This option is experimental and does not currently guarantee to
disable all GCC optimizations that are affected by rounding mode.
Future versions of GCC may provide finer control of this setting
-using C99's @code{FENV_ACCESS} pragma. This command line option
+using C99's @code{FENV_ACCESS} pragma. This command-line option
will be used to specify the default state for @code{FENV_ACCESS}.
@item -fsignaling-nans
@item -fsingle-precision-constant
@opindex fsingle-precision-constant
-Treat floating point constant as single precision constant instead of
-implicitly converting it to double precision constant.
+Treat floating-point constants as single precision instead of
+implicitly converting them to double-precision constants.
@item -fcx-limited-range
@opindex fcx-limited-range
In some places, GCC uses various constants to control the amount of
optimization that is done. For example, GCC will not inline functions
that contain more that a certain number of instructions. You can
-control some of these constants on the command-line using the
+control some of these constants on the command line using the
@option{--param} option.
The names of specific parameters, and the meaning of the values, are
The maximum number of incoming edges to consider for crossjumping.
The algorithm used by @option{-fcrossjumping} is @math{O(N^2)} in
the number of edges incoming to each block. Increasing values mean
-more aggressive optimization, making the compile time increase with
+more aggressive optimization, making the compilation time increase with
probably small improvement in executable size.
@item min-crossjump-insns
instruction to fill a delay slot. If more than this arbitrary number of
instructions is searched, the time savings from filling the delay slot
will be minimal so stop searching. Increasing values mean more
-aggressive optimization, making the compile time increase with probably
-small improvement in executable run time.
+aggressive optimization, making the compilation time increase with probably
+small improvement in execution time.
@item max-delay-slot-live-search
When trying to fill delay slots, the maximum number of instructions to
consider when searching for a block with valid live register
information. Increasing this arbitrarily chosen value means more
-aggressive optimization, increasing the compile time. This parameter
+aggressive optimization, increasing the compilation time. This parameter
should be removed when the delay slot code is rewritten to maintain the
control-flow graph.
@item max-modulo-backtrack-attempts
The maximum number of backtrack attempts the scheduler should make
when modulo scheduling a loop. Larger values can exponentially increase
-compile time.
+compilation time.
@item max-inline-insns-single
Several parameters control the tree inliner used in gcc.
@item max-tail-merge-iterations
The maximum amount of iterations of the pass over the function. This is used to
-limit run time in tree tail merging. The default value is 2.
+limit compilation time in tree tail merging. The default value is 2.
@item max-unrolled-insns
The maximum number of instructions that a loop should have if that loop
constraints. The default value is 0.
@item vect-max-version-for-alignment-checks
-The maximum number of runtime checks that can be performed when
+The maximum number of run-time checks that can be performed when
doing loop versioning for alignment in the vectorizer. See option
ftree-vect-loop-version for more information.
@item vect-max-version-for-alias-checks
-The maximum number of runtime checks that can be performed when
+The maximum number of run-time checks that can be performed when
doing loop versioning for alias in the vectorizer. See option
ftree-vect-loop-version for more information.
@item max-reload-search-insns
The maximum number of instruction reload should look backward for equivalent
register. Increasing values mean more aggressive optimization, making the
-compile time increase with probably slightly better performance. The default
-value is 100.
+compilation time increase with probably slightly better performance.
+The default value is 100.
@item max-cselib-memory-locations
The maximum number of memory locations cselib should take into account.
-Increasing values mean more aggressive optimization, making the compile time
+Increasing values mean more aggressive optimization, making the compilation time
increase with probably slightly better performance. The default value is 500.
@item reorder-blocks-duplicate
instruction. This value is the best found from numerous experiments.
@item loop-invariant-max-bbs-in-loop
-Loop invariant motion can be very expensive, both in compile time and
-in amount of needed compile time memory, with very large loops. Loops
+Loop invariant motion can be very expensive, both in compilation time and
+in amount of needed compile-time memory, with very large loops. Loops
with more basic blocks than this parameter won't have loop invariant
motion optimization performed on them. The default value of the
parameter is 1000 for -O1 and 10000 for -O2 and above.
+@item loop-max-datarefs-for-datadeps
+Building data dapendencies is expensive for very large loops. This
+parameter limits the number of data references in loops that are
+considered for data dependence analysis. These large loops will not
+be handled then by the optimizations using loop data dependencies.
+The default value is 1000.
+
@item max-vartrack-size
Sets a maximum number of hash table slots to use during variable
tracking dataflow analysis of any function. If this limit is exceeded
@item max-vartrack-expr-depth
Sets a maximum number of recursion levels when attempting to map
variable names or debug temporaries to value expressions. This trades
-compile time for more complete debug information. If this is set too
+compilation time for more complete debug information. If this is set too
low, value expressions that are available and could be represented in
debug information may end up not being used; setting this higher may
enable the compiler to find more complex debug expressions, but compile
-time may grow exponentially, and even then, it may fail to find more
-usable expressions. The default is 10.
+time and memory use may grow. The default is 12.
@item min-nondebug-insn-uid
Use uids starting at this parameter for nondebug insns. The range below
@option{ipa-sra-ptr-growth-factor} times the size of the original
pointer parameter.
+@item tm-max-aggregate-size
+When making copies of thread-local variables in a transaction, this
+parameter specifies the size in bytes after which variables will be
+saved with the logging functions as opposed to save/restore code
+sequence pairs. This option only applies when using
+@option{-fgnu-tm}.
+
@item graphite-max-nb-scop-params
To avoid exponential effects in the Graphite loop transforms, the
number of parameters in a Static Control Part (SCoP) is bounded. The
default value is 10 parameters. A variable whose value is unknown at
-compile time and defined outside a SCoP is a parameter of the SCoP.
+compilation time and defined outside a SCoP is a parameter of the SCoP.
@item graphite-max-bbs-per-function
To avoid exponential effects in the detection of SCoPs, the size of
The maximum number of namespaces to consult for suggestions when C++
name lookup fails for an identifier. The default is 1000.
+@item sink-frequency-threshold
+The maximum relative execution frequency (in percents) of the target block
+relative to a statement's original block to allow statement sinking of a
+statement. Larger numbers result in more aggressive statement sinking.
+The default value is 75. A small positive adjustment is applied for
+statements with memory operands as those are even more profitable so sink.
+
@item max-stores-to-sink
The maximum number of conditional stores paires that can be sunk. Set to 0
if either vectorization (@option{-ftree-vectorize}) or if-conversion
(@option{-ftree-loop-if-convert}) is disabled. The default is 2.
+@item allow-load-data-races
+Allow optimizers to introduce new data races on loads.
+Set to 1 to allow, otherwise to 0. This option is enabled by default
+unless implicitly set by the @option{-fmemory-model=} option.
+
@item allow-store-data-races
Allow optimizers to introduce new data races on stores.
Set to 1 to allow, otherwise to 0. This option is enabled by default
unless implicitly set by the @option{-fmemory-model=} option.
+@item allow-packed-load-data-races
+Allow optimizers to introduce new data races on packed data loads.
+Set to 1 to allow, otherwise to 0. This option is enabled by default
+unless implicitly set by the @option{-fmemory-model=} option.
+
+@item allow-packed-store-data-races
+Allow optimizers to introduce new data races on packed data stores.
+Set to 1 to allow, otherwise to 0. This option is enabled by default
+unless implicitly set by the @option{-fmemory-model=} option.
+
@item case-values-threshold
The smallest number of different values for which it is best to use a
jump-table instead of a tree of conditional branches. If the value is
options into @option{-isystem} options for the preprocessor. In this case,
the compiler appends @samp{include} to the prefix.
-The run-time support file @file{libgcc.a} can also be searched for using
+The runtime support file @file{libgcc.a} can also be searched for using
the @option{-B} prefix, if needed. If it is not found there, the two
standard prefixes above are tried, and that is all. The file is left
out of the link if it is not found by those means.
the leading dash is omitted when specifying this option, and it is
automatically inserted if the substitution is performed. Thus the spec
string @samp{%@{foo@}} would match the command-line option @option{-foo}
-and would output the command line option @option{-foo}.
+and would output the command-line option @option{-foo}.
@item %W@{@code{S}@}
Like %@{@code{S}@} but mark last argument supplied within as a file to be
@c in Machine Dependent Options
@menu
+* Adapteva Epiphany Options::
* ARM Options::
* AVR Options::
* Blackfin Options::
* PDP-11 Options::
* picoChip Options::
* PowerPC Options::
+* RL78 Options::
* RS/6000 and PowerPC Options::
* RX Options::
* S/390 and zSeries Options::
* zSeries Options::
@end menu
+@node Adapteva Epiphany Options
+@subsection Adapteva Epiphany Options
+
+These @samp{-m} options are defined for Adapteva Epiphany:
+
+@table @gcctabopt
+@item -mhalf-reg-file
+@opindex mhalf-reg-file
+Don't allocate any register in the range @code{r32}@dots{}@code{r63}.
+That allows code to run on hardware variants that lack these registers.
+
+@item -mprefer-short-insn-regs
+@opindex mprefer-short-insn-regs
+Preferrentially allocate registers that allow short instruction generation.
+This can result in increasesd instruction count, so if this reduces or
+increases code size might vary from case to case.
+
+@item -mbranch-cost=@var{num}
+@opindex mbranch-cost
+Set the cost of branches to roughly @var{num} ``simple'' instructions.
+This cost is only a heuristic and is not guaranteed to produce
+consistent results across releases.
+
+@item -mcmove
+@opindex mcmove
+Enable the generation of conditional moves.
+
+@item -mnops=@var{num}
+@opindex mnops
+Emit @var{num} nops before every other generated instruction.
+
+@item -mno-soft-cmpsf
+@opindex mno-soft-cmpsf
+For single-precision floating-point comparisons, emit an fsub instruction
+and test the flags. This is faster than a software comparison, but can
+get incorrect results in the presence of NaNs, or when two different small
+numbers are compared such that their difference is calculated as zero.
+The default is @option{-msoft-cmpsf}, which uses slower, but IEEE-compliant,
+software comparisons.
+
+@item -mstack-offset=@var{num}
+@opindex mstack-offset
+Set the offset between the top of the stack and the stack pointer.
+E.g., a value of 8 means that the eight bytes in the range sp+0@dots{}sp+7
+can be used by leaf functions without stack allocation.
+Values other than @samp{8} or @samp{16} are untested and unlikely to work.
+Note also that this option changes the ABI, compiling a program with a
+different stack offset than the libraries have been compiled with
+will generally not work.
+This option can be useful if you want to evaluate if a different stack
+offset would give you better code, but to actually use a different stack
+offset to build working programs, it is recommended to configure the
+toolchain with the appropriate @samp{--with-stack-offset=@var{num}} option.
+
+@item -mno-round-nearest
+@opindex mno-round-nearest
+Make the scheduler assume that the rounding mode has been set to
+truncating. The default is @option{-mround-nearest}.
+
+@item -mlong-calls
+@opindex mlong-calls
+If not otherwise specified by an attribute, assume all calls might be beyond
+the offset range of the b / bl instructions, and therefore load the
+function address into a register before performing a (otherwise direct) call.
+This is the default.
+
+@item -mshort-calls
+@opindex short-calls
+If not otherwise specified by an attribute, assume all direct calls are
+in the range of the b / bl instructions, so use these instructions
+for direct calls. The default is @option{-mlong-calls}.
+
+@item -msmall16
+@opindex msmall16
+Assume addresses can be loaded as 16 bit unsigned values. This does not
+apply to function addresses for which @option{-mlong-calls} semantics
+are in effect.
+
+@item -mfp-mode=@var{mode}
+@opindex mfp-mode
+Set the prevailing mode of the floating-point unit.
+This determines the floating-point mode that is provided and expected
+at function call and return time. Making this mode match the mode you
+predominantly need at function start can make your programs smaller and
+faster by avoiding unnecessary mode switches.
+
+@var{mode} can be set to one the following values:
+
+@table @samp
+@item caller
+Any mode at function entry is valid, and retained or restored when
+the function returns, and when it calls other functions.
+This mode is useful for compiling libraries or other compilation units
+you might want to incorporate into different programs with different
+prevailing FPU modes, and the convenience of being able to use a single
+object file outweighs the size and speed overhead for any extra
+mode switching that might be needed, compared with what would be needed
+with a more specific choice of prevailing FPU mode.
+
+@item truncate
+This is the mode used for floating-point calculations with
+truncating (i.e.@: round towards zero) rounding mode. That includes
+conversion from floating point to integer.
+
+@item round-nearest
+This is the mode used for floating-point calculations with
+round-to-nearest-or-even rounding mode.
+
+@item int
+This is the mode used to perform integer calculations in the FPU, e.g.@:
+integer multiply, or integer multiply-and-accumulate.
+@end table
+
+The default is @option{-mfp-mode=caller}
+
+@item -mnosplit-lohi
+@opindex mnosplit-lohi
+@item -mno-postinc
+@opindex mno-postinc
+@item -mno-postmodify
+@opindex mno-postmodify
+Code generation tweaks that disable, respectively, splitting of 32
+bit loads, generation of post-increment addresses, and generation of
+post-modify addresses. The defaults are @option{msplit-lohi},
+@option{-mpost-inc}, and @option{-mpost-modify}.
+
+@item -mnovect-double
+@opindex mno-vect-double
+Change the preferred SIMD mode to SImode. The default is
+@option{-mvect-double}, which uses DImode as preferred SIMD mode.
+
+@item -max-vect-align=@var{num}
+@opindex max-vect-align
+The maximum alignment for SIMD vector mode types.
+@var{num} may be 4 or 8. The default is 8.
+Note that this is an ABI change, even though many library function
+interfaces will be unaffected, if they don't use SIMD vector modes
+in places where they affect size and/or alignment of relevant types.
+
+@item -msplit-vecmove-early
+@opindex msplit-vecmove-early
+Split vector moves into single word moves before reload. In theory this
+could give better register allocation, but so far the reverse seems to be
+generally the case.
+
+@item -m1reg-@var{reg}
+@opindex m1reg-
+Specify a register to hold the constant @minus{}1, which makes loading small negative
+constants and certain bitmasks faster.
+Allowable values for reg are r43 and r63, which specify to use that register
+as a fixed register, and none, which means that no register is used for this
+purpose. The default is @option{-m1reg-none}.
+
+@end table
+
@node ARM Options
@subsection ARM Options
@cindex ARM options
every function (that actually uses some stack space). If there is
insufficient space available then either the function
@samp{__rt_stkovf_split_small} or @samp{__rt_stkovf_split_big} will be
-called, depending upon the amount of stack space required. The run time
+called, depending upon the amount of stack space required. The runtime
system is required to provide these functions. The default is
@option{-mno-apcs-stack-check}, since this produces smaller code.
@c not currently implemented
@item -mapcs-float
@opindex mapcs-float
-Pass floating point arguments using the float point registers. This is
+Pass floating-point arguments using the floating-point registers. This is
one of the variants of the APCS@. This option is recommended if the
-target hardware has a floating point unit or if a lot of floating point
+target hardware has a floating-point unit or if a lot of floating-point
arithmetic is going to be performed by the code. The default is
@option{-mno-apcs-float}, since integer only code is slightly increased in
size if @option{-mapcs-float} is used.
@samp{arm10e}, @samp{arm1020e}, @samp{arm1022e},
@samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
@samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
-@samp{cortex-a5}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a15},
-@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5},
+@samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9},
+@samp{cortex-a15}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5},
@samp{cortex-m4}, @samp{cortex-m3},
@samp{cortex-m1},
@samp{cortex-m0},
@samp{fa526}, @samp{fa626},
@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}.
+
@option{-mcpu=generic-@var{arch}} is also permissible, and is
equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}.
See @option{-mtune} for more information.
+@option{-mcpu=native} causes the compiler to auto-detect the CPU
+of the build computer. At present, this feature is only supported on
+Linux, and not all architectures are recognised. If the auto-detect is
+unsuccessful the option has no effect.
+
@item -mtune=@var{name}
@opindex mtune
This option is very similar to the @option{-mcpu=} option, except that
range, and avoiding performance pitfalls of other CPUs. The effects of
this option may change in future GCC versions as CPU models come and go.
+@option{-mtune=native} causes the compiler to auto-detect the CPU
+of the build computer. At present, this feature is only supported on
+Linux, and not all architectures are recognised. If the auto-detect is
+unsuccessful the option has no effect.
+
@item -march=@var{name}
@opindex march
This specifies the name of the target ARM architecture. GCC uses this
@samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m},
@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
+@option{-march=native} causes the compiler to auto-detect the architecture
+of the build computer. At present, this feature is only supported on
+Linux, and not all architectures are recognised. If the auto-detect is
+unsuccessful the option has no effect.
+
@item -mfpu=@var{name}
@itemx -mfpe=@var{number}
@itemx -mfp=@var{number}
@opindex mfpu
@opindex mfpe
@opindex mfp
-This specifies what floating point hardware (or hardware emulation) is
+This specifies what floating-point hardware (or hardware emulation) is
available on the target. Permissible names are: @samp{fpa}, @samp{fpe2},
@samp{fpe3}, @samp{maverick}, @samp{vfp}, @samp{vfpv3}, @samp{vfpv3-fp16},
@samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd}, @samp{vfpv3xd-fp16},
of GCC@.
If @option{-msoft-float} is specified this specifies the format of
-floating point values.
+floating-point values.
If the selected floating-point hardware includes the NEON extension
(e.g. @option{-mfpu}=@samp{neon}), note that floating-point
@item -msingle-pic-base
@opindex msingle-pic-base
Treat the register used for PIC addressing as read-only, rather than
-loading it in the prologue for each function. The run-time system is
+loading it in the prologue for each function. The runtime system is
responsible for initializing this register with an appropriate value
before execution begins.
Insert NOPs into the instruction stream to in order to work around
problems with invalid Maverick instruction combinations. This option
is only valid if the @option{-mcpu=ep9312} option has been used to
-enable generation of instructions for the Cirrus Maverick floating
-point co-processor. This option is not enabled by default, since the
+enable generation of instructions for the Cirrus Maverick floating-point
+co-processor. This option is not enabled by default, since the
problem is only present in older Maverick implementations. The default
can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns}
switch.
@table @gcctabopt
@item -mmcu=@var{mcu}
@opindex mmcu
-Specify ATMEL AVR instruction set or MCU type.
+Specify Atmel AVR instruction set architectures (ISA) or MCU type.
-Instruction set avr1 is for the minimal AVR core, not supported by the C
-compiler, only for assembler programs (MCU types: at90s1200, attiny10,
-attiny11, attiny12, attiny15, attiny28).
+For a complete list of @var{mcu} values that are supported by avr-gcc,
+see the compiler output when called with the @code{--help=target}
+command line option.
+The default for this option is@tie{}@code{avr2}.
-Instruction set avr2 (default) is for the classic AVR core with up to
-8K program memory space (MCU types: at90s2313, at90s2323, attiny22,
-at90s2333, at90s2343, at90s4414, at90s4433, at90s4434, at90s8515,
-at90c8534, at90s8535).
+avr-gcc supports the following AVR devices and ISAs:
-Instruction set avr3 is for the classic AVR core with up to 128K program
-memory space (MCU types: atmega103, atmega603, at43usb320, at76c711).
+@table @code
-Instruction set avr4 is for the enhanced AVR core with up to 8K program
-memory space (MCU types: atmega8, atmega83, atmega85).
+@item avr1
+This ISA is implemented by the minimal AVR core and supported
+for assembler only.
+@*@var{mcu}@tie{}= @code{at90s1200},
+@code{attiny10}, @code{attiny11}, @code{attiny12}, @code{attiny15},
+@code{attiny28}.
+
+@item avr2
+``Classic'' devices with up to 8@tie{}KiB of program memory.
+@*@var{mcu}@tie{}= @code{at90s2313}, @code{attiny26}, @code{at90c8534},
+@dots{}
+
+@item avr25
+``Classic'' devices with up to 8@tie{}KiB of program memory and with
+the @code{MOVW} instruction.
+@*@var{mcu}@tie{}= @code{attiny2313}, @code{attiny261}, @code{attiny24},
+@dots{}
+
+@item avr3
+``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of program memory.
+@*@var{mcu}@tie{}= @code{at43usb355}, @code{at76c711}.
+
+@item avr31
+``Classic'' devices with 128@tie{}KiB of program memory.
+@*@var{mcu}@tie{}= @code{atmega103}, @code{at43usb320}.
+
+@item avr35
+``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of program
+memory and with the @code{MOVW} instruction.
+@*@var{mcu}@tie{}= @code{at90usb162}, @code{atmega8u2},
+@code{attiny167}, @dots{}
+
+@item avr4
+``Enhanced'' devices with up to 8@tie{}KiB of program memory.
+@*@var{mcu}@tie{}= @code{atmega8}, @code{atmega88}, @code{at90pwm81},
+@dots{}
+
+@item avr5
+``Enhanced'' devices with 16@tie{}KiB up to 64@tie{}KiB of program memory.
+@*@var{mcu}@tie{}= @code{atmega16}, @code{atmega6490}, @code{at90can64},
+@dots{}
+
+@item avr51
+``Enhanced'' devices with 128@tie{}KiB of program memory.
+@*@var{mcu}@tie{}= @code{atmega128}, @code{at90can128}, @code{at90usb1287},
+@dots{}
+
+@item avr6
+``Enhanced'' devices with 3-byte PC, i.e.@: with at least 256@tie{}KiB
+of program memory.
+@*@var{mcu}@tie{}= @code{atmega2560}, @code{atmega2561}.
-Instruction set avr5 is for the enhanced AVR core with up to 128K program
-memory space (MCU types: atmega16, atmega161, atmega163, atmega32, atmega323,
-atmega64, atmega128, at43usb355, at94k).
+@end table
-@item -mno-interrupts
-@opindex mno-interrupts
-Generated code is not compatible with hardware interrupts.
-Code size will be smaller.
+
+@item -maccumulate-args
+@opindex maccumulate-args
+Accumulate outgoing function arguments and acquire/release the needed
+stack space for outgoing function arguments once in function
+prologue/epilogue. Without this option, outgoing arguments are pushed
+before calling a function and popped afterwards.
+
+Popping the arguments after the function call can be expensive on
+AVR so that accumulating the stack space might lead to smaller
+executables because arguments need not to be removed from the
+stack after such a function call.
+
+This option can lead to reduced code size for functions that perform
+several calls to functions which get their arguments on the stack like
+calls to printf-like functions.
+
+@item -mbranch-cost=@var{cost}
+@opindex mbranch-cost
+Set the branch costs for conditional branch instructions to
+@var{cost}. Reasonable values for @var{cost} are small, non-negative
+integers. The default branch cost is 0.
@item -mcall-prologues
@opindex mcall-prologues
Functions prologues/epilogues expanded as call to appropriate
subroutines. Code size will be smaller.
-@item -mtiny-stack
-@opindex mtiny-stack
-Change only the low 8 bits of the stack pointer.
-
@item -mint8
@opindex mint8
Assume int to be 8 bit integer. This affects the sizes of all types: A
and long long will be 4 bytes. Please note that this option does not
comply to the C standards, but it will provide you with smaller code
size.
+
+@item -mno-interrupts
+@opindex mno-interrupts
+Generated code is not compatible with hardware interrupts.
+Code size will be smaller.
+
+@item -mrelax
+@opindex mrelax
+Try to replace @code{CALL} resp.@: @code{JMP} instruction by the shorter
+@code{RCALL} resp.@: @code{RJMP} instruction if applicable.
+Setting @code{-mrelax} just adds the @code{--relax} option to the
+linker command line when the linker is called.
+
+Jump relaxing is performed by the linker because jump offsets are not
+known before code is located. Therefore, the assembler code generated by the
+compiler will be the same, but the instructions in the executable may
+differ from instructions in the assembler code.
+
+@item -mshort-calls
+@opindex mshort-calls
+Use @code{RCALL}/@code{RJMP} instructions even on devices with
+16@tie{}KiB or more of program memory, i.e.@: on devices that
+have the @code{CALL} and @code{JMP} instructions.
+See also the @code{-mrelax} command line option.
+
+@item -mstrict-X
+@opindex mstrict-X
+Use address register @code{X} in a way proposed by the hardware. This means
+that @code{X} will only be used in indirect, post-increment or
+pre-decrement addressing.
+
+Without this option, the @code{X} register may be used in the same way
+as @code{Y} or @code{Z} which then is emulated by additional
+instructions.
+For example, loading a value with @code{X+const} addressing with a
+small non-negative @code{const < 64} to a register @var{Rn} will be
+performed as
+
+@example
+adiw r26, const ; X += const
+ld @var{Rn}, X ; @var{Rn} = *X
+sbiw r26, const ; X -= const
+@end example
+
+@item -mtiny-stack
+@opindex mtiny-stack
+Only use the lower 8@tie{}bits of the stack pointer and assume that the high
+byte of SP is always zero.
+@end table
+
+@subsubsection @code{EIND} and Devices with more than 128 Ki Bytes of Flash
+
+Pointers in the implementation are 16@tie{}bits wide.
+The address of a function or label is represented as word address so
+that indirect jumps and calls can target any code address in the
+range of 64@tie{}Ki words.
+
+In order to facilitate indirect jump on devices with more than 128@tie{}Ki
+bytes of program memory space, there is a special function register called
+@code{EIND} that serves as most significant part of the target address
+when @code{EICALL} or @code{EIJMP} instructions are used.
+
+Indirect jumps and calls on these devices are handled as follows by
+the compiler and are subject to some limitations:
+
+@itemize @bullet
+
+@item
+The compiler never sets @code{EIND}.
+
+@item
+The startup code from libgcc never sets @code{EIND}.
+Notice that startup code is a blend of code from libgcc and avr-libc.
+For the impact of avr-libc on @code{EIND}, see the
+@w{@uref{http://nongnu.org/avr-libc/user-manual,avr-libc user manual}}.
+
+@item
+The compiler uses @code{EIND} implicitely in @code{EICALL}/@code{EIJMP}
+instructions or might read @code{EIND} directly in order to emulate an
+indirect call/jump by means of a @code{RET} instruction.
+
+@item
+The compiler assumes that @code{EIND} never changes during the startup
+code or during the application. In particular, @code{EIND} is not
+saved/restored in function or interrupt service routine
+prologue/epilogue.
+
+@item
+It is legitimate for user-specific startup code to set up @code{EIND}
+early, for example by means of initialization code located in
+section @code{.init3}. Such code runs prior to general startup code
+that initializes RAM and calls constructors.
+
+@item
+For indirect calls to functions and computed goto, the linker will
+generate @emph{stubs}. Stubs are jump pads sometimes also called
+@emph{trampolines}. Thus, the indirect call/jump will jump to such a stub.
+The stub contains a direct jump to the desired address.
+
+@item
+Stubs will be generated automatically by the linker if
+the following two conditions are met:
+@itemize @minus
+
+@item The address of a label is taken by means of the @code{gs} modifier
+(short for @emph{generate stubs}) like so:
+@example
+LDI r24, lo8(gs(@var{func}))
+LDI r25, hi8(gs(@var{func}))
+@end example
+@item The final location of that label is in a code segment
+@emph{outside} the segment where the stubs are located.
+@end itemize
+
+@item
+The compiler will emit such @code{gs} modifiers for code labels in the
+following situations:
+@itemize @minus
+@item Taking address of a function or code label.
+@item Computed goto.
+@item If prologue-save function is used, see @option{-mcall-prologues}
+command-line option.
+@item Switch/case dispatch tables. If you do not want such dispatch
+tables you can specify the @option{-fno-jump-tables} command-line option.
+@item C and C++ constructors/destructors called during startup/shutdown.
+@item If the tools hit a @code{gs()} modifier explained above.
+@end itemize
+
+@item
+The default linker script is arranged for code with @code{EIND = 0}.
+If code is supposed to work for a setup with @code{EIND != 0}, a custom
+linker script has to be used in order to place the sections whose
+name start with @code{.trampolines} into the segment where @code{EIND}
+points to.
+
+@item
+Jumping to non-symbolic addresses like so is @emph{not} supported:
+
+@example
+int main (void)
+@{
+ /* Call function at word address 0x2 */
+ return ((int(*)(void)) 0x2)();
+@}
+@end example
+
+Instead, a stub has to be set up, i.e.@: the function has to be called
+through a symbol (@code{func_4} in the example):
+
+@example
+int main (void)
+@{
+ extern int func_4 (void);
+
+ /* Call function at byte address 0x4 */
+ return func_4();
+@}
+@end example
+
+and the application be linked with @code{-Wl,--defsym,func_4=0x4}.
+Alternatively, @code{func_4} can be defined in the linker script.
+@end itemize
+
+@subsubsection AVR Built-in Macros
+
+avr-gcc defines several built-in macros so that the user code can test
+for presence of absence of features. Almost any of the following
+built-in macros are deduced from device capabilities and thus
+triggered by the @code{-mmcu=} command-line option.
+
+For even more AVR-specific built-in macros see
+@ref{AVR Named Address Spaces} and @ref{AVR Built-in Functions}.
+
+@table @code
+
+@item __AVR_@var{Device}__
+Setting @code{-mmcu=@var{device}} defines this built-in macro that reflects
+the device's name. For example, @code{-mmcu=atmega8} will define the
+built-in macro @code{__AVR_ATmega8__}, @code{-mmcu=attiny261a} defines
+@code{__AVR_ATtiny261A__}, etc.
+
+The built-in macros' names follow
+the scheme @code{__AVR_@var{Device}__} where @var{Device} is
+the device name as from the AVR user manual. The difference between
+@var{Device} in the built-in macro and @var{device} in
+@code{-mmcu=@var{device}} is that the latter is always lower case.
+
+@item __AVR_HAVE_RAMPZ__
+@item __AVR_HAVE_ELPM__
+The device has the @code{RAMPZ} special function register and thus the
+@code{ELPM} instruction.
+
+@item __AVR_HAVE_ELPMX__
+The device has the @code{ELPM R@var{n},Z} and @code{ELPM
+R@var{n},Z+} instructions.
+
+@item __AVR_HAVE_MOVW__
+The device has the @code{MOVW} instruction to perform 16-bit
+register-register moves.
+
+@item __AVR_HAVE_LPMX__
+The device has the @code{LPM R@var{n},Z} and @code{LPM
+R@var{n},Z+} instructions.
+
+@item __AVR_HAVE_MUL__
+The device has a hardware multiplier.
+
+@item __AVR_HAVE_JMP_CALL__
+The device has the @code{JMP} and @code{CALL} instructions.
+This is the case for devices with at least 16@tie{}KiB of program
+memory and if @code{-mshort-calls} is not set.
+
+@item __AVR_HAVE_EIJMP_EICALL__
+@item __AVR_3_BYTE_PC__
+The device has the @code{EIJMP} and @code{EICALL} instructions.
+This is the case for devices with at least 256@tie{}KiB of program memory.
+This also means that the program counter
+(PC) is 3@tie{}bytes wide.
+
+@item __AVR_2_BYTE_PC__
+The program counter (PC) is 2@tie{}bytes wide. This is the case for devices
+with up to 128@tie{}KiB of program memory.
+
+@item __AVR_HAVE_8BIT_SP__
+@item __AVR_HAVE_16BIT_SP__
+The stack pointer (SP) is 8@tie{}bits resp. 16@tie{}bits wide.
+The definition of these macros is affected by @code{-mtiny-stack}.
+
+@item __NO_INTERRUPTS__
+This macro reflects the @code{-mno-interrupts} command line option.
+
+@item __AVR_ERRATA_SKIP__
+@item __AVR_ERRATA_SKIP_JMP_CALL__
+Some AVR devices (AT90S8515, ATmega103) must not skip 32-bit
+instructions because of a hardware erratum. Skip instructions are
+@code{SBRS}, @code{SBRC}, @code{SBIS}, @code{SBIC} and @code{CPSE}.
+The second macro is only defined if @code{__AVR_HAVE_JMP_CALL__} is also
+set.
+
+@item __AVR_SFR_OFFSET__=@var{offset}
+Instructions that can address I/O special function registers directly
+like @code{IN}, @code{OUT}, @code{SBI}, etc.@: may use a different
+address as if addressed by an instruction to access RAM like @code{LD}
+or @code{STS}. This offset depends on the device architecture and has
+to be subtracted from the RAM address in order to get the
+respective I/O@tie{}address.
+
@end table
@node Blackfin Options
@item -micplb
@opindex micplb
-Assume that ICPLBs are enabled at runtime. This has an effect on certain
+Assume that ICPLBs are enabled at run time. This has an effect on certain
anomaly workarounds. For Linux targets, the default is to assume ICPLBs
are enabled; for standalone applications the default is off.
@end table
@opindex mno-fp-regs
Generate code that uses (does not use) the floating-point register set.
@option{-mno-fp-regs} implies @option{-msoft-float}. If the floating-point
-register set is not used, floating point operands are passed in integer
+register set is not used, floating-point operands are passed in integer
registers as if they were integers and floating-point results are passed
in @code{$0} instead of @code{$f0}. This is a non-standard calling sequence,
so any function with a floating-point argument or return value called by code
@item -mieee
@opindex mieee
The Alpha architecture implements floating-point hardware optimized for
-maximum performance. It is mostly compliant with the IEEE floating
-point standard. However, for full compliance, software assistance is
-required. This option generates code fully IEEE compliant code
+maximum performance. It is mostly compliant with the IEEE floating-point
+standard. However, for full compliance, software assistance is
+required. This option generates code fully IEEE-compliant code
@emph{except} that the @var{inexact-flag} is not maintained (see below).
If this option is turned on, the preprocessor macro @code{_IEEE_FP} is
defined during compilation. The resulting code is less efficient but is
@table @samp
@item n
-Normal IEEE rounding mode. Floating point numbers are rounded towards
+Normal IEEE rounding mode. Floating-point numbers are rounded towards
the nearest machine number or towards the even machine number in case
of a tie.
Round towards minus infinity.
@item c
-Chopped rounding mode. Floating point numbers are rounded towards zero.
+Chopped rounding mode. Floating-point numbers are rounded towards zero.
@item d
-Dynamic rounding mode. A field in the floating point control register
+Dynamic rounding mode. A field in the floating-point control register
(@var{fpcr}, see Alpha architecture reference manual) controls the
rounding mode in effect. The C library initializes this register for
rounding towards plus infinity. Thus, unless your program modifies the
@item -mtrap-precision=@var{trap-precision}
@opindex mtrap-precision
-In the Alpha architecture, floating point traps are imprecise. This
+In the Alpha architecture, floating-point traps are imprecise. This
means without software assistance it is impossible to recover from a
floating trap and program execution normally needs to be terminated.
GCC can generate code that can assist operating system trap handlers
-in determining the exact location that caused a floating point trap.
+in determining the exact location that caused a floating-point trap.
Depending on the requirements of an application, different levels of
precisions can be selected:
@table @samp
@item p
Program precision. This option is the default and means a trap handler
-can only identify which program caused a floating point exception.
+can only identify which program caused a floating-point exception.
@item f
Function precision. The trap handler can determine the function that
-caused a floating point exception.
+caused a floating-point exception.
@item i
Instruction precision. The trap handler can determine the exact
-instruction that caused a floating point exception.
+instruction that caused a floating-point exception.
@end table
Other Alpha compilers provide the equivalent options called
Normally GCC examines a 32- or 64-bit integer constant to
see if it can construct it from smaller constants in two or three
instructions. If it cannot, it will output the constant as a literal and
-generate code to load it from the data segment at runtime.
+generate code to load it from the data segment at run time.
Use this option to require GCC to construct @emph{all} integer constants
using code, even if it takes more instructions (the maximum is six).
@itemx -mfloat-ieee
@opindex mfloat-vax
@opindex mfloat-ieee
-Generate code that uses (does not use) VAX F and G floating point
+Generate code that uses (does not use) VAX F and G floating-point
arithmetic instead of IEEE single and double precision.
@item -mexplicit-relocs
@item -mno-lsim
@opindex mno-lsim
-Assume that run-time support has been provided and so there is no need
+Assume that runtime support has been provided and so there is no need
to include the simulator library (@file{libsim.a}) on the linker
command line.
@item -mgpr-32
@opindex mgpr-32
-Only use the first 32 general purpose registers.
+Only use the first 32 general-purpose registers.
@item -mgpr-64
@opindex mgpr-64
-Use all 64 general purpose registers.
+Use all 64 general-purpose registers.
@item -mfpr-32
@opindex mfpr-32
-Use only the first 32 floating point registers.
+Use only the first 32 floating-point registers.
@item -mfpr-64
@opindex mfpr-64
-Use all 64 floating point registers
+Use all 64 floating-point registers.
@item -mhard-float
@opindex mhard-float
-Use hardware instructions for floating point operations.
+Use hardware instructions for floating-point operations.
@item -msoft-float
@opindex msoft-float
-Use library routines for floating point operations.
+Use library routines for floating-point operations.
@item -malloc-cc
@opindex malloc-cc
@item -mdouble
@opindex mdouble
-Use floating point double instructions.
+Use floating-point double instructions.
@item -mno-double
@opindex mno-double
-Do not use floating point double instructions.
+Do not use floating-point double instructions.
@item -mmedia
@opindex mmedia
@item -mdisable-fpregs
@opindex mdisable-fpregs
-Prevent floating point registers from being used in any manner. This is
-necessary for compiling kernels which perform lazy context switching of
-floating point registers. If you use this option and attempt to perform
-floating point operations, the compiler will abort.
+Prevent floating-point registers from being used in any manner. This is
+necessary for compiling kernels that perform lazy context switching of
+floating-point registers. If you use this option and attempt to perform
+floating-point operations, the compiler aborts.
@item -mdisable-indexing
@opindex mdisable-indexing
AMD Family 10h core based CPUs with x86-64 instruction set support. (This
supersets MMX, SSE, SSE2, SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bit
instruction set extensions.)
+@item bdver1
+AMD Family 15h core based CPUs with x86-64 instruction set support. (This
+supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A,
+SSSE3, SSE4.1, SSE4.2, 3DNow!, enhanced 3DNow!, ABM and 64-bit
+instruction set extensions.)
+@item btver1
+AMD Family 14h core based CPUs with x86-64 instruction set support. (This
+supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit
+instruction set extensions.)
@item winchip-c6
IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction
set support.
While picking a specific @var{cpu-type} will schedule things appropriately
for that particular chip, the compiler will not generate any code that
-does not run on the i386 without the @option{-march=@var{cpu-type}} option
-being used.
+does not run on the default machine type without the @option{-march=@var{cpu-type}}
+option being used. For example, if GCC is configured for i686-pc-linux-gnu
+then @option{-mtune=pentium4} will generate code that is tuned for Pentium4
+but will still run on i686 machines.
@item -march=@var{cpu-type}
@opindex march
@item -mfpmath=@var{unit}
@opindex mfpmath
-Generate floating point arithmetics for selected unit @var{unit}. The choices
+Generate floating-point arithmetic for selected unit @var{unit}. The choices
for @var{unit} are:
@table @samp
@item 387
-Use the standard 387 floating point coprocessor present majority of chips and
-emulated otherwise. Code compiled with this option will run almost everywhere.
-The temporary results are computed in 80bit precision instead of precision
-specified by the type resulting in slightly different results compared to most
+Use the standard 387 floating-point coprocessor present on the majority of chips and
+emulated otherwise. Code compiled with this option runs almost everywhere.
+The temporary results are computed in 80-bit precision instead of the precision
+specified by the type, resulting in slightly different results compared to most
of other chips. See @option{-ffloat-store} for more detailed description.
This is the default choice for i386 compiler.
@item sse
-Use scalar floating point instructions present in the SSE instruction set.
+Use scalar floating-point instructions present in the SSE instruction set.
This instruction set is supported by Pentium3 and newer chips, in the AMD line
by Athlon-4, Athlon-xp and Athlon-mp chips. The earlier version of SSE
-instruction set supports only single precision arithmetics, thus the double and
-extended precision arithmetics is still done using 387. Later version, present
-only in Pentium4 and the future AMD x86-64 chips supports double precision
-arithmetics too.
+instruction set supports only single-precision arithmetic, thus the double and
+extended-precision arithmetic are still done using 387. A later version, present
+only in Pentium4 and the future AMD x86-64 chips, supports double-precision
+arithmetic too.
For the i386 compiler, you need to use @option{-march=@var{cpu-type}}, @option{-msse}
or @option{-msse2} switches to enable SSE extensions and make this option
@itemx -mno-ieee-fp
@opindex mieee-fp
@opindex mno-ieee-fp
-Control whether or not the compiler uses IEEE floating point
+Control whether or not the compiler uses IEEE floating-point
comparisons. These handle correctly the case where the result of a
comparison is unordered.
own arrangements to provide suitable library functions for
cross-compilation.
-On machines where a function returns floating point results in the 80387
-register stack, some floating point opcodes may be emitted even if
+On machines where a function returns floating-point results in the 80387
+register stack, some floating-point opcodes may be emitted even if
@option{-msoft-float} is used.
@item -mno-fp-ret-in-387
Setting the rounding of floating-point operations to less than the default
80 bits can speed some programs by 2% or more. Note that some mathematical
-libraries assume that extended precision (80 bit) floating-point operations
+libraries assume that extended-precision (80-bit) floating-point operations
are enabled by default; routines in such libraries could suffer significant
loss of accuracy, typically through so-called "catastrophic cancellation",
when this option is used to set the precision to less than extended precision.
@opindex mstackrealign
Realign the stack at entry. On the Intel x86, the @option{-mstackrealign}
option will generate an alternate prologue and epilogue that realigns the
-runtime stack if necessary. This supports mixing legacy codes that keep
+run-time stack if necessary. This supports mixing legacy codes that keep
a 4-byte aligned stack with modern codes that keep a 16-byte stack for
SSE compatibility. See also the attribute @code{force_align_arg_pointer},
applicable to individual functions.
These options will enable GCC to use these extended instructions in
generated code, even without @option{-mfpmath=sse}. Applications which
-perform runtime CPU detection must compile separate files for each
+perform run-time CPU detection must compile separate files for each
supported architecture, using the appropriate flags. In particular,
the file containing the CPU detection code should be compiled without
these options.
CMPXCHG16B allows for atomic operations on 128-bit double quadword (or oword)
data types. This is useful for high resolution counters that could be updated
by multiple processors (or cores). This instruction is generated as part of
-atomic built-in functions: see @ref{Atomic Builtins} for details.
+atomic built-in functions: see @ref{__sync Builtins} or
+@ref{__atomic Builtins} for details.
@item -msahf
@opindex msahf
This option will enable GCC to use RCPSS and RSQRTSS instructions (and their
vectorized variants RCPPS and RSQRTPS) with an additional Newton-Raphson step
to increase precision instead of DIVSS and SQRTSS (and their vectorized
-variants) for single precision floating point arguments. These instructions
+variants) for single-precision floating-point arguments. These instructions
are generated only when @option{-funsafe-math-optimizations} is enabled
together with @option{-finite-math-only} and @option{-fno-trapping-math}.
Note that while the throughput of the sequence is higher than the throughput
of the non-reciprocal instruction, the precision of the sequence can be
decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994).
-Note that GCC implements 1.0f/sqrtf(x) in terms of RSQRTSS (or RSQRTPS)
+Note that GCC implements @code{1.0f/sqrtf(@var{x})} in terms of RSQRTSS
+(or RSQRTPS) already with @option{-ffast-math} (or the above option
+combination), and doesn't need @option{-mrecip}.
+
+Also note that GCC emits the above sequence with additional Newton-Raphson step
+for vectorized single-float division and vectorized @code{sqrtf(@var{x})}
already with @option{-ffast-math} (or the above option combination), and
doesn't need @option{-mrecip}.
@item -minline-stringops-dynamically
@opindex minline-stringops-dynamically
-For string operation of unknown size, inline runtime checks so for small
-blocks inline code is used, while for large blocks library call is used.
+For string operations of unknown size, use run-time checks with
+inline code for small blocks and a library call for large blocks.
@item -mstringop-strategy=@var{alg}
@opindex mstringop-strategy=@var{alg}
@item -m8bit-idiv
@itemx -mno-8bit-idiv
@opindex 8bit-idiv
-On some processors, like Intel Atom, 8bit unsigned integer divide is
-much faster than 32bit/64bit integer divide. This option will generate a
-runt-time check. If both dividend and divisor are within range of 0
-to 255, 8bit unsigned integer divide will be used instead of
-32bit/64bit integer divide.
+On some processors, like Intel Atom, 8-bit unsigned integer divide is
+much faster than 32-bit/64-bit integer divide. This option generates a
+run-time check. If both dividend and divisor are within range of 0
+to 255, 8-bit unsigned integer divide is used instead of
+32-bit/64-bit integer divide.
@item -mavx256-split-unaligned-load
@item -mavx256-split-unaligned-store
@item -minline-float-divide-min-latency
@opindex minline-float-divide-min-latency
-Generate code for inline divides of floating point values
+Generate code for inline divides of floating-point values
using the minimum latency algorithm.
@item -minline-float-divide-max-throughput
@opindex minline-float-divide-max-throughput
-Generate code for inline divides of floating point values
+Generate code for inline divides of floating-point values
using the maximum throughput algorithm.
@item -mno-inline-float-divide
@opindex mno-inline-float-divide
-Do not generate inline code for divides of floating point values.
+Do not generate inline code for divides of floating-point values.
@item -minline-int-divide-min-latency
@opindex minline-int-divide-min-latency
@item -mcfv4e
@opindex mcfv4e
Generate output for a ColdFire V4e family CPU (e.g.@: 547x/548x).
-This includes use of hardware floating point instructions.
+This includes use of hardware floating-point instructions.
The option is equivalent to @option{-mcpu=547x}, and is now
deprecated in favor of that option.
@item -mno-lsim
@opindex mno-lsim
-Assume that run-time support has been provided and so omit the
+Assume that runtime support has been provided and so omit the
simulator library (@file{libsim.a)} from the linker command line.
@item -mstack-increment=@var{size}
coprocessors, optional instructions, and peripherals. The
@code{MeP-Integrator} tool, not part of GCC, provides these
configurations through this option; using this option is the same as
-using all the corresponding command line options. The default
+using all the corresponding command-line options. The default
configuration is @code{default}.
@item -mcop
@item -mhard-float
@opindex mhard-float
-Use hardware floating point instructions.
+Use hardware floating-point instructions.
@item -mmemcpy
@opindex mmemcpy
@item -mxl-float-convert
@opindex mxl-float-convert
-Use hardware floating point conversion instructions.
+Use hardware floating-point conversion instructions.
@item -mxl-float-sqrt
@opindex mxl-float-sqrt
-Use hardware floating point square root instruction.
+Use hardware floating-point square root instruction.
@item -mxl-mode-@var{app-model}
Select application model @var{app-model}. Valid models are
@samp{1004kc}, @samp{1004kf2_1}, @samp{1004kf1_1},
@samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a},
@samp{m4k},
-@samp{octeon},
+@samp{octeon}, @samp{octeon+}, @samp{octeon2},
@samp{orion},
@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
@samp{r4600}, @samp{r4650}, @samp{r6000}, @samp{r8000},
@itemx -mno-fused-madd
@opindex mfused-madd
@opindex mno-fused-madd
-Enable (disable) use of the floating point multiply-accumulate
+Enable (disable) use of the floating-point multiply-accumulate
instructions, when they are available. The default is
@option{-mfused-madd}.
@opindex mfix-sb1
Work around certain SB-1 CPU core errata.
(This flag currently works around the SB-1 revision 2
-``F1'' and ``F2'' floating point errata.)
+``F1'' and ``F2'' floating-point errata.)
@item -mr10k-cache-barrier=@var{setting}
@opindex mr10k-cache-barrier
These are listed under @xref{RS/6000 and PowerPC Options}.
+@node RL78 Options
+@subsection RL78 Options
+@cindex RL78 Options
+
+@table @gcctabopt
+
+@item -msim
+@opindex msim
+Links in additional target libraries to support operation within a
+simulator.
+
+@item -mmul=none
+@itemx -mmul=g13
+@itemx -mmul=rl78
+@opindex mmul
+Specifies the type of hardware multiplication support to be used. The
+default is @code{none}, which uses software multiplication functions.
+The @code{g13} option is for the hardware multiply/divide peripheral
+only on the RL78/G13 targets. The @code{rl78} option is for the
+standard hardware multiplication defined in the RL78 software manual.
+
+@end table
+
@node RS/6000 and PowerPC Options
@subsection IBM RS/6000 and PowerPC Options
@cindex RS/6000 and PowerPC Options
processor and other processors that support the PowerPC V2.01
architecture.
The @option{-mpopcntb} option allows GCC to generate the popcount and
-double precision FP reciprocal estimate instruction implemented on the
+double-precision FP reciprocal estimate instruction implemented on the
POWER5 processor and other processors that support the PowerPC V2.02
architecture.
The @option{-mpopcntd} option allows GCC to generate the popcount
instruction implemented on the POWER6 processor and other processors
that support the PowerPC V2.05 architecture.
The @option{-mmfpgpr} option allows GCC to generate the FP move to/from
-general purpose register instructions implemented on the POWER6X
+general-purpose register instructions implemented on the POWER6X
processor and other processors that support the extended PowerPC V2.05
architecture.
-The @option{-mhard-dfp} option allows GCC to generate the decimal floating
-point instructions implemented on some POWER processors.
+The @option{-mhard-dfp} option allows GCC to generate the decimal
+floating-point instructions implemented on some POWER processors.
The @option{-mpowerpc64} option allows GCC to generate the additional
64-bit instructions that are found in the full PowerPC64 architecture
@item -mfloat-gprs=@var{yes/single/double/no}
@itemx -mfloat-gprs
@opindex mfloat-gprs
-This switch enables or disables the generation of floating point
-operations on the general purpose registers for architectures that
+This switch enables or disables the generation of floating-point
+operations on the general-purpose registers for architectures that
support it.
The argument @var{yes} or @var{single} enables the use of
-single-precision floating point operations.
+single-precision floating-point operations.
The argument @var{double} enables the use of single and
-double-precision floating point operations.
+double-precision floating-point operations.
-The argument @var{no} disables floating point operations on the
-general purpose registers.
+The argument @var{no} disables floating-point operations on the
+general-purpose registers.
This option is currently only available on the MPC854x.
@option{-mno-fp-in-toc} prevents GCC from putting floating-point
constants in the TOC and @option{-mno-sum-in-toc} forces GCC to
generate code to calculate the sum of an address and a constant at
-run-time instead of putting that sum into the TOC@. You may specify one
+run time instead of putting that sum into the TOC@. You may specify one
or both of these options. Each causes GCC to produce very slightly
slower and larger code at the expense of conserving TOC space.
The AIX calling convention was extended but not initially documented to
handle an obscure K&R C case of calling a function that takes the
address of its arguments with fewer arguments than declared. IBM XL
-compilers access floating point arguments which do not fit in the
+compilers access floating-point arguments that do not fit in the
RSA from the stack when a subroutine is compiled without
optimization. Because always storing floating-point arguments on the
stack is inefficient and rarely needed, this option is not enabled by
@opindex msoft-float
@opindex mhard-float
Generate code that does not use (uses) the floating-point register set.
-Software floating point emulation is provided if you use the
+Software floating-point emulation is provided if you use the
@option{-msoft-float} option, and pass the option to GCC when linking.
@item -msingle-float
@itemx -mdouble-float
@opindex msingle-float
@opindex mdouble-float
-Generate code for single or double-precision floating point operations.
+Generate code for single- or double-precision floating-point operations.
@option{-mdouble-float} implies @option{-msingle-float}.
@item -msimple-fpu
@opindex msimple-fpu
-Do not generate sqrt and div instructions for hardware floating point unit.
+Do not generate sqrt and div instructions for hardware floating-point unit.
@item -mfpu
@opindex mfpu
-Specify type of floating point unit. Valid values are @var{sp_lite}
+Specify type of floating-point unit. Valid values are @var{sp_lite}
(equivalent to -msingle-float -msimple-fpu), @var{dp_lite} (equivalent
to -mdouble-float -msimple-fpu), @var{sp_full} (equivalent to -msingle-float),
and @var{dp_full} (equivalent to -mdouble-float).
@item -mxilinx-fpu
@opindex mxilinx-fpu
-Perform optimizations for floating point unit on Xilinx PPC 405/440.
+Perform optimizations for the floating-point unit on Xilinx PPC 405/440.
@item -mmultiple
@itemx -mno-multiple
@itemx -mno-fused-madd
@opindex mfused-madd
@opindex mno-fused-madd
-Generate code that uses (does not use) the floating point multiply and
+Generate code that uses (does not use) the floating-point multiply and
accumulate instructions. These instructions are generated by default
-if hardware floating point is used. The machine dependent
-@option{-mfused-madd} option is now mapped to the machine independent
+if hardware floating point is used. The machine-dependent
+@option{-mfused-madd} option is now mapped to the machine-independent
@option{-ffp-contract=fast} option, and @option{-mno-fused-madd} is
mapped to @option{-ffp-contract=off}.
@opindex mrelocatable
@opindex mno-relocatable
Generate code that allows (does not allow) a static executable to be
-relocated to a different address at runtime. A simple embedded
+relocated to a different address at run time. A simple embedded
PowerPC system loader should relocate the entire contents of
@code{.got2} and 4-byte locations listed in the @code{.fixup} section,
a table of 32-bit addresses generated by this option. For this to
@opindex mno-relocatable-lib
Like @option{-mrelocatable}, @option{-mrelocatable-lib} generates a
@code{.fixup} section to allow static executables to be relocated at
-runtime, but @option{-mrelocatable-lib} does not use the smaller stack
+run time, but @option{-mrelocatable-lib} does not use the smaller stack
alignment of @option{-mrelocatable}. Objects compiled with
@option{-mrelocatable-lib} may be linked with objects compiled with
any combination of the @option{-mrelocatable} options.
@item -msingle-pic-base
@opindex msingle-pic-base
Treat the register used for PIC addressing as read-only, rather than
-loading it in the prologue for each function. The run-time system is
+loading it in the prologue for each function. The runtime system is
responsible for initializing this register with an appropriate value
before execution begins.
@item -mabi=ibmlongdouble
@opindex mabi=ibmlongdouble
-Change the current ABI to use IBM extended precision long double.
+Change the current ABI to use IBM extended-precision long double.
This is a PowerPC 32-bit SYSV ABI option.
@item -mabi=ieeelongdouble
@opindex mabi=ieeelongdouble
-Change the current ABI to use IEEE extended precision long double.
+Change the current ABI to use IEEE extended-precision long double.
This is a PowerPC 32-bit Linux ABI option.
@item -mprototype
variable argument functions are properly prototyped. Otherwise, the
compiler must insert an instruction before every non prototyped call to
set or clear bit 6 of the condition code register (@var{CR}) to
-indicate whether floating point values were passed in the floating point
-registers in case the function takes a variable arguments. With
+indicate whether floating-point values were passed in the floating-point
+registers in case the function takes variable arguments. With
@option{-mprototype}, only calls to prototyped variable argument functions
will set or clear the bit.
This option will enable GCC to use the reciprocal estimate and
reciprocal square root estimate instructions with additional
Newton-Raphson steps to increase precision instead of doing a divide or
-square root and divide for floating point arguments. You should use
+square root and divide for floating-point arguments. You should use
the @option{-ffast-math} option when using @option{-mrecip} (or at
least @option{-funsafe-math-optimizations},
@option{-finite-math-only}, @option{-freciprocal-math} and
@code{default}: enable the default instructions, equivalent to @option{-mrecip},
@code{none}: disable all estimate instructions, equivalent to @option{-mno-recip};
@code{div}: enable the reciprocal approximation instructions for both single and double precision;
-@code{divf}: enable the single precision reciprocal approximation instructions;
-@code{divd}: enable the double precision reciprocal approximation instructions;
+@code{divf}: enable the single-precision reciprocal approximation instructions;
+@code{divd}: enable the double-precision reciprocal approximation instructions;
@code{rsqrt}: enable the reciprocal square root approximation instructions for both single and double precision;
-@code{rsqrtf}: enable the single precision reciprocal square root approximation instructions;
-@code{rsqrtd}: enable the double precision reciprocal square root approximation instructions;
+@code{rsqrtf}: enable the single-precision reciprocal square root approximation instructions;
+@code{rsqrtd}: enable the double-precision reciprocal square root approximation instructions;
So for example, @option{-mrecip=all,!rsqrtd} would enable the
all of the reciprocal estimate instructions, except for the
@code{FRSQRTE}, @code{XSRSQRTEDP}, and @code{XVRSQRTEDP} instructions
-which handle the double precision reciprocal square root calculations.
+which handle the double-precision reciprocal square root calculations.
@item -mrecip-precision
@itemx -mno-recip-precision
@opindex mrecip-precision
Assume (do not assume) that the reciprocal estimate instructions
-provide higher precision estimates than is mandated by the powerpc
+provide higher-precision estimates than is mandated by the PowerPC
ABI. Selecting @option{-mcpu=power6} or @option{-mcpu=power7}
-automatically selects @option{-mrecip-precision}. The double
-precision square root estimate instructions are not generated by
-default on low precision machines, since they do not provide an
+automatically selects @option{-mrecip-precision}. The double-precision
+square root estimate instructions are not generated by
+default on low-precision machines, since they do not provide an
estimate that converges after three steps.
@item -mveclibabi=@var{type}
@opindex mfriz
Generate (do not generate) the @code{friz} instruction when the
@option{-funsafe-math-optimizations} option is used to optimize
-rounding a floating point value to 64-bit integer and back to floating
+rounding of floating-point values to 64-bit integer and back to floating
point. The @code{friz} instruction does not return the same value if
-the floating point number is too large to fit in an integer.
+the floating-point number is too large to fit in an integer.
@item -mpointers-to-nested-functions
@itemx -mno-pointers-to-nested-functions
@subsection RX Options
@cindex RX Options
-These command line options are defined for RX targets:
+These command-line options are defined for RX targets:
@table @gcctabopt
@item -m64bit-doubles
@itemx -m32bit-doubles
@opindex m64bit-doubles
@opindex m32bit-doubles
-Make the @code{double} data type be 64-bits (@option{-m64bit-doubles})
-or 32-bits (@option{-m32bit-doubles}) in size. The default is
-@option{-m32bit-doubles}. @emph{Note} RX floating point hardware only
+Make the @code{double} data type be 64 bits (@option{-m64bit-doubles})
+or 32 bits (@option{-m32bit-doubles}) in size. The default is
+@option{-m32bit-doubles}. @emph{Note} RX floating-point hardware only
works on 32-bit values, which is why the default is
@option{-m32bit-doubles}.
@opindex fpu
@opindex nofpu
Enables (@option{-fpu}) or disables (@option{-nofpu}) the use of RX
-floating point hardware. The default is enabled for the @var{RX600}
+floating-point hardware. The default is enabled for the @var{RX600}
series and disabled for the @var{RX200} series.
-Floating point instructions will only be generated for 32-bit floating
-point values however, so if the @option{-m64bit-doubles} option is in
+Floating-point instructions will only be generated for 32-bit floating-point
+values however, so if the @option{-m64bit-doubles} option is in
use then the FPU hardware will not be used for doubles.
@emph{Note} If the @option{-fpu} option is enabled then
The only difference between @var{RX600} and @var{RX610} is that the
@var{RX610} does not support the @code{MVTIPL} instruction.
-The @var{RX200} series does not have a hardware floating point unit
+The @var{RX200} series does not have a hardware floating-point unit
and so @option{-nofpu} is enabled by default when this type is
selected.
Enables the generation of position independent data. When enabled any
access to constant data will done via an offset from a base address
held in a register. This allows the location of constant data to be
-determined at run-time without requiring the executable to be
+determined at run time without requiring the executable to be
relocated, which is a benefit to embedded applications with tight
memory constraints. Data that can be modified is not affected by this
option.
The actual register chosen to hold the constant data base address
depends upon whether the @option{-msmall-data-limit} and/or the
-@option{-mint-register} command line options are enabled. Starting
+@option{-mint-register} command-line options are enabled. Starting
with register @code{r13} and proceeding downwards, registers are
allocated first to satisfy the requirements of @option{-mint-register},
then @option{-mpid} and finally @option{-msmall-data-limit}. Thus it
command line.
By default this feature is not enabled. The default can be restored
-via the @option{-mno-pid} command line option.
+via the @option{-mno-pid} command-line option.
@end table
-@emph{Note:} The generic GCC command line @option{-ffixed-@var{reg}}
+@emph{Note:} The generic GCC command-line option @option{-ffixed-@var{reg}}
has special significance to the RX port when used with the
@code{interrupt} function attribute. This attribute indicates a
function intended to process fast interrupts. GCC will will ensure
that it only uses the registers @code{r10}, @code{r11}, @code{r12}
and/or @code{r13} and only provided that the normal use of the
corresponding registers have been restricted via the
-@option{-ffixed-@var{reg}} or @option{-mint-register} command line
+@option{-ffixed-@var{reg}} or @option{-mint-register} command-line
options.
@node S/390 and zSeries Options
@itemx -mno-fused-madd
@opindex mfused-madd
@opindex mno-fused-madd
-Generate code that uses (does not use) the floating point multiply and
+Generate code that uses (does not use) the floating-point multiply and
accumulate instructions. These instructions are generated by default if
hardware floating point is used.
@item -mwarn-framesize=@var{framesize}
@opindex mwarn-framesize
Emit a warning if the current function exceeds the given frame size. Because
-this is a compile time check it doesn't need to be a real problem when the program
+this is a compile-time check it doesn't need to be a real problem when the program
runs. It is intended to identify functions which most probably cause
a stack overflow. It is useful to be used in an environment with limited stack
size e.g.@: the linux kernel.
@item -m2a-single-only
@opindex m2a-single-only
Generate code for the SH2a-FPU, in such a way that no double-precision
-floating point operations are used.
+floating-point operations are used.
@item -m2a-single
@opindex m2a-single
@item -m4a-single-only
@opindex m4a-single-only
Generate code for the SH4a, in such a way that no double-precision
-floating point operations are used.
+floating-point operations are used.
@item -m4a-single
@opindex m4a-single
@item -mieee
@opindex mieee
-Increase IEEE-compliance of floating-point code.
+Increase IEEE compliance of floating-point code.
At the moment, this is equivalent to @option{-fno-finite-math-only}.
When generating 16 bit SH opcodes, getting IEEE-conforming results for
comparisons of NANs / infinities incurs extra overhead in every
-floating point comparison, therefore the default is set to
+floating-point comparison, therefore the default is set to
@option{-ffinite-math-only}.
@item -minline-ic_invalidate
This option is deprecated. It pads structures to multiple of 4 bytes,
which is incompatible with the SH ABI@.
+@item -msoft-atomic
+@opindex msoft-atomic
+Generate software atomic sequences for the atomic operations.
+This is the default when the target is @code{sh-*-linux*}.
+
@item -mspace
@opindex mspace
Optimize for space instead of speed. Implied by @option{-Os}.
inv:call2, inv:fp .
"fp" performs the operation in floating point. This has a very high latency,
but needs only a few instructions, so it might be a good choice if
-your code has enough easily exploitable ILP to allow the compiler to
-schedule the floating point instructions together with other instructions.
-Division by zero causes a floating point exception.
+your code has enough easily-exploitable ILP to allow the compiler to
+schedule the floating-point instructions together with other instructions.
+Division by zero causes a floating-point exception.
"inv" uses integer operations to calculate the inverse of the divisor,
and then multiplies the dividend with the inverse. This strategy allows
cse and hoisting of the inverse calculation. Division by zero calculates
@itemx -mhard-float
@opindex mfpu
@opindex mhard-float
-Generate output containing floating point instructions. This is the
+Generate output containing floating-point instructions. This is the
default.
@item -mno-fpu
used, but this cannot be done directly in cross-compilation. You must make
your own arrangements to provide suitable library functions for
cross-compilation. The embedded targets @samp{sparc-*-aout} and
-@samp{sparclite-*-*} do provide software floating point support.
+@samp{sparclite-*-*} do provide software floating-point support.
@option{-msoft-float} changes the calling convention in the output file;
therefore, it is only useful if you compile @emph{all} of a program with
@item -mhard-quad-float
@opindex mhard-quad-float
-Generate output containing quad-word (long double) floating point
+Generate output containing quad-word (long double) floating-point
instructions.
@item -msoft-quad-float
@opindex msoft-quad-float
Generate output containing library calls for quad-word (long double)
-floating point instructions. The functions called are those specified
+floating-point instructions. The functions called are those specified
in the SPARC ABI@. This is the default.
As of this writing, there are no SPARC implementations that have hardware
-support for the quad-word floating point instructions. They all invoke
+support for the quad-word floating-point instructions. They all invoke
a trap handler for one of these instructions, and then the trap handler
emulates the effect of the instruction. Because of the trap handler overhead,
this is much slower than calling the ABI library routines. Thus the
absolute address. Otherwise, it assumes they have 4 byte alignment.
Specifying this option avoids some rare compatibility problems with code
generated by other compilers. It is not the default because it results
-in a performance loss, especially for floating point code.
+in a performance loss, especially for floating-point code.
@item -mno-faster-structs
@itemx -mfaster-structs
Here is a list of each supported architecture and their supported
implementations.
-@smallexample
- v7: cypress
- v8: supersparc, hypersparc, leon
- sparclite: f930, f934, sparclite86x
- sparclet: tsc701
- v9: ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4
-@end smallexample
+@table @asis
+@item v7
+cypress
+
+@item v8
+supersparc, hypersparc, leon
+
+@item sparclite
+f930, f934, sparclite86x
+
+@item sparclet
+tsc701
+
+@item v9
+ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4
+@end table
By default (unless configured otherwise), GCC generates code for the V7
variant of the SPARC architecture. With @option{-mcpu=cypress}, the compiler
The 64-bit environment sets int to 32 bits and long and pointer
to 64 bits.
-@item -mcmodel=medlow
-@opindex mcmodel=medlow
-Generate code for the Medium/Low code model: 64-bit addresses, programs
+@item -mcmodel=@var{which}
+@opindex mcmodel
+Set the code model to one of
+
+@table @samp
+@item medlow
+The Medium/Low code model: 64-bit addresses, programs
must be linked in the low 32 bits of memory. Programs can be statically
or dynamically linked.
-@item -mcmodel=medmid
-@opindex mcmodel=medmid
-Generate code for the Medium/Middle code model: 64-bit addresses, programs
+@item medmid
+The Medium/Middle code model: 64-bit addresses, programs
must be linked in the low 44 bits of memory, the text and data segments must
be less than 2GB in size and the data segment must be located within 2GB of
the text segment.
-@item -mcmodel=medany
-@opindex mcmodel=medany
-Generate code for the Medium/Anywhere code model: 64-bit addresses, programs
+@item medany
+The Medium/Anywhere code model: 64-bit addresses, programs
may be linked anywhere in memory, the text and data segments must be less
than 2GB in size and the data segment must be located within 2GB of the
text segment.
-@item -mcmodel=embmedany
-@opindex mcmodel=embmedany
-Generate code for the Medium/Anywhere code model for embedded systems:
+@item embmedany
+The Medium/Anywhere code model for embedded systems:
64-bit addresses, the text and data segments must be less than 2GB in
size, both starting anywhere in memory (determined at link time). The
global register %g4 points to the base of the data segment. Programs
are statically linked and PIC is not supported.
+@end table
+
+@item -mmemory-model=@var{mem-model}
+@opindex mmemory-model
+Set the memory model in force on the processor to one of
+
+@table @samp
+@item default
+The default memory model for the processor and operating system.
+
+@item rmo
+Relaxed Memory Order
+
+@item pso
+Partial Store Order
+
+@item tso
+Total Store Order
+
+@item sc
+Sequential Consistency
+@end table
+
+These memory models are formally defined in Appendix D of the Sparc V9
+architecture manual, as set in the processor's @code{PSTATE.MM} field.
@item -mstack-bias
@itemx -mno-stack-bias
@item -mg
@opindex mg
-Output code for g-format floating point numbers instead of d-format.
+Output code for G-format floating-point numbers instead of D-format.
@end table
@node VxWorks Options
Generate code that allows trapping instructions to throw exceptions.
Note that this requires platform-specific runtime support that does
not exist everywhere. Moreover, it only allows @emph{trapping}
-instructions to throw exceptions, i.e.@: memory references or floating
-point instructions. It does not allow exceptions to be thrown from
+instructions to throw exceptions, i.e.@: memory references or floating-point
+instructions. It does not allow exceptions to be thrown from
arbitrary signal handlers such as @code{SIGALRM}.
@item -funwind-tables
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