@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-@c 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+@c 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
@c Free Software Foundation, Inc.
@c This is part of the GCC manual.
@c For copying conditions, see the file gcc.texi.
@c man begin COPYRIGHT
Copyright @copyright{} 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
@cindex options, grouping
The @command{gcc} program accepts options and file names as operands. Many
options have multi-letter names; therefore multiple single-letter options
-may @emph{not} be grouped: @option{-dr} is very different from @w{@samp{-d
--r}}.
+may @emph{not} be grouped: @option{-dv} is very different from @w{@samp{-d
+-v}}.
@cindex order of options
@cindex options, order
-Wmissing-format-attribute -Wmissing-include-dirs @gol
-Wmissing-noreturn -Wno-mudflap @gol
-Wno-multichar -Wnonnull -Wno-overflow @gol
--Woverlength-strings -Wpacked -Wpadded @gol
--Wparentheses -Wpointer-arith -Wno-pointer-to-int-cast @gol
+-Woverlength-strings -Wpacked -Wpacked-bitfield-compat -Wpadded @gol
+-Wparentheses -Wpedantic-ms-format -Wno-pedantic-ms-format @gol
+-Wpointer-arith -Wno-pointer-to-int-cast @gol
-Wredundant-decls @gol
-Wreturn-type -Wsequence-point -Wshadow @gol
-Wsign-compare -Wsign-conversion -Wstack-protector @gol
-Wstrict-aliasing -Wstrict-aliasing=n @gol
-Wstrict-overflow -Wstrict-overflow=@var{n} @gol
--Wswitch -Wswitch-default -Wswitch-enum @gol
+-Wswitch -Wswitch-default -Wswitch-enum -Wsync-nand @gol
-Wsystem-headers -Wtrigraphs -Wtype-limits -Wundef -Wuninitialized @gol
-Wunknown-pragmas -Wno-pragmas -Wunreachable-code @gol
-Wunused -Wunused-function -Wunused-label -Wunused-parameter @gol
-ffunction-sections -fgcse -fgcse-after-reload -fgcse-las -fgcse-lm @gol
-fgcse-sm -fif-conversion -fif-conversion2 -findirect-inlining @gol
-finline-functions -finline-functions-called-once -finline-limit=@var{n} @gol
--finline-small-functions -fipa-cp -fipa-cp-clone -fipa-marix-reorg -fipa-pta @gol
+-finline-small-functions -fipa-cp -fipa-cp-clone -fipa-matrix-reorg -fipa-pta @gol
-fipa-pure-const -fipa-reference -fipa-struct-reorg @gol
--fipa-type-escape -fira -fira-algorithm=@var{algorithm} @gol
--fira-coalesce -fno-ira-share-save-slots @gol
+-fipa-type-escape -fira-algorithm=@var{algorithm} @gol
+-fira-region=@var{region} -fira-coalesce -fno-ira-share-save-slots @gol
-fno-ira-share-spill-slots -fira-verbose=@var{n} @gol
-fivopts -fkeep-inline-functions -fkeep-static-consts @gol
-floop-block -floop-interchange -floop-strip-mine @gol
@gccoptlist{@var{object-file-name} -l@var{library} @gol
-nostartfiles -nodefaultlibs -nostdlib -pie -rdynamic @gol
-s -static -static-libgcc -shared -shared-libgcc -symbolic @gol
--Wl,@var{option} -Xlinker @var{option} @gol
+-T @var{script} -Wl,@var{option} -Xlinker @var{option} @gol
-u @var{symbol}}
@item Directory Options
-mthumb -marm @gol
-mtpcs-frame -mtpcs-leaf-frame @gol
-mcaller-super-interworking -mcallee-super-interworking @gol
--mtp=@var{name}
--mword-relocations}
+-mtp=@var{name} @gol
+-mword-relocations @gol
+-mfix-cortex-m3-ldrd}
@emph{AVR Options}
@gccoptlist{-mmcu=@var{mcu} -msize -minit-stack=@var{n} -mno-interrupts @gol
-mno-id-shared-library -mshared-library-id=@var{n} @gol
-mleaf-id-shared-library -mno-leaf-id-shared-library @gol
-msep-data -mno-sep-data -mlong-calls -mno-long-calls @gol
--mfast-fp -minline-plt -mmulticore -mcorea -mcoreb -msdram}
+-mfast-fp -minline-plt -mmulticore -mcorea -mcoreb -msdram @gol
+-micplb}
@emph{CRIS Options}
@gccoptlist{-mcpu=@var{cpu} -march=@var{cpu} -mtune=@var{cpu} @gol
@emph{DEC Alpha/VMS Options}
@gccoptlist{-mvms-return-codes}
+@emph{FR30 Options}
+@gccoptlist{-msmall-model -mno-lsim}
+
@emph{FRV Options}
@gccoptlist{-mgpr-32 -mgpr-64 -mfpr-32 -mfpr-64 @gol
-mhard-float -msoft-float @gol
-momit-leaf-frame-pointer -mno-red-zone -mno-tls-direct-seg-refs @gol
-mcmodel=@var{code-model} @gol
-m32 -m64 -mlarge-data-threshold=@var{num} @gol
--mfused-madd -mno-fused-madd}
+-mfused-madd -mno-fused-madd -msse2avx}
@emph{IA-64 Options}
@gccoptlist{-mbig-endian -mlittle-endian -mgnu-as -mgnu-ld -mno-pic @gol
-mshared -mno-shared -mplt -mno-plt -mxgot -mno-xgot @gol
-mgp32 -mgp64 -mfp32 -mfp64 -mhard-float -msoft-float @gol
-msingle-float -mdouble-float -mdsp -mno-dsp -mdspr2 -mno-dspr2 @gol
+-mfpu=@var{fpu-type} @gol
-msmartmips -mno-smartmips @gol
-mpaired-single -mno-paired-single -mdmx -mno-mdmx @gol
-mips3d -mno-mips3d -mmt -mno-mt -mllsc -mno-llsc @gol
-mmemcpy -mno-memcpy -mlong-calls -mno-long-calls @gol
-mmad -mno-mad -mfused-madd -mno-fused-madd -nocpp @gol
-mfix-r4000 -mno-fix-r4000 -mfix-r4400 -mno-fix-r4400 @gol
--mfix-vr4120 -mno-fix-vr4120 -mfix-vr4130 -mno-fix-vr4130 @gol
--mfix-sb1 -mno-fix-sb1 @gol
+-mfix-r10000 -mno-fix-r10000 -mfix-vr4120 -mno-fix-vr4120 @gol
+-mfix-vr4130 -mno-fix-vr4130 -mfix-sb1 -mno-fix-sb1 @gol
-mflush-func=@var{func} -mno-flush-func @gol
-mbranch-cost=@var{num} -mbranch-likely -mno-branch-likely @gol
-mfp-exceptions -mno-fp-exceptions @gol
-msoft-float -mhard-float -mmultiple -mno-multiple @gol
-msingle-float -mdouble-float -msimple-fpu @gol
-mstring -mno-string -mupdate -mno-update @gol
+-mavoid-indexed-addresses -mno-avoid-indexed-addresses @gol
-mfused-madd -mno-fused-madd -mbit-align -mno-bit-align @gol
-mstrict-align -mno-strict-align -mrelocatable @gol
-mno-relocatable -mrelocatable-lib -mno-relocatable-lib @gol
-mspe -mno-spe @gol
-mspe=yes -mspe=no @gol
-mpaired @gol
+-mgen-cell-microcode -mwarn-cell-microcode @gol
-mvrsave -mno-vrsave @gol
-mmulhw -mno-mulhw @gol
-mdlmzb -mno-dlmzb @gol
The compiler can accept several base standards, such as @samp{c89} or
@samp{c++98}, and GNU dialects of those standards, such as
-@samp{gnu89} or @samp{gnu++98}. By specifing a base standard, the
+@samp{gnu89} or @samp{gnu++98}. By specifying a base standard, the
compiler will accept all programs following that standard and those
using GNU extensions that do not contradict it. For example,
@samp{-std=c89} turns off certain features of GCC that are
incompatible with ISO C90, such as the @code{asm} and @code{typeof}
keywords, but not other GNU extensions that do not have a meaning in
ISO C90, such as omitting the middle term of a @code{?:}
-expression. On the other hand, by specifing a GNU dialect of a
+expression. On the other hand, by specifying a GNU dialect of a
standard, all features the compiler support are enabled, even when
those features change the meaning of the base standard and some
strict-conforming programs may be rejected. The particular standard
functions will have linkage like inline functions; they just won't be
inlined by default.
-@item -Wabi @r{(C++ and Objective-C++ only)}
+@item -Wabi @r{(C, Objective-C, C++ and Objective-C++ only)}
@opindex Wabi
@opindex Wno-abi
Warn when G++ generates code that is probably not compatible with the
@end itemize
+It also warns psABI related changes. The known psABI changes at this
+point include:
+
+@itemize @bullet
+
+@item
+For SYSV/x86-64, when passing union with long double, it is changed to
+pass in memory as specified in psABI. For example:
+
+@smallexample
+union U @{
+ long double ld;
+ int i;
+@};
+@end smallexample
+
+@noindent
+@code{union U} will always be passed in memory.
+
+@end itemize
+
@item -Wctor-dtor-privacy @r{(C++ and Objective-C++ only)}
@opindex Wctor-dtor-privacy
@opindex Wno-ctor-dtor-privacy
Warn also about the use of an uncasted @code{NULL} as sentinel. When
compiling only with GCC this is a valid sentinel, as @code{NULL} is defined
to @code{__null}. Although it is a null pointer constant not a null pointer,
-it is guaranteed to of the same size as a pointer. But this use is
+it is guaranteed to be of the same size as a pointer. But this use is
not portable across different compilers.
@item -Wno-non-template-friend @r{(C++ and Objective-C++ only)}
enumeration. @code{case} labels outside the enumeration range also
provoke warnings when this option is used.
+@item -Wsync-nand @r{(C and C++ only)}
+@opindex Wsync-nand
+@opindex Wno-sync-nand
+Warn when @code{__sync_fetch_and_nand} and @code{__sync_nand_and_fetch}
+built-in functions are used. These functions changed semantics in GCC 4.4.
+
@item -Wtrigraphs
@opindex Wtrigraphs
@opindex Wno-trigraphs
@option{-funsafe-loop-optimizations} warn if the compiler made
such assumptions.
+@item -Wno-pedantic-ms-format @r{(MinGW targets only)}
+@opindex Wno-pedantic-ms-format
+@opindex Wpedantic-ms-format
+Disables the warnings about non-ISO @code{printf} / @code{scanf} format
+width specifiers @code{I32}, @code{I64}, and @code{I} used on Windows targets
+depending on the MS runtime, when you are using the options @option{-Wformat}
+and @option{-pedantic} without gnu-extensions.
+
@item -Wpointer-arith
@opindex Wpointer-arith
@opindex Wno-pointer-arith
@opindex Wempty-body
@opindex Wno-empty-body
Warn if an empty body occurs in an @samp{if}, @samp{else} or @samp{do
-while} statement. Additionally, in C++, warn when an empty body occurs
-in a @samp{while} or @samp{for} statement with no whitespacing before
-the semicolon. This warning is also enabled by @option{-Wextra}.
+while} statement. This warning is also enabled by @option{-Wextra}.
@item -Wenum-compare @r{(C++ and Objective-C++ only)}
@opindex Wenum-compare
@end group
@end smallexample
+@item -Wpacked-bitfield-compat
+@opindex Wpacked-bitfield-compat
+@opindex Wno-packed-bitfield-compat
+The 4.1, 4.2 and 4.3 series of GCC ignore the @code{packed} attribute
+on bit-fields of type @code{char}. This has been fixed in GCC 4.4 but
+the change can lead to differences in the structure layout. GCC
+informs you when the offset of such a field has changed in GCC 4.4.
+For example there is no longer a 4-bit padding between field @code{a}
+and @code{b} in this structure:
+
+@smallexample
+struct foo
+@{
+ char a:4;
+ char b:8;
+@} __attribute__ ((packed));
+@end smallexample
+
+This warning is enabled by default. Use
+@option{-Wno-packed-bitfield-compat} to disable this warning.
+
@item -Wpadded
@opindex Wpadded
@opindex Wno-padded
switches may have different effects when @option{-E} is used for
preprocessing.
-Most debug dumps can be enabled either passing a letter to the @option{-d}
-option, or with a long @option{-fdump-rtl} switch; here are the possible
-letters for use in @var{letters} and @var{pass}, and their meanings:
+Debug dumps can be enabled with a @option{-fdump-rtl} switch or some
+@option{-d} option @var{letters}. Here are the possible
+letters for use in @var{pass} and @var{letters}, and their meanings:
@table @gcctabopt
-@item -dA
-@opindex dA
-Annotate the assembler output with miscellaneous debugging information.
+
+@item -fdump-rtl-alignments
+@opindex fdump-rtl-alignments
+Dump after branch alignments have been computed.
+
+@item -fdump-rtl-asmcons
+@opindex fdump-rtl-asmcons
+Dump after fixing rtl statements that have unsatisfied in/out constraints.
+
+@item -fdump-rtl-auto_inc_dec
+@opindex fdump-rtl-auto_inc_dec
+Dump after auto-inc-dec discovery. This pass is only run on
+architectures that have auto inc or auto dec instructions.
+
+@item -fdump-rtl-barriers
+@opindex fdump-rtl-barriers
+Dump after cleaning up the barrier instructions.
+
+@item -fdump-rtl-bbpart
+@opindex fdump-rtl-bbpart
+Dump after partitioning hot and cold basic blocks.
@item -fdump-rtl-bbro
@opindex fdump-rtl-bbro
-Dump after block reordering, to @file{@var{file}.148r.bbro}.
+Dump after block reordering.
+
+@item -fdump-rtl-btl1
+@itemx -fdump-rtl-btl2
+@opindex fdump-rtl-btl2
+@opindex fdump-rtl-btl2
+@option{-fdump-rtl-btl1} and @option{-fdump-rtl-btl2} enable dumping
+after the two branch
+target load optimization passes.
+
+@item -fdump-rtl-bypass
+@opindex fdump-rtl-bypass
+Dump after jump bypassing and control flow optimizations.
@item -fdump-rtl-combine
@opindex fdump-rtl-combine
-Dump after the RTL instruction combination pass, to the file
-@file{@var{file}.129r.combine}.
+Dump after the RTL instruction combination pass.
+
+@item -fdump-rtl-compgotos
+@opindex fdump-rtl-compgotos
+Dump after dumplicating the computed gotos.
@item -fdump-rtl-ce1
@itemx -fdump-rtl-ce2
+@itemx -fdump-rtl-ce3
@opindex fdump-rtl-ce1
@opindex fdump-rtl-ce2
-@option{-fdump-rtl-ce1} enable dumping after the
-first if conversion, to the file @file{@var{file}.117r.ce1}.
-@option{-fdump-rtl-ce2} enable dumping after the second if
-conversion, to the file @file{@var{file}.130r.ce2}.
+@opindex fdump-rtl-ce3
+@option{-fdump-rtl-ce1}, @option{-fdump-rtl-ce2}, and
+@option{-fdump-rtl-ce3} enable dumping after the three
+if conversion passes.
+
+@itemx -fdump-rtl-cprop_hardreg
+@opindex fdump-rtl-cprop_hardreg
+Dump after hard register copy propagation.
+
+@itemx -fdump-rtl-csa
+@opindex fdump-rtl-csa
+Dump after combining stack adjustments.
+
+@item -fdump-rtl-cse1
+@itemx -fdump-rtl-cse2
+@opindex fdump-rtl-cse1
+@opindex fdump-rtl-cse2
+@option{-fdump-rtl-cse1} and @option{-fdump-rtl-cse2} enable dumping after
+the two common sub-expression elimination passes.
+
+@itemx -fdump-rtl-dce
+@opindex fdump-rtl-dce
+Dump after the standalone dead code elimination passes.
-@item -fdump-rtl-btl
@itemx -fdump-rtl-dbr
-@opindex fdump-rtl-btl
@opindex fdump-rtl-dbr
-@option{-fdump-rtl-btl} enable dumping after branch
-target load optimization, to @file{@var{file}.31.btl}.
-@option{-fdump-rtl-dbr} enable dumping after delayed branch
-scheduling, to @file{@var{file}.36.dbr}.
+Dump after delayed branch scheduling.
-@item -dD
-@opindex dD
-Dump all macro definitions, at the end of preprocessing, in addition to
-normal output.
-
-@item -fdump-rtl-ce3
-@opindex fdump-rtl-ce3
-Dump after the third if conversion, to @file{@var{file}.146r.ce3}.
-
-@item -fdump-rtl-cfg
-@itemx -fdump-rtl-life
-@opindex fdump-rtl-cfg
-@opindex fdump-rtl-life
-@option{-fdump-rtl-cfg} enable dumping after control
-and data flow analysis, to @file{@var{file}.116r.cfg}.
-@option{-fdump-rtl-cfg} enable dumping dump after life analysis,
-to @file{@var{file}.128r.life1} and @file{@var{file}.135r.life2}.
-
-@item -fdump-rtl-greg
-@opindex fdump-rtl-greg
-Dump after global register allocation, to @file{@var{file}.139r.greg}.
-
-@item -fdump-rtl-gcse
-@itemx -fdump-rtl-bypass
-@opindex fdump-rtl-gcse
-@opindex fdump-rtl-bypass
-@option{-fdump-rtl-gcse} enable dumping after GCSE, to
-@file{@var{file}.114r.gcse}. @option{-fdump-rtl-bypass}
-enable dumping after jump bypassing and control flow optimizations, to
-@file{@var{file}.115r.bypass}.
+@item -fdump-rtl-dce1
+@itemx -fdump-rtl-dce2
+@opindex fdump-rtl-dce1
+@opindex fdump-rtl-dce2
+@option{-fdump-rtl-dce1} and @option{-fdump-rtl-dce2} enable dumping after
+the two dead store elimination passes.
@item -fdump-rtl-eh
@opindex fdump-rtl-eh
-Dump after finalization of EH handling code, to @file{@var{file}.02.eh}.
+Dump after finalization of EH handling code.
-@item -fdump-rtl-sibling
-@opindex fdump-rtl-sibling
-Dump after sibling call optimizations, to @file{@var{file}.106r.sibling}.
+@item -fdump-rtl-eh_ranges
+@opindex fdump-rtl-eh_ranges
+Dump after conversion of EH handling range regions.
+
+@item -fdump-rtl-expand
+@opindex fdump-rtl-expand
+Dump after RTL generation.
+
+@item -fdump-rtl-fwprop1
+@itemx -fdump-rtl-fwprop2
+@opindex fdump-rtl-fwprop1
+@opindex fdump-rtl-fwprop2
+@option{-fdump-rtl-fwprop1} and @option{-fdump-rtl-fwprop2} enable
+dumping after the two forward propagation passes.
+
+@item -fdump-rtl-gcse1
+@itemx -fdump-rtl-gcse2
+@opindex fdump-rtl-gcse1
+@opindex fdump-rtl-gcse2
+@option{-fdump-rtl-gcse1} and @option{-fdump-rtl-gcse2} enable dumping
+after global common subexpression elimination.
+
+@item -fdump-rtl-init-regs
+@opindex fdump-rtl-init-regs
+Dump after the initialization of the registers.
+
+@item -fdump-rtl-initvals
+@opindex fdump-rtl-initvals
+Dump after the computation of the initial value sets.
+
+@itemx -fdump-rtl-into_cfglayout
+@opindex fdump-rtl-into_cfglayout
+Dump after converting to cfglayout mode.
+
+@item -fdump-rtl-ira
+@opindex fdump-rtl-ira
+Dump after iterated register allocation.
@item -fdump-rtl-jump
@opindex fdump-rtl-jump
-Dump after the first jump optimization, to @file{@var{file}.112r.jump}.
-
-@item -fdump-rtl-stack
-@opindex fdump-rtl-stack
-Dump after conversion from GCC's "flat register file" registers to the
-x87's stack-like registers, to @file{@var{file}.152r.stack}.
-
-@item -fdump-rtl-lreg
-@opindex fdump-rtl-lreg
-Dump after local register allocation, to @file{@var{file}.138r.lreg}.
+Dump after the second jump optimization.
@item -fdump-rtl-loop2
@opindex fdump-rtl-loop2
-@option{-dL} and @option{-fdump-rtl-loop2} enable dumping after the
-loop optimization pass, to @file{@var{file}.119r.loop2},
-@file{@var{file}.120r.loop2_init},
-@file{@var{file}.121r.loop2_invariant}, and
-@file{@var{file}.125r.loop2_done}.
-
-@item -fdump-rtl-sms
-@opindex fdump-rtl-sms
-Dump after modulo scheduling, to @file{@var{file}.136r.sms}.
+@option{-fdump-rtl-loop2} enables dumping after the rtl
+loop optimization passes.
@item -fdump-rtl-mach
@opindex fdump-rtl-mach
-Dump after performing the machine dependent reorganization pass, to
-@file{@var{file}.155r.mach} if that pass exists.
+Dump after performing the machine dependent reorganization pass, if that
+pass exists.
+
+@item -fdump-rtl-mode_sw
+@opindex fdump-rtl-mode_sw
+Dump after removing redundant mode switches.
@item -fdump-rtl-rnreg
@opindex fdump-rtl-rnreg
-Dump after register renumbering, to @file{@var{file}.147r.rnreg}.
+Dump after register renumbering.
-@item -fdump-rtl-regmove
-@opindex fdump-rtl-regmove
-Dump after the register move pass, to @file{@var{file}.132r.regmove}.
+@itemx -fdump-rtl-outof_cfglayout
+@opindex fdump-rtl-outof_cfglayout
+Dump after converting from cfglayout mode.
+
+@item -fdump-rtl-peephole2
+@opindex fdump-rtl-peephole2
+Dump after the peephole pass.
@item -fdump-rtl-postreload
@opindex fdump-rtl-postreload
-Dump after post-reload optimizations, to @file{@var{file}.24.postreload}.
+Dump after post-reload optimizations.
-@item -fdump-rtl-expand
-@opindex fdump-rtl-expand
-Dump after RTL generation, to @file{@var{file}.104r.expand}.
+@itemx -fdump-rtl-pro_and_epilogue
+@opindex fdump-rtl-pro_and_epilogue
+Dump after generating the function pro and epilogues.
-@item -fdump-rtl-sched2
-@opindex fdump-rtl-sched2
-Dump after the second scheduling pass, to @file{@var{file}.149r.sched2}.
-
-@item -fdump-rtl-cse
-@opindex fdump-rtl-cse
-Dump after CSE (including the jump optimization that sometimes follows
-CSE), to @file{@var{file}.113r.cse}.
+@item -fdump-rtl-regmove
+@opindex fdump-rtl-regmove
+Dump after the register move pass.
@item -fdump-rtl-sched1
+@itemx -fdump-rtl-sched2
@opindex fdump-rtl-sched1
-Dump after the first scheduling pass, to @file{@var{file}.136r.sched1}.
+@opindex fdump-rtl-sched2
+@option{-fdump-rtl-sched1} and @option{-fdump-rtl-sched2} enable dumping
+after the basic block scheduling passes.
-@item -fdump-rtl-cse2
-@opindex fdump-rtl-cse2
-Dump after the second CSE pass (including the jump optimization that
-sometimes follows CSE), to @file{@var{file}.127r.cse2}.
+@item -fdump-rtl-see
+@opindex fdump-rtl-see
+Dump after sign extension elimination.
-@item -fdump-rtl-tracer
-@opindex fdump-rtl-tracer
-Dump after running tracer, to @file{@var{file}.118r.tracer}.
+@item -fdump-rtl-seqabstr
+@opindex fdump-rtl-seqabstr
+Dump after common sequence discovery.
-@item -fdump-rtl-vpt
-@itemx -fdump-rtl-vartrack
-@opindex fdump-rtl-vpt
-@opindex fdump-rtl-vartrack
-@option{-fdump-rtl-vpt} enable dumping after the value
-profile transformations, to @file{@var{file}.10.vpt}.
-@option{-fdump-rtl-vartrack} enable dumping after variable tracking,
-to @file{@var{file}.154r.vartrack}.
+@item -fdump-rtl-shorten
+@opindex fdump-rtl-shorten
+Dump after shortening branches.
-@item -fdump-rtl-flow2
-@opindex fdump-rtl-flow2
-Dump after the second flow pass, to @file{@var{file}.142r.flow2}.
+@item -fdump-rtl-sibling
+@opindex fdump-rtl-sibling
+Dump after sibling call optimizations.
+
+@item -fdump-rtl-split1
+@itemx -fdump-rtl-split2
+@itemx -fdump-rtl-split3
+@itemx -fdump-rtl-split4
+@itemx -fdump-rtl-split5
+@opindex fdump-rtl-split1
+@opindex fdump-rtl-split2
+@opindex fdump-rtl-split3
+@opindex fdump-rtl-split4
+@opindex fdump-rtl-split5
+@option{-fdump-rtl-split1}, @option{-fdump-rtl-split2},
+@option{-fdump-rtl-split3}, @option{-fdump-rtl-split4} and
+@option{-fdump-rtl-split5} enable dumping after five rounds of
+instruction splitting.
-@item -fdump-rtl-peephole2
-@opindex fdump-rtl-peephole2
-Dump after the peephole pass, to @file{@var{file}.145r.peephole2}.
+@item -fdump-rtl-sms
+@opindex fdump-rtl-sms
+Dump after modulo scheduling. This pass is only run on some
+architectures.
+
+@item -fdump-rtl-stack
+@opindex fdump-rtl-stack
+Dump after conversion from GCC's "flat register file" registers to the
+x87's stack-like registers. This pass is only run on x86 variants.
+
+@item -fdump-rtl-subreg1
+@itemx -fdump-rtl-subreg2
+@opindex fdump-rtl-subreg1
+@opindex fdump-rtl-subreg2
+@option{-fdump-rtl-subreg1} and @option{-fdump-rtl-subreg2} enable dumping after
+the two subreg expansion passes.
+
+@item -fdump-rtl-unshare
+@opindex fdump-rtl-unshare
+Dump after all rtl has been unshared.
+
+@item -fdump-rtl-vartrack
+@opindex fdump-rtl-vartrack
+Dump after variable tracking.
+
+@item -fdump-rtl-vregs
+@opindex fdump-rtl-vregs
+Dump after converting virtual registers to hard registers.
@item -fdump-rtl-web
@opindex fdump-rtl-web
-Dump after live range splitting, to @file{@var{file}.126r.web}.
+Dump after live range splitting.
+
+@item -fdump-rtl-regclass
+@itemx -fdump-rtl-subregs_of_mode_init
+@itemx -fdump-rtl-subregs_of_mode_finish
+@itemx -fdump-rtl-dfinit
+@itemx -fdump-rtl-dfinish
+@opindex fdump-rtl-regclass
+@opindex fdump-rtl-subregs_of_mode_init
+@opindex fdump-rtl-subregs_of_mode_finish
+@opindex fdump-rtl-dfinit
+@opindex fdump-rtl-dfinish
+These dumps are defined but always produce empty files.
@item -fdump-rtl-all
@opindex fdump-rtl-all
Produce all the dumps listed above.
+@item -dA
+@opindex dA
+Annotate the assembler output with miscellaneous debugging information.
+
+@item -dD
+@opindex dD
+Dump all macro definitions, at the end of preprocessing, in addition to
+normal output.
+
@item -dH
@opindex dH
Produce a core dump whenever an error occurs.
@item -dv
@opindex dv
-For each of the other indicated dump files (either with @option{-d} or
-@option{-fdump-rtl-@var{pass}}), dump a representation of the control flow
-graph suitable for viewing with VCG to @file{@var{file}.@var{pass}.vcg}.
+For each of the other indicated dump files (@option{-fdump-rtl-@var{pass}}),
+dump a representation of the control flow graph suitable for viewing with VCG
+to @file{@var{file}.@var{pass}.vcg}.
@item -dx
@opindex dx
Just generate RTL for a function instead of compiling it. Usually used
-with @samp{r} (@option{-fdump-rtl-expand}).
+with @option{-fdump-rtl-expand}.
@item -dy
@opindex dy
@item -fdump-noaddr
@opindex fdump-noaddr
-When doing debugging dumps (see @option{-d} option above), suppress
-address output. This makes it more feasible to use diff on debugging
-dumps for compiler invocations with different compiler binaries and/or
-different text / bss / data / heap / stack / dso start locations.
+When doing debugging dumps, suppress address output. This makes it more
+feasible to use diff on debugging dumps for compiler invocations with
+different compiler binaries and/or different
+text / bss / data / heap / stack / dso start locations.
@item -fdump-unnumbered
@opindex fdump-unnumbered
-When doing debugging dumps (see @option{-d} option above), suppress instruction
-numbers and address output. This makes it more feasible to
-use diff on debugging dumps for compiler invocations with different
-options, in particular with and without @option{-g}.
+When doing debugging dumps, suppress instruction numbers and address output.
+This makes it more feasible to use diff on debugging dumps for compiler
+invocations with different options, in particular with and without
+@option{-g}.
@item -fdump-translation-unit @r{(C++ only)}
@itemx -fdump-translation-unit-@var{options} @r{(C++ only)}
@opindex fsched-verbose
On targets that use instruction scheduling, this option controls the
amount of debugging output the scheduler prints. This information is
-written to standard error, unless @option{-dS} or @option{-dR} is
-specified, in which case it is output to the usual dump
-listing file, @file{.sched} or @file{.sched2} respectively. However
-for @var{n} greater than nine, the output is always printed to standard
-error.
+written to standard error, unless @option{-fdump-rtl-sched1} or
+@option{-fdump-rtl-sched2} is specified, in which case it is output
+to the usual dump listing file, @file{.sched} or @file{.sched2}
+respectively. However for @var{n} greater than nine, the output is
+always printed to standard error.
For @var{n} greater than zero, @option{-fsched-verbose} outputs the
-same information as @option{-dRS}. For @var{n} greater than one, it
-also output basic block probabilities, detailed ready list information
-and unit/insn info. For @var{n} greater than two, it includes RTL
-at abort point, control-flow and regions info. And for @var{n} over
-four, @option{-fsched-verbose} also includes dependence info.
+same information as @option{-fdump-rtl-sched1} and @option{-fdump-rtl-sched2}.
+For @var{n} greater than one, it also output basic block probabilities,
+detailed ready list information and unit/insn info. For @var{n} greater
+than two, it includes RTL at abort point, control-flow and regions info.
+And for @var{n} over four, @option{-fsched-verbose} also includes
+dependence info.
@item -save-temps
@opindex save-temps
@item -O2
@opindex O2
Optimize even more. GCC performs nearly all supported optimizations
-that do not involve a space-speed tradeoff. The compiler does not
-perform loop unrolling or function inlining when you specify @option{-O2}.
+that do not involve a space-speed tradeoff.
As compared to @option{-O}, this option increases both compilation time
and the performance of the generated code.
This option implies @option{-fmerge-constants}. In addition to
@option{-fmerge-constants} this considers e.g.@: even constant initialized
arrays or initialized constant variables with integral or floating point
-types. Languages like C or C++ require each non-automatic variable to
-have distinct location, so using this option will result in non-conforming
+types. Languages like C or C++ require each variable, including multiple
+instances of the same variable in recursive calls, to have distinct locations,
+so using this option will result in non-conforming
behavior.
@item -fmodulo-sched
Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}.
-@item -fira
-@opindex fira
-Use the integrated register allocator (@acronym{IRA}) for register
-allocation. It is a default if @acronym{IRA} has been ported for the
-target.
-
@item -fira-algorithm=@var{algorithm}
-Use specified algorithm for the integrated register allocator. The
-@var{algorithm} argument should be one of @code{regional}, @code{CB},
-or @code{mixed}. The second algorithm specifies Chaitin-Briggs
-coloring, the first one specifies regional coloring based on
-Chaitin-Briggs coloring, and the third one which is the default
-specifies a mix of Chaitin-Briggs and regional algorithms where loops
-with small register pressure are ignored. The first algorithm can
-give best result for machines with small size and irregular register
-set, the second one is faster and generates decent code and the
-smallest size code, and the mixed algorithm usually give the best
-results in most cases and for most architectures.
+Use specified coloring algorithm for the integrated register
+allocator. The @var{algorithm} argument should be @code{priority} or
+@code{CB}. The first algorithm specifies Chow's priority coloring,
+the second one specifies Chaitin-Briggs coloring. The second
+algorithm can be unimplemented for some architectures. If it is
+implemented, it is the default because Chaitin-Briggs coloring as a
+rule generates a better code.
+
+@item -fira-region=@var{region}
+Use specified regions for the integrated register allocator. The
+@var{region} argument should be one of @code{all}, @code{mixed}, or
+@code{one}. The first value means using all loops as register
+allocation regions, the second value which is the default means using
+all loops except for loops with small register pressure as the
+regions, and third one means using all function as a single region.
+The first value can give best result for machines with small size and
+irregular register set, the third one results in faster and generates
+decent code and the smallest size code, and the default value usually
+give the best results in most cases and for most architectures.
@item -fira-coalesce
@opindex fira-coalesce
of the matrix. The second optimization is matrix transposing that
attemps to change the order of the matrix's dimensions in order to
improve cache locality.
-Both optimizations need fwhole-program flag.
-Transposing is enabled only if profiling information is avaliable.
+Both optimizations need the @option{-fwhole-program} flag.
+Transposing is enabled only if profiling information is available.
@item -ftree-sink
loop strip mining will transform the loop as if the user had written:
@smallexample
DO II = 1, N, 4
- DO I = II, min (II + 4, N)
+ DO I = II, min (II + 3, N)
A(I) = A(I) + C
ENDDO
ENDDO
@smallexample
DO II = 1, N, 64
DO JJ = 1, M, 64
- DO I = II, min (II + 64, N)
- DO J = JJ, min (JJ + 64, M)
+ DO I = II, min (II + 63, N)
+ DO J = JJ, min (JJ + 63, M)
A(J, I) = B(I) + C(J)
ENDDO
ENDDO
The following options are enabled: @code{-fprofile-arcs}, @code{-fprofile-values}, @code{-fvpt}.
If @var{path} is specified, GCC will look at the @var{path} to find
-the profile feeedback data files. See @option{-fprofile-dir}.
+the profile feedback data files. See @option{-fprofile-dir}.
@item -fprofile-use
@itemx -fprofile-use=@var{path}
the enhanced partial redundancy elimination optimization can run away,
consuming all of the memory available on the host machine. This
parameter sets a limit on the length of the sets that are computed,
-which prevents the runaway behaviour. Setting a value of 0 for
-this paramter will allow an unlimited set length.
+which prevents the runaway behavior. Setting a value of 0 for
+this parameter will allow an unlimited set length.
@item sccvn-max-scc-size
Maximum size of a strongly connected component (SCC) during SCCVN
@item ira-max-loops-num
IRA uses a regional register allocation by default. If a function
-contains loops more than number given by the parameter, non-regional
-register allocator will be used even when option
-@option{-fira-algorithm} is given. The default value of the parameter
-is 20.
+contains loops more than number given by the parameter, only at most
+given number of the most frequently executed loops will form regions
+for the regional register allocation. The default value of the
+parameter is 100.
+
+@item ira-max-conflict-table-size
+Although IRA uses a sophisticated algorithm of compression conflict
+table, the table can be still big for huge functions. If the conflict
+table for a function could be more than size in MB given by the
+parameter, the conflict table is not built and faster, simpler, and
+lower quality register allocation algorithm will be used. The
+algorithm do not use pseudo-register conflicts. The default value of
+the parameter is 2000.
+
+@item loop-invariant-max-bbs-in-loop
+Loop invariant motion can be very expensive, both in compile time and
+in amount of needed compile time memory, with very large loops. Loops
+with more basic blocks than this parameter won't have loop invariant
+motion optimization performed on them. The default value of the
+parameter is 1000 for -O1 and 10000 for -O2 and above.
@end table
@end table
option @samp{-Xlinker -z -Xlinker defs}). Only a few systems support
this option.
+@item -T @var{script}
+@opindex T
+@cindex linker script
+Use @var{script} as the linker script. This option is supported by most
+systems using the GNU linker. On some targets, such as bare-board
+targets without an operating system, the @option{-T} option may be required
+when linking to avoid references to undefined symbols.
+
@item -Xlinker @var{option}
@opindex Xlinker
Pass @var{option} as an option to the linker. You can use this to
supply system-specific linker options which GCC does not know how to
recognize.
-If you want to pass an option that takes an argument, you must use
+If you want to pass an option that takes a separate argument, you must use
@option{-Xlinker} twice, once for the option and once for the argument.
For example, to pass @option{-assert definitions}, you must write
@samp{-Xlinker -assert -Xlinker definitions}. It does not work to write
@option{-Xlinker "-assert definitions"}, because this passes the entire
string as a single argument, which is not what the linker expects.
+When using the GNU linker, it is usually more convenient to pass
+arguments to linker options using the @option{@var{option}=@var{value}}
+syntax than as separate arguments. For example, you can specify
+@samp{-Xlinker -Map=output.map} rather than
+@samp{-Xlinker -Map -Xlinker output.map}. Other linkers may not support
+this syntax for command-line options.
+
@item -Wl,@var{option}
@opindex Wl
Pass @var{option} as an option to the linker. If @var{option} contains
-commas, it is split into multiple options at the commas.
+commas, it is split into multiple options at the commas. You can use this
+syntax to pass an argument to the option.
+For example, @samp{-Wl,-Map,output.map} passes @samp{-Map output.map} to the
+linker. When using the GNU linker, you can also get the same effect with
+@samp{-Wl,-Map=output.map}.
@item -u @var{symbol}
@opindex u
arm-elf}, meaning to compile for an arm processor with elf binaries,
then you would specify @option{-b arm-elf} to run that cross compiler.
Because there are other options beginning with @option{-b}, the
-configuration must contain a hyphen.
+configuration must contain a hyphen, or @option{-b} alone should be one
+argument followed by the configuration in the next argument.
@item -V @var{version}
@opindex V
* Darwin Options::
* DEC Alpha Options::
* DEC Alpha/VMS Options::
+* FR30 Options::
* FRV Options::
* GNU/Linux Options::
* H8/300 Options::
by default. This can be overridden with the @code{section} attribute.
@xref{Variable Attributes}.
+@item -mfix-cortex-m3-ldrd
+@opindex mfix-cortex-m3-ldrd
+Some Cortex-M3 cores can cause data corruption when @code{ldrd} instructions
+with overlapping destination and base registers are used. This option avoids
+generating these instructions. This option is enabled by default when
+@option{-mcpu=cortex-m3} is specified.
+
@end table
@node ARM Options
@samp{arm620}, @samp{arm7}, @samp{arm7m}, @samp{arm7d}, @samp{arm7dm},
@samp{arm7di}, @samp{arm7dmi}, @samp{arm70}, @samp{arm700},
@samp{arm700i}, @samp{arm710}, @samp{arm710c}, @samp{arm7100},
+@samp{arm720},
@samp{arm7500}, @samp{arm7500fe}, @samp{arm7tdmi}, @samp{arm7tdmi-s},
-@samp{arm8}, @samp{strongarm}, @samp{strongarm110}, @samp{strongarm1100},
+@samp{arm710t}, @samp{arm720t}, @samp{arm740t},
+@samp{strongarm}, @samp{strongarm110}, @samp{strongarm1100},
+@samp{strongarm1110},
@samp{arm8}, @samp{arm810}, @samp{arm9}, @samp{arm9e}, @samp{arm920},
@samp{arm920t}, @samp{arm922t}, @samp{arm946e-s}, @samp{arm966e-s},
@samp{arm968e-s}, @samp{arm926ej-s}, @samp{arm940t}, @samp{arm9tdmi},
@samp{arm10e}, @samp{arm1020e}, @samp{arm1022e},
@samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
@samp{arm1156t2-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
-@samp{cortex-a8}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m3},
+@samp{cortex-a8}, @samp{cortex-a9},
+@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m3},
@samp{cortex-m1},
-@samp{xscale}, @samp{iwmmxt}, @samp{ep9312}.
+@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
@item -mtune=@var{name}
@opindex mtune
assembly code. This option can be used in conjunction with or instead
of the @option{-mcpu=} option. Permissible names are: @samp{armv2},
@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t},
-@samp{armv5}, @samp{armv5t}, @samp{armv5te}, @samp{armv6}, @samp{armv6j},
+@samp{armv5}, @samp{armv5t}, @samp{armv5e}, @samp{armv5te},
+@samp{armv6}, @samp{armv6j},
@samp{armv6t2}, @samp{armv6z}, @samp{armv6zk}, @samp{armv6-m},
@samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m},
-@samp{iwmmxt}, @samp{ep9312}.
+@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
@item -mfpu=@var{name}
@itemx -mfpe=@var{number}
Only generate absolute relocations on word sized values (i.e. R_ARM_ABS32).
This is enabled by default on targets (uClinux, SymbianOS) where the runtime
loader imposes this restriction, and when @option{-fpic} or @option{-fPIC}
-is speficied.
+is specified.
@end table
@item -mcpu=@var{cpu}@r{[}-@var{sirevision}@r{]}
@opindex mcpu=
Specifies the name of the target Blackfin processor. Currently, @var{cpu}
-can be one of @samp{bf522}, @samp{bf523}, @samp{bf524},
-@samp{bf525}, @samp{bf526}, @samp{bf527},
-@samp{bf531}, @samp{bf532}, @samp{bf533}, @samp{bf534},
-@samp{bf536}, @samp{bf537}, @samp{bf538}, @samp{bf539},
+can be one of @samp{bf512}, @samp{bf514}, @samp{bf516}, @samp{bf518},
+@samp{bf522}, @samp{bf523}, @samp{bf524}, @samp{bf525}, @samp{bf526},
+@samp{bf527}, @samp{bf531}, @samp{bf532}, @samp{bf533},
+@samp{bf534}, @samp{bf536}, @samp{bf537}, @samp{bf538}, @samp{bf539},
@samp{bf542}, @samp{bf544}, @samp{bf547}, @samp{bf548}, @samp{bf549},
@samp{bf561}.
The optional @var{sirevision} specifies the silicon revision of the target
link scripts will be used to put the application into SDRAM.
Loader should initialize SDRAM before loading the application
into SDRAM. This option defines @code{__BFIN_SDRAM}.
+
+@item -micplb
+@opindex micplb
+Assume that ICPLBs are enabled at runtime. This has an effect on certain
+anomaly workarounds. For Linux targets, the default is to assume ICPLBs
+are enabled; for standalone applications the default is off.
@end table
@node CRIS Options
style condition (e.g.@: error) codes.
@end table
+@node FR30 Options
+@subsection FR30 Options
+@cindex FR30 Options
+
+These options are defined specifically for the FR30 port.
+
+@table @gcctabopt
+
+@item -msmall-model
+@opindex msmall-model
+Use the small address space model. This can produce smaller code, but
+it does assume that all symbolic values and addresses will fit into a
+20-bit range.
+
+@item -mno-lsim
+@opindex mno-lsim
+Assume that run-time support has been provided and so there is no need
+to include the simulator library (@file{libsim.a}) on the linker
+command line.
+
+@end table
+
@node FRV Options
@subsection FRV Options
@cindex FRV Options
@code{long double} will be modified. Hence they will not be binary
compatible with arrays or structures in code compiled without that switch.
-@item -mmlarge-data-threshold=@var{number}
+@item -mlarge-data-threshold=@var{number}
@opindex mlarge-data-threshold=@var{number}
When @option{-mcmodel=medium} is specified, the data greater than
@var{threshold} are placed in large data section. This value must be the
if the ISA supports such instructions. The -mfused-madd option is on by
default. The fused multiply-add instructions have a different
rounding behavior compared to executing a multiply followed by an add.
+
+@item -msse2avx
+@itemx -mno-sse2avx
+@opindex msse2avx
+Specify that the assembler should encode SSE instructions with VEX
+prefix. The option @option{-mavx} turns this on by default.
@end table
These @samp{-m} switches are supported in addition to the above
@item -mcmodel=medium
@opindex mcmodel=medium
Generate code for the medium model: The program is linked in the lower 2
-GB of the address space but symbols can be located anywhere in the
-address space. Programs can be statically or dynamically linked, but
-building of shared libraries are not supported with the medium model.
+GB of the address space. Small symbols are also placed there. Symbols
+with sizes larger than @option{-mlarge-data-threshold} are put into
+large data or bss sections and can be located above 2GB. Programs can
+be statically or dynamically linked.
@item -mcmodel=large
@opindex mcmodel=large
@opindex m210
@opindex m340
Generate code for the 210 processor.
+
+@item -mno-lsim
+@opindex no-lsim
+Assume that run-time support has been provided and so omit the
+simulator library (@file{libsim.a)} from the linker command line.
+
+@item -mstack-increment=@var{size}
+@opindex mstack-increment
+Set the maximum amount for a single stack increment operation. Large
+values can increase the speed of progrqams which contain functions
+that need a large amount of stack space, but they can also trigger a
+segmentation fault if the stack is extended too much. The default
+value is 0x1000.
+
@end table
@node MIPS Options
@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
@samp{r4600}, @samp{r4650}, @samp{r6000}, @samp{r8000},
@samp{rm7000}, @samp{rm9000},
+@samp{r10000}, @samp{r12000}, @samp{r14000}, @samp{r16000},
@samp{sb1},
@samp{sr71000},
@samp{vr4100}, @samp{vr4111}, @samp{vr4120}, @samp{vr4130}, @samp{vr4300},
immediately after starting an integer division.
@end itemize
+@item -mfix-r10000
+@itemx -mno-fix-r10000
+@opindex mfix-r10000
+@opindex mno-fix-r10000
+Work around certain R10000 errata:
+@itemize @minus
+@item
+@code{ll}/@code{sc} sequences may not behave atomically on revisions
+prior to 3.0. They may deadlock on revisions 2.6 and earlier.
+@end itemize
+
+This option can only be used if the target architecture supports
+branch-likely instructions. @option{-mfix-r10000} is the default when
+@option{-march=r10000} is used; @option{-mno-fix-r10000} is the default
+otherwise.
+
@item -mfix-vr4120
@itemx -mno-fix-vr4120
@opindex mfix-vr4120
warnings can be generated, for example, when compiling code which
performs byte-level memory operations on the MAC AE type. The MAC AE has
no hardware support for byte-level memory operations, so all byte
-load/stores must be synthesised from word load/store operations. This is
+load/stores must be synthesized from word load/store operations. This is
inefficient and a warning will be generated indicating to the programmer
that they should rewrite the code to avoid byte operations, or to target
an AE type which has the necessary hardware support. This option enables
@opindex mno-vrsave
Generate VRSAVE instructions when generating AltiVec code.
+@item -mgen-cell-microcode
+@opindex mgen-cell-microcode
+Generate Cell microcode instructions
+
+@item -mwarn-cell-microcode
+@opindex mwarn-cell-microcode
+Warning when a Cell microcode instruction is going to emitted. An example
+of a Cell microcode instruction is a variable shift.
+
@item -msecure-plt
@opindex msecure-plt
Generate code that allows ld and ld.so to build executables and shared
@opindex msimple-fpu
Do not generate sqrt and div instructions for hardware floating point unit.
+@item -mfpu
+@opindex mfpu
+Specify type of floating point unit. Valid values are @var{sp_lite}
+(equivalent to -msingle-float -msimple-fpu), @var{dp_lite} (equivalent
+to -mdouble-float -msimple-fpu), @var{sp_full} (equivalent to -msingle-float),
+and @var{dp_full} (equivalent to -mdouble-float).
+
+@item -mxilinx-fpu
+@opindex mxilinx-fpu
+Perform optimizations for floating point unit on Xilinx PPC 405/440.
+
@item -mmultiple
@itemx -mno-multiple
@opindex mmultiple
stored, which means code that walks the stack frame across interrupts or
signals may get corrupted data.
+@item -mavoid-indexed-addresses
+@item -mno-avoid-indexed-addresses
+@opindex mavoid-indexed-addresses
+@opindex mno-avoid-indexed-addresses
+Generate code that tries to avoid (not avoid) the use of indexed load
+or store instructions. These instructions can incur a performance
+penalty on Power6 processors in certain situations, such as when
+stepping through large arrays that cross a 16M boundary. This option
+is enabled by default when targetting Power6 and disabled otherwise.
+
@item -mfused-madd
@itemx -mno-fused-madd
@opindex mfused-madd
OSDN Git Service
