-Wunknown-pragmas -Wno-pragmas -Wunreachable-code @gol
-Wunused -Wunused-function -Wunused-label -Wunused-parameter @gol
-Wunused-value -Wunused-variable -Wvariadic-macros @gol
--Wwrite-strings}
+-Wvolatile-register-var -Wwrite-strings}
@item C-only Warning Options
@gccoptlist{-Wbad-function-cast -Wmissing-declarations @gol
-mpoke-function-name @gol
-mthumb -marm @gol
-mtpcs-frame -mtpcs-leaf-frame @gol
--mcaller-super-interworking -mcallee-super-interworking}
+-mcaller-super-interworking -mcallee-super-interworking @gol
+-mtp=@var{name}}
@emph{AVR Options}
@gccoptlist{-mmcu=@var{mcu} -msize -minit-stack=@var{n} -mno-interrupts @gol
-single_module -static -sub_library -sub_umbrella @gol
-twolevel_namespace -umbrella -undefined @gol
-unexported_symbols_list -weak_reference_mismatches @gol
--whatsloaded -F -gused -gfull -mmacosx-min-version=@var{version} @gol
+-whatsloaded -F -gused -gfull -mmacosx-version-min=@var{version} @gol
-mone-byte-bool}
@emph{DEC Alpha Options}
-maltivec -mno-altivec @gol
-mpowerpc-gpopt -mno-powerpc-gpopt @gol
-mpowerpc-gfxopt -mno-powerpc-gfxopt @gol
+-mmfcrf -mno-mfcrf -mpopcntb -mno-popcntb -mfprnd -mno-fprnd @gol
-mnew-mnemonics -mold-mnemonics @gol
-mfull-toc -mminimal-toc -mno-fp-in-toc -mno-sum-in-toc @gol
-m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol
assembler assembler-with-cpp
ada
f77 f77-cpp-input ratfor
-f95
+f95 f95-cpp-input
java
treelang
@end smallexample
alternate syntax when in pedantic ISO C99 mode. This is default.
To inhibit the warning messages, use @option{-Wno-variadic-macros}.
+@item -Wvolatile-register-var
+@opindex Wvolatile-register-var
+@opindex Wno-volatile-register-var
+Warn if a register variable is declared volatile. The volatile
+modifier does not inhibit all optimizations that may eliminate reads
+and/or writes to register variables.
+
@item -Wdisabled-optimization
@opindex Wdisabled-optimization
Warn if a requested optimization pass is disabled. This warning does
value is ignored in the case where all instructions in the block being
crossjumped from are matched. The default value is 5.
+@item max-grow-copy-bb-insns
+The maximum code size expansion factor when copying basic blocks
+instead of jumping. The expansion is relative to a jump instruction.
+The default value is 8.
+
@item max-goto-duplication-insns
The maximum number of instructions to duplicate to a block that jumps
to a computed goto. To avoid @math{O(N^2)} behavior in a number of
The default value is 100 which limits large function growth to 2.0 times
the original size.
+@item large-unit-insns
+The limit specifying large translation unit. Growth caused by inlining of
+units larger than this limit is limited by @option{--param inline-unit-growth}.
+For small units this might be too tight (consider unit consisting of function A
+that is inline and B that just calls A three time. If B is small relative to
+A, the growth of unit is 300\% and yet such inlining is very sane. For very
+large units consisting of small inlininable functions however the overall unit
+growth limit is needed to avoid exponential explosion of code size. Thus for
+smaller units, the size is increased to @option{--param large-unit-insns}
+before aplying @option{--param inline-unit-growth}. The default is 10000
+
@item inline-unit-growth
Specifies maximal overall growth of the compilation unit caused by inlining.
This parameter is ignored when @option{-funit-at-a-time} is not used.
Select fraction of the maximal frequency of executions of basic block in
function given basic block needs to have to be considered hot
+@item max-predicted-iterations
+The maximum number of loop iterations we predict statically. This is useful
+in cases where function contain single loop with known bound and other loop
+with unknown. We predict the known number of iterations correctly, while
+the unknown number of iterations average to roughly 10. This means that the
+loop without bounds would appear artificially cold relative to the other one.
+
@item tracer-dynamic-coverage
@itemx tracer-dynamic-coverage-feedback
Maximum number of basic blocks on path that cse considers. The default is 10.
+@item max-cse-insns
+The maximum instructions CSE process before flushing. The default is 1000.
+
@item global-var-threshold
Counts the number of function calls (@var{n}) and the number of
Increasing values mean more aggressive optimization, making the compile time
increase with probably slightly better performance. The default value is 500.
+@item max-flow-memory-location
+Similar as @option{max-cselib-memory-location} but for dataflow liveness.
+The default value is 100.
+
@item reorder-blocks-duplicate
@itemx reorder-blocks-duplicate-feedback
The minimum size of buffers (i.e. arrays) that will receive stack smashing
protection when @option{-fstack-protection} is used.
+@item max-jump-thread-duplication-stmts
+Maximum number of statements allowed in a block that needs to be
+duplicated when threading jumps.
@end table
@end table
@item -mabi=@var{name}
@opindex mabi
Generate code for the specified ABI@. Permissible values are: @samp{apcs-gnu},
-@samp{atpcs}, @samp{aapcs} and @samp{iwmmxt}.
+@samp{atpcs}, @samp{aapcs}, @samp{aapcs-linux} and @samp{iwmmxt}.
@item -mapcs-frame
@opindex mapcs-frame
compiled for interworking or not. There is a small overhead in the cost
of executing a function pointer if this option is enabled.
+@item -mtp=@var{name}
+@opindex mtp
+Specify the access model for the thread local storage pointer. The valid
+models are @option{soft}, which generates calls to @code{__aeabi_read_tp},
+@option{cp15}, which fetches the thread pointer from @code{cp15} directly
+(supported in the arm6k architecture), and @option{auto}, which uses the
+best available method for the selected processor. The default setting is
+@option{auto}.
+
@end table
@node AVR Options
@item -masm=@var{dialect}
@opindex masm=@var{dialect}
-Output asm instructions using selected @var{dialect}. Supported choices are
-@samp{intel} or @samp{att} (the default one).
+Output asm instructions using selected @var{dialect}. Supported
+choices are @samp{intel} or @samp{att} (the default one). Darwin does
+not support @samp{intel}.
@item -mieee-fp
@itemx -mno-ieee-fp
@opindex mno-sse
@opindex m3dnow
@opindex mno-3dnow
-These switches enable or disable the use of built-in functions that allow
-direct access to the MMX, SSE, SSE2, SSE3 and 3Dnow extensions of the
-instruction set.
-
-@xref{X86 Built-in Functions}, for details of the functions enabled
-and disabled by these switches.
+These switches enable or disable the use of instructions in the MMX,
+SSE, SSE2 or 3DNow! extended instruction sets. These extensions are
+also available as built-in functions: see @ref{X86 Built-in Functions},
+for details of the functions enabled and disabled by these switches.
To have SSE/SSE2 instructions generated automatically from floating-point
-code, see @option{-mfpmath=sse}.
+code (as opposed to 387 instructions), see @option{-mfpmath=sse}.
+
+These options will enable GCC to use these extended instructions in
+generated code, even without @option{-mfpmath=sse}. Applications which
+perform runtime CPU detection must compile separate files for each
+supported architecture, using the appropriate flags. In particular,
+the file containing the CPU detection code should be compiled without
+these options.
@item -mpush-args
@itemx -mno-push-args
Specify bit size of immediate TLS offsets. Valid values are 14, 22, and
64.
-@item -mtune-arch=@var{cpu-type}
-@opindex mtune-arch
+@item -mtune=@var{cpu-type}
+@opindex mtune
Tune the instruction scheduling for a particular CPU, Valid values are
itanium, itanium1, merced, itanium2, and mckinley.
@itemx -mno-powerpc-gfxopt
@itemx -mpowerpc64
@itemx -mno-powerpc64
+@itemx -mmfcrf
+@itemx -mno-mfcrf
+@itemx -mpopcntb
+@itemx -mno-popcntb
+@itemx -mfprnd
+@itemx -mno-fprnd
@opindex mpower
@opindex mno-power
@opindex mpower2
@opindex mno-powerpc-gfxopt
@opindex mpowerpc64
@opindex mno-powerpc64
+@opindex mmfcrf
+@opindex mno-mfcrf
+@opindex mpopcntb
+@opindex mno-popcntb
+@opindex mfprnd
+@opindex mno-fprnd
GCC supports two related instruction set architectures for the
RS/6000 and PowerPC@. The @dfn{POWER} instruction set are those
instructions supported by the @samp{rios} chip set used in the original
RS/6000 systems and the @dfn{PowerPC} instruction set is the
-architecture of the Motorola MPC5xx, MPC6xx, MPC8xx microprocessors, and
-the IBM 4xx microprocessors.
+architecture of the Freescale MPC5xx, MPC6xx, MPC8xx microprocessors, and
+the IBM 4xx, 6xx, and follow-on microprocessors.
Neither architecture is a subset of the other. However there is a
large common subset of instructions supported by both. An MQ
use the optional PowerPC architecture instructions in the Graphics
group, including floating-point select.
+The @option{-mmfcrf} option allows GCC to generate the move from
+condition register field instruction implemented on the POWER4
+processor and other processors that support the PowerPC V2.01
+architecture.
+The @option{-mpopcntb} option allows GCC to generate the popcount and
+double precision FP reciprocal estimate instruction implemented on the
+POWER5 processor and other processors that support the PowerPC V2.02
+architecture.
+The @option{-mfprnd} option allows GCC to generate the FP round to
+integer instructions implemented on the POWER5+ processor and other
+processors that support the PowerPC V2.03 architecture.
+
The @option{-mpowerpc64} option allows GCC to generate the additional
64-bit instructions that are found in the full PowerPC64 architecture
and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to
@samp{601}, @samp{602}, @samp{603}, @samp{603e}, @samp{604},
@samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400},
@samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
-@samp{860}, @samp{970}, @samp{8540}, @samp{common}, @samp{ec603e}, @samp{G3},
+@samp{860}, @samp{970}, @samp{8540}, @samp{ec603e}, @samp{G3},
@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
-@samp{power4}, @samp{power5}, @samp{powerpc}, @samp{powerpc64},
+@samp{power4}, @samp{power5}, @samp{power5+},
+@samp{common}, @samp{powerpc}, @samp{powerpc64},
@samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}.
@option{-mcpu=common} selects a completely generic processor. Code
others.
The @option{-mcpu} options automatically enable or disable the
-following options: @option{-maltivec}, @option{-mhard-float},
-@option{-mmfcrf}, @option{-mmultiple}, @option{-mnew-mnemonics},
-@option{-mpower}, @option{-mpower2}, @option{-mpowerpc64},
-@option{-mpowerpc-gpopt}, @option{-mpowerpc-gfxopt},
-@option{-mstring}. The particular options set for any particular CPU
-will vary between compiler versions, depending on what setting seems
-to produce optimal code for that CPU; it doesn't necessarily reflect
-the actual hardware's capabilities. If you wish to set an individual
-option to a particular value, you may specify it after the
-@option{-mcpu} option, like @samp{-mcpu=970 -mno-altivec}.
+following options: @option{-maltivec}, @option{-mfprnd},
+@option{-mhard-float}, @option{-mmfcrf}, @option{-mmultiple},
+@option{-mnew-mnemonics}, @option{-mpopcntb}, @option{-mpower},
+@option{-mpower2}, @option{-mpowerpc64}, @option{-mpowerpc-gpopt},
+@option{-mpowerpc-gfxopt}, @option{-mstring}. The particular options
+set for any particular CPU will vary between compiler versions,
+depending on what setting seems to produce optimal code for that CPU;
+it doesn't necessarily reflect the actual hardware's capabilities. If
+you wish to set an individual option to a particular value, you may
+specify it after the @option{-mcpu} option, like @samp{-mcpu=970
+-mno-altivec}.
On AIX, the @option{-maltivec} and @option{-mpowerpc64} options are
-not enabled or disabled by the @option{-mcpu} option at present, since
+not enabled or disabled by the @option{-mcpu} option at present because
AIX does not have full support for these options. You may still
enable or disable them individually if you're sure it'll work in your
environment.
if the stack size is @var{stack-guard} bytes above the @var{stack-size}
(remember that the stack on s390 grows downward). These options are intended to
be used to help debugging stack overflow problems. The additionally emitted code
-cause only little overhead and hence can also be used in production like systems
+causes only little overhead and hence can also be used in production like systems
without greater performance degradation. The given values have to be exact
-powers of 2 and @var{stack-size} has to be greater than @var{stack-guard}.
+powers of 2 and @var{stack-size} has to be greater than @var{stack-guard} without
+exceeding 64k.
In order to be efficient the extra code makes the assumption that the stack starts
at an address aligned to the value given by @var{stack-size}.
@end table
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