@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-@c 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+@c 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
@c Free Software Foundation, Inc.
@c This is part of the GCC manual.
@c For copying conditions, see the file gcc.texi.
@c man begin COPYRIGHT
Copyright @copyright{} 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
-fno-nonansi-builtins -fno-operator-names @gol
-fno-optional-diags -fpermissive @gol
-fno-pretty-templates @gol
--frepo -fno-rtti -fstats -ftemplate-depth-@var{n} @gol
+-frepo -fno-rtti -fstats -ftemplate-depth=@var{n} @gol
-fno-threadsafe-statics -fuse-cxa-atexit -fno-weak -nostdinc++ @gol
-fno-default-inline -fvisibility-inlines-hidden @gol
-fvisibility-ms-compat @gol
--Wabi -Wctor-dtor-privacy @gol
+-Wabi -Wconversion-null -Wctor-dtor-privacy @gol
-Wnon-virtual-dtor -Wreorder @gol
-Weffc++ -Wstrict-null-sentinel @gol
-Wno-non-template-friend -Wold-style-cast @gol
-Wstrict-overflow -Wstrict-overflow=@var{n} @gol
-Wswitch -Wswitch-default -Wswitch-enum -Wsync-nand @gol
-Wsystem-headers -Wtrigraphs -Wtype-limits -Wundef -Wuninitialized @gol
--Wunknown-pragmas -Wno-pragmas -Wunreachable-code @gol
+-Wunknown-pragmas -Wno-pragmas @gol
-Wunsuffixed-float-constants -Wunused -Wunused-function @gol
-Wunused-label -Wunused-parameter -Wno-unused-result -Wunused-value -Wunused-variable @gol
-Wvariadic-macros -Wvla @gol
-frandom-seed=@var{string} -fsched-verbose=@var{n} @gol
-fsel-sched-verbose -fsel-sched-dump-cfg -fsel-sched-pipelining-verbose @gol
-ftest-coverage -ftime-report -fvar-tracking @gol
--fvar-tracking-assigments -fvar-tracking-assignments-toggle @gol
+-fvar-tracking-assignments -fvar-tracking-assignments-toggle @gol
-g -g@var{level} -gtoggle -gcoff -gdwarf-@var{version} @gol
-ggdb -gstabs -gstabs+ -gstrict-dwarf -gno-strict-dwarf @gol
-gvms -gxcoff -gxcoff+ @gol
-freciprocal-math -fregmove -frename-registers -freorder-blocks @gol
-freorder-blocks-and-partition -freorder-functions @gol
-frerun-cse-after-loop -freschedule-modulo-scheduled-loops @gol
--frounding-math -fsched2-use-superblocks @gol
--fsched2-use-traces -fsched-pressure @gol
+-frounding-math -fsched2-use-superblocks -fsched-pressure @gol
-fsched-spec-load -fsched-spec-load-dangerous @gol
-fsched-stalled-insns-dep[=@var{n}] -fsched-stalled-insns[=@var{n}] @gol
-fsched-group-heuristic -fsched-critical-path-heuristic @gol
-mincoming-stack-boundary=@var{num}
-mcld -mcx16 -msahf -mmovbe -mcrc32 -mrecip @gol
-mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol
--maes -mpclmul @gol
--msse4a -m3dnow -mpopcnt -mabm -mfma4 @gol
+-maes -mpclmul -mfused-madd @gol
+-msse4a -m3dnow -mpopcnt -mabm -mfma4 -mxop -mlwp @gol
-mthreads -mno-align-stringops -minline-all-stringops @gol
-minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol
-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
@emph{IA-64/VMS Options}
@gccoptlist{-mvms-return-codes -mdebug-main=@var{prefix} -mmalloc64}
+@emph{LM32 Options}
+@gccoptlist{-mbarrel-shift-enabled -mdivide-enabled -mmultiply-enabled @gol
+-msign-extend-enabled -muser-enabled}
+
@emph{M32R/D Options}
@gccoptlist{-m32r2 -m32rx -m32r @gol
-mdebug @gol
-mbranch-cost=@var{num} -mbranch-likely -mno-branch-likely @gol
-mfp-exceptions -mno-fp-exceptions @gol
-mvr4130-align -mno-vr4130-align -msynci -mno-synci @gol
--mrelax-pic-calls -mno-relax-pic-calls}
+-mrelax-pic-calls -mno-relax-pic-calls -mmcount-ra-address}
@emph{MMIX Options}
@gccoptlist{-mlibfuncs -mno-libfuncs -mepsilon -mno-epsilon -mabi=gnu @gol
-msdata=@var{opt} -mvxworks -G @var{num} -pthread}
@emph{RX Options}
-@gccoptlist{-m64bit-doubles -m32bit-doubles -mieee -mno-ieee@gol
+@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol
+-mcpu= -patch=@gol
-mbig-endian-data -mlittle-endian-data @gol
-msmall-data @gol
-msim -mno-sim@gol
-mas100-syntax -mno-as100-syntax@gol
-mrelax@gol
-mmax-constant-size=@gol
--mint-register=}
+-mint-register=@gol
+-msave-acc-in-interrupts}
@emph{S/390 and zSeries Options}
@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol
The default is version 2.
+Version 3 corrects an error in mangling a constant address as a
+template argument.
+
+Version 4 implements a standard mangling for vector types.
+
+See also @option{-Wabi}.
+
@item -fno-access-control
@opindex fno-access-control
Turn off all access checking. This switch is mainly useful for working
Emit statistics about front-end processing at the end of the compilation.
This information is generally only useful to the G++ development team.
-@item -ftemplate-depth-@var{n}
+@item -ftemplate-depth=@var{n}
@opindex ftemplate-depth
Set the maximum instantiation depth for template classes to @var{n}.
A limit on the template instantiation depth is needed to detect
concerned about the fact that code generated by G++ may not be binary
compatible with code generated by other compilers.
-The known incompatibilities at this point include:
+The known incompatibilities in @option{-fabi-version=2} (the default) include:
+
+@itemize @bullet
+
+@item
+A template with a non-type template parameter of reference type is
+mangled incorrectly:
+@smallexample
+extern int N;
+template <int &> struct S @{@};
+void n (S<N>) @{2@}
+@end smallexample
+
+This is fixed in @option{-fabi-version=3}.
+
+@item
+SIMD vector types declared using @code{__attribute ((vector_size))} are
+mangled in a non-standard way that does not allow for overloading of
+functions taking vectors of different sizes.
+
+The mangling is changed in @option{-fabi-version=4}.
+@end itemize
+
+The known incompatibilities in @option{-fabi-version=1} include:
@itemize @bullet
conversions between signed and unsigned integers can be disabled by
using @option{-Wno-sign-conversion}.
-For C++, also warn for conversions between @code{NULL} and non-pointer
-types; confusing overload resolution for user-defined conversions; and
-conversions that will never use a type conversion operator:
-conversions to @code{void}, the same type, a base class or a reference
-to them. Warnings about conversions between signed and unsigned
-integers are disabled by default in C++ unless
+For C++, also warn for confusing overload resolution for user-defined
+conversions; and conversions that will never use a type conversion
+operator: conversions to @code{void}, the same type, a base class or a
+reference to them. Warnings about conversions between signed and
+unsigned integers are disabled by default in C++ unless
@option{-Wsign-conversion} is explicitly enabled.
+@item -Wno-conversion-null @r{(C++)}
+@opindex Wconversion-null
+@opindex Wno-conversion-null
+Do not warn for conversions between @code{NULL} and non-pointer
+types. @option{-Wconversion-null} is enabled by default.
+
@item -Wempty-body
@opindex Wempty-body
@opindex Wno-empty-body
@opindex Wno-nested-externs
Warn if an @code{extern} declaration is encountered within a function.
-@item -Wunreachable-code
-@opindex Wunreachable-code
-@opindex Wno-unreachable-code
-Warn if the compiler detects that code will never be executed.
-
-This option is intended to warn when the compiler detects that at
-least a whole line of source code will never be executed, because
-some condition is never satisfied or because it is after a
-procedure that never returns.
-
-It is possible for this option to produce a warning even though there
-are circumstances under which part of the affected line can be executed,
-so care should be taken when removing apparently-unreachable code.
-
-For instance, when a function is inlined, a warning may mean that the
-line is unreachable in only one inlined copy of the function.
-
-This option is not made part of @option{-Wall} because in a debugging
-version of a program there is often substantial code which checks
-correct functioning of the program and is, hopefully, unreachable
-because the program does work. Another common use of unreachable
-code is to provide behavior which is selectable at compile-time.
-
@item -Winline
@opindex Winline
@opindex Wno-inline
Dump each function after applying vectorization of loops. The file name is
made by appending @file{.vect} to the source file name.
+@item slp
+@opindex fdump-tree-slp
+Dump each function after applying vectorization of basic blocks. The file name
+is made by appending @file{.slp} to the source file name.
+
@item vrp
@opindex fdump-tree-vrp
Dump each function after Value Range Propagation (VRP). The file name
level that @option{-fdump-tree-vect-stats} uses.
Higher verbosity levels mean either more information dumped for each
reported loop, or same amount of information reported for more loops:
-If @var{n}=3, alignment related information is added to the reports.
-If @var{n}=4, data-references related information (e.g.@: memory dependences,
+if @var{n}=3, vectorizer cost model information is reported.
+If @var{n}=4, alignment related information is added to the reports.
+If @var{n}=5, data-references related information (e.g.@: memory dependences,
memory access-patterns) is added to the reports.
-If @var{n}=5, the vectorizer reports also non-vectorized inner-most loops
+If @var{n}=6, the vectorizer reports also non-vectorized inner-most loops
that did not pass the first analysis phase (i.e., may not be countable, or
may have complicated control-flow).
-If @var{n}=6, the vectorizer reports also non-vectorized nested loops.
-For @var{n}=7, all the information the vectorizer generates during its
+If @var{n}=7, the vectorizer reports also non-vectorized nested loops.
+If @var{n}=8, SLP related information is added to the reports.
+For @var{n}=9, all the information the vectorizer generates during its
analysis and transformation is reported. This is the same verbosity level
that @option{-fdump-tree-vect-details} uses.
amount of debugging output the scheduler prints. This information is
written to standard error, unless @option{-fdump-rtl-sched1} or
@option{-fdump-rtl-sched2} is specified, in which case it is output
-to the usual dump listing file, @file{.sched} or @file{.sched2}
+to the usual dump listing file, @file{.sched1} or @file{.sched2}
respectively. However for @var{n} greater than nine, the output is
always printed to standard error.
Not all optimizations are controlled directly by a flag. Only
optimizations that have a flag are listed in this section.
-Most of the optimizations are not enabled if a @option{-O} level is not set on
-the command line, even if individual optimization flags are specified.
+Most optimizations are only enabled if an @option{-O} level is set on
+the command line. Otherwise they are disabled, even if individual
+optimization flags are specified.
Depending on the target and how GCC was configured, a slightly different
set of optimizations may be enabled at each @option{-O} level than
by allowing other instructions to be issued until the result of the load
or floating point instruction is required.
-Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}.
+Enabled at levels @option{-O2}, @option{-O3}.
@item -fschedule-insns2
@opindex fschedule-insns2
with @option{-fschedule-insns} or @option{-fschedule-insns2} or
at @option{-O2} or higher.
-@item -fsched2-use-traces
-@opindex fsched2-use-traces
-Use @option{-fsched2-use-superblocks} algorithm when scheduling after register
-allocation and additionally perform code duplication in order to increase the
-size of superblocks using tracer pass. See @option{-ftracer} for details on
-trace formation.
-
-This mode should produce faster but significantly longer programs. Also
-without @option{-fbranch-probabilities} the traces constructed may not
-match the reality and hurt the performance. This only makes
-sense when scheduling after register allocation, i.e.@: with
-@option{-fschedule-insns2} or at @option{-O2} or higher.
-
@item -freschedule-modulo-scheduled-loops
@opindex freschedule-modulo-scheduled-loops
The modulo scheduling comes before the traditional scheduling, if a loop
Perform loop vectorization on trees. This flag is enabled by default at
@option{-O3}.
+@item -ftree-slp-vectorize
+@opindex ftree-slp-vectorize
+Perform basic block vectorization on trees. This flag is enabled by default at
+@option{-O3} and when @option{-ftree-vectorize} is enabled.
+
@item -ftree-vect-loop-version
@opindex ftree-vect-loop-version
Perform loop versioning when doing loop vectorization on trees. When a loop
strict version check, so bytecode files generated in one version of
GCC will not work with an older/newer version of GCC.
+Link time optimization does not play well with generating debugging
+information. Combining @option{-flto} or @option{-fwhopr} with
+@option{-g} is experimental.
+
This option is disabled by default.
@item -fwhopr
Disabled by default.
+This option is experimental.
+
@item -fwpa
@opindex fwpa
This is an internal option used by GCC when compiling with
and thus may not be used when ordered comparisons are required.
This option requires that both @option{-fno-signed-zeros} and
@option{-fno-trapping-math} be in effect. Moreover, it doesn't make
-much sense with @option{-frounding-math}.
+much sense with @option{-frounding-math}. For Fortran the option
+is automatically enabled when both @option{-fno-signed-zeros} and
+@option{-fno-trapping-math} are in effect.
The default is @option{-fno-associative-math}.
make debugging impossible, since variables will no longer stay in
a ``home register''.
-Enabled by default with @option{-funroll-loops}.
+Enabled by default with @option{-funroll-loops} and @option{-fpeel-loops}.
@item -ftracer
@opindex ftracer
parameter, then structure reorganization is not applied to this structure.
The default is 10.
-@item predictable-branch-cost-outcome
+@item predictable-branch-outcome
When branch is predicted to be taken with probability lower than this threshold
(in percent), then it is considered well predictable. The default is 10.
motion optimization performed on them. The default value of the
parameter is 1000 for -O1 and 10000 for -O2 and above.
+@item max-vartrack-size
+Sets a maximum number of hash table slots to use during variable
+tracking dataflow analysis of any function. If this limit is exceeded
+with variable tracking at assignments enabled, analysis for that
+function is retried without it, after removing all debug insns from
+the function. If the limit is exceeded even without debug insns, var
+tracking analysis is completely disabled for the function. Setting
+the parameter to zero makes it unlimited.
+
@item min-nondebug-insn-uid
Use uids starting at this parameter for nondebug insns. The range below
the parameter is reserved exclusively for debug insns created by
* i386 and x86-64 Windows Options::
* IA-64 Options::
* IA-64/VMS Options::
+* LM32 Options::
* M32C Options::
* M32R/D Options::
* M680x0 Options::
@samp{arm10e}, @samp{arm1020e}, @samp{arm1022e},
@samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
@samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
-@samp{cortex-a8}, @samp{cortex-a9},
+@samp{cortex-a5}, @samp{cortex-a8}, @samp{cortex-a9},
@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m3},
@samp{cortex-m1},
@samp{cortex-m0},
@opindex mfp
This specifies what floating point hardware (or hardware emulation) is
available on the target. Permissible names are: @samp{fpa}, @samp{fpe2},
-@samp{fpe3}, @samp{maverick}, @samp{vfp}, @samp{vfpv3}, @samp{vfpv3-d16},
-@samp{neon}, and @samp{neon-fp16}. @option{-mfp} and @option{-mfpe}
-are synonyms for @option{-mfpu}=@samp{fpe}@var{number}, for compatibility
-with older versions of GCC@.
+@samp{fpe3}, @samp{maverick}, @samp{vfp}, @samp{vfpv3}, @samp{vfpv3-fp16},
+@samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd}, @samp{vfpv3xd-fp16},
+@samp{neon}, @samp{neon-fp16}, @samp{vfpv4}, @samp{vfpv4-d16},
+@samp{fpv4-sp-d16} and @samp{neon-vfpv4}.
+@option{-mfp} and @option{-mfpe} are synonyms for
+@option{-mfpu}=@samp{fpe}@var{number}, for compatibility with older versions
+of GCC@.
If @option{-msoft-float} is specified this specifies the format of
floating point values.
@itemx -mno-sse4a
@itemx -mfma4
@itemx -mno-fma4
+@itemx -mxop
+@itemx -mno-xop
+@itemx -mlwp
+@itemx -mno-lwp
@itemx -m3dnow
@itemx -mno-3dnow
@itemx -mpopcnt
@opindex m3dnow
@opindex mno-3dnow
These switches enable or disable the use of instructions in the MMX,
-SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AES, PCLMUL, SSE4A, FMA4, ABM or
-3DNow!@: extended instruction sets.
+SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AES, PCLMUL, SSE4A, FMA4, XOP,
+LWP, ABM or 3DNow!@: extended instruction sets.
These extensions are also available as built-in functions: see
@ref{X86 Built-in Functions}, for details of the functions enabled and
disabled by these switches.
the file containing the CPU detection code should be compiled without
these options.
+@item -mfused-madd
+@itemx -mno-fused-madd
+@opindex mfused-madd
+@opindex mno-fused-madd
+Do (don't) generate code that uses the fused multiply/add or multiply/subtract
+instructions. The default is to use these instructions.
+
@item -mcld
@opindex mcld
This option instructs GCC to emit a @code{cld} instruction in the prologue
of the non-reciprocal instruction, the precision of the sequence can be
decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994).
+Note that GCC implements 1.0f/sqrtf(x) in terms of RSQRTSS (or RSQRTPS)
+already with @option{-ffast-math} (or the above option combination), and
+doesn't need @option{-mrecip}.
+
@item -mveclibabi=@var{type}
@opindex mveclibabi
Specifies the ABI type to use for vectorizing intrinsics using an
@opindex mfused-madd
@opindex mno-fused-madd
Do (don't) generate code that uses the fused multiply/add or multiply/subtract
-instructions. The default is to use these instructions.
+instructions. The default is to use these instructions.
@item -mno-dwarf2-asm
@itemx -mdwarf2-asm
Default to 64bit memory allocation routines.
@end table
+@node LM32 Options
+@subsection LM32 Options
+@cindex LM32 options
+
+These @option{-m} options are defined for the Lattice Mico32 architecture:
+
+@table @gcctabopt
+@item -mbarrel-shift-enabled
+@opindex mbarrel-shift-enabled
+Enable barrel-shift instructions.
+
+@item -mdivide-enabled
+@opindex mdivide-enabled
+Enable divide and modulus instructions.
+
+@item -mmultiply-enabled
+@opindex multiply-enabled
+Enable multiply instructions.
+
+@item -msign-extend-enabled
+@opindex msign-extend-enabled
+Enable sign extend instructions.
+
+@item -muser-enabled
+@opindex muser-enabled
+Enable user-defined instructions.
+
+@end table
+
@node M32C Options
@subsection M32C Options
@cindex M32C options
directive and @code{-mexplicit-relocs} is in effect. With
@code{-mno-explicit-relocs}, this optimization can be performed by the
assembler and the linker alone without help from the compiler.
+
+@item -mmcount-ra-address
+@itemx -mno-mcount-ra-address
+@opindex mmcount-ra-address
+@opindex mno-mcount-ra-address
+Emit (do not emit) code that allows @code{_mcount} to modify the
+calling function's return address. When enabled, this option extends
+the usual @code{_mcount} interface with a new @var{ra-address}
+parameter, which has type @code{intptr_t *} and is passed in register
+@code{$12}. @code{_mcount} can then modify the return address by
+doing both of the following:
+@itemize
+@item
+Returning the new address in register @code{$31}.
+@item
+Storing the new address in @code{*@var{ra-address}},
+if @var{ra-address} is nonnull.
+@end itemize
+
+The default is @option{-mno-mcount-ra-address}.
+
@end table
@node MMIX Options
@samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{630}, @samp{740},
@samp{7400}, @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
@samp{860}, @samp{970}, @samp{8540}, @samp{a2}, @samp{e300c2},
-@samp{e300c3}, @samp{e500mc}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
-@samp{power}, @samp{power2}, @samp{power3}, @samp{power4},
-@samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, @samp{power7},
-@samp{common}, @samp{powerpc}, @samp{powerpc64}, @samp{rios},
+@samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{ec603e}, @samp{G3},
+@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
+@samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x},
+@samp{power7}, @samp{common}, @samp{powerpc}, @samp{powerpc64}, @samp{rios},
@samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}.
@option{-mcpu=common} selects a completely generic processor. Code
signals may get corrupted data.
@item -mavoid-indexed-addresses
-@item -mno-avoid-indexed-addresses
+@itemx -mno-avoid-indexed-addresses
@opindex mavoid-indexed-addresses
@opindex mno-avoid-indexed-addresses
Generate code that tries to avoid (not avoid) the use of indexed load
@subsection RX Options
@cindex RX Options
-These @option{-m} options are defined for RX implementations:
+These command line options are defined for RX targets:
@table @gcctabopt
@item -m64bit-doubles
@opindex m32bit-doubles
Make the @code{double} data type be 64-bits (@option{-m64bit-doubles})
or 32-bits (@option{-m32bit-doubles}) in size. The default is
-@option{-m32bit-doubles}. @emph{Note} the RX's hardware floating
-point instructions are only used for 32-bit floating point values, and
-then only if @option{-ffast-math} has been specified on the command
-line. This is because the RX FPU instructions do not properly support
-denormal (or sub-normal) values.
+@option{-m32bit-doubles}. @emph{Note} RX floating point hardware only
+works on 32-bit values, which is why the default is
+@option{-m32bit-doubles}.
+
+@item -fpu
+@itemx -nofpu
+@opindex fpu
+@opindex nofpu
+Enables (@option{-fpu}) or disables (@option{-nofpu}) the use of RX
+floating point hardware. The default is enabled for the @var{RX600}
+series and disabled for the @var{RX200} series.
+
+Floating point instructions will only be generated for 32-bit floating
+point values however, so if the @option{-m64bit-doubles} option is in
+use then the FPU hardware will not be used for doubles.
+
+@emph{Note} If the @option{-fpu} option is enabled then
+@option{-funsafe-math-optimizations} is also enabled automatically.
+This is because the RX FPU instructions are themselves unsafe.
+
+@item -mcpu=@var{name}
+@itemx -patch=@var{name}
+@opindex -mcpu
+@opindex -patch
+Selects the type of RX CPU to be targeted. Currently three types are
+supported, the generic @var{RX600} and @var{RX200} series hardware and
+the specific @var{RX610} cpu. The default is @var{RX600}.
+
+The only difference between @var{RX600} and @var{RX610} is that the
+@var{RX610} does not support the @code{MVTIPL} instruction.
+
+The @var{RX200} series does not have a hardware floating point unit
+and so @option{-nofpu} is enabled by default when this type is
+selected.
@item -mbig-endian-data
@itemx -mlittle-endian-data
Note, common variables (variables which have not been initialised) and
constants are not placed into the small data area as they are assigned
-to other sections in the output executeable.
+to other sections in the output executable.
The default value is zero, which disables this feature. Note, this
feature is not enabled by default with higher optimization levels
-(@option{-O2} etc) because of the potentially deterimental effects of
+(@option{-O2} etc) because of the potentially detrimental effects of
reserving register @code{r13}. It is up to the programmer to
experiment and discover whether this feature is of benefit to their
program.
@item -msim
-@item -mno-sim
+@itemx -mno-sim
@opindex msim
@opindex mno-sim
Use the simulator runtime. The default is to use the libgloss board
specific runtime.
@item -mas100-syntax
-@item -mno-as100-syntax
+@itemx -mno-as100-syntax
@opindex mas100-syntax
@opindex mno-as100-syntax
When generating assembler output use a syntax that is compatible with
@opindex mmax-constant-size
Specifies the maxium size, in bytes, of a constant that can be used as
an operand in a RX instruction. Although the RX instruction set does
-allow consants of up to 4 bytes in length to be used in instructions,
+allow constants of up to 4 bytes in length to be used in instructions,
a longer value equates to a longer instruction. Thus in some
circumstances it can be beneficial to restrict the size of constants
that are used in instructions. Constants that are too big are instead
placed into a constant pool and referenced via register indirection.
-The value @var{N} can be between 0 and 3. A value of 0, the default,
-means that constants of any size are allowed.
+The value @var{N} can be between 0 and 4. A value of 0 (the default)
+or 4 means that constants of any size are allowed.
@item -mrelax
@opindex mrelax
@code{r12}. A value of 3 reserves @code{r13}, @code{r12} and
@code{r11}, and a value of 4 reserves @code{r13} through @code{r10}.
A value of 0, the default, does not reserve any registers.
+
+@item -msave-acc-in-interrupts
+@opindex msave-acc-in-interrupts
+Specifies that interrupt handler functions should preserve the
+accumulator register. This is only necessary if normal code might use
+the accumulator register, for example because it performs 64-bit
+multiplications. The default is to ignore the accumulator as this
+makes the interrupt handlers faster.
+
@end table
@emph{Note:} The generic GCC command line @option{-ffixed-@var{reg}}
@opindex municode
This option is available for mingw-w64 targets. It specifies
that the UNICODE macro is getting pre-defined and that the
-unicode capable runtime startup code is choosen.
+unicode capable runtime startup code is chosen.
@item -mwin32
@opindex mwin32
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