@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-@c 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+@c 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
@c Free Software Foundation, Inc.
@c This is part of the GCC manual.
@c For copying conditions, see the file gcc.texi.
@c man begin COPYRIGHT
Copyright @copyright{} 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
@cindex options, grouping
The @command{gcc} program accepts options and file names as operands. Many
options have multi-letter names; therefore multiple single-letter options
-may @emph{not} be grouped: @option{-dr} is very different from @w{@samp{-d
--r}}.
+may @emph{not} be grouped: @option{-dv} is very different from @w{@samp{-d
+-v}}.
@cindex order of options
@cindex options, order
@xref{Warning Options,,Options to Request or Suppress Warnings}.
@gccoptlist{-fsyntax-only -pedantic -pedantic-errors @gol
-w -Wextra -Wall -Waddress -Waggregate-return -Warray-bounds @gol
--Wno-attributes -Wc++-compat -Wc++0x-compat -Wcast-align -Wcast-qual @gol
+-Wno-attributes -Wno-builtin-macro-redefined @gol
+-Wc++-compat -Wc++0x-compat -Wcast-align -Wcast-qual @gol
-Wchar-subscripts -Wclobbered -Wcomment @gol
-Wconversion -Wcoverage-mismatch -Wno-deprecated @gol
-Wno-deprecated-declarations -Wdisabled-optimization @gol
-Wmissing-format-attribute -Wmissing-include-dirs @gol
-Wmissing-noreturn -Wno-mudflap @gol
-Wno-multichar -Wnonnull -Wno-overflow @gol
--Woverlength-strings -Wpacked -Wpadded @gol
--Wparentheses -Wpointer-arith -Wno-pointer-to-int-cast @gol
+-Woverlength-strings -Wpacked -Wpacked-bitfield-compat -Wpadded @gol
+-Wparentheses -Wpedantic-ms-format -Wno-pedantic-ms-format @gol
+-Wpointer-arith -Wno-pointer-to-int-cast @gol
-Wredundant-decls @gol
-Wreturn-type -Wsequence-point -Wshadow @gol
-Wsign-compare -Wsign-conversion -Wstack-protector @gol
-Wstrict-aliasing -Wstrict-aliasing=n @gol
-Wstrict-overflow -Wstrict-overflow=@var{n} @gol
--Wswitch -Wswitch-default -Wswitch-enum @gol
+-Wswitch -Wswitch-default -Wswitch-enum -Wsync-nand @gol
-Wsystem-headers -Wtrigraphs -Wtype-limits -Wundef -Wuninitialized @gol
-Wunknown-pragmas -Wno-pragmas -Wunreachable-code @gol
-Wunused -Wunused-function -Wunused-label -Wunused-parameter @gol
@xref{Debugging Options,,Options for Debugging Your Program or GCC}.
@gccoptlist{-d@var{letters} -dumpspecs -dumpmachine -dumpversion @gol
-fdbg-cnt-list -fdbg-cnt=@var{counter-value-list} @gol
--fdump-noaddr -fdump-unnumbered -fdump-translation-unit@r{[}-@var{n}@r{]} @gol
+-fdump-noaddr -fdump-unnumbered @gol
+-fdump-translation-unit@r{[}-@var{n}@r{]} @gol
-fdump-class-hierarchy@r{[}-@var{n}@r{]} @gol
-fdump-ipa-all -fdump-ipa-cgraph -fdump-ipa-inline @gol
-fdump-statistics @gol
-feliminate-unused-debug-symbols -femit-class-debug-always @gol
-fmem-report -fpre-ipa-mem-report -fpost-ipa-mem-report -fprofile-arcs @gol
-frandom-seed=@var{string} -fsched-verbose=@var{n} @gol
+-fsel-sched-verbose -fsel-sched-dump-cfg -fsel-sched-pipelining-verbose @gol
-ftest-coverage -ftime-report -fvar-tracking @gol
-g -g@var{level} -gcoff -gdwarf-2 @gol
-ggdb -gstabs -gstabs+ -gvms -gxcoff -gxcoff+ @gol
--fno-merge-debug-strings -fdebug-prefix-map=@var{old}=@var{new} @gol
+-fno-merge-debug-strings -fno-dwarf2-cfi-asm @gol
+-fdebug-prefix-map=@var{old}=@var{new} @gol
-femit-struct-debug-baseonly -femit-struct-debug-reduced @gol
-femit-struct-debug-detailed@r{[}=@var{spec-list}@r{]} @gol
-p -pg -print-file-name=@var{library} -print-libgcc-file-name @gol
-falign-labels[=@var{n}] -falign-loops[=@var{n}] -fassociative-math @gol
-fauto-inc-dec -fbranch-probabilities -fbranch-target-load-optimize @gol
-fbranch-target-load-optimize2 -fbtr-bb-exclusive -fcaller-saves @gol
--fcheck-data-deps -fcprop-registers -fcrossjumping -fcse-follow-jumps @gol
--fcse-skip-blocks -fcx-fortran-rules -fcx-limited-range @gol
+-fcheck-data-deps -fconserve-stack -fcprop-registers -fcrossjumping @gol
+-fcse-follow-jumps -fcse-skip-blocks -fcx-fortran-rules -fcx-limited-range @gol
-fdata-sections -fdce -fdce @gol
-fdelayed-branch -fdelete-null-pointer-checks -fdse -fdse @gol
-fearly-inlining -fexpensive-optimizations -ffast-math @gol
-ffunction-sections -fgcse -fgcse-after-reload -fgcse-las -fgcse-lm @gol
-fgcse-sm -fif-conversion -fif-conversion2 -findirect-inlining @gol
-finline-functions -finline-functions-called-once -finline-limit=@var{n} @gol
--finline-small-functions -fipa-cp -fipa-marix-reorg -fipa-pta @gol
+-finline-small-functions -fipa-cp -fipa-cp-clone -fipa-matrix-reorg -fipa-pta @gol
-fipa-pure-const -fipa-reference -fipa-struct-reorg @gol
--fipa-type-escape -fivopts -fkeep-inline-functions -fkeep-static-consts @gol
+-fipa-type-escape -fira-algorithm=@var{algorithm} @gol
+-fira-region=@var{region} -fira-coalesce -fno-ira-share-save-slots @gol
+-fno-ira-share-spill-slots -fira-verbose=@var{n} @gol
+-fivopts -fkeep-inline-functions -fkeep-static-consts @gol
+-floop-block -floop-interchange -floop-strip-mine @gol
-fmerge-all-constants -fmerge-constants -fmodulo-sched @gol
-fmodulo-sched-allow-regmoves -fmove-loop-invariants -fmudflap @gol
-fmudflapir -fmudflapth -fno-branch-count-reg -fno-default-inline @gol
-fno-toplevel-reorder -fno-trapping-math -fno-zero-initialized-in-bss @gol
-fomit-frame-pointer -foptimize-register-move -foptimize-sibling-calls @gol
-fpeel-loops -fpredictive-commoning -fprefetch-loop-arrays @gol
--fprofile-dir=@var{path} -fprofile-generate -fprofile-generate=@var{path} @gol
+-fprofile-correction -fprofile-dir=@var{path} -fprofile-generate @gol
+-fprofile-generate=@var{path} @gol
-fprofile-use -fprofile-use=@var{path} -fprofile-values @gol
-freciprocal-math -fregmove -frename-registers -freorder-blocks @gol
-freorder-blocks-and-partition -freorder-functions @gol
-fsched2-use-traces -fsched-spec-load -fsched-spec-load-dangerous @gol
-fsched-stalled-insns-dep[=@var{n}] -fsched-stalled-insns[=@var{n}] @gol
-fschedule-insns -fschedule-insns2 -fsection-anchors -fsee @gol
+-fselective-scheduling -fselective-scheduling2 @gol
+-fsel-sched-pipelining -fsel-sched-pipelining-outer-loops @gol
-fsignaling-nans -fsingle-precision-constant -fsplit-ivs-in-unroller @gol
-fsplit-wide-types -fstack-protector -fstack-protector-all @gol
-fstrict-aliasing -fstrict-overflow -fthread-jumps -ftracer @gol
-ftree-loop-distribution @gol
-ftree-loop-ivcanon -ftree-loop-linear -ftree-loop-optimize @gol
-ftree-parallelize-loops=@var{n} -ftree-pre -ftree-reassoc @gol
--ftree-sink -ftree-sra -ftree-store-ccp -ftree-switch-conversion @gol
+-ftree-sink -ftree-sra -ftree-switch-conversion @gol
-ftree-ter -ftree-vect-loop-version -ftree-vectorize -ftree-vrp @gol
-funit-at-a-time -funroll-all-loops -funroll-loops @gol
-funsafe-loop-optimizations -funsafe-math-optimizations -funswitch-loops @gol
@gccoptlist{@var{object-file-name} -l@var{library} @gol
-nostartfiles -nodefaultlibs -nostdlib -pie -rdynamic @gol
-s -static -static-libgcc -shared -shared-libgcc -symbolic @gol
--Wl,@var{option} -Xlinker @var{option} @gol
+-T @var{script} -Wl,@var{option} -Xlinker @var{option} @gol
-u @var{symbol}}
@item Directory Options
-mthumb -marm @gol
-mtpcs-frame -mtpcs-leaf-frame @gol
-mcaller-super-interworking -mcallee-super-interworking @gol
--mtp=@var{name}}
+-mtp=@var{name} @gol
+-mword-relocations @gol
+-mfix-cortex-m3-ldrd}
@emph{AVR Options}
@gccoptlist{-mmcu=@var{mcu} -msize -minit-stack=@var{n} -mno-interrupts @gol
-mno-id-shared-library -mshared-library-id=@var{n} @gol
-mleaf-id-shared-library -mno-leaf-id-shared-library @gol
-msep-data -mno-sep-data -mlong-calls -mno-long-calls @gol
--mfast-fp -minline-plt -mmulticore -mcorea -mcoreb -msdram}
+-mfast-fp -minline-plt -mmulticore -mcorea -mcoreb -msdram @gol
+-micplb}
@emph{CRIS Options}
@gccoptlist{-mcpu=@var{cpu} -march=@var{cpu} -mtune=@var{cpu} @gol
-mpreferred-stack-boundary=@var{num}
-mincoming-stack-boundary=@var{num}
-mcld -mcx16 -msahf -mrecip @gol
--mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 @gol
+-mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol
-maes -mpclmul @gol
-msse4a -m3dnow -mpopcnt -mabm -msse5 @gol
-mthreads -mno-align-stringops -minline-all-stringops @gol
-momit-leaf-frame-pointer -mno-red-zone -mno-tls-direct-seg-refs @gol
-mcmodel=@var{code-model} @gol
-m32 -m64 -mlarge-data-threshold=@var{num} @gol
--mfused-madd -mno-fused-madd}
+-mfused-madd -mno-fused-madd -msse2avx}
@emph{IA-64 Options}
@gccoptlist{-mbig-endian -mlittle-endian -mgnu-as -mgnu-ld -mno-pic @gol
-mips16 -mno-mips16 -mflip-mips16 @gol
-minterlink-mips16 -mno-interlink-mips16 @gol
-mabi=@var{abi} -mabicalls -mno-abicalls @gol
--mshared -mno-shared -mxgot -mno-xgot -mgp32 -mgp64 @gol
--mfp32 -mfp64 -mhard-float -msoft-float @gol
+-mshared -mno-shared -mplt -mno-plt -mxgot -mno-xgot @gol
+-mgp32 -mgp64 -mfp32 -mfp64 -mhard-float -msoft-float @gol
-msingle-float -mdouble-float -mdsp -mno-dsp -mdspr2 -mno-dspr2 @gol
+-mfpu=@var{fpu-type} @gol
-msmartmips -mno-smartmips @gol
-mpaired-single -mno-paired-single -mdmx -mno-mdmx @gol
-mips3d -mno-mips3d -mmt -mno-mt -mllsc -mno-llsc @gol
-mmemcpy -mno-memcpy -mlong-calls -mno-long-calls @gol
-mmad -mno-mad -mfused-madd -mno-fused-madd -nocpp @gol
-mfix-r4000 -mno-fix-r4000 -mfix-r4400 -mno-fix-r4400 @gol
--mfix-vr4120 -mno-fix-vr4120 -mfix-vr4130 -mno-fix-vr4130 @gol
--mfix-sb1 -mno-fix-sb1 @gol
+-mfix-r10000 -mno-fix-r10000 -mfix-vr4120 -mno-fix-vr4120 @gol
+-mfix-vr4130 -mno-fix-vr4130 -mfix-sb1 -mno-fix-sb1 @gol
-mflush-func=@var{func} -mno-flush-func @gol
-mbranch-cost=@var{num} -mbranch-likely -mno-branch-likely @gol
-mfp-exceptions -mno-fp-exceptions @gol
-mbranch-expensive -mbranch-cheap @gol
-msplit -mno-split -munix-asm -mdec-asm}
+@emph{picoChip Options}
+@gccoptlist{-mae=@var{ae_type} -mvliw-lookahead=@var{N}
+-msymbol-as-address -mno-inefficient-warnings}
+
@emph{PowerPC Options}
See RS/6000 and PowerPC Options.
-m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol
-malign-power -malign-natural @gol
-msoft-float -mhard-float -mmultiple -mno-multiple @gol
+-msingle-float -mdouble-float -msimple-fpu @gol
-mstring -mno-string -mupdate -mno-update @gol
+-mavoid-indexed-addresses -mno-avoid-indexed-addresses @gol
-mfused-madd -mno-fused-madd -mbit-align -mno-bit-align @gol
-mstrict-align -mno-strict-align -mrelocatable @gol
-mno-relocatable -mrelocatable-lib -mno-relocatable-lib @gol
-mspe -mno-spe @gol
-mspe=yes -mspe=no @gol
-mpaired @gol
+-mgen-cell-microcode -mwarn-cell-microcode @gol
-mvrsave -mno-vrsave @gol
-mmulhw -mno-mulhw @gol
-mdlmzb -mno-dlmzb @gol
@emph{S/390 and zSeries Options}
@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol
--mhard-float -msoft-float -mlong-double-64 -mlong-double-128 @gol
+-mhard-float -msoft-float -mhard-dfp -mno-hard-dfp @gol
+-mlong-double-64 -mlong-double-128 @gol
-mbackchain -mno-backchain -mpacked-stack -mno-packed-stack @gol
-msmall-exec -mno-small-exec -mmvcle -mno-mvcle @gol
-m64 -m31 -mdebug -mno-debug -mesa -mzarch @gol
The compiler can accept several base standards, such as @samp{c89} or
@samp{c++98}, and GNU dialects of those standards, such as
-@samp{gnu89} or @samp{gnu++98}. By specifing a base standard, the
+@samp{gnu89} or @samp{gnu++98}. By specifying a base standard, the
compiler will accept all programs following that standard and those
using GNU extensions that do not contradict it. For example,
@samp{-std=c89} turns off certain features of GCC that are
incompatible with ISO C90, such as the @code{asm} and @code{typeof}
keywords, but not other GNU extensions that do not have a meaning in
ISO C90, such as omitting the middle term of a @code{?:}
-expression. On the other hand, by specifing a GNU dialect of a
+expression. On the other hand, by specifying a GNU dialect of a
standard, all features the compiler support are enabled, even when
those features change the meaning of the base standard and some
strict-conforming programs may be rejected. The particular standard
With the @option{-fno-builtin-@var{function}} option
only the built-in function @var{function} is
disabled. @var{function} must not begin with @samp{__builtin_}. If a
-function is named this is not built-in in this version of GCC, this
+function is named that is not built-in in this version of GCC, this
option is ignored. There is no corresponding
@option{-fbuiltin-@var{function}} option; if you wish to enable
built-in functions selectively when using @option{-fno-builtin} or
functions will have linkage like inline functions; they just won't be
inlined by default.
-@item -Wabi @r{(C++ and Objective-C++ only)}
+@item -Wabi @r{(C, Objective-C, C++ and Objective-C++ only)}
@opindex Wabi
@opindex Wno-abi
Warn when G++ generates code that is probably not compatible with the
@end itemize
+It also warns psABI related changes. The known psABI changes at this
+point include:
+
+@itemize @bullet
+
+@item
+For SYSV/x86-64, when passing union with long double, it is changed to
+pass in memory as specified in psABI. For example:
+
+@smallexample
+union U @{
+ long double ld;
+ int i;
+@};
+@end smallexample
+
+@noindent
+@code{union U} will always be passed in memory.
+
+@end itemize
+
@item -Wctor-dtor-privacy @r{(C++ and Objective-C++ only)}
@opindex Wctor-dtor-privacy
@opindex Wno-ctor-dtor-privacy
Warn also about the use of an uncasted @code{NULL} as sentinel. When
compiling only with GCC this is a valid sentinel, as @code{NULL} is defined
to @code{__null}. Although it is a null pointer constant not a null pointer,
-it is guaranteed to of the same size as a pointer. But this use is
+it is guaranteed to be of the same size as a pointer. But this use is
not portable across different compilers.
@item -Wno-non-template-friend @r{(C++ and Objective-C++ only)}
@item -Wmain
@opindex Wmain
@opindex Wno-main
-Warn if the type of @samp{main} is suspicious. @samp{main} should be a
-function with external linkage, returning int, taking either zero
-arguments, two, or three arguments of appropriate types.
-This warning is enabled by @option{-Wall}.
+Warn if the type of @samp{main} is suspicious. @samp{main} should be
+a function with external linkage, returning int, taking either zero
+arguments, two, or three arguments of appropriate types. This warning
+is enabled by default in C++ and is enabled by either @option{-Wall}
+or @option{-pedantic}.
@item -Wmissing-braces
@opindex Wmissing-braces
enumeration. @code{case} labels outside the enumeration range also
provoke warnings when this option is used.
+@item -Wsync-nand @r{(C and C++ only)}
+@opindex Wsync-nand
+@opindex Wno-sync-nand
+Warn when @code{__sync_fetch_and_nand} and @code{__sync_nand_and_fetch}
+built-in functions are used. These functions changed semantics in GCC 4.4.
+
@item -Wtrigraphs
@opindex Wtrigraphs
@opindex Wno-trigraphs
@option{-funsafe-loop-optimizations} warn if the compiler made
such assumptions.
+@item -Wno-pedantic-ms-format @r{(MinGW targets only)}
+@opindex Wno-pedantic-ms-format
+@opindex Wpedantic-ms-format
+Disables the warnings about non-ISO @code{printf} / @code{scanf} format
+width specifiers @code{I32}, @code{I64}, and @code{I} used on Windows targets
+depending on the MS runtime, when you are using the options @option{-Wformat}
+and @option{-pedantic} without gnu-extensions.
+
@item -Wpointer-arith
@opindex Wpointer-arith
@opindex Wno-pointer-arith
@opindex Wwrite-strings
@opindex Wno-write-strings
When compiling C, give string constants the type @code{const
-char[@var{length}]} so that
-copying the address of one into a non-@code{const} @code{char *}
-pointer will get a warning; when compiling C++, warn about the
-deprecated conversion from string literals to @code{char *}. This
-warning, by default, is enabled for C++ programs.
-These warnings will help you find at
-compile time code that can try to write into a string constant, but
-only if you have been very careful about using @code{const} in
-declarations and prototypes. Otherwise, it will just be a nuisance;
-this is why we did not make @option{-Wall} request these warnings.
+char[@var{length}]} so that copying the address of one into a
+non-@code{const} @code{char *} pointer will get a warning. These
+warnings will help you find at compile time code that can try to write
+into a string constant, but only if you have been very careful about
+using @code{const} in declarations and prototypes. Otherwise, it will
+just be a nuisance. This is why we did not make @option{-Wall} request
+these warnings.
+
+When compiling C++, warn about the deprecated conversion from string
+literals to @code{char *}. This warning is enabled by default for C++
+programs.
@item -Wclobbered
@opindex Wclobbered
@opindex Wempty-body
@opindex Wno-empty-body
Warn if an empty body occurs in an @samp{if}, @samp{else} or @samp{do
-while} statement. Additionally, in C++, warn when an empty body occurs
-in a @samp{while} or @samp{for} statement with no whitespacing before
-the semicolon. This warning is also enabled by @option{-Wextra}.
+while} statement. This warning is also enabled by @option{-Wextra}.
@item -Wenum-compare @r{(C++ and Objective-C++ only)}
@opindex Wenum-compare
etc. This will not stop errors for incorrect use of supported
attributes.
+@item -Wno-builtin-macro-redefined
+@opindex Wno-builtin-macro-redefined
+@opindex Wbuiltin-macro-redefined
+Do not warn if certain built-in macros are redefined. This suppresses
+warnings for redefinition of @code{__TIMESTAMP__}, @code{__TIME__},
+@code{__DATE__}, @code{__FILE__}, and @code{__BASE_FILE__}.
+
@item -Wstrict-prototypes @r{(C and Objective-C only)}
@opindex Wstrict-prototypes
@opindex Wno-strict-prototypes
@end group
@end smallexample
+@item -Wpacked-bitfield-compat
+@opindex Wpacked-bitfield-compat
+@opindex Wno-packed-bitfield-compat
+The 4.1, 4.2 and 4.3 series of GCC ignore the @code{packed} attribute
+on bit-fields of type @code{char}. This has been fixed in GCC 4.4 but
+the change can lead to differences in the structure layout. GCC
+informs you when the offset of such a field has changed in GCC 4.4.
+For example there is no longer a 4-bit padding between field @code{a}
+and @code{b} in this structure:
+
+@smallexample
+struct foo
+@{
+ char a:4;
+ char b:8;
+@} __attribute__ ((packed));
+@end smallexample
+
+This warning is enabled by default. Use
+@option{-Wno-packed-bitfield-compat} to disable this warning.
+
@item -Wpadded
@opindex Wpadded
@opindex Wno-padded
When compiling files in directory @file{@var{old}}, record debugging
information describing them as in @file{@var{new}} instead.
+@item -fno-dwarf2-cfi-asm
+@opindex fdwarf2-cfi-asm
+@opindex fno-dwarf2-cfi-asm
+Emit DWARF 2 unwind info as compiler generated @code{.eh_frame} section
+instead of using GAS @code{.cfi_*} directives.
+
@cindex @command{prof}
@item -p
@opindex p
switches may have different effects when @option{-E} is used for
preprocessing.
-Most debug dumps can be enabled either passing a letter to the @option{-d}
-option, or with a long @option{-fdump-rtl} switch; here are the possible
-letters for use in @var{letters} and @var{pass}, and their meanings:
+Debug dumps can be enabled with a @option{-fdump-rtl} switch or some
+@option{-d} option @var{letters}. Here are the possible
+letters for use in @var{pass} and @var{letters}, and their meanings:
@table @gcctabopt
-@item -dA
-@opindex dA
-Annotate the assembler output with miscellaneous debugging information.
+
+@item -fdump-rtl-alignments
+@opindex fdump-rtl-alignments
+Dump after branch alignments have been computed.
+
+@item -fdump-rtl-asmcons
+@opindex fdump-rtl-asmcons
+Dump after fixing rtl statements that have unsatisfied in/out constraints.
+
+@item -fdump-rtl-auto_inc_dec
+@opindex fdump-rtl-auto_inc_dec
+Dump after auto-inc-dec discovery. This pass is only run on
+architectures that have auto inc or auto dec instructions.
+
+@item -fdump-rtl-barriers
+@opindex fdump-rtl-barriers
+Dump after cleaning up the barrier instructions.
+
+@item -fdump-rtl-bbpart
+@opindex fdump-rtl-bbpart
+Dump after partitioning hot and cold basic blocks.
@item -fdump-rtl-bbro
@opindex fdump-rtl-bbro
-Dump after block reordering, to @file{@var{file}.148r.bbro}.
+Dump after block reordering.
+
+@item -fdump-rtl-btl1
+@itemx -fdump-rtl-btl2
+@opindex fdump-rtl-btl2
+@opindex fdump-rtl-btl2
+@option{-fdump-rtl-btl1} and @option{-fdump-rtl-btl2} enable dumping
+after the two branch
+target load optimization passes.
+
+@item -fdump-rtl-bypass
+@opindex fdump-rtl-bypass
+Dump after jump bypassing and control flow optimizations.
@item -fdump-rtl-combine
@opindex fdump-rtl-combine
-Dump after the RTL instruction combination pass, to the file
-@file{@var{file}.129r.combine}.
+Dump after the RTL instruction combination pass.
+
+@item -fdump-rtl-compgotos
+@opindex fdump-rtl-compgotos
+Dump after dumplicating the computed gotos.
@item -fdump-rtl-ce1
@itemx -fdump-rtl-ce2
+@itemx -fdump-rtl-ce3
@opindex fdump-rtl-ce1
@opindex fdump-rtl-ce2
-@option{-fdump-rtl-ce1} enable dumping after the
-first if conversion, to the file @file{@var{file}.117r.ce1}.
-@option{-fdump-rtl-ce2} enable dumping after the second if
-conversion, to the file @file{@var{file}.130r.ce2}.
+@opindex fdump-rtl-ce3
+@option{-fdump-rtl-ce1}, @option{-fdump-rtl-ce2}, and
+@option{-fdump-rtl-ce3} enable dumping after the three
+if conversion passes.
+
+@itemx -fdump-rtl-cprop_hardreg
+@opindex fdump-rtl-cprop_hardreg
+Dump after hard register copy propagation.
+
+@itemx -fdump-rtl-csa
+@opindex fdump-rtl-csa
+Dump after combining stack adjustments.
+
+@item -fdump-rtl-cse1
+@itemx -fdump-rtl-cse2
+@opindex fdump-rtl-cse1
+@opindex fdump-rtl-cse2
+@option{-fdump-rtl-cse1} and @option{-fdump-rtl-cse2} enable dumping after
+the two common sub-expression elimination passes.
+
+@itemx -fdump-rtl-dce
+@opindex fdump-rtl-dce
+Dump after the standalone dead code elimination passes.
-@item -fdump-rtl-btl
@itemx -fdump-rtl-dbr
-@opindex fdump-rtl-btl
@opindex fdump-rtl-dbr
-@option{-fdump-rtl-btl} enable dumping after branch
-target load optimization, to @file{@var{file}.31.btl}.
-@option{-fdump-rtl-dbr} enable dumping after delayed branch
-scheduling, to @file{@var{file}.36.dbr}.
+Dump after delayed branch scheduling.
-@item -dD
-@opindex dD
-Dump all macro definitions, at the end of preprocessing, in addition to
-normal output.
-
-@item -fdump-rtl-ce3
-@opindex fdump-rtl-ce3
-Dump after the third if conversion, to @file{@var{file}.146r.ce3}.
-
-@item -fdump-rtl-cfg
-@itemx -fdump-rtl-life
-@opindex fdump-rtl-cfg
-@opindex fdump-rtl-life
-@option{-fdump-rtl-cfg} enable dumping after control
-and data flow analysis, to @file{@var{file}.116r.cfg}.
-@option{-fdump-rtl-cfg} enable dumping dump after life analysis,
-to @file{@var{file}.128r.life1} and @file{@var{file}.135r.life2}.
-
-@item -fdump-rtl-greg
-@opindex fdump-rtl-greg
-Dump after global register allocation, to @file{@var{file}.139r.greg}.
-
-@item -fdump-rtl-gcse
-@itemx -fdump-rtl-bypass
-@opindex fdump-rtl-gcse
-@opindex fdump-rtl-bypass
-@option{-fdump-rtl-gcse} enable dumping after GCSE, to
-@file{@var{file}.114r.gcse}. @option{-fdump-rtl-bypass}
-enable dumping after jump bypassing and control flow optimizations, to
-@file{@var{file}.115r.bypass}.
+@item -fdump-rtl-dce1
+@itemx -fdump-rtl-dce2
+@opindex fdump-rtl-dce1
+@opindex fdump-rtl-dce2
+@option{-fdump-rtl-dce1} and @option{-fdump-rtl-dce2} enable dumping after
+the two dead store elimination passes.
@item -fdump-rtl-eh
@opindex fdump-rtl-eh
-Dump after finalization of EH handling code, to @file{@var{file}.02.eh}.
+Dump after finalization of EH handling code.
-@item -fdump-rtl-sibling
-@opindex fdump-rtl-sibling
-Dump after sibling call optimizations, to @file{@var{file}.106r.sibling}.
+@item -fdump-rtl-eh_ranges
+@opindex fdump-rtl-eh_ranges
+Dump after conversion of EH handling range regions.
+
+@item -fdump-rtl-expand
+@opindex fdump-rtl-expand
+Dump after RTL generation.
+
+@item -fdump-rtl-fwprop1
+@itemx -fdump-rtl-fwprop2
+@opindex fdump-rtl-fwprop1
+@opindex fdump-rtl-fwprop2
+@option{-fdump-rtl-fwprop1} and @option{-fdump-rtl-fwprop2} enable
+dumping after the two forward propagation passes.
+
+@item -fdump-rtl-gcse1
+@itemx -fdump-rtl-gcse2
+@opindex fdump-rtl-gcse1
+@opindex fdump-rtl-gcse2
+@option{-fdump-rtl-gcse1} and @option{-fdump-rtl-gcse2} enable dumping
+after global common subexpression elimination.
+
+@item -fdump-rtl-init-regs
+@opindex fdump-rtl-init-regs
+Dump after the initialization of the registers.
+
+@item -fdump-rtl-initvals
+@opindex fdump-rtl-initvals
+Dump after the computation of the initial value sets.
+
+@itemx -fdump-rtl-into_cfglayout
+@opindex fdump-rtl-into_cfglayout
+Dump after converting to cfglayout mode.
+
+@item -fdump-rtl-ira
+@opindex fdump-rtl-ira
+Dump after iterated register allocation.
@item -fdump-rtl-jump
@opindex fdump-rtl-jump
-Dump after the first jump optimization, to @file{@var{file}.112r.jump}.
-
-@item -fdump-rtl-stack
-@opindex fdump-rtl-stack
-Dump after conversion from GCC's "flat register file" registers to the
-x87's stack-like registers, to @file{@var{file}.152r.stack}.
-
-@item -fdump-rtl-lreg
-@opindex fdump-rtl-lreg
-Dump after local register allocation, to @file{@var{file}.138r.lreg}.
+Dump after the second jump optimization.
@item -fdump-rtl-loop2
@opindex fdump-rtl-loop2
-@option{-dL} and @option{-fdump-rtl-loop2} enable dumping after the
-loop optimization pass, to @file{@var{file}.119r.loop2},
-@file{@var{file}.120r.loop2_init},
-@file{@var{file}.121r.loop2_invariant}, and
-@file{@var{file}.125r.loop2_done}.
-
-@item -fdump-rtl-sms
-@opindex fdump-rtl-sms
-Dump after modulo scheduling, to @file{@var{file}.136r.sms}.
+@option{-fdump-rtl-loop2} enables dumping after the rtl
+loop optimization passes.
@item -fdump-rtl-mach
@opindex fdump-rtl-mach
-Dump after performing the machine dependent reorganization pass, to
-@file{@var{file}.155r.mach} if that pass exists.
+Dump after performing the machine dependent reorganization pass, if that
+pass exists.
+
+@item -fdump-rtl-mode_sw
+@opindex fdump-rtl-mode_sw
+Dump after removing redundant mode switches.
@item -fdump-rtl-rnreg
@opindex fdump-rtl-rnreg
-Dump after register renumbering, to @file{@var{file}.147r.rnreg}.
+Dump after register renumbering.
-@item -fdump-rtl-regmove
-@opindex fdump-rtl-regmove
-Dump after the register move pass, to @file{@var{file}.132r.regmove}.
+@itemx -fdump-rtl-outof_cfglayout
+@opindex fdump-rtl-outof_cfglayout
+Dump after converting from cfglayout mode.
+
+@item -fdump-rtl-peephole2
+@opindex fdump-rtl-peephole2
+Dump after the peephole pass.
@item -fdump-rtl-postreload
@opindex fdump-rtl-postreload
-Dump after post-reload optimizations, to @file{@var{file}.24.postreload}.
+Dump after post-reload optimizations.
-@item -fdump-rtl-expand
-@opindex fdump-rtl-expand
-Dump after RTL generation, to @file{@var{file}.104r.expand}.
-
-@item -fdump-rtl-sched2
-@opindex fdump-rtl-sched2
-Dump after the second scheduling pass, to @file{@var{file}.149r.sched2}.
+@itemx -fdump-rtl-pro_and_epilogue
+@opindex fdump-rtl-pro_and_epilogue
+Dump after generating the function pro and epilogues.
-@item -fdump-rtl-cse
-@opindex fdump-rtl-cse
-Dump after CSE (including the jump optimization that sometimes follows
-CSE), to @file{@var{file}.113r.cse}.
+@item -fdump-rtl-regmove
+@opindex fdump-rtl-regmove
+Dump after the register move pass.
@item -fdump-rtl-sched1
+@itemx -fdump-rtl-sched2
@opindex fdump-rtl-sched1
-Dump after the first scheduling pass, to @file{@var{file}.136r.sched1}.
+@opindex fdump-rtl-sched2
+@option{-fdump-rtl-sched1} and @option{-fdump-rtl-sched2} enable dumping
+after the basic block scheduling passes.
-@item -fdump-rtl-cse2
-@opindex fdump-rtl-cse2
-Dump after the second CSE pass (including the jump optimization that
-sometimes follows CSE), to @file{@var{file}.127r.cse2}.
+@item -fdump-rtl-see
+@opindex fdump-rtl-see
+Dump after sign extension elimination.
-@item -fdump-rtl-tracer
-@opindex fdump-rtl-tracer
-Dump after running tracer, to @file{@var{file}.118r.tracer}.
+@item -fdump-rtl-seqabstr
+@opindex fdump-rtl-seqabstr
+Dump after common sequence discovery.
-@item -fdump-rtl-vpt
-@itemx -fdump-rtl-vartrack
-@opindex fdump-rtl-vpt
-@opindex fdump-rtl-vartrack
-@option{-fdump-rtl-vpt} enable dumping after the value
-profile transformations, to @file{@var{file}.10.vpt}.
-@option{-fdump-rtl-vartrack} enable dumping after variable tracking,
-to @file{@var{file}.154r.vartrack}.
+@item -fdump-rtl-shorten
+@opindex fdump-rtl-shorten
+Dump after shortening branches.
-@item -fdump-rtl-flow2
-@opindex fdump-rtl-flow2
-Dump after the second flow pass, to @file{@var{file}.142r.flow2}.
+@item -fdump-rtl-sibling
+@opindex fdump-rtl-sibling
+Dump after sibling call optimizations.
+
+@item -fdump-rtl-split1
+@itemx -fdump-rtl-split2
+@itemx -fdump-rtl-split3
+@itemx -fdump-rtl-split4
+@itemx -fdump-rtl-split5
+@opindex fdump-rtl-split1
+@opindex fdump-rtl-split2
+@opindex fdump-rtl-split3
+@opindex fdump-rtl-split4
+@opindex fdump-rtl-split5
+@option{-fdump-rtl-split1}, @option{-fdump-rtl-split2},
+@option{-fdump-rtl-split3}, @option{-fdump-rtl-split4} and
+@option{-fdump-rtl-split5} enable dumping after five rounds of
+instruction splitting.
-@item -fdump-rtl-peephole2
-@opindex fdump-rtl-peephole2
-Dump after the peephole pass, to @file{@var{file}.145r.peephole2}.
+@item -fdump-rtl-sms
+@opindex fdump-rtl-sms
+Dump after modulo scheduling. This pass is only run on some
+architectures.
+
+@item -fdump-rtl-stack
+@opindex fdump-rtl-stack
+Dump after conversion from GCC's "flat register file" registers to the
+x87's stack-like registers. This pass is only run on x86 variants.
+
+@item -fdump-rtl-subreg1
+@itemx -fdump-rtl-subreg2
+@opindex fdump-rtl-subreg1
+@opindex fdump-rtl-subreg2
+@option{-fdump-rtl-subreg1} and @option{-fdump-rtl-subreg2} enable dumping after
+the two subreg expansion passes.
+
+@item -fdump-rtl-unshare
+@opindex fdump-rtl-unshare
+Dump after all rtl has been unshared.
+
+@item -fdump-rtl-vartrack
+@opindex fdump-rtl-vartrack
+Dump after variable tracking.
+
+@item -fdump-rtl-vregs
+@opindex fdump-rtl-vregs
+Dump after converting virtual registers to hard registers.
@item -fdump-rtl-web
@opindex fdump-rtl-web
-Dump after live range splitting, to @file{@var{file}.126r.web}.
+Dump after live range splitting.
+
+@item -fdump-rtl-regclass
+@itemx -fdump-rtl-subregs_of_mode_init
+@itemx -fdump-rtl-subregs_of_mode_finish
+@itemx -fdump-rtl-dfinit
+@itemx -fdump-rtl-dfinish
+@opindex fdump-rtl-regclass
+@opindex fdump-rtl-subregs_of_mode_init
+@opindex fdump-rtl-subregs_of_mode_finish
+@opindex fdump-rtl-dfinit
+@opindex fdump-rtl-dfinish
+These dumps are defined but always produce empty files.
@item -fdump-rtl-all
@opindex fdump-rtl-all
Produce all the dumps listed above.
+@item -dA
+@opindex dA
+Annotate the assembler output with miscellaneous debugging information.
+
+@item -dD
+@opindex dD
+Dump all macro definitions, at the end of preprocessing, in addition to
+normal output.
+
@item -dH
@opindex dH
Produce a core dump whenever an error occurs.
@item -dv
@opindex dv
-For each of the other indicated dump files (either with @option{-d} or
-@option{-fdump-rtl-@var{pass}}), dump a representation of the control flow
-graph suitable for viewing with VCG to @file{@var{file}.@var{pass}.vcg}.
+For each of the other indicated dump files (@option{-fdump-rtl-@var{pass}}),
+dump a representation of the control flow graph suitable for viewing with VCG
+to @file{@var{file}.@var{pass}.vcg}.
@item -dx
@opindex dx
Just generate RTL for a function instead of compiling it. Usually used
-with @samp{r} (@option{-fdump-rtl-expand}).
+with @option{-fdump-rtl-expand}.
@item -dy
@opindex dy
@item -fdump-noaddr
@opindex fdump-noaddr
-When doing debugging dumps (see @option{-d} option above), suppress
-address output. This makes it more feasible to use diff on debugging
-dumps for compiler invocations with different compiler binaries and/or
-different text / bss / data / heap / stack / dso start locations.
+When doing debugging dumps, suppress address output. This makes it more
+feasible to use diff on debugging dumps for compiler invocations with
+different compiler binaries and/or different
+text / bss / data / heap / stack / dso start locations.
@item -fdump-unnumbered
@opindex fdump-unnumbered
-When doing debugging dumps (see @option{-d} option above), suppress instruction
-numbers and address output. This makes it more feasible to
-use diff on debugging dumps for compiler invocations with different
-options, in particular with and without @option{-g}.
+When doing debugging dumps, suppress instruction numbers and address output.
+This makes it more feasible to use diff on debugging dumps for compiler
+invocations with different options, in particular with and without
+@option{-g}.
@item -fdump-translation-unit @r{(C++ only)}
@itemx -fdump-translation-unit-@var{options} @r{(C++ only)}
@opindex fsched-verbose
On targets that use instruction scheduling, this option controls the
amount of debugging output the scheduler prints. This information is
-written to standard error, unless @option{-dS} or @option{-dR} is
-specified, in which case it is output to the usual dump
-listing file, @file{.sched} or @file{.sched2} respectively. However
-for @var{n} greater than nine, the output is always printed to standard
-error.
+written to standard error, unless @option{-fdump-rtl-sched1} or
+@option{-fdump-rtl-sched2} is specified, in which case it is output
+to the usual dump listing file, @file{.sched} or @file{.sched2}
+respectively. However for @var{n} greater than nine, the output is
+always printed to standard error.
For @var{n} greater than zero, @option{-fsched-verbose} outputs the
-same information as @option{-dRS}. For @var{n} greater than one, it
-also output basic block probabilities, detailed ready list information
-and unit/insn info. For @var{n} greater than two, it includes RTL
-at abort point, control-flow and regions info. And for @var{n} over
-four, @option{-fsched-verbose} also includes dependence info.
+same information as @option{-fdump-rtl-sched1} and @option{-fdump-rtl-sched2}.
+For @var{n} greater than one, it also output basic block probabilities,
+detailed ready list information and unit/insn info. For @var{n} greater
+than two, it includes RTL at abort point, control-flow and regions info.
+And for @var{n} over four, @option{-fsched-verbose} also includes
+dependence info.
@item -save-temps
@opindex save-temps
@opindex print-sysroot
Print the target sysroot directory that will be used during
compilation. This is the target sysroot specified either at configure
-time or or using the @option{--sysroot} option, possibly with an extra
+time or using the @option{--sysroot} option, possibly with an extra
suffix that depends on compilation options. If no target sysroot is
specified, the option prints nothing.
@item -O2
@opindex O2
Optimize even more. GCC performs nearly all supported optimizations
-that do not involve a space-speed tradeoff. The compiler does not
-perform loop unrolling or function inlining when you specify @option{-O2}.
+that do not involve a space-speed tradeoff.
As compared to @option{-O}, this option increases both compilation time
and the performance of the generated code.
This option implies @option{-fmerge-constants}. In addition to
@option{-fmerge-constants} this considers e.g.@: even constant initialized
arrays or initialized constant variables with integral or floating point
-types. Languages like C or C++ require each non-automatic variable to
-have distinct location, so using this option will result in non-conforming
+types. Languages like C or C++ require each variable, including multiple
+instances of the same variable in recursive calls, to have distinct locations,
+so using this option will result in non-conforming
behavior.
@item -fmodulo-sched
Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}.
+@item -fira-algorithm=@var{algorithm}
+Use specified coloring algorithm for the integrated register
+allocator. The @var{algorithm} argument should be @code{priority} or
+@code{CB}. The first algorithm specifies Chow's priority coloring,
+the second one specifies Chaitin-Briggs coloring. The second
+algorithm can be unimplemented for some architectures. If it is
+implemented, it is the default because Chaitin-Briggs coloring as a
+rule generates a better code.
+
+@item -fira-region=@var{region}
+Use specified regions for the integrated register allocator. The
+@var{region} argument should be one of @code{all}, @code{mixed}, or
+@code{one}. The first value means using all loops as register
+allocation regions, the second value which is the default means using
+all loops except for loops with small register pressure as the
+regions, and third one means using all function as a single region.
+The first value can give best result for machines with small size and
+irregular register set, the third one results in faster and generates
+decent code and the smallest size code, and the default value usually
+give the best results in most cases and for most architectures.
+
+@item -fira-coalesce
+@opindex fira-coalesce
+Do optimistic register coalescing. This option might be profitable for
+architectures with big regular register files.
+
+@item -fno-ira-share-save-slots
+@opindex fno-ira-share-save-slots
+Switch off sharing stack slots used for saving call used hard
+registers living through a call. Each hard register will get a
+separate stack slot and as a result function stack frame will be
+bigger.
+
+@item -fno-ira-share-spill-slots
+@opindex fno-ira-share-spill-slots
+Switch off sharing stack slots allocated for pseudo-registers. Each
+pseudo-register which did not get a hard register will get a separate
+stack slot and as a result function stack frame will be bigger.
+
+@item -fira-verbose=@var{n}
+@opindex fira-verbose
+Set up how verbose dump file for the integrated register allocator
+will be. Default value is 5. If the value is greater or equal to 10,
+the dump file will be stderr as if the value were @var{n} minus 10.
+
@item -fdelayed-branch
@opindex fdelayed-branch
If supported for the target machine, attempt to reorder instructions
was modulo scheduled we may want to prevent the later scheduling passes
from changing its schedule, we use this option to control that.
+@item -fselective-scheduling
+@opindex fselective-scheduling
+Schedule instructions using selective scheduling algorithm. Selective
+scheduling runs instead of the first scheduler pass.
+
+@item -fselective-scheduling2
+@opindex fselective-scheduling2
+Schedule instructions using selective scheduling algorithm. Selective
+scheduling runs instead of the second scheduler pass.
+
+@item -fsel-sched-pipelining
+@opindex fsel-sched-pipelining
+Enable software pipelining of innermost loops during selective scheduling.
+This option has no effect until one of @option{-fselective-scheduling} or
+@option{-fselective-scheduling2} is turned on.
+
+@item -fsel-sched-pipelining-outer-loops
+@opindex fsel-sched-pipelining-outer-loops
+When pipelining loops during selective scheduling, also pipeline outer loops.
+This option has no effect until @option{-fsel-sched-pipelining} is turned on.
+
@item -fcaller-saves
@opindex fcaller-saves
Enable values to be allocated in registers that will be clobbered by
Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}.
+@item -fconserve-stack
+@opindex fconserve-stack
+Attempt to minimize stack usage. The compiler will attempt to use less
+stack space, even if that makes the program slower. This option
+implies setting the @option{large-stack-frame} parameter to 100
+and the @option{large-stack-frame-growth} parameter to 400.
+
@item -ftree-reassoc
@opindex ftree-reassoc
Perform reassociation on trees. This flag is enabled by default
This optimization analyzes the program to determine when values passed
to functions are constants and then optimizes accordingly.
This optimization can substantially increase performance
-if the application has constants passed to functions, but
-because this optimization can create multiple copies of functions,
-it may significantly increase code size.
+if the application has constants passed to functions.
+This flag is enabled by default at @option{-O2}, @option{-Os} and @option{-O3}.
+
+@item -fipa-cp-clone
+@opindex fipa-cp-clone
+Perform function cloning to make interprocedural constant propagation stronger.
+When enabled, interprocedural constant propagation will perform function cloning
+when externally visible function can be called with constant arguments.
+Because this optimization can create multiple copies of functions,
+it may significantly increase code size
+(see @option{--param ipcp-unit-growth=@var{value}}).
+This flag is enabled by default at @option{-O3}.
@item -fipa-matrix-reorg
@opindex fipa-matrix-reorg
of the matrix. The second optimization is matrix transposing that
attemps to change the order of the matrix's dimensions in order to
improve cache locality.
-Both optimizations need fwhole-program flag.
-Transposing is enabled only if profiling information is avaliable.
+Both optimizations need the @option{-fwhole-program} flag.
+Transposing is enabled only if profiling information is available.
@item -ftree-sink
pass only operates on local scalar variables and is enabled by default
at @option{-O} and higher.
-@item -ftree-store-ccp
-@opindex ftree-store-ccp
-Perform sparse conditional constant propagation (CCP) on trees. This
-pass operates on both local scalar variables and memory stores and
-loads (global variables, structures, arrays, etc). This flag is
-enabled by default at @option{-O2} and higher.
-
@item -ftree-switch-conversion
Perform conversion of simple initializations in a switch to
initializations from a scalar array. This flag is enabled by default
Perform linear loop transformations on tree. This flag can improve cache
performance and allow further loop optimizations to take place.
+@item -floop-interchange
+Perform loop interchange transformations on loops. Interchanging two
+nested loops switches the inner and outer loops. For example, given a
+loop like:
+@smallexample
+DO J = 1, M
+ DO I = 1, N
+ A(J, I) = A(J, I) * C
+ ENDDO
+ENDDO
+@end smallexample
+loop interchange will transform the loop as if the user had written:
+@smallexample
+DO I = 1, N
+ DO J = 1, M
+ A(J, I) = A(J, I) * C
+ ENDDO
+ENDDO
+@end smallexample
+which can be beneficial when @code{N} is larger than the caches,
+because in Fortran, the elements of an array are stored in memory
+contiguously by column, and the original loop iterates over rows,
+potentially creating at each access a cache miss. This optimization
+applies to all the languages supported by GCC and is not limited to
+Fortran.
+
+@item -floop-strip-mine
+Perform loop strip mining transformations on loops. Strip mining
+splits a loop into two nested loops. The outer loop has strides
+equal to the strip size and the inner loop has strides of the
+original loop within a strip. For example, given a loop like:
+@smallexample
+DO I = 1, N
+ A(I) = A(I) + C
+ENDDO
+@end smallexample
+loop strip mining will transform the loop as if the user had written:
+@smallexample
+DO II = 1, N, 4
+ DO I = II, min (II + 3, N)
+ A(I) = A(I) + C
+ ENDDO
+ENDDO
+@end smallexample
+This optimization applies to all the languages supported by GCC and is
+not limited to Fortran.
+
+@item -floop-block
+Perform loop blocking transformations on loops. Blocking strip mines
+each loop in the loop nest such that the memory accesses of the
+element loops fit inside caches. For example, given a loop like:
+@smallexample
+DO I = 1, N
+ DO J = 1, M
+ A(J, I) = B(I) + C(J)
+ ENDDO
+ENDDO
+@end smallexample
+loop blocking will transform the loop as if the user had written:
+@smallexample
+DO II = 1, N, 64
+ DO JJ = 1, M, 64
+ DO I = II, min (II + 63, N)
+ DO J = JJ, min (JJ + 63, M)
+ A(J, I) = B(I) + C(J)
+ ENDDO
+ ENDDO
+ ENDDO
+ENDDO
+@end smallexample
+which can be beneficial when @code{M} is larger than the caches,
+because the innermost loop will iterate over a smaller amount of data
+that can be kept in the caches. This optimization applies to all the
+languages supported by GCC and is not limited to Fortran.
+
@item -fcheck-data-deps
@opindex fcheck-data-deps
Compare the results of several data dependence analyzers. This option
Enabled at levels @option{-O}, @option{-O2}, @option{-O3}, @option{-Os}.
+@item -fprofile-correction
+@opindex fprofile-correction
+Profiles collected using an instrumented binary for multi-threaded programs may
+be inconsistent due to missed counter updates. When this option is specified,
+GCC will use heuristics to correct or smooth out such inconsistencies. By
+default, GCC will emit an error message when an inconsistent profile is detected.
+
@item -fprofile-dir=@var{path}
@opindex fprofile-dir
The following options are enabled: @code{-fprofile-arcs}, @code{-fprofile-values}, @code{-fvpt}.
If @var{path} is specified, GCC will look at the @var{path} to find
-the profile feeedback data files. See @option{-fprofile-dir}.
+the profile feedback data files. See @option{-fprofile-dir}.
@item -fprofile-use
@itemx -fprofile-use=@var{path}
parameter, then structure reorganization is not applied to this structure.
The default is 10.
+@item predictable-branch-cost-outcome
+When branch is predicted to be taken with probability lower than this threshold
+(in percent), then it is considered well predictable. The default is 10.
+
@item max-crossjump-edges
The maximum number of incoming edges to consider for crossjumping.
The algorithm used by @option{-fcrossjumping} is @math{O(N^2)} in
@item large-function-insns
The limit specifying really large functions. For functions larger than this
-limit after inlining inlining is constrained by
+limit after inlining, inlining is constrained by
@option{--param large-function-growth}. This parameter is useful primarily
to avoid extreme compilation time caused by non-linear algorithms used by the
backend.
The default value is 30 which limits unit growth to 1.3 times the original
size.
+@item ipcp-unit-growth
+Specifies maximal overall growth of the compilation unit caused by
+interprocedural constant propagation. The default value is 10 which limits
+unit growth to 1.1 times the original size.
+
@item large-stack-frame
The limit specifying large stack frames. While inlining the algorithm is trying
to not grow past this limit too much. Default value is 256 bytes.
The maximum number of blocks in a region to be considered for
interblock scheduling. The default value is 10.
+@item max-pipeline-region-blocks
+The maximum number of blocks in a region to be considered for
+pipelining in the selective scheduler. The default value is 15.
+
@item max-sched-region-insns
The maximum number of insns in a region to be considered for
interblock scheduling. The default value is 100.
+@item max-pipeline-region-insns
+The maximum number of insns in a region to be considered for
+pipelining in the selective scheduler. The default value is 200.
+
@item min-spec-prob
The minimum probability (in percents) of reaching a source block
for interblock speculative scheduling. The default value is 40.
speculative insn will be scheduled.
The default value is 40.
-@item max-last-value-rtl
+@item sched-mem-true-dep-cost
+Minimal distance (in CPU cycles) between store and load targeting same
+memory locations. The default value is 1.
+
+@item selsched-max-lookahead
+The maximum size of the lookahead window of selective scheduling. It is a
+depth of search for available instructions.
+The default value is 50.
+
+@item selsched-max-sched-times
+The maximum number of times that an instruction will be scheduled during
+selective scheduling. This is the limit on the number of iterations
+through which the instruction may be pipelined. The default value is 2.
+
+@item selsched-max-insns-to-rename
+The maximum number of best instructions in the ready list that are considered
+for renaming in the selective scheduler. The default value is 2.
+@item max-last-value-rtl
The maximum size measured as number of RTLs that can be recorded in an expression
in combiner for a pseudo register as last known value of that register. The default
is 10000.
the enhanced partial redundancy elimination optimization can run away,
consuming all of the memory available on the host machine. This
parameter sets a limit on the length of the sets that are computed,
-which prevents the runaway behaviour. Setting a value of 0 for
-this paramter will allow an unlimited set length.
+which prevents the runaway behavior. Setting a value of 0 for
+this parameter will allow an unlimited set length.
@item sccvn-max-scc-size
Maximum size of a strongly connected component (SCC) during SCCVN
function will not be done and optimizations depending on it will
be disabled. The default maximum SCC size is 10000.
+@item ira-max-loops-num
+IRA uses a regional register allocation by default. If a function
+contains loops more than number given by the parameter, only at most
+given number of the most frequently executed loops will form regions
+for the regional register allocation. The default value of the
+parameter is 100.
+
+@item ira-max-conflict-table-size
+Although IRA uses a sophisticated algorithm of compression conflict
+table, the table can be still big for huge functions. If the conflict
+table for a function could be more than size in MB given by the
+parameter, the conflict table is not built and faster, simpler, and
+lower quality register allocation algorithm will be used. The
+algorithm do not use pseudo-register conflicts. The default value of
+the parameter is 2000.
+
+@item loop-invariant-max-bbs-in-loop
+Loop invariant motion can be very expensive, both in compile time and
+in amount of needed compile time memory, with very large loops. Loops
+with more basic blocks than this parameter won't have loop invariant
+motion optimization performed on them. The default value of the
+parameter is 1000 for -O1 and 10000 for -O2 and above.
+
@end table
@end table
option @samp{-Xlinker -z -Xlinker defs}). Only a few systems support
this option.
+@item -T @var{script}
+@opindex T
+@cindex linker script
+Use @var{script} as the linker script. This option is supported by most
+systems using the GNU linker. On some targets, such as bare-board
+targets without an operating system, the @option{-T} option may be required
+when linking to avoid references to undefined symbols.
+
@item -Xlinker @var{option}
@opindex Xlinker
Pass @var{option} as an option to the linker. You can use this to
supply system-specific linker options which GCC does not know how to
recognize.
-If you want to pass an option that takes an argument, you must use
+If you want to pass an option that takes a separate argument, you must use
@option{-Xlinker} twice, once for the option and once for the argument.
For example, to pass @option{-assert definitions}, you must write
@samp{-Xlinker -assert -Xlinker definitions}. It does not work to write
@option{-Xlinker "-assert definitions"}, because this passes the entire
string as a single argument, which is not what the linker expects.
+When using the GNU linker, it is usually more convenient to pass
+arguments to linker options using the @option{@var{option}=@var{value}}
+syntax than as separate arguments. For example, you can specify
+@samp{-Xlinker -Map=output.map} rather than
+@samp{-Xlinker -Map -Xlinker output.map}. Other linkers may not support
+this syntax for command-line options.
+
@item -Wl,@var{option}
@opindex Wl
Pass @var{option} as an option to the linker. If @var{option} contains
-commas, it is split into multiple options at the commas.
+commas, it is split into multiple options at the commas. You can use this
+syntax to pass an argument to the option.
+For example, @samp{-Wl,-Map,output.map} passes @samp{-Map output.map} to the
+linker. When using the GNU linker, you can also get the same effect with
+@samp{-Wl,-Map=output.map}.
@item -u @var{symbol}
@opindex u
arm-elf}, meaning to compile for an arm processor with elf binaries,
then you would specify @option{-b arm-elf} to run that cross compiler.
Because there are other options beginning with @option{-b}, the
-configuration must contain a hyphen.
+configuration must contain a hyphen, or @option{-b} alone should be one
+argument followed by the configuration in the next argument.
@item -V @var{version}
@opindex V
* MMIX Options::
* MN10300 Options::
* PDP-11 Options::
+* picoChip Options::
* PowerPC Options::
* RS/6000 and PowerPC Options::
* S/390 and zSeries Options::
by default. This can be overridden with the @code{section} attribute.
@xref{Variable Attributes}.
+@item -mfix-cortex-m3-ldrd
+@opindex mfix-cortex-m3-ldrd
+Some Cortex-M3 cores can cause data corruption when @code{ldrd} instructions
+with overlapping destination and base registers are used. This option avoids
+generating these instructions. This option is enabled by default when
+@option{-mcpu=cortex-m3} is specified.
+
@end table
@node ARM Options
locate the start if functions inside an executable piece of code. The
default is @option{-msched-prolog}.
+@item -mfloat-abi=@var{name}
+@opindex mfloat-abi
+Specifies which floating-point ABI to use. Permissible values
+are: @samp{soft}, @samp{softfp} and @samp{hard}.
+
+Specifying @samp{soft} causes GCC to generate output containing
+library calls for floating-point operations.
+@samp{softfp} allows the generation of code using hardware floating-point
+instructions, but still uses the soft-float calling conventions.
+@samp{hard} allows generation of floating-point instructions
+and uses FPU-specific calling conventions.
+
+Using @option{-mfloat-abi=hard} with VFP coprocessors is not supported.
+Use @option{-mfloat-abi=softfp} with the appropriate @option{-mfpu} option
+to allow the compiler to generate code that makes use of the hardware
+floating-point capabilities for these CPUs.
+
+The default depends on the specific target configuration. Note that
+the hard-float and soft-float ABIs are not link-compatible; you must
+compile your entire program with the same ABI, and link with a
+compatible set of libraries.
+
@item -mhard-float
@opindex mhard-float
-Generate output containing floating point instructions. This is the
-default.
+Equivalent to @option{-mfloat-abi=hard}.
@item -msoft-float
@opindex msoft-float
-Generate output containing library calls for floating point.
-@strong{Warning:} the requisite libraries are not available for all ARM
-targets. Normally the facilities of the machine's usual C compiler are
-used, but this cannot be done directly in cross-compilation. You must make
-your own arrangements to provide suitable library functions for
-cross-compilation.
-
-@option{-msoft-float} changes the calling convention in the output file;
-therefore, it is only useful if you compile @emph{all} of a program with
-this option. In particular, you need to compile @file{libgcc.a}, the
-library that comes with GCC, with @option{-msoft-float} in order for
-this to work.
-
-@item -mfloat-abi=@var{name}
-@opindex mfloat-abi
-Specifies which ABI to use for floating point values. Permissible values
-are: @samp{soft}, @samp{softfp} and @samp{hard}.
-
-@samp{soft} and @samp{hard} are equivalent to @option{-msoft-float}
-and @option{-mhard-float} respectively. @samp{softfp} allows the generation
-of floating point instructions, but still uses the soft-float calling
-conventions.
+Equivalent to @option{-mfloat-abi=soft}.
@item -mlittle-endian
@opindex mlittle-endian
@samp{arm620}, @samp{arm7}, @samp{arm7m}, @samp{arm7d}, @samp{arm7dm},
@samp{arm7di}, @samp{arm7dmi}, @samp{arm70}, @samp{arm700},
@samp{arm700i}, @samp{arm710}, @samp{arm710c}, @samp{arm7100},
+@samp{arm720},
@samp{arm7500}, @samp{arm7500fe}, @samp{arm7tdmi}, @samp{arm7tdmi-s},
-@samp{arm8}, @samp{strongarm}, @samp{strongarm110}, @samp{strongarm1100},
+@samp{arm710t}, @samp{arm720t}, @samp{arm740t},
+@samp{strongarm}, @samp{strongarm110}, @samp{strongarm1100},
+@samp{strongarm1110},
@samp{arm8}, @samp{arm810}, @samp{arm9}, @samp{arm9e}, @samp{arm920},
@samp{arm920t}, @samp{arm922t}, @samp{arm946e-s}, @samp{arm966e-s},
@samp{arm968e-s}, @samp{arm926ej-s}, @samp{arm940t}, @samp{arm9tdmi},
@samp{arm10e}, @samp{arm1020e}, @samp{arm1022e},
@samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
@samp{arm1156t2-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
-@samp{cortex-a8}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m3},
+@samp{cortex-a8}, @samp{cortex-a9},
+@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m3},
@samp{cortex-m1},
-@samp{xscale}, @samp{iwmmxt}, @samp{ep9312}.
+@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
@item -mtune=@var{name}
@opindex mtune
assembly code. This option can be used in conjunction with or instead
of the @option{-mcpu=} option. Permissible names are: @samp{armv2},
@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t},
-@samp{armv5}, @samp{armv5t}, @samp{armv5te}, @samp{armv6}, @samp{armv6j},
+@samp{armv5}, @samp{armv5t}, @samp{armv5e}, @samp{armv5te},
+@samp{armv6}, @samp{armv6j},
@samp{armv6t2}, @samp{armv6z}, @samp{armv6zk}, @samp{armv6-m},
@samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m},
-@samp{iwmmxt}, @samp{ep9312}.
+@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
@item -mfpu=@var{name}
@itemx -mfpe=@var{number}
best available method for the selected processor. The default setting is
@option{auto}.
+@item -mword-relocations
+@opindex mword-relocations
+Only generate absolute relocations on word sized values (i.e. R_ARM_ABS32).
+This is enabled by default on targets (uClinux, SymbianOS) where the runtime
+loader imposes this restriction, and when @option{-fpic} or @option{-fPIC}
+is specified.
+
@end table
@node AVR Options
@item -mcpu=@var{cpu}@r{[}-@var{sirevision}@r{]}
@opindex mcpu=
Specifies the name of the target Blackfin processor. Currently, @var{cpu}
-can be one of @samp{bf522}, @samp{bf523}, @samp{bf524},
-@samp{bf525}, @samp{bf526}, @samp{bf527},
-@samp{bf531}, @samp{bf532}, @samp{bf533}, @samp{bf534},
-@samp{bf536}, @samp{bf537}, @samp{bf538}, @samp{bf539},
+can be one of @samp{bf512}, @samp{bf514}, @samp{bf516}, @samp{bf518},
+@samp{bf522}, @samp{bf523}, @samp{bf524}, @samp{bf525}, @samp{bf526},
+@samp{bf527}, @samp{bf531}, @samp{bf532}, @samp{bf533},
+@samp{bf534}, @samp{bf536}, @samp{bf537}, @samp{bf538}, @samp{bf539},
@samp{bf542}, @samp{bf544}, @samp{bf547}, @samp{bf548}, @samp{bf549},
@samp{bf561}.
The optional @var{sirevision} specifies the silicon revision of the target
link scripts will be used to put the application into SDRAM.
Loader should initialize SDRAM before loading the application
into SDRAM. This option defines @code{__BFIN_SDRAM}.
+
+@item -micplb
+@opindex micplb
+Assume that ICPLBs are enabled at runtime. This has an effect on certain
+anomaly workarounds. For Linux targets, the default is to assume ICPLBs
+are enabled; for standalone applications the default is off.
@end table
@node CRIS Options
@code{long double} will be modified. Hence they will not be binary
compatible with arrays or structures in code compiled without that switch.
-@item -mmlarge-data-threshold=@var{number}
+@item -mlarge-data-threshold=@var{number}
@opindex mlarge-data-threshold=@var{number}
When @option{-mcmodel=medium} is specified, the data greater than
@var{threshold} are placed in large data section. This value must be the
Set 80387 floating-point precision to 32, 64 or 80 bits. When @option{-mpc32}
is specified, the significands of results of floating-point operations are
-rounded to 24 bits (single precision); @option{-mpc64} rounds the the
+rounded to 24 bits (single precision); @option{-mpc64} rounds the
significands of results of floating-point operations to 53 bits (double
precision) and @option{-mpc80} rounds the significands of results of
floating-point operations to 64 bits (extended double precision), which is
@itemx -mno-sse4.2
@itemx -msse4
@itemx -mno-sse4
+@itemx -mavx
+@itemx -mno-avx
@itemx -maes
@itemx -mno-aes
@itemx -mpclmul
@opindex m3dnow
@opindex mno-3dnow
These switches enable or disable the use of instructions in the MMX,
-SSE, SSE2, SSE3, SSSE3, SSE4.1, AES, PCLMUL, SSE4A, SSE5, ABM or
+SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AES, PCLMUL, SSE4A, SSE5, ABM or
3DNow!@: extended instruction sets.
These extensions are also available as built-in functions: see
@ref{X86 Built-in Functions}, for details of the functions enabled and
To have SSE/SSE2 instructions generated automatically from floating-point
code (as opposed to 387 instructions), see @option{-mfpmath=sse}.
+GCC depresses SSEx instructions when @option{-mavx} is used. Instead, it
+generates new AVX instructions or AVX equivalence for all SSEx instructions
+when needed.
+
These options will enable GCC to use these extended instructions in
generated code, even without @option{-mfpmath=sse}. Applications which
perform runtime CPU detection must compile separate files for each
if the ISA supports such instructions. The -mfused-madd option is on by
default. The fused multiply-add instructions have a different
rounding behavior compared to executing a multiply followed by an add.
+
+@item -msse2avx
+@itemx -mno-sse2avx
+@opindex msse2avx
+Specify that the assembler should encode SSE instructions with VEX
+prefix. The option @option{-mavx} turns this on by default.
@end table
These @samp{-m} switches are supported in addition to the above
@item -mcmodel=medium
@opindex mcmodel=medium
Generate code for the medium model: The program is linked in the lower 2
-GB of the address space but symbols can be located anywhere in the
-address space. Programs can be statically or dynamically linked, but
-building of shared libraries are not supported with the medium model.
+GB of the address space. Small symbols are also placed there. Symbols
+with sizes larger than @option{-mlarge-data-threshold} are put into
+large data or bss sections and can be located above 2GB. Programs can
+be statically or dynamically linked.
@item -mcmodel=large
@opindex mcmodel=large
@samp{74kc}, @samp{74kf2_1}, @samp{74kf1_1}, @samp{74kf3_2},
@samp{loongson2e}, @samp{loongson2f},
@samp{m4k},
+@samp{octeon},
@samp{orion},
@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
@samp{r4600}, @samp{r4650}, @samp{r6000}, @samp{r8000},
@samp{rm7000}, @samp{rm9000},
+@samp{r10000}, @samp{r12000}, @samp{r14000}, @samp{r16000},
@samp{sb1},
@samp{sr71000},
@samp{vr4100}, @samp{vr4111}, @samp{vr4120}, @samp{vr4130}, @samp{vr4300},
@option{-mshared} is the default.
+@item -mplt
+@itemx -mno-plt
+@opindex mplt
+@opindex mno-plt
+Assume (do not assume) that the static and dynamic linkers
+support PLTs and copy relocations. This option only affects
+@samp{-mno-shared -mabicalls}. For the n64 ABI, this option
+has no effect without @samp{-msym32}.
+
+You can make @option{-mplt} the default by configuring
+GCC with @option{--with-mips-plt}. The default is
+@option{-mno-plt} otherwise.
+
@item -mxgot
@itemx -mno-xgot
@opindex mxgot
immediately after starting an integer division.
@end itemize
+@item -mfix-r10000
+@itemx -mno-fix-r10000
+@opindex mfix-r10000
+@opindex mno-fix-r10000
+Work around certain R10000 errata:
+@itemize @minus
+@item
+@code{ll}/@code{sc} sequences may not behave atomically on revisions
+prior to 3.0. They may deadlock on revisions 2.6 and earlier.
+@end itemize
+
+This option can only be used if the target architecture supports
+branch-likely instructions. @option{-mfix-r10000} is the default when
+@option{-march=r10000} is used; @option{-mno-fix-r10000} is the default
+otherwise.
+
@item -mfix-vr4120
@itemx -mno-fix-vr4120
@opindex mfix-vr4120
(This flag currently works around the SB-1 revision 2
``F1'' and ``F2'' floating point errata.)
+@item -mr10k-cache-barrier=@var{setting}
+@opindex mr10k-cache-barrier
+Specify whether GCC should insert cache barriers to avoid the
+side-effects of speculation on R10K processors.
+
+In common with many processors, the R10K tries to predict the outcome
+of a conditional branch and speculatively executes instructions from
+the ``taken'' branch. It later aborts these instructions if the
+predicted outcome was wrong. However, on the R10K, even aborted
+instructions can have side effects.
+
+This problem only affects kernel stores and, depending on the system,
+kernel loads. As an example, a speculatively-executed store may load
+the target memory into cache and mark the cache line as dirty, even if
+the store itself is later aborted. If a DMA operation writes to the
+same area of memory before the ``dirty'' line is flushed, the cached
+data will overwrite the DMA-ed data. See the R10K processor manual
+for a full description, including other potential problems.
+
+One workaround is to insert cache barrier instructions before every memory
+access that might be speculatively executed and that might have side
+effects even if aborted. @option{-mr10k-cache-barrier=@var{setting}}
+controls GCC's implementation of this workaround. It assumes that
+aborted accesses to any byte in the following regions will not have
+side effects:
+
+@enumerate
+@item
+the memory occupied by the current function's stack frame;
+
+@item
+the memory occupied by an incoming stack argument;
+
+@item
+the memory occupied by an object with a link-time-constant address.
+@end enumerate
+
+It is the kernel's responsibility to ensure that speculative
+accesses to these regions are indeed safe.
+
+If the input program contains a function declaration such as:
+
+@smallexample
+void foo (void);
+@end smallexample
+
+then the implementation of @code{foo} must allow @code{j foo} and
+@code{jal foo} to be executed speculatively. GCC honors this
+restriction for functions it compiles itself. It expects non-GCC
+functions (such as hand-written assembly code) to do the same.
+
+The option has three forms:
+
+@table @gcctabopt
+@item -mr10k-cache-barrier=load-store
+Insert a cache barrier before a load or store that might be
+speculatively executed and that might have side effects even
+if aborted.
+
+@item -mr10k-cache-barrier=store
+Insert a cache barrier before a store that might be speculatively
+executed and that might have side effects even if aborted.
+
+@item -mr10k-cache-barrier=none
+Disable the insertion of cache barriers. This is the default setting.
+@end table
+
@item -mflush-func=@var{func}
@itemx -mno-flush-func
@opindex mflush-func
PDP-11 target other than @samp{pdp11-*-bsd}.
@end table
+@node picoChip Options
+@subsection picoChip Options
+@cindex picoChip options
+
+These @samp{-m} options are defined for picoChip implementations:
+
+@table @gcctabopt
+
+@item -mae=@var{ae_type}
+@opindex mcpu
+Set the instruction set, register set, and instruction scheduling
+parameters for array element type @var{ae_type}. Supported values
+for @var{ae_type} are @samp{ANY}, @samp{MUL}, and @samp{MAC}.
+
+@option{-mae=ANY} selects a completely generic AE type. Code
+generated with this option will run on any of the other AE types. The
+code will not be as efficient as it would be if compiled for a specific
+AE type, and some types of operation (e.g., multiplication) will not
+work properly on all types of AE.
+
+@option{-mae=MUL} selects a MUL AE type. This is the most useful AE type
+for compiled code, and is the default.
+
+@option{-mae=MAC} selects a DSP-style MAC AE. Code compiled with this
+option may suffer from poor performance of byte (char) manipulation,
+since the DSP AE does not provide hardware support for byte load/stores.
+
+@item -msymbol-as-address
+Enable the compiler to directly use a symbol name as an address in a
+load/store instruction, without first loading it into a
+register. Typically, the use of this option will generate larger
+programs, which run faster than when the option isn't used. However, the
+results vary from program to program, so it is left as a user option,
+rather than being permanently enabled.
+
+@item -mno-inefficient-warnings
+Disables warnings about the generation of inefficient code. These
+warnings can be generated, for example, when compiling code which
+performs byte-level memory operations on the MAC AE type. The MAC AE has
+no hardware support for byte-level memory operations, so all byte
+load/stores must be synthesized from word load/store operations. This is
+inefficient and a warning will be generated indicating to the programmer
+that they should rewrite the code to avoid byte operations, or to target
+an AE type which has the necessary hardware support. This option enables
+the warning to be turned off.
+
+@end table
+
@node PowerPC Options
@subsection PowerPC Options
@cindex PowerPC options
@gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol
-mnew-mnemonics -mpopcntb -mpower -mpower2 -mpowerpc64 @gol
--mpowerpc-gpopt -mpowerpc-gfxopt -mstring -mmulhw -mdlmzb -mmfpgpr}
+-mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol
+-msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr}
The particular options set for any particular CPU will vary between
compiler versions, depending on what setting seems to produce optimal
@opindex mno-vrsave
Generate VRSAVE instructions when generating AltiVec code.
+@item -mgen-cell-microcode
+@opindex mgen-cell-microcode
+Generate Cell microcode instructions
+
+@item -mwarn-cell-microcode
+@opindex mwarn-cell-microcode
+Warning when a Cell microcode instruction is going to emitted. An example
+of a Cell microcode instruction is a variable shift.
+
@item -msecure-plt
@opindex msecure-plt
Generate code that allows ld and ld.so to build executables and shared
Software floating point emulation is provided if you use the
@option{-msoft-float} option, and pass the option to GCC when linking.
+@item -msingle-float
+@itemx -mdouble-float
+@opindex msingle-float
+@opindex mdouble-float
+Generate code for single or double-precision floating point operations.
+@option{-mdouble-float} implies @option{-msingle-float}.
+
+@item -msimple-fpu
+@opindex msimple-fpu
+Do not generate sqrt and div instructions for hardware floating point unit.
+
+@item -mfpu
+@opindex mfpu
+Specify type of floating point unit. Valid values are @var{sp_lite}
+(equivalent to -msingle-float -msimple-fpu), @var{dp_lite} (equivalent
+to -mdouble-float -msimple-fpu), @var{sp_full} (equivalent to -msingle-float),
+and @var{dp_full} (equivalent to -mdouble-float).
+
+@item -mxilinx-fpu
+@opindex mxilinx-fpu
+Perform optimizations for floating point unit on Xilinx PPC 405/440.
+
@item -mmultiple
@itemx -mno-multiple
@opindex mmultiple
stored, which means code that walks the stack frame across interrupts or
signals may get corrupted data.
+@item -mavoid-indexed-addresses
+@item -mno-avoid-indexed-addresses
+@opindex mavoid-indexed-addresses
+@opindex mno-avoid-indexed-addresses
+Generate code that tries to avoid (not avoid) the use of indexed load
+or store instructions. These instructions can incur a performance
+penalty on Power6 processors in certain situations, such as when
+stepping through large arrays that cross a 16M boundary. This option
+is enabled by default when targetting Power6 and disabled otherwise.
+
@item -mfused-madd
@itemx -mno-fused-madd
@opindex mfused-madd
operations. When @option{-mhard-float} is specified, the compiler
generates IEEE floating-point instructions. This is the default.
+@item -mhard-dfp
+@itemx -mno-hard-dfp
+@opindex mhard-dfp
+@opindex mno-hard-dfp
+Use (do not use) the hardware decimal-floating-point instructions for
+decimal-floating-point operations. When @option{-mno-hard-dfp} is
+specified, functions in @file{libgcc.a} will be used to perform
+decimal-floating-point operations. When @option{-mhard-dfp} is
+specified, the compiler generates decimal-floating-point hardware
+instructions. This is the default for @option{-march=z9-ec} or higher.
+
@item -mlong-double-64
@itemx -mlong-double-128
@opindex mlong-double-64
@opindex march
Generate code that will run on @var{cpu-type}, which is the name of a system
representing a certain processor type. Possible values for
-@var{cpu-type} are @samp{g5}, @samp{g6}, @samp{z900}, and @samp{z990}.
+@var{cpu-type} are @samp{g5}, @samp{g6}, @samp{z900}, @samp{z990},
+@samp{z9-109}, @samp{z9-ec} and @samp{z10}.
When generating code using the instructions available on z/Architecture,
the default is @option{-march=z900}. Otherwise, the default is
@option{-march=g5}.
two registers separated by a dash. Multiple register ranges can be
specified separated by a comma.
+@item -mdual-nops
+@itemx -mdual-nops=@var{n}
+@opindex mdual-nops
+By default, GCC will insert nops to increase dual issue when it expects
+it to increase performance. @var{n} can be a value from 0 to 10. A
+smaller @var{n} will insert fewer nops. 10 is the default, 0 is the
+same as @option{-mno-dual-nops}. Disabled with @option{-Os}.
+
+@item -mhint-max-nops=@var{n}
+@opindex mhint-max-nops
+Maximum number of nops to insert for a branch hint. A branch hint must
+be at least 8 instructions away from the branch it is effecting. GCC
+will insert up to @var{n} nops to enforce this, otherwise it will not
+generate the branch hint.
+
+@item -mhint-max-distance=@var{n}
+@opindex mhint-max-distance
+The encoding of the branch hint instruction limits the hint to be within
+256 instructions of the branch it is effecting. By default, GCC makes
+sure it is within 125.
+
+@item -msafe-hints
+@opindex msafe-hints
+Work around a hardware bug which causes the SPU to stall indefinitely.
+By default, GCC will insert the @code{hbrp} instruction to make sure
+this stall won't happen.
+
@end table
@node System V Options
detected on nearly all systems if there is only one stack.
Note that this switch does not actually cause checking to be done; the
-operating system must do that. The switch causes generation of code
-to ensure that the operating system sees the stack being extended.
+operating system or the language runtime must do that. The switch causes
+generation of code to ensure that they see the stack being extended.
+
+You can additionally specify a string parameter: @code{no} means no
+checking, @code{generic} means force the use of old-style checking,
+@code{specific} means use the best checking method and is equivalent
+to bare @option{-fstack-check}.
+
+Old-style checking is a generic mechanism that requires no specific
+target support in the compiler but comes with the following drawbacks:
+
+@enumerate
+@item
+Modified allocation strategy for large objects: they will always be
+allocated dynamically if their size exceeds a fixed threshold.
+
+@item
+Fixed limit on the size of the static frame of functions: when it is
+topped by a particular function, stack checking is not reliable and
+a warning is issued by the compiler.
+
+@item
+Inefficiency: because of both the modified allocation strategy and the
+generic implementation, the performances of the code are hampered.
+@end enumerate
+
+Note that old-style stack checking is also the fallback method for
+@code{specific} if no target support has been added in the compiler.
@item -fstack-limit-register=@var{reg}
@itemx -fstack-limit-symbol=@var{sym}
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