@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
-@c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+@c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
@c Free Software Foundation, Inc.
@c This is part of the GCC manual.
also available in C++. @xref{C++ Extensions,,Extensions to the
C++ Language}, for extensions that apply @emph{only} to C++.
-Some features that are in ISO C99 but not C89 or C++ are also, as
-extensions, accepted by GCC in C89 mode and in C++.
+Some features that are in ISO C99 but not C90 or C++ are also, as
+extensions, accepted by GCC in C90 mode and in C++.
@menu
* Statement Exprs:: Putting statements and declarations inside expressions.
* Typeof:: @code{typeof}: referring to the type of an expression.
* Conditionals:: Omitting the middle operand of a @samp{?:} expression.
* Long Long:: Double-word integers---@code{long long int}.
+* __int128:: 128-bit integers---@code{__int128}.
* Complex:: Data types for complex numbers.
* Floating Types:: Additional Floating Types.
* Half-Precision:: Half-Precision Floating Point.
* Decimal Float:: Decimal Floating Types.
* Hex Floats:: Hexadecimal floating-point constants.
* Fixed-Point:: Fixed-Point Types.
+* Named Address Spaces::Named address spaces.
* Zero Length:: Zero-length arrays.
* Variable Length:: Arrays whose length is computed at run time.
* Empty Structures:: Structures with no members.
* Type Attributes:: Specifying attributes of types.
* Alignment:: Inquiring about the alignment of a type or variable.
* Inline:: Defining inline functions (as fast as macros).
+* Volatiles:: What constitutes an access to a volatile object.
* Extended Asm:: Assembler instructions with C expressions as operands.
(With them you can define ``built-in'' functions.)
* Constraints:: Constraints for asm operands
the number of dynamic relocations that are needed, and by consequence,
allows the data to be read-only.
-The @code{&&foo} expressions for the same label might have different values
-if the containing function is inlined or cloned. If a program relies on
-them being always the same, @code{__attribute__((__noinline__))} should
-be used to prevent inlining. If @code{&&foo} is used
-in a static variable initializer, inlining is forbidden.
+The @code{&&foo} expressions for the same label might have different
+values if the containing function is inlined or cloned. If a program
+relies on them being always the same,
+@code{__attribute__((__noinline__,__noclone__))} should be used to
+prevent inlining and cloning. If @code{&&foo} is used in a static
+variable initializer, inlining and cloning is forbidden.
@node Nested Functions
@section Nested Functions
safe.
GCC implements taking the address of a nested function using a technique
-called @dfn{trampolines}. A paper describing them is available as
-
-@noindent
-@uref{http://people.debian.org/~aaronl/Usenix88-lexic.pdf}.
+called @dfn{trampolines}. This technique was described in
+@cite{Lexical Closures for C++} (Thomas M. Breuel, USENIX
+C++ Conference Proceedings, October 17-21, 1988).
A nested function can jump to a label inherited from a containing
function, provided the label was explicitly declared in the containing
returned by @code{__builtin_apply}.
@end deftypefn
-@deftypefn {Built-in Function} __builtin_va_arg_pack ()
+@deftypefn {Built-in Function} {} __builtin_va_arg_pack ()
This built-in function represents all anonymous arguments of an inline
function. It can be used only in inline functions which will be always
inlined, never compiled as a separate function, such as those using
@end smallexample
@end deftypefn
-@deftypefn {Built-in Function} __builtin_va_arg_pack_len ()
+@deftypefn {Built-in Function} {size_t} __builtin_va_arg_pack_len ()
This built-in function returns the number of anonymous arguments of
an inline function. It can be used only in inline functions which
will be always inlined, never compiled as a separate function, such
x ? x : y
@end smallexample
-@cindex side effect in ?:
-@cindex ?: side effect
+@cindex side effect in @code{?:}
+@cindex @code{?:} side effect
@noindent
In this simple case, the ability to omit the middle operand is not
especially useful. When it becomes useful is when the first operand does,
the middle operand uses the value already computed without the undesirable
effects of recomputing it.
+@node __int128
+@section 128-bits integers
+@cindex @code{__int128} data types
+
+As an extension the integer scalar type @code{__int128} is supported for
+targets having an integer mode wide enough to hold 128-bit.
+Simply write @code{__int128} for a signed 128-bit integer, or
+@code{unsigned __int128} for an unsigned 128-bit integer. There is no
+support in GCC to express an integer constant of type @code{__int128}
+for targets having @code{long long} integer with less then 128 bit width.
+
@node Long Long
@section Double-Word Integers
@cindex @code{long long} data types
@cindex @code{ULL} integer suffix
ISO C99 supports data types for integers that are at least 64 bits wide,
-and as an extension GCC supports them in C89 mode and in C++.
+and as an extension GCC supports them in C90 mode and in C++.
Simply write @code{long long int} for a signed integer, or
@code{unsigned long long int} for an unsigned integer. To make an
integer constant of type @code{long long int}, add the suffix @samp{LL}
@cindex @code{__complex__} keyword
ISO C99 supports complex floating data types, and as an extension GCC
-supports them in C89 mode and in C++, and supports complex integer data
+supports them in C90 mode and in C++, and supports complex integer data
types which are not part of ISO C99. You can declare complex types
using the keyword @code{_Complex}. As an extension, the older GNU
keyword @code{__complex__} is also supported.
Not all targets support additional floating point types. @code{__float80}
and @code{__float128} types are supported on i386, x86_64 and ia64 targets.
+The @code{__float128} type is supported on hppa HP-UX targets.
@node Half-Precision
@section Half-Precision Floating Point
ARM provides hardware support for conversions between
@code{__fp16} and @code{float} values
as an extension to VFP and NEON (Advanced SIMD). GCC generates
-code using the instructions provided by this extension if you compile
-with the options @option{-mfpu=neon-fp16 -mfloat-abi=softfp},
+code using these hardware instructions if you compile with
+options to select an FPU that provides them;
+for example, @option{-mfpu=neon-fp16 -mfloat-abi=softfp},
in addition to the @option{-mfp16-format} option to select
a half-precision format.
ISO C99 supports floating-point numbers written not only in the usual
decimal notation, such as @code{1.55e1}, but also numbers such as
@code{0x1.fp3} written in hexadecimal format. As a GNU extension, GCC
-supports this in C89 mode (except in some cases when strictly
+supports this in C90 mode (except in some cases when strictly
conforming) and in C++. In that format the
@samp{0x} hex introducer and the @samp{p} or @samp{P} exponent field are
mandatory. The exponent is a decimal number that indicates the power of
Fixed-point types are supported by the DWARF2 debug information format.
+@node Named Address Spaces
+@section Named address spaces
+@cindex named address spaces
+
+As an extension, the GNU C compiler supports named address spaces as
+defined in the N1275 draft of ISO/IEC DTR 18037. Support for named
+address spaces in GCC will evolve as the draft technical report changes.
+Calling conventions for any target might also change. At present, only
+the SPU and M32C targets support other address spaces. On the SPU target, for
+example, variables may be declared as belonging to another address space
+by qualifying the type with the @code{__ea} address space identifier:
+
+@smallexample
+extern int __ea i;
+@end smallexample
+
+When the variable @code{i} is accessed, the compiler will generate
+special code to access this variable. It may use runtime library
+support, or generate special machine instructions to access that address
+space.
+
+The @code{__ea} identifier may be used exactly like any other C type
+qualifier (e.g., @code{const} or @code{volatile}). See the N1275
+document for more details.
+
+On the M32C target, with the R8C and M16C cpu variants, variables
+qualified with @code{__far} are accessed using 32-bit addresses in
+order to access memory beyond the first 64k bytes. If @code{__far} is
+used with the M32CM or M32C cpu variants, it has no effect.
+
@node Zero Length
@section Arrays of Length Zero
@cindex arrays of length zero
@cindex VLAs
Variable-length automatic arrays are allowed in ISO C99, and as an
-extension GCC accepts them in C89 mode and in C++. (However, GCC's
-implementation of variable-length arrays does not yet conform in detail
-to the ISO C99 standard.) These arrays are
+extension GCC accepts them in C90 mode and in C++. These arrays are
declared like any other automatic arrays, but with a length that is not
a constant expression. The storage is allocated at the point of
declaration and deallocated when the brace-level is exited. For
may be subscripted, although they may not be modified or used after
the next sequence point and the unary @samp{&} operator may not be
applied to them. As an extension, GCC allows such arrays to be
-subscripted in C89 mode, though otherwise they do not decay to
+subscripted in C90 mode, though otherwise they do not decay to
pointers outside C99 mode. For example,
-this is valid in GNU C though not valid in C89:
+this is valid in GNU C though not valid in C90:
@smallexample
@group
a cast containing an initializer. Its value is an object of the
type specified in the cast, containing the elements specified in
the initializer; it is an lvalue. As an extension, GCC supports
-compound literals in C89 mode and in C++.
+compound literals in C90 mode and in C++.
Usually, the specified type is a structure. Assume that
@code{struct foo} and @code{structure} are declared as shown:
@cindex case labels in initializers
@cindex designated initializers
-Standard C89 requires the elements of an initializer to appear in a fixed
+Standard C90 requires the elements of an initializer to appear in a fixed
order, the same as the order of the elements in the array or structure
being initialized.
In ISO C99 you can give the elements in any order, specifying the array
indices or structure field names they apply to, and GNU C allows this as
-an extension in C89 mode as well. This extension is not
+an extension in C90 mode as well. This extension is not
implemented in GNU C++.
To specify an array index, write
ISO C99 and ISO C++ allow declarations and code to be freely mixed
within compound statements. As an extension, GCC also allows this in
-C89 mode. For example, you could do:
+C90 mode. For example, you could do:
@smallexample
int i;
@cindex functions that do not pop the argument stack on the 386
@cindex functions that have different compilation options on the 386
@cindex functions that have different optimization options
+@cindex functions that are dynamically resolved
In GNU C, you declare certain things about functions called in your program
which help the compiler optimize function calls and check your code more
attribute specification inside double parentheses. The following
attributes are currently defined for functions on all targets:
@code{aligned}, @code{alloc_size}, @code{noreturn},
-@code{returns_twice}, @code{noinline}, @code{always_inline},
-@code{flatten}, @code{pure}, @code{const}, @code{nothrow},
-@code{sentinel}, @code{format}, @code{format_arg},
-@code{no_instrument_function}, @code{section}, @code{constructor},
+@code{returns_twice}, @code{noinline}, @code{noclone},
+@code{always_inline}, @code{flatten}, @code{pure}, @code{const},
+@code{nothrow}, @code{sentinel}, @code{format}, @code{format_arg},
+@code{no_instrument_function}, @code{no_split_stack},
+@code{section}, @code{constructor},
@code{destructor}, @code{used}, @code{unused}, @code{deprecated},
-@code{weak}, @code{malloc}, @code{alias}, @code{warn_unused_result},
-@code{nonnull}, @code{gnu_inline}, @code{externally_visible},
-@code{hot}, @code{cold}, @code{artificial}, @code{error}
-and @code{warning}.
-Several other attributes are defined for functions on particular
-target systems. Other attributes, including @code{section} are
-supported for variables declarations (@pxref{Variable Attributes}) and
-for types (@pxref{Type Attributes}).
+@code{weak}, @code{malloc}, @code{alias}, @code{ifunc},
+@code{warn_unused_result}, @code{nonnull}, @code{gnu_inline},
+@code{externally_visible}, @code{hot}, @code{cold}, @code{artificial},
+@code{error} and @code{warning}. Several other attributes are defined
+for functions on particular target systems. Other attributes,
+including @code{section} are supported for variables declarations
+(@pxref{Variable Attributes}) and for types (@pxref{Type Attributes}).
+
+GCC plugins may provide their own attributes.
You may also specify attributes with @samp{__} preceding and following
each keyword. This allows you to use them in header files without
@cindex @code{gnu_inline} function attribute
This attribute should be used with a function which is also declared
with the @code{inline} keyword. It directs GCC to treat the function
-as if it were defined in gnu89 mode even when compiling in C99 or
+as if it were defined in gnu90 mode even when compiling in C99 or
gnu99 mode.
If the function is declared @code{extern}, then this definition of the
or using the caller location for all instructions within the inlined
body.
+@item bank_switch
+@cindex interrupt handler functions
+When added to an interrupt handler with the M32C port, causes the
+prologue and epilogue to use bank switching to preserve the registers
+rather than saving them on the stack.
+
@item flatten
@cindex @code{flatten} function attribute
Generally, inlining into a function is limited. For a function marked with
The @code{deprecated} attribute can also be used for variables and
types (@pxref{Variable Attributes}, @pxref{Type Attributes}.)
+@item disinterrupt
+@cindex @code{disinterrupt} attribute
+On MeP targets, this attribute causes the compiler to emit
+instructions to disable interrupts for the duration of the given
+function.
+
@item dllexport
@cindex @code{__declspec(dllexport)}
On Microsoft Windows targets and Symbian OS targets the
attribute also implies ``default'' visibility. It is an error to
explicitly specify any other visibility.
-Currently, the @code{dllexport} attribute is ignored for inlined
-functions, unless the @option{-fkeep-inline-functions} flag has been
-used. The attribute is also ignored for undefined symbols.
+In previous versions of GCC, the @code{dllexport} attribute was ignored
+for inlined functions, unless the @option{-fkeep-inline-functions} flag
+had been used. The default behaviour now is to emit all dllexported
+inline functions; however, this can cause object file-size bloat, in
+which case the old behaviour can be restored by using
+@option{-fno-keep-inline-dllexport}.
+
+The attribute is also ignored for undefined symbols.
When applied to C++ classes, the attribute marks defined non-inlined
member functions and static data members as exports. Static consts
@cindex @code{externally_visible} attribute.
This attribute, attached to a global variable or function, nullifies
the effect of the @option{-fwhole-program} command-line option, so the
-object remains visible outside the current compilation unit.
+object remains visible outside the current compilation unit. If @option{-fwhole-program} is used together with @option{-flto} and @command{gold} is used as the linker plugin, @code{externally_visible} attributes are automatically added to functions (not variable yet due to a current @command{gold} issue) that are accessed outside of LTO objects according to resolution file produced by @command{gold}. For other linkers that cannot generate resolution file, explicit @code{externally_visible} attributes are still necessary.
@item far
@cindex functions which handle memory bank switching
instead of using @code{rts}. The board-specific return routine simulates
the @code{rtc}.
+On MeP targets this causes the compiler to use a calling convention
+which assumes the called function is too far away for the built-in
+addressing modes.
+
+@item fast_interrupt
+@cindex interrupt handler functions
+Use this attribute on the M32C and RX ports to indicate that the specified
+function is a fast interrupt handler. This is just like the
+@code{interrupt} attribute, except that @code{freit} is used to return
+instead of @code{reit}.
+
@item fastcall
@cindex functions that pop the argument stack on the 386
On the Intel 386, the @code{fastcall} attribute causes the compiler to
pop the arguments off the stack. If the number of arguments is variable all
arguments are pushed on the stack.
+@item thiscall
+@cindex functions that pop the argument stack on the 386
+On the Intel 386, the @code{thiscall} attribute causes the compiler to
+pass the first argument (if of integral type) in the register ECX.
+Subsequent and other typed arguments are passed on the stack. The called
+function will pop the arguments off the stack.
+If the number of arguments is variable all arguments are pushed on the
+stack.
+The @code{thiscall} attribute is intended for C++ non-static member functions.
+As gcc extension this calling convention can be used for C-functions
+and for static member methods.
+
@item format (@var{archetype}, @var{string-index}, @var{first-to-check})
@cindex @code{format} function attribute
@opindex Wformat
are @code{printf_unlocked} and @code{fprintf_unlocked}.
@xref{C Dialect Options,,Options Controlling C Dialect}.
-The target may provide additional types of format checks.
+For Objective-C dialects, @code{NSString} (or @code{__NSString__}) is
+recognized in the same context. Declarations including these format attributes
+will be parsed for correct syntax, however the result of checking of such format
+strings is not yet defined, and will not be carried out by this version of the
+compiler.
+
+The target may also provide additional types of format checks.
@xref{Target Format Checks,,Format Checks Specific to Particular
Target Machines}.
is used. @xref{C Dialect Options,,Options
Controlling C Dialect}.
+For Objective-C dialects, the @code{format-arg} attribute may refer to an
+@code{NSString} reference for compatibility with the @code{format} attribute
+above.
+
+The target may also allow additional types in @code{format-arg} attributes.
+@xref{Target Format Checks,,Format Checks Specific to Particular
+Target Machines}.
+
@item function_vector
@cindex calling functions through the function vector on H8/300, M16C, M32C and SH2A processors
Use this attribute on the H8/300, H8/300H, and H8S to indicate that the specified
@item interrupt
@cindex interrupt handler functions
-Use this attribute on the ARM, AVR, CRX, M32C, M32R/D, m68k, MIPS
-and Xstormy16 ports to indicate that the specified function is an
+Use this attribute on the ARM, AVR, M32C, M32R/D, m68k, MeP, MIPS,
+RX and Xstormy16 ports to indicate that the specified function is an
interrupt handler. The compiler will generate function entry and exit
sequences suitable for use in an interrupt handler when this attribute
is present.
-Note, interrupt handlers for the Blackfin, H8/300, H8/300H, H8S, and
-SH processors can be specified via the @code{interrupt_handler} attribute.
+Note, interrupt handlers for the Blackfin, H8/300, H8/300H, H8S, MicroBlaze,
+and SH processors can be specified via the @code{interrupt_handler} attribute.
Note, on the AVR, interrupts will be enabled inside the function.
void __attribute__ ((interrupt, keep_interrupts_masked)) v2 ();
void __attribute__ ((interrupt, use_debug_exception_return)) v3 ();
void __attribute__ ((interrupt, use_shadow_register_set,
- keep_interrupts_masked)) v4 ();
+ keep_interrupts_masked)) v4 ();
void __attribute__ ((interrupt, use_shadow_register_set,
- use_debug_exception_return)) v5 ();
+ use_debug_exception_return)) v5 ();
void __attribute__ ((interrupt, keep_interrupts_masked,
- use_debug_exception_return)) v6 ();
+ use_debug_exception_return)) v6 ();
void __attribute__ ((interrupt, use_shadow_register_set,
- keep_interrupts_masked,
- use_debug_exception_return)) v7 ();
+ keep_interrupts_masked,
+ use_debug_exception_return)) v7 ();
+@end smallexample
+
+@item ifunc ("@var{resolver}")
+@cindex @code{ifunc} attribute
+The @code{ifunc} attribute is used to mark a function as an indirect
+function using the STT_GNU_IFUNC symbol type extension to the ELF
+standard. This allows the resolution of the symbol value to be
+determined dynamically at load time, and an optimized version of the
+routine can be selected for the particular processor or other system
+characteristics determined then. To use this attribute, first define
+the implementation functions available, and a resolver function that
+returns a pointer to the selected implementation function. The
+implementation functions' declarations must match the API of the
+function being implemented, the resolver's declaration is be a
+function returning pointer to void function returning void:
+
+@smallexample
+void *my_memcpy (void *dst, const void *src, size_t len)
+@{
+ @dots{}
+@}
+
+static void (*resolve_memcpy (void)) (void)
+@{
+ return my_memcpy; // we'll just always select this routine
+@}
+@end smallexample
+
+The exported header file declaring the function the user calls would
+contain:
+
+@smallexample
+extern void *memcpy (void *, const void *, size_t);
+@end smallexample
+
+allowing the user to call this as a regular function, unaware of the
+implementation. Finally, the indirect function needs to be defined in
+the same translation unit as the resolver function:
+
+@smallexample
+void *memcpy (void *, const void *, size_t)
+ __attribute__ ((ifunc ("resolve_memcpy")));
@end smallexample
+Indirect functions cannot be weak, and require a recent binutils (at
+least version 2.20.1), and GNU C library (at least version 2.11.1).
+
@item interrupt_handler
@cindex interrupt handler functions on the Blackfin, m68k, H8/300 and SH processors
Use this attribute on the Blackfin, m68k, H8/300, H8/300H, H8S, and SH to
With @option{-mfdpic}, function calls with a such function as the callee
or caller will use inlined PLT.
+@item l2
+@cindex @code{l2} function attribute
+On the Blackfin, this attribute specifies a function to be placed into L2
+SRAM. The function will be put into a specific section named
+@code{.l1.text}. With @option{-mfdpic}, callers of such functions will use
+an inlined PLT.
+
+@item leaf
+@cindex @code{leaf} function attribute
+Calls to external functions with this attribute must return to the current
+compilation unit only by return or by exception handling. In particular, leaf
+functions are not allowed to call callback function passed to it from the current
+compilation unit or directly call functions exported by the unit or longjmp
+into the unit. Leaf function might still call functions from other compilation
+units and thus they are not necessarily leaf in the sense that they contain no
+function calls at all.
+
+The attribute is intended for library functions to improve dataflow analysis.
+The compiler takes the hint that any data not escaping the current compilation unit can
+not be used or modified by the leaf function. For example, the @code{sin} function
+is a leaf function, but @code{qsort} is not.
+
+Note that leaf functions might invoke signals and signal handlers might be
+defined in the current compilation unit and use static variables. The only
+compliant way to write such a signal handler is to declare such variables
+@code{volatile}.
+
+The attribute has no effect on functions defined within the current compilation
+unit. This is to allow easy merging of multiple compilation units into one,
+for example, by using the link time optimization. For this reason the
+attribute is not allowed on types to annotate indirect calls.
+
@item long_call/short_call
@cindex indirect calls on ARM
This attribute specifies how a particular function is called on
ARM@. Both attributes override the @option{-mlong-calls} (@pxref{ARM Options})
-command line switch and @code{#pragma long_calls} settings. The
+command-line switch and @code{#pragma long_calls} settings. The
@code{long_call} attribute indicates that the function might be far
away from the call site and require a different (more expensive)
calling sequence. The @code{short_call} attribute always places
GNU/Linux and other systems. The default is to use the Microsoft ABI
when targeting Windows. On all other systems, the default is the AMD ABI.
-Note, This feature is currently sorried out for Windows targets trying to
+Note, the @code{ms_abi} attribute for Windows targets currently requires
+the @option{-maccumulate-outgoing-args} option.
+
+@item callee_pop_aggregate_return (@var{number})
+@cindex @code{callee_pop_aggregate_return} attribute
+
+On 32-bit i?86-*-* targets, you can control by those attribute for
+aggregate return in memory, if the caller is responsible to pop the hidden
+pointer together with the rest of the arguments - @var{number} equal to
+zero -, or if the callee is responsible to pop hidden pointer - @var{number}
+equal to one.
+
+For i?86-netware, the caller pops the stack for the hidden arguments pointing
+to aggregate return value. This differs from the default i386 ABI which assumes
+that the callee pops the stack for hidden pointer.
+
+@item ms_hook_prologue
+@cindex @code{ms_hook_prologue} attribute
+
+On 32 bit i[34567]86-*-* targets and 64 bit x86_64-*-* targets, you can use
+this function attribute to make gcc generate the "hot-patching" function
+prologue used in Win32 API functions in Microsoft Windows XP Service Pack 2
+and newer.
@item naked
@cindex function without a prologue/epilogue code
-Use this attribute on the ARM, AVR, IP2K and SPU ports to indicate that
+Use this attribute on the ARM, AVR, MCORE, RX and SPU ports to indicate that
the specified function does not need prologue/epilogue sequences generated by
the compiler. It is up to the programmer to provide these sequences. The
only statements that can be safely included in naked functions are
This attribute can be used to cancel the effect of the @option{-mlong-calls}
option.
+On MeP targets this attribute causes the compiler to assume the called
+function is close enough to use the normal calling convention,
+overriding the @code{-mtf} command line option.
+
@item nesting
@cindex Allow nesting in an interrupt handler on the Blackfin processor.
Use this attribute together with @code{interrupt_handler},
be generated at entry and exit of most user-compiled functions.
Functions with this attribute will not be so instrumented.
+@item no_split_stack
+@cindex @code{no_split_stack} function attribute
+@opindex fsplit-stack
+If @option{-fsplit-stack} is given, functions will have a small
+prologue which decides whether to split the stack. Functions with the
+@code{no_split_stack} attribute will not have that prologue, and thus
+may run with only a small amount of stack space available.
+
@item noinline
@cindex @code{noinline} function attribute
This function attribute prevents a function from being considered for
(@pxref{Extended Asm}) in the called function, to serve as a special
side-effect.
+@item noclone
+@cindex @code{noclone} function attribute
+This function attribute prevents a function from being considered for
+cloning - a mechanism which produces specialized copies of functions
+and which is (currently) performed by interprocedural constant
+propagation.
+
@item nonnull (@var{arg-index}, @dots{})
@cindex @code{nonnull} function attribute
The @code{nonnull} attribute specifies that some function parameters should
and larger code, while other functions can be called with less
aggressive options.
+@item pcs
+@cindex @code{pcs} function attribute
+
+The @code{pcs} attribute can be used to control the calling convention
+used for a function on ARM. The attribute takes an argument that specifies
+the calling convention to use.
+
+When compiling using the AAPCS ABI (or a variant of that) then valid
+values for the argument are @code{"aapcs"} and @code{"aapcs-vfp"}. In
+order to use a variant other than @code{"aapcs"} then the compiler must
+be permitted to use the appropriate co-processor registers (i.e., the
+VFP registers must be available in order to use @code{"aapcs-vfp"}).
+For example,
+
+@smallexample
+/* Argument passed in r0, and result returned in r0+r1. */
+double f2d (float) __attribute__((pcs("aapcs")));
+@end smallexample
+
+Variadic functions always use the @code{"aapcs"} calling convention and
+the compiler will reject attempts to specify an alternative.
+
@item pure
@cindex @code{pure} function attribute
Many functions have no effects except the return value and their
all registers except the stack pointer should be saved in the prologue
regardless of whether they are used or not.
+@item save_volatiles
+@cindex save volatile registers on the MicroBlaze
+Use this attribute on the MicroBlaze to indicate that the function is
+an interrupt handler. All volatile registers (in addition to non-volatile
+registers) will be saved in the function prologue. If the function is a leaf
+function, only volatiles used by the function are saved. A normal function
+return is generated instead of a return from interrupt.
+
@item section ("@var{section-name}")
@cindex @code{section} function attribute
Normally, the compiler places the code it generates in the @code{text} section.
@cindex @code{target("sse4a")} attribute
Enable/disable the generation of the SSE4A instructions.
-@item sse5
-@itemx no-sse5
-@cindex @code{target("sse5")} attribute
-Enable/disable the generation of the SSE5 instructions.
+@item fma4
+@itemx no-fma4
+@cindex @code{target("fma4")} attribute
+Enable/disable the generation of the FMA4 instructions.
+
+@item xop
+@itemx no-xop
+@cindex @code{target("xop")} attribute
+Enable/disable the generation of the XOP instructions.
+
+@item lwp
+@itemx no-lwp
+@cindex @code{target("lwp")} attribute
+Enable/disable the generation of the LWP instructions.
@item ssse3
@itemx no-ssse3
different options.
@end table
-On the 386, you can use either multiple strings to specify multiple
-options, or you can separate the option with a comma (@code{,}).
+On the PowerPC, the following options are allowed:
+
+@table @samp
+@item altivec
+@itemx no-altivec
+@cindex @code{target("altivec")} attribute
+Generate code that uses (does not use) AltiVec instructions. In
+32-bit code, you cannot enable Altivec instructions unless
+@option{-mabi=altivec} was used on the command line.
+
+@item cmpb
+@itemx no-cmpb
+@cindex @code{target("cmpb")} attribute
+Generate code that uses (does not use) the compare bytes instruction
+implemented on the POWER6 processor and other processors that support
+the PowerPC V2.05 architecture.
+
+@item dlmzb
+@itemx no-dlmzb
+@cindex @code{target("dlmzb")} attribute
+Generate code that uses (does not use) the string-search @samp{dlmzb}
+instruction on the IBM 405, 440, 464 and 476 processors. This instruction is
+generated by default when targetting those processors.
+
+@item fprnd
+@itemx no-fprnd
+@cindex @code{target("fprnd")} attribute
+Generate code that uses (does not use) the FP round to integer
+instructions implemented on the POWER5+ processor and other processors
+that support the PowerPC V2.03 architecture.
+
+@item hard-dfp
+@itemx no-hard-dfp
+@cindex @code{target("hard-dfp")} attribute
+Generate code that uses (does not use) the decimal floating point
+instructions implemented on some POWER processors.
+
+@item isel
+@itemx no-isel
+@cindex @code{target("isel")} attribute
+Generate code that uses (does not use) ISEL instruction.
+
+@item mfcrf
+@itemx no-mfcrf
+@cindex @code{target("mfcrf")} attribute
+Generate code that uses (does not use) the move from condition
+register field instruction implemented on the POWER4 processor and
+other processors that support the PowerPC V2.01 architecture.
+
+@item mfpgpr
+@itemx no-mfpgpr
+@cindex @code{target("mfpgpr")} attribute
+Generate code that uses (does not use) the FP move to/from general
+purpose register instructions implemented on the POWER6X processor and
+other processors that support the extended PowerPC V2.05 architecture.
+
+@item mulhw
+@itemx no-mulhw
+@cindex @code{target("mulhw")} attribute
+Generate code that uses (does not use) the half-word multiply and
+multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors.
+These instructions are generated by default when targetting those
+processors.
+
+@item multiple
+@itemx no-multiple
+@cindex @code{target("multiple")} attribute
+Generate code that uses (does not use) the load multiple word
+instructions and the store multiple word instructions.
+
+@item update
+@itemx no-update
+@cindex @code{target("update")} attribute
+Generate code that uses (does not use) the load or store instructions
+that update the base register to the address of the calculated memory
+location.
+
+@item popcntb
+@itemx no-popcntb
+@cindex @code{target("popcntb")} attribute
+Generate code that uses (does not use) the popcount and double
+precision FP reciprocal estimate instruction implemented on the POWER5
+processor and other processors that support the PowerPC V2.02
+architecture.
+
+@item popcntd
+@itemx no-popcntd
+@cindex @code{target("popcntd")} attribute
+Generate code that uses (does not use) the popcount instruction
+implemented on the POWER7 processor and other processors that support
+the PowerPC V2.06 architecture.
+
+@item powerpc-gfxopt
+@itemx no-powerpc-gfxopt
+@cindex @code{target("powerpc-gfxopt")} attribute
+Generate code that uses (does not use) the optional PowerPC
+architecture instructions in the Graphics group, including
+floating-point select.
+
+@item powerpc-gpopt
+@itemx no-powerpc-gpopt
+@cindex @code{target("powerpc-gpopt")} attribute
+Generate code that uses (does not use) the optional PowerPC
+architecture instructions in the General Purpose group, including
+floating-point square root.
+
+@item recip-precision
+@itemx no-recip-precision
+@cindex @code{target("recip-precision")} attribute
+Assume (do not assume) that the reciprocal estimate instructions
+provide higher precision estimates than is mandated by the powerpc
+ABI.
+
+@item string
+@itemx no-string
+@cindex @code{target("string")} attribute
+Generate code that uses (does not use) the load string instructions
+and the store string word instructions to save multiple registers and
+do small block moves.
+
+@item vsx
+@itemx no-vsx
+@cindex @code{target("vsx")} attribute
+Generate code that uses (does not use) vector/scalar (VSX)
+instructions, and also enable the use of built-in functions that allow
+more direct access to the VSX instruction set. In 32-bit code, you
+cannot enable VSX or Altivec instructions unless
+@option{-mabi=altivec} was used on the command line.
+
+@item friz
+@itemx no-friz
+@cindex @code{target("friz")} attribute
+Generate (do not generate) the @code{friz} instruction when the
+@option{-funsafe-math-optimizations} option is used to optimize
+rounding a floating point value to 64-bit integer and back to floating
+point. The @code{friz} instruction does not return the same value if
+the floating point number is too large to fit in an integer.
+
+@item avoid-indexed-addresses
+@itemx no-avoid-indexed-addresses
+@cindex @code{target("avoid-indexed-addresses")} attribute
+Generate code that tries to avoid (not avoid) the use of indexed load
+or store instructions.
+
+@item paired
+@itemx no-paired
+@cindex @code{target("paired")} attribute
+Generate code that uses (does not use) the generation of PAIRED simd
+instructions.
+
+@item longcall
+@itemx no-longcall
+@cindex @code{target("longcall")} attribute
+Generate code that assumes (does not assume) that all calls are far
+away so that a longer more expensive calling sequence is required.
+
+@item cpu=@var{CPU}
+@cindex @code{target("cpu=@var{CPU}")} attribute
+Specify the architecture to generate code for when compiling the
+function. If you select the @code{"target("cpu=power7)"} attribute when
+generating 32-bit code, VSX and Altivec instructions are not generated
+unless you use the @option{-mabi=altivec} option on the command line.
+
+@item tune=@var{TUNE}
+@cindex @code{target("tune=@var{TUNE}")} attribute
+Specify the architecture to tune for when compiling the function. If
+you do not specify the @code{target("tune=@var{TUNE}")} attribute and
+you do specify the @code{target("cpu=@var{CPU}")} attribute,
+compilation will tune for the @var{CPU} architecture, and not the
+default tuning specified on the command line.
+@end table
+
+On the 386/x86_64 and PowerPC backends, you can use either multiple
+strings to specify multiple options, or you can separate the option
+with a comma (@code{,}).
-On the 386, the inliner will not inline a function that has different
-target options than the caller, unless the callee has a subset of the
-target options of the caller. For example a function declared with
-@code{target("sse5")} can inline a function with
-@code{target("sse2")}, since @code{-msse5} implies @code{-msse2}.
+On the 386/x86_64 and PowerPC backends, the inliner will not inline a
+function that has different target options than the caller, unless the
+callee has a subset of the target options of the caller. For example
+a function declared with @code{target("sse3")} can inline a function
+with @code{target("sse2")}, since @code{-msse3} implies @code{-msse2}.
The @code{target} attribute is not implemented in GCC versions earlier
-than 4.4, and at present only the 386 uses it.
+than 4.4 for the i386/x86_64 and 4.6 for the PowerPC backends. It is
+not currently implemented for other backends.
@item tiny_data
@cindex tiny data section on the H8/300H and H8S
If both the template and enclosing class have explicit visibility, the
visibility from the template is used.
+@item vliw
+@cindex @code{vliw} attribute
+On MeP, the @code{vliw} attribute tells the compiler to emit
+instructions in VLIW mode instead of core mode. Note that this
+attribute is not allowed unless a VLIW coprocessor has been configured
+and enabled through command line options.
+
@item warn_unused_result
@cindex @code{warn_unused_result} attribute
The @code{warn_unused_result} attribute causes a warning to be emitted
A weak reference is an alias that does not by itself require a
definition to be given for the target symbol. If the target symbol is
-only referenced through weak references, then the becomes a @code{weak}
+only referenced through weak references, then it becomes a @code{weak}
undefined symbol. If it is directly referenced, however, then such
strong references prevail, and a definition will be required for the
symbol, not necessarily in the same translation unit.
declaration @code{T D} specifies the type
``@var{derived-declarator-type-list} @var{Type}'' for @var{ident}, then
@code{T D1} specifies the type ``@var{derived-declarator-type-list}
-@var{type-qualifier-and-attribute-specifier-list} @var{Type}'' for
+@var{type-qualifier-and-attribute-specifier-list} pointer to @var{Type}'' for
@var{ident}.
For example,
@node C++ Comments
@section C++ Style Comments
-@cindex //
+@cindex @code{//}
@cindex C++ comments
@cindex comments, C++ style
such comments, and they are included in the 1999 C standard. However,
C++ style comments are not recognized if you specify an @option{-std}
option specifying a version of ISO C before C99, or @option{-ansi}
-(equivalent to @option{-std=c89}).
+(equivalent to @option{-std=c90}).
@node Dollar Signs
@section Dollar Signs in Identifier Names
You can use the sequence @samp{\e} in a string or character constant to
stand for the ASCII character @key{ESC}.
-@node Alignment
-@section Inquiring on Alignment of Types or Variables
-@cindex alignment
-@cindex type alignment
-@cindex variable alignment
-
-The keyword @code{__alignof__} allows you to inquire about how an object
-is aligned, or the minimum alignment usually required by a type. Its
-syntax is just like @code{sizeof}.
-
-For example, if the target machine requires a @code{double} value to be
-aligned on an 8-byte boundary, then @code{__alignof__ (double)} is 8.
-This is true on many RISC machines. On more traditional machine
-designs, @code{__alignof__ (double)} is 4 or even 2.
-
-Some machines never actually require alignment; they allow reference to any
-data type even at an odd address. For these machines, @code{__alignof__}
-reports the smallest alignment that GCC will give the data type, usually as
-mandated by the target ABI.
-
-If the operand of @code{__alignof__} is an lvalue rather than a type,
-its value is the required alignment for its type, taking into account
-any minimum alignment specified with GCC's @code{__attribute__}
-extension (@pxref{Variable Attributes}). For example, after this
-declaration:
-
-@smallexample
-struct foo @{ int x; char y; @} foo1;
-@end smallexample
-
-@noindent
-the value of @code{__alignof__ (foo1.y)} is 1, even though its actual
-alignment is probably 2 or 4, the same as @code{__alignof__ (int)}.
-
-It is an error to ask for the alignment of an incomplete type.
-
@node Variable Attributes
@section Specifying Attributes of Variables
@cindex attribute of variables
@cindex @code{tls_model} attribute
The @code{tls_model} attribute sets thread-local storage model
(@pxref{Thread-Local}) of a particular @code{__thread} variable,
-overriding @option{-ftls-model=} command line switch on a per-variable
+overriding @option{-ftls-model=} command-line switch on a per-variable
basis.
The @var{tls_model} argument should be one of @code{global-dynamic},
@code{local-dynamic}, @code{initial-exec} or @code{local-exec}.
@table @code
@item l1_data
-@item l1_data_A
-@item l1_data_B
+@itemx l1_data_A
+@itemx l1_data_B
@cindex @code{l1_data} variable attribute
@cindex @code{l1_data_A} variable attribute
@cindex @code{l1_data_B} variable attribute
named @code{.l1.data}. Those with @code{l1_data_A} attribute will be put into
the specific section named @code{.l1.data.A}. Those with @code{l1_data_B}
attribute will be put into the specific section named @code{.l1.data.B}.
+
+@item l2
+@cindex @code{l2} variable attribute
+Use this attribute on the Blackfin to place the variable into L2 SRAM.
+Variables with @code{l2} attribute will be put into the specific section
+named @code{.l2.data}.
@end table
@subsection M32R/D Variable Attributes
addresses).
@end table
+@anchor{MeP Variable Attributes}
+@subsection MeP Variable Attributes
+
+The MeP target has a number of addressing modes and busses. The
+@code{near} space spans the standard memory space's first 16 megabytes
+(24 bits). The @code{far} space spans the entire 32-bit memory space.
+The @code{based} space is a 128 byte region in the memory space which
+is addressed relative to the @code{$tp} register. The @code{tiny}
+space is a 65536 byte region relative to the @code{$gp} register. In
+addition to these memory regions, the MeP target has a separate 16-bit
+control bus which is specified with @code{cb} attributes.
+
+@table @code
+
+@item based
+Any variable with the @code{based} attribute will be assigned to the
+@code{.based} section, and will be accessed with relative to the
+@code{$tp} register.
+
+@item tiny
+Likewise, the @code{tiny} attribute assigned variables to the
+@code{.tiny} section, relative to the @code{$gp} register.
+
+@item near
+Variables with the @code{near} attribute are assumed to have addresses
+that fit in a 24-bit addressing mode. This is the default for large
+variables (@code{-mtiny=4} is the default) but this attribute can
+override @code{-mtiny=} for small variables, or override @code{-ml}.
+
+@item far
+Variables with the @code{far} attribute are addressed using a full
+32-bit address. Since this covers the entire memory space, this
+allows modules to make no assumptions about where variables might be
+stored.
+
+@item io
+@itemx io (@var{addr})
+Variables with the @code{io} attribute are used to address
+memory-mapped peripherals. If an address is specified, the variable
+is assigned that address, else it is not assigned an address (it is
+assumed some other module will assign an address). Example:
+
+@example
+int timer_count __attribute__((io(0x123)));
+@end example
+
+@item cb
+@itemx cb (@var{addr})
+Variables with the @code{cb} attribute are used to access the control
+bus, using special instructions. @code{addr} indicates the control bus
+address. Example:
+
+@example
+int cpu_clock __attribute__((cb(0x123)));
+@end example
+
+@end table
+
@anchor{i386 Variable Attributes}
@subsection i386 Variable Attributes
@code{__attribute__} instead of @code{__declspec} if you prefer, but
most Symbian OS code uses @code{__declspec}.)
+@anchor{MeP Type Attributes}
+@subsection MeP Type Attributes
+
+Many of the MeP variable attributes may be applied to types as well.
+Specifically, the @code{based}, @code{tiny}, @code{near}, and
+@code{far} attributes may be applied to either. The @code{io} and
+@code{cb} attributes may not be applied to types.
+
@anchor{i386 Type Attributes}
@subsection i386 Type Attributes
Language Extensions Specification. It is intended to support the
@code{__vector} keyword.
+@node Alignment
+@section Inquiring on Alignment of Types or Variables
+@cindex alignment
+@cindex type alignment
+@cindex variable alignment
+
+The keyword @code{__alignof__} allows you to inquire about how an object
+is aligned, or the minimum alignment usually required by a type. Its
+syntax is just like @code{sizeof}.
+
+For example, if the target machine requires a @code{double} value to be
+aligned on an 8-byte boundary, then @code{__alignof__ (double)} is 8.
+This is true on many RISC machines. On more traditional machine
+designs, @code{__alignof__ (double)} is 4 or even 2.
+
+Some machines never actually require alignment; they allow reference to any
+data type even at an odd address. For these machines, @code{__alignof__}
+reports the smallest alignment that GCC will give the data type, usually as
+mandated by the target ABI.
+
+If the operand of @code{__alignof__} is an lvalue rather than a type,
+its value is the required alignment for its type, taking into account
+any minimum alignment specified with GCC's @code{__attribute__}
+extension (@pxref{Variable Attributes}). For example, after this
+declaration:
+
+@smallexample
+struct foo @{ int x; char y; @} foo1;
+@end smallexample
+
+@noindent
+the value of @code{__alignof__ (foo1.y)} is 1, even though its actual
+alignment is probably 2 or 4, the same as @code{__alignof__ (int)}.
+
+It is an error to ask for the alignment of an incomplete type.
+
@node Inline
@section An Inline Function is As Fast As a Macro
GCC implements three different semantics of declaring a function
inline. One is available with @option{-std=gnu89} or
@option{-fgnu89-inline} or when @code{gnu_inline} attribute is present
-on all inline declarations, another when @option{-std=c99} or
-@option{-std=gnu99} (without @option{-fgnu89-inline}), and the third
+on all inline declarations, another when
+@option{-std=c99}, @option{-std=c1x},
+@option{-std=gnu99} or @option{-std=gnu1x}
+(without @option{-fgnu89-inline}), and the third
is used when compiling C++.
To declare a function inline, use the @code{inline} keyword in its
static inline int
inc (int *a)
@{
- (*a)++;
+ return (*a)++;
@}
@end smallexample
-If you are writing a header file to be included in ISO C89 programs, write
+If you are writing a header file to be included in ISO C90 programs, write
@code{__inline__} instead of @code{inline}. @xref{Alternate Keywords}.
The three types of inlining behave similarly in two important cases:
inline int
inc (int *a)
@{
- (*a)++;
+ return (*a)++;
@}
@end smallexample
inline void foo (const char) __attribute__((always_inline));
@end smallexample
-The remainder of this section is specific to GNU C89 inlining.
+The remainder of this section is specific to GNU C90 inlining.
@cindex non-static inline function
When an inline function is not @code{static}, then the compiler must assume
to be inlined. If any uses of the function remain, they will refer to
the single copy in the library.
+@node Volatiles
+@section When is a Volatile Object Accessed?
+@cindex accessing volatiles
+@cindex volatile read
+@cindex volatile write
+@cindex volatile access
+
+C has the concept of volatile objects. These are normally accessed by
+pointers and used for accessing hardware or inter-thread
+communication. The standard encourages compilers to refrain from
+optimizations concerning accesses to volatile objects, but leaves it
+implementation defined as to what constitutes a volatile access. The
+minimum requirement is that at a sequence point all previous accesses
+to volatile objects have stabilized and no subsequent accesses have
+occurred. Thus an implementation is free to reorder and combine
+volatile accesses which occur between sequence points, but cannot do
+so for accesses across a sequence point. The use of volatile does
+not allow you to violate the restriction on updating objects multiple
+times between two sequence points.
+
+Accesses to non-volatile objects are not ordered with respect to
+volatile accesses. You cannot use a volatile object as a memory
+barrier to order a sequence of writes to non-volatile memory. For
+instance:
+
+@smallexample
+int *ptr = @var{something};
+volatile int vobj;
+*ptr = @var{something};
+vobj = 1;
+@end smallexample
+
+Unless @var{*ptr} and @var{vobj} can be aliased, it is not guaranteed
+that the write to @var{*ptr} will have occurred by the time the update
+of @var{vobj} has happened. If you need this guarantee, you must use
+a stronger memory barrier such as:
+
+@smallexample
+int *ptr = @var{something};
+volatile int vobj;
+*ptr = @var{something};
+asm volatile ("" : : : "memory");
+vobj = 1;
+@end smallexample
+
+A scalar volatile object is read when it is accessed in a void context:
+
+@smallexample
+volatile int *src = @var{somevalue};
+*src;
+@end smallexample
+
+Such expressions are rvalues, and GCC implements this as a
+read of the volatile object being pointed to.
+
+Assignments are also expressions and have an rvalue. However when
+assigning to a scalar volatile, the volatile object is not reread,
+regardless of whether the assignment expression's rvalue is used or
+not. If the assignment's rvalue is used, the value is that assigned
+to the volatile object. For instance, there is no read of @var{vobj}
+in all the following cases:
+
+@smallexample
+int obj;
+volatile int vobj;
+vobj = @var{something};
+obj = vobj = @var{something};
+obj ? vobj = @var{onething} : vobj = @var{anotherthing};
+obj = (@var{something}, vobj = @var{anotherthing});
+@end smallexample
+
+If you need to read the volatile object after an assignment has
+occurred, you must use a separate expression with an intervening
+sequence point.
+
+As bitfields are not individually addressable, volatile bitfields may
+be implicitly read when written to, or when adjacent bitfields are
+accessed. Bitfield operations may be optimized such that adjacent
+bitfields are only partially accessed, if they straddle a storage unit
+boundary. For these reasons it is unwise to use volatile bitfields to
+access hardware.
+
@node Extended Asm
@section Assembler Instructions with C Expression Operands
@cindex extended @code{asm}
Speaking of labels, jumps from one @code{asm} to another are not
supported. The compiler's optimizers do not know about these jumps, and
therefore they cannot take account of them when deciding how to
-optimize.
+optimize. @xref{Extended asm with goto}.
@cindex macros containing @code{asm}
Usually the most convenient way to use these @code{asm} instructions is to
an assembler instruction access to the condition code left by previous
instructions.
+@anchor{Extended asm with goto}
+As of GCC version 4.5, @code{asm goto} may be used to have the assembly
+jump to one or more C labels. In this form, a fifth section after the
+clobber list contains a list of all C labels to which the assembly may jump.
+Each label operand is implicitly self-named. The @code{asm} is also assumed
+to fall through to the next statement.
+
+This form of @code{asm} is restricted to not have outputs. This is due
+to a internal restriction in the compiler that control transfer instructions
+cannot have outputs. This restriction on @code{asm goto} may be lifted
+in some future version of the compiler. In the mean time, @code{asm goto}
+may include a memory clobber, and so leave outputs in memory.
+
+@smallexample
+int frob(int x)
+@{
+ int y;
+ asm goto ("frob %%r5, %1; jc %l[error]; mov (%2), %%r5"
+ : : "r"(x), "r"(&y) : "r5", "memory" : error);
+ return y;
+ error:
+ return -1;
+@}
+@end smallexample
+
+In this (inefficient) example, the @code{frob} instruction sets the
+carry bit to indicate an error. The @code{jc} instruction detects
+this and branches to the @code{error} label. Finally, the output
+of the @code{frob} instruction (@code{%r5}) is stored into the memory
+for variable @code{y}, which is later read by the @code{return} statement.
+
+@smallexample
+void doit(void)
+@{
+ int i = 0;
+ asm goto ("mfsr %%r1, 123; jmp %%r1;"
+ ".pushsection doit_table;"
+ ".long %l0, %l1, %l2, %l3;"
+ ".popsection"
+ : : : "r1" : label1, label2, label3, label4);
+ __builtin_unreachable ();
+
+ label1:
+ f1();
+ return;
+ label2:
+ f2();
+ return;
+ label3:
+ i = 1;
+ label4:
+ f3(i);
+@}
+@end smallexample
+
+In this (also inefficient) example, the @code{mfsr} instruction reads
+an address from some out-of-band machine register, and the following
+@code{jmp} instruction branches to that address. The address read by
+the @code{mfsr} instruction is assumed to have been previously set via
+some application-specific mechanism to be one of the four values stored
+in the @code{doit_table} section. Finally, the @code{asm} is followed
+by a call to @code{__builtin_unreachable} to indicate that the @code{asm}
+does not in fact fall through.
+
+@smallexample
+#define TRACE1(NUM) \
+ do @{ \
+ asm goto ("0: nop;" \
+ ".pushsection trace_table;" \
+ ".long 0b, %l0;" \
+ ".popsection" \
+ : : : : trace#NUM); \
+ if (0) @{ trace#NUM: trace(); @} \
+ @} while (0)
+#define TRACE TRACE1(__COUNTER__)
+@end smallexample
+
+In this example (which in fact inspired the @code{asm goto} feature)
+we want on rare occasions to call the @code{trace} function; on other
+occasions we'd like to keep the overhead to the absolute minimum.
+The normal code path consists of a single @code{nop} instruction.
+However, we record the address of this @code{nop} together with the
+address of a label that calls the @code{trace} function. This allows
+the @code{nop} instruction to be patched at runtime to be an
+unconditional branch to the stored label. It is assumed that an
+optimizing compiler will move the labeled block out of line, to
+optimize the fall through path from the @code{asm}.
+
If you are writing a header file that should be includable in ISO C
programs, write @code{__asm__} instead of @code{asm}. @xref{Alternate
Keywords}.
including ISO C programs. The keywords @code{asm}, @code{typeof} and
@code{inline} are not available in programs compiled with
@option{-ansi} or @option{-std} (although @code{inline} can be used in a
-program compiled with @option{-std=c99}). The ISO C99 keyword
+program compiled with @option{-std=c99} or @option{-std=c1x}). The
+ISO C99 keyword
@code{restrict} is only available when @option{-std=gnu99} (which will
eventually be the default) or @option{-std=c99} (or the equivalent
-@option{-std=iso9899:1999}) is used.
+@option{-std=iso9899:1999}), or an option for a later standard
+version, is used.
The way to solve these problems is to put @samp{__} at the beginning and
end of each problematical keyword. For example, use @code{__asm__}
random value. In addition, @code{__builtin_frame_address} may be used
to determine if the top of the stack has been reached.
+Additional post-processing of the returned value may be needed, see
+@code{__builtin_extract_return_address}.
+
This function should only be used with a nonzero argument for debugging
purposes.
@end deftypefn
+@deftypefn {Built-in Function} {void *} __builtin_extract_return_address (void *@var{addr})
+The address as returned by @code{__builtin_return_address} may have to be fed
+through this function to get the actual encoded address. For example, on the
+31-bit S/390 platform the highest bit has to be masked out, or on SPARC
+platforms an offset has to be added for the true next instruction to be
+executed.
+
+If no fixup is needed, this function simply passes through @var{addr}.
+@end deftypefn
+
+@deftypefn {Built-in Function} {void *} __builtin_frob_return_address (void *@var{addr})
+This function does the reverse of @code{__builtin_extract_return_address}.
+@end deftypefn
+
@deftypefn {Built-in Function} {void *} __builtin_frame_address (unsigned int @var{level})
This function is similar to @code{__builtin_return_address}, but it
returns the address of the function frame rather than the return address
On some targets, the instruction set contains SIMD vector instructions that
operate on multiple values contained in one large register at the same time.
-For example, on the i386 the MMX, 3Dnow! and SSE extensions can be used
+For example, on the i386 the MMX, 3DNow!@: and SSE extensions can be used
this way.
The first step in using these extensions is to provide the necessary data
elements are the negative or complemented values of the corresponding
elements in the operand.
+In C it is possible to use shifting operators @code{<<}, @code{>>} on
+integer-type vectors. The operation is defined as following: @code{@{a0,
+a1, @dots{}, an@} >> @{b0, b1, @dots{}, bn@} == @{a0 >> b0, a1 >> b1,
+@dots{}, an >> bn@}}@. Vector operands must have the same number of
+elements. Additionally second operands can be a scalar integer in which
+case the scalar is converted to the type used by the vector operand (with
+possible truncation) and each element of this new vector is the scalar's
+value.
+Consider the following code.
+
+@smallexample
+typedef int v4si __attribute__ ((vector_size (16)));
+
+v4si a, b;
+
+b = a >> 1; /* b = a >> @{1,1,1,1@}; */
+@end smallexample
+
+In C vectors can be subscripted as if the vector were an array with
+the same number of elements and base type. Out of bound accesses
+invoke undefined behavior at runtime. Warnings for out of bound
+accesses for vector subscription can be enabled with
+@option{-Warray-bounds}.
+
You can declare variables and use them in function calls and returns, as
well as in assignments and some casts. You can specify a vector type as
a return type for a function. Vector types can also be used as function
@opindex ansi
@opindex std
-Outside strict ISO C mode (@option{-ansi}, @option{-std=c89} or
-@option{-std=c99}), the functions
+Outside strict ISO C mode (@option{-ansi}, @option{-std=c90},
+@option{-std=c99} or @option{-std=c1x}), the functions
@code{_exit}, @code{alloca}, @code{bcmp}, @code{bzero},
@code{dcgettext}, @code{dgettext}, @code{dremf}, @code{dreml},
@code{drem}, @code{exp10f}, @code{exp10l}, @code{exp10}, @code{ffsll},
@code{yn}
may be handled as built-in functions.
All these functions have corresponding versions
-prefixed with @code{__builtin_}, which may be used even in strict C89
+prefixed with @code{__builtin_}, which may be used even in strict C90
mode.
The ISO C99 functions
@code{tgamma}, @code{truncf}, @code{truncl}, @code{trunc},
@code{vfscanf}, @code{vscanf}, @code{vsnprintf} and @code{vsscanf}
are handled as built-in functions
-except in strict ISO C90 mode (@option{-ansi} or @option{-std=c89}).
+except in strict ISO C90 mode (@option{-ansi} or @option{-std=c90}).
There are also built-in versions of the ISO C99 functions
@code{acosf}, @code{acosl}, @code{asinf}, @code{asinl}, @code{atan2f},
@code{iswspace}, @code{iswupper}, @code{iswxdigit}, @code{towlower} and
@code{towupper}
are handled as built-in functions
-except in strict ISO C90 mode (@option{-ansi} or @option{-std=c89}).
+except in strict ISO C90 mode (@option{-ansi} or @option{-std=c90}).
The ISO C90 functions
@code{abort}, @code{abs}, @code{acos}, @code{asin}, @code{atan2},
You can use the built-in function @code{__builtin_choose_expr} to
evaluate code depending on the value of a constant expression. This
built-in function returns @var{exp1} if @var{const_exp}, which is an
-integer constant expression, is nonzero. Otherwise it returns 0.
+integer constant expression, is nonzero. Otherwise it returns @var{exp2}.
This built-in function is analogous to the @samp{? :} operator in C,
except that the expression returned has its type unaltered by promotion
* Alpha Built-in Functions::
* ARM iWMMXt Built-in Functions::
* ARM NEON Intrinsics::
+* AVR Built-in Functions::
* Blackfin Built-in Functions::
* FR-V Built-in Functions::
* X86 Built-in Functions::
* MIPS Loongson Built-in Functions::
* Other MIPS Built-in Functions::
* picoChip Built-in Functions::
-* PowerPC AltiVec Built-in Functions::
+* PowerPC AltiVec/VSX Built-in Functions::
+* RX Built-in Functions::
* SPARC VIS Built-in Functions::
* SPU Built-in Functions::
@end menu
@include arm-neon-intrinsics.texi
+@node AVR Built-in Functions
+@subsection AVR Built-in Functions
+
+For each built-in function for AVR, there is an equally named,
+uppercase built-in macro defined. That way users can easily query if
+or if not a specific built-in is implemented or not. For example, if
+@code{__builtin_avr_nop} is available the macro
+@code{__BUILTIN_AVR_NOP} is defined to @code{1} and undefined otherwise.
+
+The following built-in functions map to the respective machine
+instruction, i.e. @code{nop}, @code{sei}, @code{cli}, @code{sleep},
+@code{wdr}, @code{swap}, @code{fmul}, @code{fmuls}
+resp. @code{fmulsu}. The latter three are only available if the AVR
+device actually supports multiplication.
+
+@smallexample
+void __builtin_avr_nop (void)
+void __builtin_avr_sei (void)
+void __builtin_avr_cli (void)
+void __builtin_avr_sleep (void)
+void __builtin_avr_wdr (void)
+unsigned char __builtin_avr_swap (unsigned char)
+unsigned int __builtin_avr_fmul (unsigned char, unsigned char)
+int __builtin_avr_fmuls (char, char)
+int __builtin_avr_fmulsu (char, unsigned char)
+@end smallexample
+
+In order to delay execution for a specific number of cycles, GCC
+implements
+@smallexample
+void __builtin_avr_delay_cycles (unsigned long ticks)
+@end smallexample
+
+@code{ticks} is the number of ticks to delay execution. Note that this
+built-in does not take into account the effect of interrupts which
+might increase delay time. @code{ticks} must be a compile time
+integer constant; delays with a variable number of cycles are not supported.
+
@node Blackfin Built-in Functions
@subsection Blackfin Built-in Functions
vector of eight 8-bit integers. Some of the built-in functions operate on
MMX registers as a whole 64-bit entity, these use @code{V1DI} as their mode.
-If 3Dnow extensions are enabled, @code{V2SF} is used as a mode for a vector
+If 3DNow!@: extensions are enabled, @code{V2SF} is used as a mode for a vector
of two 32-bit floating point values.
If SSE extensions are enabled, @code{V4SF} is used for a vector of four 32-bit
Generates the @code{pclmulqdq} machine instruction.
@end table
+The following built-in function is available when @option{-mfsgsbase} is
+used. All of them generate the machine instruction that is part of the
+name.
+
+@smallexample
+unsigned int __builtin_ia32_rdfsbase32 (void)
+unsigned long long __builtin_ia32_rdfsbase64 (void)
+unsigned int __builtin_ia32_rdgsbase32 (void)
+unsigned long long __builtin_ia32_rdgsbase64 (void)
+void _writefsbase_u32 (unsigned int)
+void _writefsbase_u64 (unsigned long long)
+void _writegsbase_u32 (unsigned int)
+void _writegsbase_u64 (unsigned long long)
+@end smallexample
+
+The following built-in function is available when @option{-mrdrnd} is
+used. All of them generate the machine instruction that is part of the
+name.
+
+@smallexample
+unsigned int __builtin_ia32_rdrand16_step (unsigned short *)
+unsigned int __builtin_ia32_rdrand32_step (unsigned int *)
+unsigned int __builtin_ia32_rdrand64_step (unsigned long long *)
+@end smallexample
+
The following built-in functions are available when @option{-msse4a} is used.
All of them generate the machine instruction that is part of the name.
v2di __builtin_ia32_insertqi (v2di, v2di, const unsigned int, const unsigned int)
@end smallexample
-The following built-in functions are available when @option{-msse5} is used.
+The following built-in functions are available when @option{-mxop} is used.
+@smallexample
+v2df __builtin_ia32_vfrczpd (v2df)
+v4sf __builtin_ia32_vfrczps (v4sf)
+v2df __builtin_ia32_vfrczsd (v2df, v2df)
+v4sf __builtin_ia32_vfrczss (v4sf, v4sf)
+v4df __builtin_ia32_vfrczpd256 (v4df)
+v8sf __builtin_ia32_vfrczps256 (v8sf)
+v2di __builtin_ia32_vpcmov (v2di, v2di, v2di)
+v2di __builtin_ia32_vpcmov_v2di (v2di, v2di, v2di)
+v4si __builtin_ia32_vpcmov_v4si (v4si, v4si, v4si)
+v8hi __builtin_ia32_vpcmov_v8hi (v8hi, v8hi, v8hi)
+v16qi __builtin_ia32_vpcmov_v16qi (v16qi, v16qi, v16qi)
+v2df __builtin_ia32_vpcmov_v2df (v2df, v2df, v2df)
+v4sf __builtin_ia32_vpcmov_v4sf (v4sf, v4sf, v4sf)
+v4di __builtin_ia32_vpcmov_v4di256 (v4di, v4di, v4di)
+v8si __builtin_ia32_vpcmov_v8si256 (v8si, v8si, v8si)
+v16hi __builtin_ia32_vpcmov_v16hi256 (v16hi, v16hi, v16hi)
+v32qi __builtin_ia32_vpcmov_v32qi256 (v32qi, v32qi, v32qi)
+v4df __builtin_ia32_vpcmov_v4df256 (v4df, v4df, v4df)
+v8sf __builtin_ia32_vpcmov_v8sf256 (v8sf, v8sf, v8sf)
+v16qi __builtin_ia32_vpcomeqb (v16qi, v16qi)
+v8hi __builtin_ia32_vpcomeqw (v8hi, v8hi)
+v4si __builtin_ia32_vpcomeqd (v4si, v4si)
+v2di __builtin_ia32_vpcomeqq (v2di, v2di)
+v16qi __builtin_ia32_vpcomequb (v16qi, v16qi)
+v4si __builtin_ia32_vpcomequd (v4si, v4si)
+v2di __builtin_ia32_vpcomequq (v2di, v2di)
+v8hi __builtin_ia32_vpcomequw (v8hi, v8hi)
+v8hi __builtin_ia32_vpcomeqw (v8hi, v8hi)
+v16qi __builtin_ia32_vpcomfalseb (v16qi, v16qi)
+v4si __builtin_ia32_vpcomfalsed (v4si, v4si)
+v2di __builtin_ia32_vpcomfalseq (v2di, v2di)
+v16qi __builtin_ia32_vpcomfalseub (v16qi, v16qi)
+v4si __builtin_ia32_vpcomfalseud (v4si, v4si)
+v2di __builtin_ia32_vpcomfalseuq (v2di, v2di)
+v8hi __builtin_ia32_vpcomfalseuw (v8hi, v8hi)
+v8hi __builtin_ia32_vpcomfalsew (v8hi, v8hi)
+v16qi __builtin_ia32_vpcomgeb (v16qi, v16qi)
+v4si __builtin_ia32_vpcomged (v4si, v4si)
+v2di __builtin_ia32_vpcomgeq (v2di, v2di)
+v16qi __builtin_ia32_vpcomgeub (v16qi, v16qi)
+v4si __builtin_ia32_vpcomgeud (v4si, v4si)
+v2di __builtin_ia32_vpcomgeuq (v2di, v2di)
+v8hi __builtin_ia32_vpcomgeuw (v8hi, v8hi)
+v8hi __builtin_ia32_vpcomgew (v8hi, v8hi)
+v16qi __builtin_ia32_vpcomgtb (v16qi, v16qi)
+v4si __builtin_ia32_vpcomgtd (v4si, v4si)
+v2di __builtin_ia32_vpcomgtq (v2di, v2di)
+v16qi __builtin_ia32_vpcomgtub (v16qi, v16qi)
+v4si __builtin_ia32_vpcomgtud (v4si, v4si)
+v2di __builtin_ia32_vpcomgtuq (v2di, v2di)
+v8hi __builtin_ia32_vpcomgtuw (v8hi, v8hi)
+v8hi __builtin_ia32_vpcomgtw (v8hi, v8hi)
+v16qi __builtin_ia32_vpcomleb (v16qi, v16qi)
+v4si __builtin_ia32_vpcomled (v4si, v4si)
+v2di __builtin_ia32_vpcomleq (v2di, v2di)
+v16qi __builtin_ia32_vpcomleub (v16qi, v16qi)
+v4si __builtin_ia32_vpcomleud (v4si, v4si)
+v2di __builtin_ia32_vpcomleuq (v2di, v2di)
+v8hi __builtin_ia32_vpcomleuw (v8hi, v8hi)
+v8hi __builtin_ia32_vpcomlew (v8hi, v8hi)
+v16qi __builtin_ia32_vpcomltb (v16qi, v16qi)
+v4si __builtin_ia32_vpcomltd (v4si, v4si)
+v2di __builtin_ia32_vpcomltq (v2di, v2di)
+v16qi __builtin_ia32_vpcomltub (v16qi, v16qi)
+v4si __builtin_ia32_vpcomltud (v4si, v4si)
+v2di __builtin_ia32_vpcomltuq (v2di, v2di)
+v8hi __builtin_ia32_vpcomltuw (v8hi, v8hi)
+v8hi __builtin_ia32_vpcomltw (v8hi, v8hi)
+v16qi __builtin_ia32_vpcomneb (v16qi, v16qi)
+v4si __builtin_ia32_vpcomned (v4si, v4si)
+v2di __builtin_ia32_vpcomneq (v2di, v2di)
+v16qi __builtin_ia32_vpcomneub (v16qi, v16qi)
+v4si __builtin_ia32_vpcomneud (v4si, v4si)
+v2di __builtin_ia32_vpcomneuq (v2di, v2di)
+v8hi __builtin_ia32_vpcomneuw (v8hi, v8hi)
+v8hi __builtin_ia32_vpcomnew (v8hi, v8hi)
+v16qi __builtin_ia32_vpcomtrueb (v16qi, v16qi)
+v4si __builtin_ia32_vpcomtrued (v4si, v4si)
+v2di __builtin_ia32_vpcomtrueq (v2di, v2di)
+v16qi __builtin_ia32_vpcomtrueub (v16qi, v16qi)
+v4si __builtin_ia32_vpcomtrueud (v4si, v4si)
+v2di __builtin_ia32_vpcomtrueuq (v2di, v2di)
+v8hi __builtin_ia32_vpcomtrueuw (v8hi, v8hi)
+v8hi __builtin_ia32_vpcomtruew (v8hi, v8hi)
+v4si __builtin_ia32_vphaddbd (v16qi)
+v2di __builtin_ia32_vphaddbq (v16qi)
+v8hi __builtin_ia32_vphaddbw (v16qi)
+v2di __builtin_ia32_vphadddq (v4si)
+v4si __builtin_ia32_vphaddubd (v16qi)
+v2di __builtin_ia32_vphaddubq (v16qi)
+v8hi __builtin_ia32_vphaddubw (v16qi)
+v2di __builtin_ia32_vphaddudq (v4si)
+v4si __builtin_ia32_vphadduwd (v8hi)
+v2di __builtin_ia32_vphadduwq (v8hi)
+v4si __builtin_ia32_vphaddwd (v8hi)
+v2di __builtin_ia32_vphaddwq (v8hi)
+v8hi __builtin_ia32_vphsubbw (v16qi)
+v2di __builtin_ia32_vphsubdq (v4si)
+v4si __builtin_ia32_vphsubwd (v8hi)
+v4si __builtin_ia32_vpmacsdd (v4si, v4si, v4si)
+v2di __builtin_ia32_vpmacsdqh (v4si, v4si, v2di)
+v2di __builtin_ia32_vpmacsdql (v4si, v4si, v2di)
+v4si __builtin_ia32_vpmacssdd (v4si, v4si, v4si)
+v2di __builtin_ia32_vpmacssdqh (v4si, v4si, v2di)
+v2di __builtin_ia32_vpmacssdql (v4si, v4si, v2di)
+v4si __builtin_ia32_vpmacsswd (v8hi, v8hi, v4si)
+v8hi __builtin_ia32_vpmacssww (v8hi, v8hi, v8hi)
+v4si __builtin_ia32_vpmacswd (v8hi, v8hi, v4si)
+v8hi __builtin_ia32_vpmacsww (v8hi, v8hi, v8hi)
+v4si __builtin_ia32_vpmadcsswd (v8hi, v8hi, v4si)
+v4si __builtin_ia32_vpmadcswd (v8hi, v8hi, v4si)
+v16qi __builtin_ia32_vpperm (v16qi, v16qi, v16qi)
+v16qi __builtin_ia32_vprotb (v16qi, v16qi)
+v4si __builtin_ia32_vprotd (v4si, v4si)
+v2di __builtin_ia32_vprotq (v2di, v2di)
+v8hi __builtin_ia32_vprotw (v8hi, v8hi)
+v16qi __builtin_ia32_vpshab (v16qi, v16qi)
+v4si __builtin_ia32_vpshad (v4si, v4si)
+v2di __builtin_ia32_vpshaq (v2di, v2di)
+v8hi __builtin_ia32_vpshaw (v8hi, v8hi)
+v16qi __builtin_ia32_vpshlb (v16qi, v16qi)
+v4si __builtin_ia32_vpshld (v4si, v4si)
+v2di __builtin_ia32_vpshlq (v2di, v2di)
+v8hi __builtin_ia32_vpshlw (v8hi, v8hi)
+@end smallexample
+
+The following built-in functions are available when @option{-mfma4} is used.
All of them generate the machine instruction that is part of the name
with MMX registers.
@smallexample
-v2df __builtin_ia32_comeqpd (v2df, v2df)
-v2df __builtin_ia32_comeqps (v2df, v2df)
-v4sf __builtin_ia32_comeqsd (v4sf, v4sf)
-v4sf __builtin_ia32_comeqss (v4sf, v4sf)
-v2df __builtin_ia32_comfalsepd (v2df, v2df)
-v2df __builtin_ia32_comfalseps (v2df, v2df)
-v4sf __builtin_ia32_comfalsesd (v4sf, v4sf)
-v4sf __builtin_ia32_comfalsess (v4sf, v4sf)
-v2df __builtin_ia32_comgepd (v2df, v2df)
-v2df __builtin_ia32_comgeps (v2df, v2df)
-v4sf __builtin_ia32_comgesd (v4sf, v4sf)
-v4sf __builtin_ia32_comgess (v4sf, v4sf)
-v2df __builtin_ia32_comgtpd (v2df, v2df)
-v2df __builtin_ia32_comgtps (v2df, v2df)
-v4sf __builtin_ia32_comgtsd (v4sf, v4sf)
-v4sf __builtin_ia32_comgtss (v4sf, v4sf)
-v2df __builtin_ia32_comlepd (v2df, v2df)
-v2df __builtin_ia32_comleps (v2df, v2df)
-v4sf __builtin_ia32_comlesd (v4sf, v4sf)
-v4sf __builtin_ia32_comless (v4sf, v4sf)
-v2df __builtin_ia32_comltpd (v2df, v2df)
-v2df __builtin_ia32_comltps (v2df, v2df)
-v4sf __builtin_ia32_comltsd (v4sf, v4sf)
-v4sf __builtin_ia32_comltss (v4sf, v4sf)
-v2df __builtin_ia32_comnepd (v2df, v2df)
-v2df __builtin_ia32_comneps (v2df, v2df)
-v4sf __builtin_ia32_comnesd (v4sf, v4sf)
-v4sf __builtin_ia32_comness (v4sf, v4sf)
-v2df __builtin_ia32_comordpd (v2df, v2df)
-v2df __builtin_ia32_comordps (v2df, v2df)
-v4sf __builtin_ia32_comordsd (v4sf, v4sf)
-v4sf __builtin_ia32_comordss (v4sf, v4sf)
-v2df __builtin_ia32_comtruepd (v2df, v2df)
-v2df __builtin_ia32_comtrueps (v2df, v2df)
-v4sf __builtin_ia32_comtruesd (v4sf, v4sf)
-v4sf __builtin_ia32_comtruess (v4sf, v4sf)
-v2df __builtin_ia32_comueqpd (v2df, v2df)
-v2df __builtin_ia32_comueqps (v2df, v2df)
-v4sf __builtin_ia32_comueqsd (v4sf, v4sf)
-v4sf __builtin_ia32_comueqss (v4sf, v4sf)
-v2df __builtin_ia32_comugepd (v2df, v2df)
-v2df __builtin_ia32_comugeps (v2df, v2df)
-v4sf __builtin_ia32_comugesd (v4sf, v4sf)
-v4sf __builtin_ia32_comugess (v4sf, v4sf)
-v2df __builtin_ia32_comugtpd (v2df, v2df)
-v2df __builtin_ia32_comugtps (v2df, v2df)
-v4sf __builtin_ia32_comugtsd (v4sf, v4sf)
-v4sf __builtin_ia32_comugtss (v4sf, v4sf)
-v2df __builtin_ia32_comulepd (v2df, v2df)
-v2df __builtin_ia32_comuleps (v2df, v2df)
-v4sf __builtin_ia32_comulesd (v4sf, v4sf)
-v4sf __builtin_ia32_comuless (v4sf, v4sf)
-v2df __builtin_ia32_comultpd (v2df, v2df)
-v2df __builtin_ia32_comultps (v2df, v2df)
-v4sf __builtin_ia32_comultsd (v4sf, v4sf)
-v4sf __builtin_ia32_comultss (v4sf, v4sf)
-v2df __builtin_ia32_comunepd (v2df, v2df)
-v2df __builtin_ia32_comuneps (v2df, v2df)
-v4sf __builtin_ia32_comunesd (v4sf, v4sf)
-v4sf __builtin_ia32_comuness (v4sf, v4sf)
-v2df __builtin_ia32_comunordpd (v2df, v2df)
-v2df __builtin_ia32_comunordps (v2df, v2df)
-v4sf __builtin_ia32_comunordsd (v4sf, v4sf)
-v4sf __builtin_ia32_comunordss (v4sf, v4sf)
v2df __builtin_ia32_fmaddpd (v2df, v2df, v2df)
v4sf __builtin_ia32_fmaddps (v4sf, v4sf, v4sf)
v2df __builtin_ia32_fmaddsd (v2df, v2df, v2df)
v4sf __builtin_ia32_fnmsubps (v4sf, v4sf, v4sf)
v2df __builtin_ia32_fnmsubsd (v2df, v2df, v2df)
v4sf __builtin_ia32_fnmsubss (v4sf, v4sf, v4sf)
-v2df __builtin_ia32_frczpd (v2df)
-v4sf __builtin_ia32_frczps (v4sf)
-v2df __builtin_ia32_frczsd (v2df, v2df)
-v4sf __builtin_ia32_frczss (v4sf, v4sf)
-v2di __builtin_ia32_pcmov (v2di, v2di, v2di)
-v2di __builtin_ia32_pcmov_v2di (v2di, v2di, v2di)
-v4si __builtin_ia32_pcmov_v4si (v4si, v4si, v4si)
-v8hi __builtin_ia32_pcmov_v8hi (v8hi, v8hi, v8hi)
-v16qi __builtin_ia32_pcmov_v16qi (v16qi, v16qi, v16qi)
-v2df __builtin_ia32_pcmov_v2df (v2df, v2df, v2df)
-v4sf __builtin_ia32_pcmov_v4sf (v4sf, v4sf, v4sf)
-v16qi __builtin_ia32_pcomeqb (v16qi, v16qi)
-v8hi __builtin_ia32_pcomeqw (v8hi, v8hi)
-v4si __builtin_ia32_pcomeqd (v4si, v4si)
-v2di __builtin_ia32_pcomeqq (v2di, v2di)
-v16qi __builtin_ia32_pcomequb (v16qi, v16qi)
-v4si __builtin_ia32_pcomequd (v4si, v4si)
-v2di __builtin_ia32_pcomequq (v2di, v2di)
-v8hi __builtin_ia32_pcomequw (v8hi, v8hi)
-v8hi __builtin_ia32_pcomeqw (v8hi, v8hi)
-v16qi __builtin_ia32_pcomfalseb (v16qi, v16qi)
-v4si __builtin_ia32_pcomfalsed (v4si, v4si)
-v2di __builtin_ia32_pcomfalseq (v2di, v2di)
-v16qi __builtin_ia32_pcomfalseub (v16qi, v16qi)
-v4si __builtin_ia32_pcomfalseud (v4si, v4si)
-v2di __builtin_ia32_pcomfalseuq (v2di, v2di)
-v8hi __builtin_ia32_pcomfalseuw (v8hi, v8hi)
-v8hi __builtin_ia32_pcomfalsew (v8hi, v8hi)
-v16qi __builtin_ia32_pcomgeb (v16qi, v16qi)
-v4si __builtin_ia32_pcomged (v4si, v4si)
-v2di __builtin_ia32_pcomgeq (v2di, v2di)
-v16qi __builtin_ia32_pcomgeub (v16qi, v16qi)
-v4si __builtin_ia32_pcomgeud (v4si, v4si)
-v2di __builtin_ia32_pcomgeuq (v2di, v2di)
-v8hi __builtin_ia32_pcomgeuw (v8hi, v8hi)
-v8hi __builtin_ia32_pcomgew (v8hi, v8hi)
-v16qi __builtin_ia32_pcomgtb (v16qi, v16qi)
-v4si __builtin_ia32_pcomgtd (v4si, v4si)
-v2di __builtin_ia32_pcomgtq (v2di, v2di)
-v16qi __builtin_ia32_pcomgtub (v16qi, v16qi)
-v4si __builtin_ia32_pcomgtud (v4si, v4si)
-v2di __builtin_ia32_pcomgtuq (v2di, v2di)
-v8hi __builtin_ia32_pcomgtuw (v8hi, v8hi)
-v8hi __builtin_ia32_pcomgtw (v8hi, v8hi)
-v16qi __builtin_ia32_pcomleb (v16qi, v16qi)
-v4si __builtin_ia32_pcomled (v4si, v4si)
-v2di __builtin_ia32_pcomleq (v2di, v2di)
-v16qi __builtin_ia32_pcomleub (v16qi, v16qi)
-v4si __builtin_ia32_pcomleud (v4si, v4si)
-v2di __builtin_ia32_pcomleuq (v2di, v2di)
-v8hi __builtin_ia32_pcomleuw (v8hi, v8hi)
-v8hi __builtin_ia32_pcomlew (v8hi, v8hi)
-v16qi __builtin_ia32_pcomltb (v16qi, v16qi)
-v4si __builtin_ia32_pcomltd (v4si, v4si)
-v2di __builtin_ia32_pcomltq (v2di, v2di)
-v16qi __builtin_ia32_pcomltub (v16qi, v16qi)
-v4si __builtin_ia32_pcomltud (v4si, v4si)
-v2di __builtin_ia32_pcomltuq (v2di, v2di)
-v8hi __builtin_ia32_pcomltuw (v8hi, v8hi)
-v8hi __builtin_ia32_pcomltw (v8hi, v8hi)
-v16qi __builtin_ia32_pcomneb (v16qi, v16qi)
-v4si __builtin_ia32_pcomned (v4si, v4si)
-v2di __builtin_ia32_pcomneq (v2di, v2di)
-v16qi __builtin_ia32_pcomneub (v16qi, v16qi)
-v4si __builtin_ia32_pcomneud (v4si, v4si)
-v2di __builtin_ia32_pcomneuq (v2di, v2di)
-v8hi __builtin_ia32_pcomneuw (v8hi, v8hi)
-v8hi __builtin_ia32_pcomnew (v8hi, v8hi)
-v16qi __builtin_ia32_pcomtrueb (v16qi, v16qi)
-v4si __builtin_ia32_pcomtrued (v4si, v4si)
-v2di __builtin_ia32_pcomtrueq (v2di, v2di)
-v16qi __builtin_ia32_pcomtrueub (v16qi, v16qi)
-v4si __builtin_ia32_pcomtrueud (v4si, v4si)
-v2di __builtin_ia32_pcomtrueuq (v2di, v2di)
-v8hi __builtin_ia32_pcomtrueuw (v8hi, v8hi)
-v8hi __builtin_ia32_pcomtruew (v8hi, v8hi)
-v4df __builtin_ia32_permpd (v2df, v2df, v16qi)
-v4sf __builtin_ia32_permps (v4sf, v4sf, v16qi)
-v4si __builtin_ia32_phaddbd (v16qi)
-v2di __builtin_ia32_phaddbq (v16qi)
-v8hi __builtin_ia32_phaddbw (v16qi)
-v2di __builtin_ia32_phadddq (v4si)
-v4si __builtin_ia32_phaddubd (v16qi)
-v2di __builtin_ia32_phaddubq (v16qi)
-v8hi __builtin_ia32_phaddubw (v16qi)
-v2di __builtin_ia32_phaddudq (v4si)
-v4si __builtin_ia32_phadduwd (v8hi)
-v2di __builtin_ia32_phadduwq (v8hi)
-v4si __builtin_ia32_phaddwd (v8hi)
-v2di __builtin_ia32_phaddwq (v8hi)
-v8hi __builtin_ia32_phsubbw (v16qi)
-v2di __builtin_ia32_phsubdq (v4si)
-v4si __builtin_ia32_phsubwd (v8hi)
-v4si __builtin_ia32_pmacsdd (v4si, v4si, v4si)
-v2di __builtin_ia32_pmacsdqh (v4si, v4si, v2di)
-v2di __builtin_ia32_pmacsdql (v4si, v4si, v2di)
-v4si __builtin_ia32_pmacssdd (v4si, v4si, v4si)
-v2di __builtin_ia32_pmacssdqh (v4si, v4si, v2di)
-v2di __builtin_ia32_pmacssdql (v4si, v4si, v2di)
-v4si __builtin_ia32_pmacsswd (v8hi, v8hi, v4si)
-v8hi __builtin_ia32_pmacssww (v8hi, v8hi, v8hi)
-v4si __builtin_ia32_pmacswd (v8hi, v8hi, v4si)
-v8hi __builtin_ia32_pmacsww (v8hi, v8hi, v8hi)
-v4si __builtin_ia32_pmadcsswd (v8hi, v8hi, v4si)
-v4si __builtin_ia32_pmadcswd (v8hi, v8hi, v4si)
-v16qi __builtin_ia32_pperm (v16qi, v16qi, v16qi)
-v16qi __builtin_ia32_protb (v16qi, v16qi)
-v4si __builtin_ia32_protd (v4si, v4si)
-v2di __builtin_ia32_protq (v2di, v2di)
-v8hi __builtin_ia32_protw (v8hi, v8hi)
-v16qi __builtin_ia32_pshab (v16qi, v16qi)
-v4si __builtin_ia32_pshad (v4si, v4si)
-v2di __builtin_ia32_pshaq (v2di, v2di)
-v8hi __builtin_ia32_pshaw (v8hi, v8hi)
-v16qi __builtin_ia32_pshlb (v16qi, v16qi)
-v4si __builtin_ia32_pshld (v4si, v4si)
-v2di __builtin_ia32_pshlq (v2di, v2di)
-v8hi __builtin_ia32_pshlw (v8hi, v8hi)
-@end smallexample
-
-The following builtin-in functions are available when @option{-msse5}
-is used. The second argument must be an integer constant and generate
-the machine instruction that is part of the name with the @samp{_imm}
-suffix removed.
-
-@smallexample
-v16qi __builtin_ia32_protb_imm (v16qi, int)
-v4si __builtin_ia32_protd_imm (v4si, int)
-v2di __builtin_ia32_protq_imm (v2di, int)
-v8hi __builtin_ia32_protw_imm (v8hi, int)
+v2df __builtin_ia32_fmaddsubpd (v2df, v2df, v2df)
+v4sf __builtin_ia32_fmaddsubps (v4sf, v4sf, v4sf)
+v2df __builtin_ia32_fmsubaddpd (v2df, v2df, v2df)
+v4sf __builtin_ia32_fmsubaddps (v4sf, v4sf, v4sf)
+v4df __builtin_ia32_fmaddpd256 (v4df, v4df, v4df)
+v8sf __builtin_ia32_fmaddps256 (v8sf, v8sf, v8sf)
+v4df __builtin_ia32_fmsubpd256 (v4df, v4df, v4df)
+v8sf __builtin_ia32_fmsubps256 (v8sf, v8sf, v8sf)
+v4df __builtin_ia32_fnmaddpd256 (v4df, v4df, v4df)
+v8sf __builtin_ia32_fnmaddps256 (v8sf, v8sf, v8sf)
+v4df __builtin_ia32_fnmsubpd256 (v4df, v4df, v4df)
+v8sf __builtin_ia32_fnmsubps256 (v8sf, v8sf, v8sf)
+v4df __builtin_ia32_fmaddsubpd256 (v4df, v4df, v4df)
+v8sf __builtin_ia32_fmaddsubps256 (v8sf, v8sf, v8sf)
+v4df __builtin_ia32_fmsubaddpd256 (v4df, v4df, v4df)
+v8sf __builtin_ia32_fmsubaddps256 (v8sf, v8sf, v8sf)
+
+@end smallexample
+
+The following built-in functions are available when @option{-mlwp} is used.
+
+@smallexample
+void __builtin_ia32_llwpcb16 (void *);
+void __builtin_ia32_llwpcb32 (void *);
+void __builtin_ia32_llwpcb64 (void *);
+void * __builtin_ia32_llwpcb16 (void);
+void * __builtin_ia32_llwpcb32 (void);
+void * __builtin_ia32_llwpcb64 (void);
+void __builtin_ia32_lwpval16 (unsigned short, unsigned int, unsigned short)
+void __builtin_ia32_lwpval32 (unsigned int, unsigned int, unsigned int)
+void __builtin_ia32_lwpval64 (unsigned __int64, unsigned int, unsigned int)
+unsigned char __builtin_ia32_lwpins16 (unsigned short, unsigned int, unsigned short)
+unsigned char __builtin_ia32_lwpins32 (unsigned int, unsigned int, unsigned int)
+unsigned char __builtin_ia32_lwpins64 (unsigned __int64, unsigned int, unsigned int)
+@end smallexample
+
+The following built-in functions are available when @option{-mbmi} is used.
+All of them generate the machine instruction that is part of the name.
+@smallexample
+unsigned int __builtin_ia32_bextr_u32(unsigned int, unsigned int);
+unsigned long long __builtin_ia32_bextr_u64 (unsigned long long, unsigned long long);
+unsigned short __builtin_ia32_lzcnt_16(unsigned short);
+unsigned int __builtin_ia32_lzcnt_u32(unsigned int);
+unsigned long long __builtin_ia32_lzcnt_u64 (unsigned long long);
+@end smallexample
+
+The following built-in functions are available when @option{-mtbm} is used.
+Both of them generate the immediate form of the bextr machine instruction.
+@smallexample
+unsigned int __builtin_ia32_bextri_u32 (unsigned int, const unsigned int);
+unsigned long long __builtin_ia32_bextri_u64 (unsigned long long, const unsigned long long);
@end smallexample
+
The following built-in functions are available when @option{-m3dnow} is used.
All of them generate the machine instruction that is part of the name.
i32 __builtin_mips_lhx (void *, i32)
i32 __builtin_mips_lwx (void *, i32)
i32 __builtin_mips_bposge32 (void)
+a64 __builtin_mips_madd (a64, i32, i32);
+a64 __builtin_mips_maddu (a64, ui32, ui32);
+a64 __builtin_mips_msub (a64, i32, i32);
+a64 __builtin_mips_msubu (a64, ui32, ui32);
+a64 __builtin_mips_mult (i32, i32);
+a64 __builtin_mips_multu (ui32, ui32);
@end smallexample
The following built-in functions map directly to a particular MIPS DSP REV 2
i32 __builtin_mips_cmpgdu_le_qb (v4i8, v4i8);
a64 __builtin_mips_dpa_w_ph (a64, v2i16, v2i16);
a64 __builtin_mips_dps_w_ph (a64, v2i16, v2i16);
-a64 __builtin_mips_madd (a64, i32, i32);
-a64 __builtin_mips_maddu (a64, ui32, ui32);
-a64 __builtin_mips_msub (a64, i32, i32);
-a64 __builtin_mips_msubu (a64, ui32, ui32);
v2i16 __builtin_mips_mul_ph (v2i16, v2i16);
v2i16 __builtin_mips_mul_s_ph (v2i16, v2i16);
q31 __builtin_mips_mulq_rs_w (q31, q31);
v2q15 __builtin_mips_mulq_s_ph (v2q15, v2q15);
q31 __builtin_mips_mulq_s_w (q31, q31);
a64 __builtin_mips_mulsa_w_ph (a64, v2i16, v2i16);
-a64 __builtin_mips_mult (i32, i32);
-a64 __builtin_mips_multu (ui32, ui32);
v4i8 __builtin_mips_precr_qb_ph (v2i16, v2i16);
v2i16 __builtin_mips_precr_sra_ph_w (i32, i32, imm0_31);
v2i16 __builtin_mips_precr_sra_r_ph_w (i32, i32, imm0_31);
@item int __builtin_subs (int @var{x}, int @var{y})
Saturating subtraction. Return the result of subtracting @var{y} from
-@var{x}, storing the value -32768 if the result overflows.
+@var{x}, storing the value @minus{}32768 if the result overflows.
@item void __builtin_halt (void)
Halt. The processor will stop execution. This built-in is useful for
when this function is available.
@end table
-@node PowerPC AltiVec Built-in Functions
+@node PowerPC AltiVec/VSX Built-in Functions
@subsection PowerPC AltiVec Built-in Functions
GCC provides an interface for the PowerPC family of processors to access
vector float
@end smallexample
+If @option{-mvsx} is used the following additional vector types are
+implemented.
+
+@smallexample
+vector unsigned long
+vector signed long
+vector double
+@end smallexample
+
+The long types are only implemented for 64-bit code generation, and
+the long type is only used in the floating point/integer conversion
+instructions.
+
GCC's implementation of the high-level language interface available from
C and C++ code differs from Motorola's documentation in several ways.
vector unsigned char vec_vavgub (vector unsigned char,
vector unsigned char);
+vector float vec_copysign (vector float);
+
vector float vec_ceil (vector float);
vector signed int vec_cmpb (vector float, vector float);
vector float vec_round (vector float);
+vector float vec_recip (vector float, vector float);
+
+vector float vec_rsqrt (vector float);
+
vector float vec_rsqrte (vector float);
vector float vec_sel (vector float, vector float, vector bool int);
int vec_any_out (vector float, vector float);
@end smallexample
+If the vector/scalar (VSX) instruction set is available, the following
+additional functions are available:
+
+@smallexample
+vector double vec_abs (vector double);
+vector double vec_add (vector double, vector double);
+vector double vec_and (vector double, vector double);
+vector double vec_and (vector double, vector bool long);
+vector double vec_and (vector bool long, vector double);
+vector double vec_andc (vector double, vector double);
+vector double vec_andc (vector double, vector bool long);
+vector double vec_andc (vector bool long, vector double);
+vector double vec_ceil (vector double);
+vector bool long vec_cmpeq (vector double, vector double);
+vector bool long vec_cmpge (vector double, vector double);
+vector bool long vec_cmpgt (vector double, vector double);
+vector bool long vec_cmple (vector double, vector double);
+vector bool long vec_cmplt (vector double, vector double);
+vector float vec_div (vector float, vector float);
+vector double vec_div (vector double, vector double);
+vector double vec_floor (vector double);
+vector double vec_ld (int, const vector double *);
+vector double vec_ld (int, const double *);
+vector double vec_ldl (int, const vector double *);
+vector double vec_ldl (int, const double *);
+vector unsigned char vec_lvsl (int, const volatile double *);
+vector unsigned char vec_lvsr (int, const volatile double *);
+vector double vec_madd (vector double, vector double, vector double);
+vector double vec_max (vector double, vector double);
+vector double vec_min (vector double, vector double);
+vector float vec_msub (vector float, vector float, vector float);
+vector double vec_msub (vector double, vector double, vector double);
+vector float vec_mul (vector float, vector float);
+vector double vec_mul (vector double, vector double);
+vector float vec_nearbyint (vector float);
+vector double vec_nearbyint (vector double);
+vector float vec_nmadd (vector float, vector float, vector float);
+vector double vec_nmadd (vector double, vector double, vector double);
+vector double vec_nmsub (vector double, vector double, vector double);
+vector double vec_nor (vector double, vector double);
+vector double vec_or (vector double, vector double);
+vector double vec_or (vector double, vector bool long);
+vector double vec_or (vector bool long, vector double);
+vector double vec_perm (vector double,
+ vector double,
+ vector unsigned char);
+vector double vec_rint (vector double);
+vector double vec_recip (vector double, vector double);
+vector double vec_rsqrt (vector double);
+vector double vec_rsqrte (vector double);
+vector double vec_sel (vector double, vector double, vector bool long);
+vector double vec_sel (vector double, vector double, vector unsigned long);
+vector double vec_sub (vector double, vector double);
+vector float vec_sqrt (vector float);
+vector double vec_sqrt (vector double);
+void vec_st (vector double, int, vector double *);
+void vec_st (vector double, int, double *);
+vector double vec_trunc (vector double);
+vector double vec_xor (vector double, vector double);
+vector double vec_xor (vector double, vector bool long);
+vector double vec_xor (vector bool long, vector double);
+int vec_all_eq (vector double, vector double);
+int vec_all_ge (vector double, vector double);
+int vec_all_gt (vector double, vector double);
+int vec_all_le (vector double, vector double);
+int vec_all_lt (vector double, vector double);
+int vec_all_nan (vector double);
+int vec_all_ne (vector double, vector double);
+int vec_all_nge (vector double, vector double);
+int vec_all_ngt (vector double, vector double);
+int vec_all_nle (vector double, vector double);
+int vec_all_nlt (vector double, vector double);
+int vec_all_numeric (vector double);
+int vec_any_eq (vector double, vector double);
+int vec_any_ge (vector double, vector double);
+int vec_any_gt (vector double, vector double);
+int vec_any_le (vector double, vector double);
+int vec_any_lt (vector double, vector double);
+int vec_any_nan (vector double);
+int vec_any_ne (vector double, vector double);
+int vec_any_nge (vector double, vector double);
+int vec_any_ngt (vector double, vector double);
+int vec_any_nle (vector double, vector double);
+int vec_any_nlt (vector double, vector double);
+int vec_any_numeric (vector double);
+
+vector double vec_vsx_ld (int, const vector double *);
+vector double vec_vsx_ld (int, const double *);
+vector float vec_vsx_ld (int, const vector float *);
+vector float vec_vsx_ld (int, const float *);
+vector bool int vec_vsx_ld (int, const vector bool int *);
+vector signed int vec_vsx_ld (int, const vector signed int *);
+vector signed int vec_vsx_ld (int, const int *);
+vector signed int vec_vsx_ld (int, const long *);
+vector unsigned int vec_vsx_ld (int, const vector unsigned int *);
+vector unsigned int vec_vsx_ld (int, const unsigned int *);
+vector unsigned int vec_vsx_ld (int, const unsigned long *);
+vector bool short vec_vsx_ld (int, const vector bool short *);
+vector pixel vec_vsx_ld (int, const vector pixel *);
+vector signed short vec_vsx_ld (int, const vector signed short *);
+vector signed short vec_vsx_ld (int, const short *);
+vector unsigned short vec_vsx_ld (int, const vector unsigned short *);
+vector unsigned short vec_vsx_ld (int, const unsigned short *);
+vector bool char vec_vsx_ld (int, const vector bool char *);
+vector signed char vec_vsx_ld (int, const vector signed char *);
+vector signed char vec_vsx_ld (int, const signed char *);
+vector unsigned char vec_vsx_ld (int, const vector unsigned char *);
+vector unsigned char vec_vsx_ld (int, const unsigned char *);
+
+void vec_vsx_st (vector double, int, vector double *);
+void vec_vsx_st (vector double, int, double *);
+void vec_vsx_st (vector float, int, vector float *);
+void vec_vsx_st (vector float, int, float *);
+void vec_vsx_st (vector signed int, int, vector signed int *);
+void vec_vsx_st (vector signed int, int, int *);
+void vec_vsx_st (vector unsigned int, int, vector unsigned int *);
+void vec_vsx_st (vector unsigned int, int, unsigned int *);
+void vec_vsx_st (vector bool int, int, vector bool int *);
+void vec_vsx_st (vector bool int, int, unsigned int *);
+void vec_vsx_st (vector bool int, int, int *);
+void vec_vsx_st (vector signed short, int, vector signed short *);
+void vec_vsx_st (vector signed short, int, short *);
+void vec_vsx_st (vector unsigned short, int, vector unsigned short *);
+void vec_vsx_st (vector unsigned short, int, unsigned short *);
+void vec_vsx_st (vector bool short, int, vector bool short *);
+void vec_vsx_st (vector bool short, int, unsigned short *);
+void vec_vsx_st (vector pixel, int, vector pixel *);
+void vec_vsx_st (vector pixel, int, unsigned short *);
+void vec_vsx_st (vector pixel, int, short *);
+void vec_vsx_st (vector bool short, int, short *);
+void vec_vsx_st (vector signed char, int, vector signed char *);
+void vec_vsx_st (vector signed char, int, signed char *);
+void vec_vsx_st (vector unsigned char, int, vector unsigned char *);
+void vec_vsx_st (vector unsigned char, int, unsigned char *);
+void vec_vsx_st (vector bool char, int, vector bool char *);
+void vec_vsx_st (vector bool char, int, unsigned char *);
+void vec_vsx_st (vector bool char, int, signed char *);
+@end smallexample
+
+Note that the @samp{vec_ld} and @samp{vec_st} builtins will always
+generate the Altivec @samp{LVX} and @samp{STVX} instructions even
+if the VSX instruction set is available. The @samp{vec_vsx_ld} and
+@samp{vec_vsx_st} builtins will always generate the VSX @samp{LXVD2X},
+@samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions.
+
+GCC provides a few other builtins on Powerpc to access certain instructions:
+@smallexample
+float __builtin_recipdivf (float, float);
+float __builtin_rsqrtf (float);
+double __builtin_recipdiv (double, double);
+double __builtin_rsqrt (double);
+long __builtin_bpermd (long, long);
+int __builtin_bswap16 (int);
+@end smallexample
+
+The @code{vec_rsqrt}, @code{__builtin_rsqrt}, and
+@code{__builtin_rsqrtf} functions generate multiple instructions to
+implement the reciprocal sqrt functionality using reciprocal sqrt
+estimate instructions.
+
+The @code{__builtin_recipdiv}, and @code{__builtin_recipdivf}
+functions generate multiple instructions to implement division using
+the reciprocal estimate instructions.
+
+@node RX Built-in Functions
+@subsection RX Built-in Functions
+GCC supports some of the RX instructions which cannot be expressed in
+the C programming language via the use of built-in functions. The
+following functions are supported:
+
+@deftypefn {Built-in Function} void __builtin_rx_brk (void)
+Generates the @code{brk} machine instruction.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_clrpsw (int)
+Generates the @code{clrpsw} machine instruction to clear the specified
+bit in the processor status word.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_int (int)
+Generates the @code{int} machine instruction to generate an interrupt
+with the specified value.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_machi (int, int)
+Generates the @code{machi} machine instruction to add the result of
+multiplying the top 16-bits of the two arguments into the
+accumulator.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_maclo (int, int)
+Generates the @code{maclo} machine instruction to add the result of
+multiplying the bottom 16-bits of the two arguments into the
+accumulator.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_mulhi (int, int)
+Generates the @code{mulhi} machine instruction to place the result of
+multiplying the top 16-bits of the two arguments into the
+accumulator.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_mullo (int, int)
+Generates the @code{mullo} machine instruction to place the result of
+multiplying the bottom 16-bits of the two arguments into the
+accumulator.
+@end deftypefn
+
+@deftypefn {Built-in Function} int __builtin_rx_mvfachi (void)
+Generates the @code{mvfachi} machine instruction to read the top
+32-bits of the accumulator.
+@end deftypefn
+
+@deftypefn {Built-in Function} int __builtin_rx_mvfacmi (void)
+Generates the @code{mvfacmi} machine instruction to read the middle
+32-bits of the accumulator.
+@end deftypefn
+
+@deftypefn {Built-in Function} int __builtin_rx_mvfc (int)
+Generates the @code{mvfc} machine instruction which reads the control
+register specified in its argument and returns its value.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_mvtachi (int)
+Generates the @code{mvtachi} machine instruction to set the top
+32-bits of the accumulator.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_mvtaclo (int)
+Generates the @code{mvtaclo} machine instruction to set the bottom
+32-bits of the accumulator.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_mvtc (int reg, int val)
+Generates the @code{mvtc} machine instruction which sets control
+register number @code{reg} to @code{val}.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_mvtipl (int)
+Generates the @code{mvtipl} machine instruction set the interrupt
+priority level.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_racw (int)
+Generates the @code{racw} machine instruction to round the accumulator
+according to the specified mode.
+@end deftypefn
+
+@deftypefn {Built-in Function} int __builtin_rx_revw (int)
+Generates the @code{revw} machine instruction which swaps the bytes in
+the argument so that bits 0--7 now occupy bits 8--15 and vice versa,
+and also bits 16--23 occupy bits 24--31 and vice versa.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_rmpa (void)
+Generates the @code{rmpa} machine instruction which initiates a
+repeated multiply and accumulate sequence.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_round (float)
+Generates the @code{round} machine instruction which returns the
+floating point argument rounded according to the current rounding mode
+set in the floating point status word register.
+@end deftypefn
+
+@deftypefn {Built-in Function} int __builtin_rx_sat (int)
+Generates the @code{sat} machine instruction which returns the
+saturated value of the argument.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_setpsw (int)
+Generates the @code{setpsw} machine instruction to set the specified
+bit in the processor status word.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_wait (void)
+Generates the @code{wait} machine instruction.
+@end deftypefn
+
@node SPARC VIS Built-in Functions
@subsection SPARC VIS Built-in Functions
@menu
* Solaris Format Checks::
+* Darwin Format Checks::
@end menu
@node Solaris Format Checks
conversions, and the two-argument @code{%b} conversion for displaying
bit-fields. See the Solaris man page for @code{cmn_err} for more information.
+@node Darwin Format Checks
+@subsection Darwin Format Checks
+
+Darwin targets support the @code{CFString} (or @code{__CFString__}) in the format
+attribute context. Declarations made with such attribution will be parsed for correct syntax
+and format argument types. However, parsing of the format string itself is currently undefined
+and will not be carried out by this version of the compiler.
+
+Additionally, @code{CFStringRefs} (defined by the @code{CoreFoundation} headers) may
+also be used as format arguments. Note that the relevant headers are only likely to be
+available on Darwin (OSX) installations. On such installations, the XCode and system
+documentation provide descriptions of @code{CFString}, @code{CFStringRefs} and
+associated functions.
+
@node Pragmas
@section Pragmas Accepted by GCC
@cindex pragmas
-@cindex #pragma
+@cindex @code{#pragma}
GCC supports several types of pragmas, primarily in order to compile
code originally written for other compilers. Note that in general
@menu
* ARM Pragmas::
* M32C Pragmas::
+* MeP Pragmas::
* RS/6000 and PowerPC Pragmas::
* Darwin Pragmas::
* Solaris Pragmas::
@subsection M32C Pragmas
@table @code
-@item memregs @var{number}
+@item GCC memregs @var{number}
@cindex pragma, memregs
-Overrides the command line option @code{-memregs=} for the current
+Overrides the command-line option @code{-memregs=} for the current
file. Use with care! This pragma must be before any function in the
file, and mixing different memregs values in different objects may
make them incompatible. This pragma is useful when a
performance-critical function uses a memreg for temporary values,
as it may allow you to reduce the number of memregs used.
+@item ADDRESS @var{name} @var{address}
+@cindex pragma, address
+For any declared symbols matching @var{name}, this does three things
+to that symbol: it forces the symbol to be located at the given
+address (a number), it forces the symbol to be volatile, and it
+changes the symbol's scope to be static. This pragma exists for
+compatibility with other compilers, but note that the common
+@code{1234H} numeric syntax is not supported (use @code{0x1234}
+instead). Example:
+
+@example
+#pragma ADDRESS port3 0x103
+char port3;
+@end example
+
+@end table
+
+@node MeP Pragmas
+@subsection MeP Pragmas
+
+@table @code
+
+@item custom io_volatile (on|off)
+@cindex pragma, custom io_volatile
+Overrides the command line option @code{-mio-volatile} for the current
+file. Note that for compatibility with future GCC releases, this
+option should only be used once before any @code{io} variables in each
+file.
+
+@item GCC coprocessor available @var{registers}
+@cindex pragma, coprocessor available
+Specifies which coprocessor registers are available to the register
+allocator. @var{registers} may be a single register, register range
+separated by ellipses, or comma-separated list of those. Example:
+
+@example
+#pragma GCC coprocessor available $c0...$c10, $c28
+@end example
+
+@item GCC coprocessor call_saved @var{registers}
+@cindex pragma, coprocessor call_saved
+Specifies which coprocessor registers are to be saved and restored by
+any function using them. @var{registers} may be a single register,
+register range separated by ellipses, or comma-separated list of
+those. Example:
+
+@example
+#pragma GCC coprocessor call_saved $c4...$c6, $c31
+@end example
+
+@item GCC coprocessor subclass '(A|B|C|D)' = @var{registers}
+@cindex pragma, coprocessor subclass
+Creates and defines a register class. These register classes can be
+used by inline @code{asm} constructs. @var{registers} may be a single
+register, register range separated by ellipses, or comma-separated
+list of those. Example:
+
+@example
+#pragma GCC coprocessor subclass 'B' = $c2, $c4, $c6
+
+asm ("cpfoo %0" : "=B" (x));
+@end example
+
+@item GCC disinterrupt @var{name} , @var{name} @dots{}
+@cindex pragma, disinterrupt
+For the named functions, the compiler adds code to disable interrupts
+for the duration of those functions. Any functions so named, which
+are not encountered in the source, cause a warning that the pragma was
+not used. Examples:
+
+@example
+#pragma disinterrupt foo
+#pragma disinterrupt bar, grill
+int foo () @{ @dots{} @}
+@end example
+
+@item GCC call @var{name} , @var{name} @dots{}
+@cindex pragma, call
+For the named functions, the compiler always uses a register-indirect
+call model when calling the named functions. Examples:
+
+@example
+extern int foo ();
+#pragma call foo
+@end example
+
@end table
@node RS/6000 and PowerPC Pragmas
For compatibility with the Solaris and Tru64 UNIX system headers, GCC
supports two @code{#pragma} directives which change the name used in
-assembly for a given declaration. These pragmas are only available on
-platforms whose system headers need them. To get this effect on all
-platforms supported by GCC, use the asm labels extension (@pxref{Asm
+assembly for a given declaration. @code{#pragma extern_prefix} is only
+available on platforms whose system headers need it. To get this effect
+on all platforms supported by GCC, use the asm labels extension (@pxref{Asm
Labels}).
@table @code
This pragma gives the C function @var{oldname} the assembly symbol
@var{newname}. The preprocessor macro @code{__PRAGMA_REDEFINE_EXTNAME}
-will be defined if this pragma is available (currently only on
-Solaris).
+will be defined if this pragma is available (currently on all platforms).
@item extern_prefix @var{string}
@cindex pragma, extern_prefix
@enumerate
@item @code{#pragma pack(@var{n})} simply sets the new alignment.
@item @code{#pragma pack()} sets the alignment to the one that was in
-effect when compilation started (see also command line option
-@option{-fpack-struct[=<n>]} @pxref{Code Gen Options}).
+effect when compilation started (see also command-line option
+@option{-fpack-struct[=@var{n}]} @pxref{Code Gen Options}).
@item @code{#pragma pack(push[,@var{n}])} pushes the current alignment
setting on an internal stack and then optionally sets the new alignment.
@item @code{#pragma pack(pop)} restores the alignment setting to the one
@cindex pragma, weak
This pragma declares @var{symbol} to be weak, as if the declaration
had the attribute of the same name. The pragma may appear before
-or after the declaration of @var{symbol}, but must appear before
-either its first use or its definition. It is not an error for
+or after the declaration of @var{symbol}. It is not an error for
@var{symbol} to never be defined at all.
@item #pragma weak @var{symbol1} = @var{symbol2}
@var{kind} is @samp{error} to treat this diagnostic as an error,
@samp{warning} to treat it like a warning (even if @option{-Werror} is
in effect), or @samp{ignored} if the diagnostic is to be ignored.
-@var{option} is a double quoted string which matches the command line
+@var{option} is a double quoted string which matches the command-line
option.
@example
#pragma GCC diagnostic ignored "-Wformat"
@end example
-Note that these pragmas override any command line options. Also,
-while it is syntactically valid to put these pragmas anywhere in your
-sources, the only supported location for them is before any data or
-functions are defined. Doing otherwise may result in unpredictable
-results depending on how the optimizer manages your sources. If the
-same option is listed multiple times, the last one specified is the
-one that is in effect. This pragma is not intended to be a general
-purpose replacement for command line options, but for implementing
-strict control over project policies.
+Note that these pragmas override any command-line options. GCC keeps
+track of the location of each pragma, and issues diagnostics according
+to the state as of that point in the source file. Thus, pragmas occurring
+after a line do not affect diagnostics caused by that line.
+
+@item #pragma GCC diagnostic push
+@itemx #pragma GCC diagnostic pop
+
+Causes GCC to remember the state of the diagnostics as of each
+@code{push}, and restore to that point at each @code{pop}. If a
+@code{pop} has no matching @code{push}, the command line options are
+restored.
+
+@example
+#pragma GCC diagnostic error "-Wuninitialized"
+ foo(a); /* error is given for this one */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wuninitialized"
+ foo(b); /* no diagnostic for this one */
+#pragma GCC diagnostic pop
+ foo(c); /* error is given for this one */
+#pragma GCC diagnostic pop
+ foo(d); /* depends on command line options */
+@end example
@end table
@xref{Function Attributes}, for more information about the
@code{target} attribute and the attribute syntax.
-The @samp{#pragma GCC target} pragma is not implemented in GCC
-versions earlier than 4.4, and is currently only implemented for the
-386 and x86_64 backends.
+The @code{#pragma GCC target} attribute is not implemented in GCC versions earlier
+than 4.4 for the i386/x86_64 and 4.6 for the PowerPC backends. At
+present, it is not implemented for other backends.
@end table
@table @code
@node Unnamed Fields
@section Unnamed struct/union fields within structs/unions
-@cindex struct
-@cindex union
+@cindex @code{struct}
+@cindex @code{union}
-For compatibility with other compilers, GCC allows you to define
+As permitted by ISO C1X and for compatibility with other compilers,
+GCC allows you to define
a structure or union that contains, as fields, structures and unions
without names. For example:
@end smallexample
It is ambiguous which @code{a} is being referred to with @samp{foo.a}.
-Such constructs are not supported and must be avoided. In the future,
-such constructs may be detected and treated as compilation errors.
+The compiler gives errors for such constructs.
@opindex fms-extensions
Unless @option{-fms-extensions} is used, the unnamed field must be a
@samp{struct foo;}, or a reference to a @code{typedef} name for a
previously defined structure or union type.
+@opindex fplan9-extensions
+The option @option{-fplan9-extensions} enables
+@option{-fms-extensions} as well as two other extensions. First, a
+pointer to a structure is automatically converted to a pointer to an
+anonymous field for assignments and function calls. For example:
+
+@smallexample
+struct s1 @{ int a; @};
+struct s2 @{ struct s1; @};
+extern void f1 (struct s1 *);
+void f2 (struct s2 *p) @{ f1 (p); @}
+@end smallexample
+
+In the call to @code{f1} inside @code{f2}, the pointer @code{p} is
+converted into a pointer to the anonymous field.
+
+Second, when the type of an anonymous field is a @code{typedef} for a
+@code{struct} or @code{union}, code may refer to the field using the
+name of the @code{typedef}.
+
+@smallexample
+typedef struct @{ int a; @} s1;
+struct s2 @{ s1; @};
+s1 f1 (struct s2 *p) @{ return p->s1; @}
+@end smallexample
+
+These usages are only permitted when they are not ambiguous.
+
@node Thread-Local
@section Thread-Local Storage
@cindex Thread-Local Storage
@cindex @acronym{TLS}
-@cindex __thread
+@cindex @code{__thread}
Thread-local storage (@acronym{TLS}) is a mechanism by which variables
are allocated such that there is one instance of the variable per extant
be a @var{constant-expression}, as defined in 5.19.2 of the ANSI/ISO C++
standard.
-See @uref{http://people.redhat.com/drepper/tls.pdf,
+See @uref{http://www.akkadia.org/drepper/tls.pdf,
ELF Handling For Thread-Local Storage} for a detailed explanation of
the four thread-local storage addressing models, and how the run-time
is expected to function.
Predefined Macros,cpp,The GNU C Preprocessor}).
@menu
-* Volatiles:: What constitutes an access to a volatile object.
+* C++ Volatiles:: What constitutes an access to a volatile object.
* Restricted Pointers:: C99 restricted pointers and references.
* Vague Linkage:: Where G++ puts inlines, vtables and such.
* C++ Interface:: You can use a single C++ header file for both
* Backwards Compatibility:: Compatibilities with earlier definitions of C++.
@end menu
-@node Volatiles
-@section When is a Volatile Object Accessed?
+@node C++ Volatiles
+@section When is a Volatile C++ Object Accessed?
@cindex accessing volatiles
@cindex volatile read
@cindex volatile write
@cindex volatile access
-Both the C and C++ standard have the concept of volatile objects. These
-are normally accessed by pointers and used for accessing hardware. The
-standards encourage compilers to refrain from optimizations concerning
-accesses to volatile objects. The C standard leaves it implementation
-defined as to what constitutes a volatile access. The C++ standard omits
-to specify this, except to say that C++ should behave in a similar manner
-to C with respect to volatiles, where possible. The minimum either
-standard specifies is that at a sequence point all previous accesses to
-volatile objects have stabilized and no subsequent accesses have
-occurred. Thus an implementation is free to reorder and combine
-volatile accesses which occur between sequence points, but cannot do so
-for accesses across a sequence point. The use of volatiles does not
-allow you to violate the restriction on updating objects multiple times
-within a sequence point.
-
-@xref{Qualifiers implementation, , Volatile qualifier and the C compiler}.
+The C++ standard differs from the C standard in its treatment of
+volatile objects. It fails to specify what constitutes a volatile
+access, except to say that C++ should behave in a similar manner to C
+with respect to volatiles, where possible. However, the different
+lvalueness of expressions between C and C++ complicate the behavior.
+G++ behaves the same as GCC for volatile access, @xref{C
+Extensions,,Volatiles}, for a description of GCC's behavior.
-The behavior differs slightly between C and C++ in the non-obvious cases:
+The C and C++ language specifications differ when an object is
+accessed in a void context:
@smallexample
volatile int *src = @var{somevalue};
*src;
@end smallexample
-With C, such expressions are rvalues, and GCC interprets this either as a
-read of the volatile object being pointed to or only as request to evaluate
-the side-effects. The C++ standard specifies that such expressions do not
-undergo lvalue to rvalue conversion, and that the type of the dereferenced
-object may be incomplete. The C++ standard does not specify explicitly
-that it is this lvalue to rvalue conversion which may be responsible for
-causing an access. However, there is reason to believe that it is,
-because otherwise certain simple expressions become undefined. However,
-because it would surprise most programmers, G++ treats dereferencing a
-pointer to volatile object of complete type when the value is unused as
-GCC would do for an equivalent type in C@. When the object has incomplete
-type, G++ issues a warning; if you wish to force an error, you must
-force a conversion to rvalue with, for instance, a static cast.
+The C++ standard specifies that such expressions do not undergo lvalue
+to rvalue conversion, and that the type of the dereferenced object may
+be incomplete. The C++ standard does not specify explicitly that it
+is lvalue to rvalue conversion which is responsible for causing an
+access. There is reason to believe that it is, because otherwise
+certain simple expressions become undefined. However, because it
+would surprise most programmers, G++ treats dereferencing a pointer to
+volatile object of complete type as GCC would do for an equivalent
+type in C@. When the object has incomplete type, G++ issues a
+warning; if you wish to force an error, you must force a conversion to
+rvalue with, for instance, a static cast.
When using a reference to volatile, G++ does not treat equivalent
expressions as accesses to volatiles, but instead issues a warning that
references. Again, if you wish to force a read, cast the reference to
an rvalue.
+G++ implements the same behavior as GCC does when assigning to a
+volatile object -- there is no reread of the assigned-to object, the
+assigned rvalue is reused. Note that in C++ assignment expressions
+are lvalues, and if used as an lvalue, the volatile object will be
+referred to. For instance, @var{vref} will refer to @var{vobj}, as
+expected, in the following example:
+
+@smallexample
+volatile int vobj;
+volatile int &vref = vobj = @var{something};
+@end smallexample
+
@node Restricted Pointers
@section Restricting Pointer Aliasing
@cindex restricted pointers
Make sure that any inline virtuals are declared inline in the class
body, even if they are not defined there.
-@item type_info objects
-@cindex type_info
+@item @code{type_info} objects
+@cindex @code{type_info}
@cindex RTTI
C++ requires information about types to be written out in order to
implement @samp{dynamic_cast}, @samp{typeid} and exception handling.
-For polymorphic classes (classes with virtual functions), the type_info
+For polymorphic classes (classes with virtual functions), the @samp{type_info}
object is written out along with the vtable so that @samp{dynamic_cast}
can determine the dynamic type of a class object at runtime. For all
-other types, we write out the type_info object when it is used: when
+other types, we write out the @samp{type_info} object when it is used: when
applying @samp{typeid} to an expression, throwing an object, or
referring to a type in a catch clause or exception specification.
@table @code
@item init_priority (@var{priority})
-@cindex init_priority attribute
+@cindex @code{init_priority} attribute
In Standard C++, objects defined at namespace scope are guaranteed to be
relative ordering.
@item java_interface
-@cindex java_interface attribute
+@cindex @code{java_interface} attribute
This type attribute informs C++ that the class is a Java interface. It may
only be applied to classes declared within an @code{extern "Java"} block.
false. Otherwise if @code{__has_trivial_assign (type)} is true then the trait
is true, else if @code{type} is a cv class or union type with copy assignment
operators that are known not to throw an exception then the trait is true,
-else it is false. Requires: @code{type} shall be a complete type, an array
-type of unknown bound, or is a @code{void} type.
+else it is false. Requires: @code{type} shall be a complete type,
+(possibly cv-qualified) @code{void}, or an array of unknown bound.
@item __has_nothrow_copy (type)
If @code{__has_trivial_copy (type)} is true then the trait is true, else if
@code{type} is a cv class or union type with copy constructors that
are known not to throw an exception then the trait is true, else it is false.
-Requires: @code{type} shall be a complete type, an array type of
-unknown bound, or is a @code{void} type.
+Requires: @code{type} shall be a complete type, (possibly cv-qualified)
+@code{void}, or an array of unknown bound.
@item __has_nothrow_constructor (type)
If @code{__has_trivial_constructor (type)} is true then the trait is
true, else if @code{type} is a cv class or union type (or array
thereof) with a default constructor that is known not to throw an
-exception then the trait is true, else it is false. Requires:
-@code{type} shall be a complete type, an array type of unknown bound,
-or is a @code{void} type.
+exception then the trait is true, else it is false. Requires:
+@code{type} shall be a complete type, (possibly cv-qualified)
+@code{void}, or an array of unknown bound.
@item __has_trivial_assign (type)
If @code{type} is const qualified or is a reference type then the trait is
false. Otherwise if @code{__is_pod (type)} is true then the trait is
true, else if @code{type} is a cv class or union type with a trivial
copy assignment ([class.copy]) then the trait is true, else it is
-false. Requires: @code{type} shall be a complete type, an array type
-of unknown bound, or is a @code{void} type.
+false. Requires: @code{type} shall be a complete type, (possibly
+cv-qualified) @code{void}, or an array of unknown bound.
@item __has_trivial_copy (type)
If @code{__is_pod (type)} is true or @code{type} is a reference type
then the trait is true, else if @code{type} is a cv class or union type
with a trivial copy constructor ([class.copy]) then the trait
is true, else it is false. Requires: @code{type} shall be a complete
-type, an array type of unknown bound, or is a @code{void} type.
+type, (possibly cv-qualified) @code{void}, or an array of unknown bound.
@item __has_trivial_constructor (type)
If @code{__is_pod (type)} is true then the trait is true, else if
@code{type} is a cv class or union type (or array thereof) with a
trivial default constructor ([class.ctor]) then the trait is true,
-else it is false. Requires: @code{type} shall be a complete type, an
-array type of unknown bound, or is a @code{void} type.
+else it is false. Requires: @code{type} shall be a complete
+type, (possibly cv-qualified) @code{void}, or an array of unknown bound.
@item __has_trivial_destructor (type)
If @code{__is_pod (type)} is true or @code{type} is a reference type then
the trait is true, else if @code{type} is a cv class or union type (or
array thereof) with a trivial destructor ([class.dtor]) then the trait
is true, else it is false. Requires: @code{type} shall be a complete
-type, an array type of unknown bound, or is a @code{void} type.
+type, (possibly cv-qualified) @code{void}, or an array of unknown bound.
@item __has_virtual_destructor (type)
If @code{type} is a class type with a virtual destructor
([class.dtor]) then the trait is true, else it is false. Requires:
-@code{type} shall be a complete type, an array type of unknown bound,
-or is a @code{void} type.
+@code{type} shall be a complete type, (possibly cv-qualified)
+@code{void}, or an array of unknown bound.
@item __is_abstract (type)
If @code{type} is an abstract class ([class.abstract]) then the trait
is true, else it is false. Requires: @code{type} shall be a complete
-type, an array type of unknown bound, or is a @code{void} type.
+type, (possibly cv-qualified) @code{void}, or an array of unknown bound.
@item __is_base_of (base_type, derived_type)
If @code{base_type} is a base class of @code{derived_type}
members, and @code{type} has no virtual base classes, and @code{type}
has no base classes @code{base_type} for which
@code{__is_empty (base_type)} is false. Requires: @code{type} shall
-be a complete type, an array type of unknown bound, or is a
-@code{void} type.
+be a complete type, (possibly cv-qualified) @code{void}, or an array
+of unknown bound.
@item __is_enum (type)
If @code{type} is a cv enumeration type ([basic.compound]) the trait is
true, else it is false.
+@item __is_literal_type (type)
+If @code{type} is a literal type ([basic.types]) the trait is
+true, else it is false. Requires: @code{type} shall be a complete type,
+(possibly cv-qualified) @code{void}, or an array of unknown bound.
+
@item __is_pod (type)
If @code{type} is a cv POD type ([basic.types]) then the trait is true,
-else it is false. Requires: @code{type} shall be a complete type,
-an array type of unknown bound, or is a @code{void} type.
+else it is false. Requires: @code{type} shall be a complete type,
+(possibly cv-qualified) @code{void}, or an array of unknown bound.
@item __is_polymorphic (type)
If @code{type} is a polymorphic class ([class.virtual]) then the trait
is true, else it is false. Requires: @code{type} shall be a complete
-type, an array type of unknown bound, or is a @code{void} type.
+type, (possibly cv-qualified) @code{void}, or an array of unknown bound.
+
+@item __is_standard_layout (type)
+If @code{type} is a standard-layout type ([basic.types]) the trait is
+true, else it is false. Requires: @code{type} shall be a complete
+type, (possibly cv-qualified) @code{void}, or an array of unknown bound.
+
+@item __is_trivial (type)
+If @code{type} is a trivial type ([basic.types]) the trait is
+true, else it is false. Requires: @code{type} shall be a complete
+type, (possibly cv-qualified) @code{void}, or an array of unknown bound.
@item __is_union (type)
If @code{type} is a cv union type ([basic.compound]) the trait is
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