@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
-@c 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
+@c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
+@c Free Software Foundation, Inc.
@c This is part of the GCC manual.
@c For copying conditions, see the file gcc.texi.
also available in C++. @xref{C++ Extensions,,Extensions to the
C++ Language}, for extensions that apply @emph{only} to C++.
-Some features that are in ISO C99 but not C89 or C++ are also, as
-extensions, accepted by GCC in C89 mode and in C++.
+Some features that are in ISO C99 but not C90 or C++ are also, as
+extensions, accepted by GCC in C90 mode and in C++.
@menu
* Statement Exprs:: Putting statements and declarations inside expressions.
* Local Labels:: Labels local to a block.
* Labels as Values:: Getting pointers to labels, and computed gotos.
* Nested Functions:: As in Algol and Pascal, lexical scoping of functions.
-* Constructing Calls:: Dispatching a call to another function.
+* Constructing Calls:: Dispatching a call to another function.
* Typeof:: @code{typeof}: referring to the type of an expression.
* Conditionals:: Omitting the middle operand of a @samp{?:} expression.
-* Long Long:: Double-word integers---@code{long long int}.
+* Long Long:: Double-word integers---@code{long long int}.
* Complex:: Data types for complex numbers.
* Floating Types:: Additional Floating Types.
+* Half-Precision:: Half-Precision Floating Point.
* Decimal Float:: Decimal Floating Types.
* Hex Floats:: Hexadecimal floating-point constants.
* Fixed-Point:: Fixed-Point Types.
+* Named Address Spaces::Named address spaces.
* Zero Length:: Zero-length arrays.
* Variable Length:: Arrays whose length is computed at run time.
* Empty Structures:: Structures with no members.
-* Variadic Macros:: Macros with a variable number of arguments.
+* Variadic Macros:: Macros with a variable number of arguments.
* Escaped Newlines:: Slightly looser rules for escaped newlines.
* Subscripting:: Any array can be subscripted, even if not an lvalue.
* Pointer Arith:: Arithmetic on @code{void}-pointers and function pointers.
* Initializers:: Non-constant initializers.
* Compound Literals:: Compound literals give structures, unions
- or arrays as values.
-* Designated Inits:: Labeling elements of initializers.
+ or arrays as values.
+* Designated Inits:: Labeling elements of initializers.
* Cast to Union:: Casting to union type from any member of the union.
-* Case Ranges:: `case 1 ... 9' and such.
-* Mixed Declarations:: Mixing declarations and code.
+* Case Ranges:: `case 1 ... 9' and such.
+* Mixed Declarations:: Mixing declarations and code.
* Function Attributes:: Declaring that functions have no side effects,
- or that they can never return.
+ or that they can never return.
* Attribute Syntax:: Formal syntax for attributes.
* Function Prototypes:: Prototype declarations and old-style definitions.
* C++ Comments:: C++ comments are recognized.
* Dollar Signs:: Dollar sign is allowed in identifiers.
* Character Escapes:: @samp{\e} stands for the character @key{ESC}.
-* Variable Attributes:: Specifying attributes of variables.
-* Type Attributes:: Specifying attributes of types.
+* Variable Attributes:: Specifying attributes of variables.
+* Type Attributes:: Specifying attributes of types.
* Alignment:: Inquiring about the alignment of a type or variable.
* Inline:: Defining inline functions (as fast as macros).
* Extended Asm:: Assembler instructions with C expressions as operands.
- (With them you can define ``built-in'' functions.)
+ (With them you can define ``built-in'' functions.)
* Constraints:: Constraints for asm operands
* Asm Labels:: Specifying the assembler name to use for a C symbol.
* Explicit Reg Vars:: Defining variables residing in specified registers.
* Alternate Keywords:: @code{__const__}, @code{__asm__}, etc., for header files.
* Incomplete Enums:: @code{enum foo;}, with details to follow.
-* Function Names:: Printable strings which are the name of the current
- function.
+* Function Names:: Printable strings which are the name of the current
+ function.
* Return Address:: Getting the return or frame address of a function.
* Vector Extensions:: Using vector instructions through built-in functions.
* Offsetof:: Special syntax for implementing @code{offsetof}.
-* Atomic Builtins:: Built-in functions for atomic memory access.
+* Atomic Builtins:: Built-in functions for atomic memory access.
* Object Size Checking:: Built-in functions for limited buffer overflow
checking.
* Other Builtins:: Other built-in functions.
the number of dynamic relocations that are needed, and by consequence,
allows the data to be read-only.
-The @code{&&foo} expressions for the same label might have different values
-if the containing function is inlined or cloned. If a program relies on
-them being always the same, @code{__attribute__((__noinline__))} should
-be used to prevent inlining. If @code{&&foo} is used
-in a static variable initializer, inlining is forbidden.
+The @code{&&foo} expressions for the same label might have different
+values if the containing function is inlined or cloned. If a program
+relies on them being always the same,
+@code{__attribute__((__noinline__,__noclone__))} should be used to
+prevent inlining and cloning. If @code{&&foo} is used in a static
+variable initializer, inlining and cloning is forbidden.
@node Nested Functions
@section Nested Functions
safe.
GCC implements taking the address of a nested function using a technique
-called @dfn{trampolines}. A paper describing them is available as
-
-@noindent
-@uref{http://people.debian.org/~aaronl/Usenix88-lexic.pdf}.
+called @dfn{trampolines}. This technique was described in
+@cite{Lexical Closures for C++} (Thomas M. Breuel, USENIX
+C++ Conference Proceedings, October 17-21, 1988).
A nested function can jump to a label inherited from a containing
function, provided the label was explicitly declared in the containing
used. For example, you can use it in a declaration, in a cast, or inside
of @code{sizeof} or @code{typeof}.
+The operand of @code{typeof} is evaluated for its side effects if and
+only if it is an expression of variably modified type or the name of
+such a type.
+
@code{typeof} is often useful in conjunction with the
statements-within-expressions feature. Here is how the two together can
be used to define a safe ``maximum'' macro that operates on any
@cindex @code{ULL} integer suffix
ISO C99 supports data types for integers that are at least 64 bits wide,
-and as an extension GCC supports them in C89 mode and in C++.
+and as an extension GCC supports them in C90 mode and in C++.
Simply write @code{long long int} for a signed integer, or
@code{unsigned long long int} for an unsigned integer. To make an
integer constant of type @code{long long int}, add the suffix @samp{LL}
@cindex @code{__complex__} keyword
ISO C99 supports complex floating data types, and as an extension GCC
-supports them in C89 mode and in C++, and supports complex integer data
+supports them in C90 mode and in C++, and supports complex integer data
types which are not part of ISO C99. You can declare complex types
using the keyword @code{_Complex}. As an extension, the older GNU
keyword @code{__complex__} is also supported.
@end smallexample
Not all targets support additional floating point types. @code{__float80}
-is supported on i386, x86_64 and ia64 targets and target @code{__float128}
-is supported on x86_64 and ia64 targets.
+and @code{__float128} types are supported on i386, x86_64 and ia64 targets.
+
+@node Half-Precision
+@section Half-Precision Floating Point
+@cindex half-precision floating point
+@cindex @code{__fp16} data type
+
+On ARM targets, GCC supports half-precision (16-bit) floating point via
+the @code{__fp16} type. You must enable this type explicitly
+with the @option{-mfp16-format} command-line option in order to use it.
+
+ARM supports two incompatible representations for half-precision
+floating-point values. You must choose one of the representations and
+use it consistently in your program.
+
+Specifying @option{-mfp16-format=ieee} selects the IEEE 754-2008 format.
+This format can represent normalized values in the range of @math{2^{-14}} to 65504.
+There are 11 bits of significand precision, approximately 3
+decimal digits.
+
+Specifying @option{-mfp16-format=alternative} selects the ARM
+alternative format. This representation is similar to the IEEE
+format, but does not support infinities or NaNs. Instead, the range
+of exponents is extended, so that this format can represent normalized
+values in the range of @math{2^{-14}} to 131008.
+
+The @code{__fp16} type is a storage format only. For purposes
+of arithmetic and other operations, @code{__fp16} values in C or C++
+expressions are automatically promoted to @code{float}. In addition,
+you cannot declare a function with a return value or parameters
+of type @code{__fp16}.
+
+Note that conversions from @code{double} to @code{__fp16}
+involve an intermediate conversion to @code{float}. Because
+of rounding, this can sometimes produce a different result than a
+direct conversion.
+
+ARM provides hardware support for conversions between
+@code{__fp16} and @code{float} values
+as an extension to VFP and NEON (Advanced SIMD). GCC generates
+code using these hardware instructions if you compile with
+options to select an FPU that provides them;
+for example, @option{-mfpu=neon-fp16 -mfloat-abi=softfp},
+in addition to the @option{-mfp16-format} option to select
+a half-precision format.
+
+Language-level support for the @code{__fp16} data type is
+independent of whether GCC generates code using hardware floating-point
+instructions. In cases where hardware support is not specified, GCC
+implements conversions between @code{__fp16} and @code{float} values
+as library calls.
@node Decimal Float
@section Decimal Floating Types
@cindex @code{DL} integer suffix
As an extension, the GNU C compiler supports decimal floating types as
-defined in the N1176 draft of ISO/IEC WDTR24732. Support for decimal
+defined in the N1312 draft of ISO/IEC WDTR24732. Support for decimal
floating types in GCC will evolve as the draft technical report changes.
Calling conventions for any target might also change. Not all targets
support decimal floating types.
@itemize @bullet
@item
-Translation time data type (TTDT) is not supported.
-
-@item
When the value of a decimal floating type cannot be represented in the
integer type to which it is being converted, the result is undefined
rather than the result value specified by the draft technical report.
+
+@item
+GCC does not provide the C library functionality associated with
+@file{math.h}, @file{fenv.h}, @file{stdio.h}, @file{stdlib.h}, and
+@file{wchar.h}, which must come from a separate C library implementation.
+Because of this the GNU C compiler does not define macro
+@code{__STDC_DEC_FP__} to indicate that the implementation conforms to
+the technical report.
@end itemize
Types @code{_Decimal32}, @code{_Decimal64}, and @code{_Decimal128}
ISO C99 supports floating-point numbers written not only in the usual
decimal notation, such as @code{1.55e1}, but also numbers such as
@code{0x1.fp3} written in hexadecimal format. As a GNU extension, GCC
-supports this in C89 mode (except in some cases when strictly
+supports this in C90 mode (except in some cases when strictly
conforming) and in C++. In that format the
@samp{0x} hex introducer and the @samp{p} or @samp{P} exponent field are
mandatory. The exponent is a decimal number that indicates the power of
@code{_Sat unsigned _Accum},
@code{_Sat unsigned long _Accum},
@code{_Sat unsigned long long _Accum}.
+
Fixed-point data values contain fractional and optional integral parts.
The format of fixed-point data varies and depends on the target machine.
-Support for fixed-point types includes prefix and postfix increment
-and decrement operators (@code{++}, @code{--}); unary arithmetic operators
-(@code{+}, @code{-}, @code{!}); binary arithmetic operators (@code{+},
-@code{-}, @code{*}, @code{/}); binary shift operators (@code{<<}, @code{>>});
-relational operators (@code{<}, @code{<=}, @code{>=}, @code{>});
-equality operators (@code{==}, @code{!=}); assignment operators
-(@code{+=}, @code{-=}, @code{*=}, @code{/=}, @code{<<=}, @code{>>=});
-and conversions to and from integer, floating-point, or fixed-point types.
-
-Use a suffix @samp{hr} or @samp{HR} in a literal constant of type
-@code{short _Fract} and @code{_Sat short _Fract},
-@samp{r} or @samp{R} for @code{_Fract} and @code{_Sat _Fract},
-@samp{lr} or @samp{LR} for @code{long _Fract} and @code{_Sat long _Fract},
-@samp{llr} or @samp{LLR} for @code{long long _Fract} and
-@code{_Sat long long _Fract},
-@samp{uhr} or @samp{UHR} for @code{unsigned short _Fract} and
-@code{_Sat unsigned short _Fract},
-@samp{ur} or @samp{UR} for @code{unsigned _Fract} and
-@code{_Sat unsigned _Fract},
-@samp{ulr} or @samp{ULR} for @code{unsigned long _Fract} and
-@code{_Sat unsigned long _Fract},
-@samp{ullr} or @samp{ULLR} for @code{unsigned long long _Fract}
-and @code{_Sat unsigned long long _Fract},
-@samp{hk} or @samp{HK} for @code{short _Accum} and @code{_Sat short _Accum},
-@samp{k} or @samp{K} for @code{_Accum} and @code{_Sat _Accum},
-@samp{lk} or @samp{LK} for @code{long _Accum} and @code{_Sat long _Accum},
-@samp{llk} or @samp{LLK} for @code{long long _Accum} and
-@code{_Sat long long _Accum},
-@samp{uhk} or @samp{UHK} for @code{unsigned short _Accum} and
-@code{_Sat unsigned short _Accum},
-@samp{uk} or @samp{UK} for @code{unsigned _Accum} and
-@code{_Sat unsigned _Accum},
-@samp{ulk} or @samp{ULK} for @code{unsigned long _Accum} and
-@code{_Sat unsigned long _Accum},
-and @samp{ullk} or @samp{ULLK} for @code{unsigned long long _Accum}
-and @code{_Sat unsigned long long _Accum}.
+Support for fixed-point types includes:
+@itemize @bullet
+@item
+prefix and postfix increment and decrement operators (@code{++}, @code{--})
+@item
+unary arithmetic operators (@code{+}, @code{-}, @code{!})
+@item
+binary arithmetic operators (@code{+}, @code{-}, @code{*}, @code{/})
+@item
+binary shift operators (@code{<<}, @code{>>})
+@item
+relational operators (@code{<}, @code{<=}, @code{>=}, @code{>})
+@item
+equality operators (@code{==}, @code{!=})
+@item
+assignment operators (@code{+=}, @code{-=}, @code{*=}, @code{/=},
+@code{<<=}, @code{>>=})
+@item
+conversions to and from integer, floating-point, or fixed-point types
+@end itemize
+
+Use a suffix in a fixed-point literal constant:
+@itemize
+@item @samp{hr} or @samp{HR} for @code{short _Fract} and
+@code{_Sat short _Fract}
+@item @samp{r} or @samp{R} for @code{_Fract} and @code{_Sat _Fract}
+@item @samp{lr} or @samp{LR} for @code{long _Fract} and
+@code{_Sat long _Fract}
+@item @samp{llr} or @samp{LLR} for @code{long long _Fract} and
+@code{_Sat long long _Fract}
+@item @samp{uhr} or @samp{UHR} for @code{unsigned short _Fract} and
+@code{_Sat unsigned short _Fract}
+@item @samp{ur} or @samp{UR} for @code{unsigned _Fract} and
+@code{_Sat unsigned _Fract}
+@item @samp{ulr} or @samp{ULR} for @code{unsigned long _Fract} and
+@code{_Sat unsigned long _Fract}
+@item @samp{ullr} or @samp{ULLR} for @code{unsigned long long _Fract}
+and @code{_Sat unsigned long long _Fract}
+@item @samp{hk} or @samp{HK} for @code{short _Accum} and
+@code{_Sat short _Accum}
+@item @samp{k} or @samp{K} for @code{_Accum} and @code{_Sat _Accum}
+@item @samp{lk} or @samp{LK} for @code{long _Accum} and
+@code{_Sat long _Accum}
+@item @samp{llk} or @samp{LLK} for @code{long long _Accum} and
+@code{_Sat long long _Accum}
+@item @samp{uhk} or @samp{UHK} for @code{unsigned short _Accum} and
+@code{_Sat unsigned short _Accum}
+@item @samp{uk} or @samp{UK} for @code{unsigned _Accum} and
+@code{_Sat unsigned _Accum}
+@item @samp{ulk} or @samp{ULK} for @code{unsigned long _Accum} and
+@code{_Sat unsigned long _Accum}
+@item @samp{ullk} or @samp{ULLK} for @code{unsigned long long _Accum}
+and @code{_Sat unsigned long long _Accum}
+@end itemize
GCC support of fixed-point types as specified by the draft technical report
is incomplete:
Fixed-point types are supported by the DWARF2 debug information format.
+@node Named Address Spaces
+@section Named address spaces
+@cindex named address spaces
+
+As an extension, the GNU C compiler supports named address spaces as
+defined in the N1275 draft of ISO/IEC DTR 18037. Support for named
+address spaces in GCC will evolve as the draft technical report changes.
+Calling conventions for any target might also change. At present, only
+the SPU target supports other address spaces. On the SPU target, for
+example, variables may be declared as belonging to another address space
+by qualifying the type with the @code{__ea} address space identifier:
+
+@smallexample
+extern int __ea i;
+@end smallexample
+
+When the variable @code{i} is accessed, the compiler will generate
+special code to access this variable. It may use runtime library
+support, or generate special machine instructions to access that address
+space.
+
+The @code{__ea} identifier may be used exactly like any other C type
+qualifier (e.g., @code{const} or @code{volatile}). See the N1275
+document for more details.
+
@node Zero Length
@section Arrays of Length Zero
@cindex arrays of length zero
@cindex VLAs
Variable-length automatic arrays are allowed in ISO C99, and as an
-extension GCC accepts them in C89 mode and in C++. (However, GCC's
+extension GCC accepts them in C90 mode and in C++. (However, GCC's
implementation of variable-length arrays does not yet conform in detail
to the ISO C99 standard.) These arrays are
declared like any other automatic arrays, but with a length that is not
may be subscripted, although they may not be modified or used after
the next sequence point and the unary @samp{&} operator may not be
applied to them. As an extension, GCC allows such arrays to be
-subscripted in C89 mode, though otherwise they do not decay to
+subscripted in C90 mode, though otherwise they do not decay to
pointers outside C99 mode. For example,
-this is valid in GNU C though not valid in C89:
+this is valid in GNU C though not valid in C90:
@smallexample
@group
a cast containing an initializer. Its value is an object of the
type specified in the cast, containing the elements specified in
the initializer; it is an lvalue. As an extension, GCC supports
-compound literals in C89 mode and in C++.
+compound literals in C90 mode and in C++.
Usually, the specified type is a structure. Assume that
@code{struct foo} and @code{structure} are declared as shown:
@cindex case labels in initializers
@cindex designated initializers
-Standard C89 requires the elements of an initializer to appear in a fixed
+Standard C90 requires the elements of an initializer to appear in a fixed
order, the same as the order of the elements in the array or structure
being initialized.
In ISO C99 you can give the elements in any order, specifying the array
indices or structure field names they apply to, and GNU C allows this as
-an extension in C89 mode as well. This extension is not
+an extension in C90 mode as well. This extension is not
implemented in GNU C++.
To specify an array index, write
ISO C99 and ISO C++ allow declarations and code to be freely mixed
within compound statements. As an extension, GCC also allows this in
-C89 mode. For example, you could do:
+C90 mode. For example, you could do:
@smallexample
int i;
@cindex functions that are passed arguments in registers on the 386
@cindex functions that pop the argument stack on the 386
@cindex functions that do not pop the argument stack on the 386
+@cindex functions that have different compilation options on the 386
+@cindex functions that have different optimization options
In GNU C, you declare certain things about functions called in your program
which help the compiler optimize function calls and check your code more
attribute specification inside double parentheses. The following
attributes are currently defined for functions on all targets:
@code{aligned}, @code{alloc_size}, @code{noreturn},
-@code{returns_twice}, @code{noinline}, @code{always_inline},
-@code{flatten}, @code{pure}, @code{const}, @code{nothrow},
-@code{sentinel}, @code{format}, @code{format_arg},
+@code{returns_twice}, @code{noinline}, @code{noclone},
+@code{always_inline}, @code{flatten}, @code{pure}, @code{const},
+@code{nothrow}, @code{sentinel}, @code{format}, @code{format_arg},
@code{no_instrument_function}, @code{section}, @code{constructor},
@code{destructor}, @code{used}, @code{unused}, @code{deprecated},
@code{weak}, @code{malloc}, @code{alias}, @code{warn_unused_result},
@code{nonnull}, @code{gnu_inline}, @code{externally_visible},
-@code{hot}, @code{cold}, @code{artificial}, @code{error}
-and @code{warning}.
-Several other attributes are defined for functions on particular
-target systems. Other attributes, including @code{section} are
-supported for variables declarations (@pxref{Variable Attributes}) and
-for types (@pxref{Type Attributes}).
+@code{hot}, @code{cold}, @code{artificial}, @code{error} and
+@code{warning}. Several other attributes are defined for functions on
+particular target systems. Other attributes, including @code{section}
+are supported for variables declarations (@pxref{Variable Attributes})
+and for types (@pxref{Type Attributes}).
+
+GCC plugins may provide their own attributes.
You may also specify attributes with @samp{__} preceding and following
each keyword. This allows you to use them in header files without
@cindex @code{gnu_inline} function attribute
This attribute should be used with a function which is also declared
with the @code{inline} keyword. It directs GCC to treat the function
-as if it were defined in gnu89 mode even when compiling in C99 or
+as if it were defined in gnu90 mode even when compiling in C99 or
gnu99 mode.
If the function is declared @code{extern}, then this definition of the
but it still requires the @code{inline} keyword to enable its special
behavior.
-@cindex @code{artificial} function attribute
@item artificial
+@cindex @code{artificial} function attribute
This attribute is useful for small inline wrappers which if possible
should appear during debugging as a unit, depending on the debug
info format it will either mean marking the function as artificial
or using the caller location for all instructions within the inlined
body.
-@cindex @code{flatten} function attribute
+@item bank_switch
+@cindex interrupt handler functions
+When added to an interrupt handler with the M32C port, causes the
+prologue and epilogue to use bank switching to preserve the registers
+rather than saving them on the stack.
+
@item flatten
+@cindex @code{flatten} function attribute
Generally, inlining into a function is limited. For a function marked with
this attribute, every call inside this function will be inlined, if possible.
Whether the function itself is considered for inlining depends on its size and
-the current inlining parameters. The @code{flatten} attribute only works
-reliably in unit-at-a-time mode.
+the current inlining parameters.
@item error ("@var{message}")
@cindex @code{error} function attribute
These attributes are not currently implemented for Objective-C@.
@item deprecated
+@itemx deprecated (@var{msg})
@cindex @code{deprecated} attribute.
The @code{deprecated} attribute results in a warning if the function
is used anywhere in the source file. This is useful when identifying
int (*fn_ptr)() = old_fn;
@end smallexample
-results in a warning on line 3 but not line 2.
+results in a warning on line 3 but not line 2. The optional msg
+argument, which must be a string, will be printed in the warning if
+present.
The @code{deprecated} attribute can also be used for variables and
types (@pxref{Variable Attributes}, @pxref{Type Attributes}.)
+@item disinterrupt
+@cindex @code{disinterrupt} attribute
+On MeP targets, this attribute causes the compiler to emit
+instructions to disable interrupts for the duration of the given
+function.
+
@item dllexport
@cindex @code{__declspec(dllexport)}
On Microsoft Windows targets and Symbian OS targets the
another affect---it can cause the vtable and run-time type information
for a class to be exported. This happens when the class has a
dllimport'ed constructor or a non-inline, non-pure virtual function
-and, for either of those two conditions, the class also has a inline
+and, for either of those two conditions, the class also has an inline
constructor or destructor and has a key function that is defined in
the current translation unit.
exit sequences suitable for use in an exception handler when this
attribute is present.
+@item externally_visible
+@cindex @code{externally_visible} attribute.
+This attribute, attached to a global variable or function, nullifies
+the effect of the @option{-fwhole-program} command-line option, so the
+object remains visible outside the current compilation unit.
+
@item far
@cindex functions which handle memory bank switching
On 68HC11 and 68HC12 the @code{far} attribute causes the compiler to
instead of using @code{rts}. The board-specific return routine simulates
the @code{rtc}.
+On MeP targets this causes the compiler to use a calling convention
+which assumes the called function is too far away for the built-in
+addressing modes.
+
+@item fast_interrupt
+@cindex interrupt handler functions
+Use this attribute on the M32C and RX ports to indicate that the specified
+function is a fast interrupt handler. This is just like the
+@code{interrupt} attribute, except that @code{freit} is used to return
+instead of @code{reit}.
+
@item fastcall
@cindex functions that pop the argument stack on the 386
On the Intel 386, the @code{fastcall} attribute causes the compiler to
pop the arguments off the stack. If the number of arguments is variable all
arguments are pushed on the stack.
+@item thiscall
+@cindex functions that pop the argument stack on the 386
+On the Intel 386, the @code{thiscall} attribute causes the compiler to
+pass the first argument (if of integral type) in the register ECX.
+Subsequent and other typed arguments are passed on the stack. The called
+function will pop the arguments off the stack.
+If the number of arguments is variable all arguments are pushed on the
+stack.
+The @code{thiscall} attribute is intended for C++ non-static member functions.
+As gcc extension this calling convention can be used for C-functions
+and for static member methods.
+
@item format (@var{archetype}, @var{string-index}, @var{first-to-check})
@cindex @code{format} function attribute
@opindex Wformat
@item interrupt
@cindex interrupt handler functions
-Use this attribute on the ARM, AVR, CRX, M32C, M32R/D, m68k, MS1,
-and Xstormy16 ports to indicate that the specified function is an
+Use this attribute on the ARM, AVR, CRX, M32C, M32R/D, m68k, MeP, MIPS,
+RX and Xstormy16 ports to indicate that the specified function is an
interrupt handler. The compiler will generate function entry and exit
sequences suitable for use in an interrupt handler when this attribute
is present.
On ARMv7-M the interrupt type is ignored, and the attribute means the function
may be called with a word aligned stack pointer.
+On MIPS targets, you can use the following attributes to modify the behavior
+of an interrupt handler:
+@table @code
+@item use_shadow_register_set
+@cindex @code{use_shadow_register_set} attribute
+Assume that the handler uses a shadow register set, instead of
+the main general-purpose registers.
+
+@item keep_interrupts_masked
+@cindex @code{keep_interrupts_masked} attribute
+Keep interrupts masked for the whole function. Without this attribute,
+GCC tries to reenable interrupts for as much of the function as it can.
+
+@item use_debug_exception_return
+@cindex @code{use_debug_exception_return} attribute
+Return using the @code{deret} instruction. Interrupt handlers that don't
+have this attribute return using @code{eret} instead.
+@end table
+
+You can use any combination of these attributes, as shown below:
+@smallexample
+void __attribute__ ((interrupt)) v0 ();
+void __attribute__ ((interrupt, use_shadow_register_set)) v1 ();
+void __attribute__ ((interrupt, keep_interrupts_masked)) v2 ();
+void __attribute__ ((interrupt, use_debug_exception_return)) v3 ();
+void __attribute__ ((interrupt, use_shadow_register_set,
+ keep_interrupts_masked)) v4 ();
+void __attribute__ ((interrupt, use_shadow_register_set,
+ use_debug_exception_return)) v5 ();
+void __attribute__ ((interrupt, keep_interrupts_masked,
+ use_debug_exception_return)) v6 ();
+void __attribute__ ((interrupt, use_shadow_register_set,
+ keep_interrupts_masked,
+ use_debug_exception_return)) v7 ();
+@end smallexample
+
@item interrupt_handler
@cindex interrupt handler functions on the Blackfin, m68k, H8/300 and SH processors
Use this attribute on the Blackfin, m68k, H8/300, H8/300H, H8S, and SH to
sequences and replaces the return instruction with a @code{sleep}
instruction. This attribute is available only on fido.
+@item isr
+@cindex interrupt service routines on ARM
+Use this attribute on ARM to write Interrupt Service Routines. This is an
+alias to the @code{interrupt} attribute above.
+
@item kspisusp
@cindex User stack pointer in interrupts on the Blackfin
When used together with @code{interrupt_handler}, @code{exception_handler}
With @option{-mfdpic}, function calls with a such function as the callee
or caller will use inlined PLT.
+@item l2
+@cindex @code{l2} function attribute
+On the Blackfin, this attribute specifies a function to be placed into L2
+SRAM. The function will be put into a specific section named
+@code{.l1.text}. With @option{-mfdpic}, callers of such functions will use
+an inlined PLT.
+
@item long_call/short_call
@cindex indirect calls on ARM
This attribute specifies how a particular function is called on
ARM@. Both attributes override the @option{-mlong-calls} (@pxref{ARM Options})
-command line switch and @code{#pragma long_calls} settings. The
+command-line switch and @code{#pragma long_calls} settings. The
@code{long_call} attribute indicates that the function might be far
away from the call site and require a different (more expensive)
calling sequence. The @code{short_call} attribute always places
independent and hence this attribute must not be used for objects
defined by shared libraries.
+@item ms_abi/sysv_abi
+@cindex @code{ms_abi} attribute
+@cindex @code{sysv_abi} attribute
+
+On 64-bit x86_64-*-* targets, you can use an ABI attribute to indicate
+which calling convention should be used for a function. The @code{ms_abi}
+attribute tells the compiler to use the Microsoft ABI, while the
+@code{sysv_abi} attribute tells the compiler to use the ABI used on
+GNU/Linux and other systems. The default is to use the Microsoft ABI
+when targeting Windows. On all other systems, the default is the AMD ABI.
+
+Note, the @code{ms_abi} attribute for Windows targets currently requires
+the @option{-maccumulate-outgoing-args} option.
+
+@item ms_hook_prologue
+@cindex @code{ms_hook_prologue} attribute
+
+On 32 bit i[34567]86-*-* targets, you can use this function attribute to make
+gcc generate the "hot-patching" function prologue used in Win32 API
+functions in Microsoft Windows XP Service Pack 2 and newer. This requires
+support for the swap suffix in the assembler. (GNU Binutils 2.19.51 or later)
+
@item naked
@cindex function without a prologue/epilogue code
-Use this attribute on the ARM, AVR, IP2K and SPU ports to indicate that
+Use this attribute on the ARM, AVR, IP2K, RX and SPU ports to indicate that
the specified function does not need prologue/epilogue sequences generated by
the compiler. It is up to the programmer to provide these sequences. The
only statements that can be safely included in naked functions are
This attribute can be used to cancel the effect of the @option{-mlong-calls}
option.
+On MeP targets this attribute causes the compiler to assume the called
+function is close enough to use the normal calling convention,
+overriding the @code{-mtf} command line option.
+
@item nesting
@cindex Allow nesting in an interrupt handler on the Blackfin processor.
Use this attribute together with @code{interrupt_handler},
(@pxref{Extended Asm}) in the called function, to serve as a special
side-effect.
+@item noclone
+@cindex @code{noclone} function attribute
+This function attribute prevents a function from being considered for
+cloning - a mechanism which produces specialized copies of functions
+and which is (currently) performed by interprocedural constant
+propagation.
+
@item nonnull (@var{arg-index}, @dots{})
@cindex @code{nonnull} function attribute
The @code{nonnull} attribute specifies that some function parameters should
@smallexample
extern void *
my_memcpy (void *dest, const void *src, size_t len)
- __attribute__((nonnull (1, 2)));
+ __attribute__((nonnull (1, 2)));
@end smallexample
@noindent
@smallexample
extern void *
my_memcpy (void *dest, const void *src, size_t len)
- __attribute__((nonnull));
+ __attribute__((nonnull));
@end smallexample
@item noreturn
take function pointer arguments. The @code{nothrow} attribute is not
implemented in GCC versions earlier than 3.3.
+@item optimize
+@cindex @code{optimize} function attribute
+The @code{optimize} attribute is used to specify that a function is to
+be compiled with different optimization options than specified on the
+command line. Arguments can either be numbers or strings. Numbers
+are assumed to be an optimization level. Strings that begin with
+@code{O} are assumed to be an optimization option, while other options
+are assumed to be used with a @code{-f} prefix. You can also use the
+@samp{#pragma GCC optimize} pragma to set the optimization options
+that affect more than one function.
+@xref{Function Specific Option Pragmas}, for details about the
+@samp{#pragma GCC optimize} pragma.
+
+This can be used for instance to have frequently executed functions
+compiled with more aggressive optimization options that produce faster
+and larger code, while other functions can be called with less
+aggressive options.
+
+@item pcs
+@cindex @code{pcs} function attribute
+
+The @code{pcs} attribute can be used to control the calling convention
+used for a function on ARM. The attribute takes an argument that specifies
+the calling convention to use.
+
+When compiling using the AAPCS ABI (or a variant of that) then valid
+values for the argument are @code{"aapcs"} and @code{"aapcs-vfp"}. In
+order to use a variant other than @code{"aapcs"} then the compiler must
+be permitted to use the appropriate co-processor registers (i.e., the
+VFP registers must be available in order to use @code{"aapcs-vfp"}).
+For example,
+
+@smallexample
+/* Argument passed in r0, and result returned in r0+r1. */
+double f2d (float) __attribute__((pcs("aapcs")));
+@end smallexample
+
+Variadic functions always use the @code{"aapcs"} calling convention and
+the compiler will reject attempts to specify an alternative.
+
@item pure
@cindex @code{pure} function attribute
Many functions have no effects except the return value and their
When profile feedback is available, via @option{-fprofile-use}, hot functions
are automatically detected and this attribute is ignored.
-The @code{hot} attribute is not implemented in GCC versions earlier than 4.3.
+The @code{hot} attribute is not implemented in GCC versions earlier
+than 4.3.
@item cold
@cindex @code{cold} function attribute
When profile feedback is available, via @option{-fprofile-use}, hot functions
are automatically detected and this attribute is ignored.
-The @code{hot} attribute is not implemented in GCC versions earlier than 4.3.
+The @code{cold} attribute is not implemented in GCC versions earlier than 4.3.
@item regparm (@var{number})
@cindex @code{regparm} attribute
the loader, which might assume EAX, EDX and ECX can be clobbered, as
per the standard calling conventions. Solaris 8 is affected by this.
GNU systems with GLIBC 2.1 or higher, and FreeBSD, are believed to be
-safe since the loaders there save all registers. (Lazy binding can be
+safe since the loaders there save EAX, EDX and ECX. (Lazy binding can be
disabled with the linker or the loader if desired, to avoid the
problem.)
@cindex @code{force_align_arg_pointer} attribute
On the Intel x86, the @code{force_align_arg_pointer} attribute may be
applied to individual function definitions, generating an alternate
-prologue and epilogue that realigns the runtime stack. This supports
-mixing legacy codes that run with a 4-byte aligned stack with modern
-codes that keep a 16-byte stack for SSE compatibility. The alternate
-prologue and epilogue are slower and bigger than the regular ones, and
-the alternate prologue requires a scratch register; this lowers the
-number of registers available if used in conjunction with the
-@code{regparm} attribute. The @code{force_align_arg_pointer}
-attribute is incompatible with nested functions; this is considered a
-hard error.
+prologue and epilogue that realigns the runtime stack if necessary.
+This supports mixing legacy codes that run with a 4-byte aligned stack
+with modern codes that keep a 16-byte stack for SSE compatibility.
@item resbank
@cindex @code{resbank} attribute
On the SH2A target, this attribute enables the high-speed register
saving and restoration using a register bank for @code{interrupt_handler}
-routines. Saving to the bank is performed automatcially after the CPU
+routines. Saving to the bank is performed automatically after the CPU
accepts an interrupt that uses a register bank.
The nineteen 32-bit registers comprising general register R0 to R14,
assume that the called function will pop off the stack space used to
pass arguments, unless it takes a variable number of arguments.
+@item syscall_linkage
+@cindex @code{syscall_linkage} attribute
+This attribute is used to modify the IA64 calling convention by marking
+all input registers as live at all function exits. This makes it possible
+to restart a system call after an interrupt without having to save/restore
+the input registers. This also prevents kernel data from leaking into
+application code.
+
+@item target
+@cindex @code{target} function attribute
+The @code{target} attribute is used to specify that a function is to
+be compiled with different target options than specified on the
+command line. This can be used for instance to have functions
+compiled with a different ISA (instruction set architecture) than the
+default. You can also use the @samp{#pragma GCC target} pragma to set
+more than one function to be compiled with specific target options.
+@xref{Function Specific Option Pragmas}, for details about the
+@samp{#pragma GCC target} pragma.
+
+For instance on a 386, you could compile one function with
+@code{target("sse4.1,arch=core2")} and another with
+@code{target("sse4a,arch=amdfam10")} that would be equivalent to
+compiling the first function with @option{-msse4.1} and
+@option{-march=core2} options, and the second function with
+@option{-msse4a} and @option{-march=amdfam10} options. It is up to the
+user to make sure that a function is only invoked on a machine that
+supports the particular ISA it was compiled for (for example by using
+@code{cpuid} on 386 to determine what feature bits and architecture
+family are used).
+
+@smallexample
+int core2_func (void) __attribute__ ((__target__ ("arch=core2")));
+int sse3_func (void) __attribute__ ((__target__ ("sse3")));
+@end smallexample
+
+On the 386, the following options are allowed:
+
+@table @samp
+@item abm
+@itemx no-abm
+@cindex @code{target("abm")} attribute
+Enable/disable the generation of the advanced bit instructions.
+
+@item aes
+@itemx no-aes
+@cindex @code{target("aes")} attribute
+Enable/disable the generation of the AES instructions.
+
+@item mmx
+@itemx no-mmx
+@cindex @code{target("mmx")} attribute
+Enable/disable the generation of the MMX instructions.
+
+@item pclmul
+@itemx no-pclmul
+@cindex @code{target("pclmul")} attribute
+Enable/disable the generation of the PCLMUL instructions.
+
+@item popcnt
+@itemx no-popcnt
+@cindex @code{target("popcnt")} attribute
+Enable/disable the generation of the POPCNT instruction.
+
+@item sse
+@itemx no-sse
+@cindex @code{target("sse")} attribute
+Enable/disable the generation of the SSE instructions.
+
+@item sse2
+@itemx no-sse2
+@cindex @code{target("sse2")} attribute
+Enable/disable the generation of the SSE2 instructions.
+
+@item sse3
+@itemx no-sse3
+@cindex @code{target("sse3")} attribute
+Enable/disable the generation of the SSE3 instructions.
+
+@item sse4
+@itemx no-sse4
+@cindex @code{target("sse4")} attribute
+Enable/disable the generation of the SSE4 instructions (both SSE4.1
+and SSE4.2).
+
+@item sse4.1
+@itemx no-sse4.1
+@cindex @code{target("sse4.1")} attribute
+Enable/disable the generation of the sse4.1 instructions.
+
+@item sse4.2
+@itemx no-sse4.2
+@cindex @code{target("sse4.2")} attribute
+Enable/disable the generation of the sse4.2 instructions.
+
+@item sse4a
+@itemx no-sse4a
+@cindex @code{target("sse4a")} attribute
+Enable/disable the generation of the SSE4A instructions.
+
+@item fma4
+@itemx no-fma4
+@cindex @code{target("fma4")} attribute
+Enable/disable the generation of the FMA4 instructions.
+
+@item xop
+@itemx no-xop
+@cindex @code{target("xop")} attribute
+Enable/disable the generation of the XOP instructions.
+
+@item lwp
+@itemx no-lwp
+@cindex @code{target("lwp")} attribute
+Enable/disable the generation of the LWP instructions.
+
+@item ssse3
+@itemx no-ssse3
+@cindex @code{target("ssse3")} attribute
+Enable/disable the generation of the SSSE3 instructions.
+
+@item cld
+@itemx no-cld
+@cindex @code{target("cld")} attribute
+Enable/disable the generation of the CLD before string moves.
+
+@item fancy-math-387
+@itemx no-fancy-math-387
+@cindex @code{target("fancy-math-387")} attribute
+Enable/disable the generation of the @code{sin}, @code{cos}, and
+@code{sqrt} instructions on the 387 floating point unit.
+
+@item fused-madd
+@itemx no-fused-madd
+@cindex @code{target("fused-madd")} attribute
+Enable/disable the generation of the fused multiply/add instructions.
+
+@item ieee-fp
+@itemx no-ieee-fp
+@cindex @code{target("ieee-fp")} attribute
+Enable/disable the generation of floating point that depends on IEEE arithmetic.
+
+@item inline-all-stringops
+@itemx no-inline-all-stringops
+@cindex @code{target("inline-all-stringops")} attribute
+Enable/disable inlining of string operations.
+
+@item inline-stringops-dynamically
+@itemx no-inline-stringops-dynamically
+@cindex @code{target("inline-stringops-dynamically")} attribute
+Enable/disable the generation of the inline code to do small string
+operations and calling the library routines for large operations.
+
+@item align-stringops
+@itemx no-align-stringops
+@cindex @code{target("align-stringops")} attribute
+Do/do not align destination of inlined string operations.
+
+@item recip
+@itemx no-recip
+@cindex @code{target("recip")} attribute
+Enable/disable the generation of RCPSS, RCPPS, RSQRTSS and RSQRTPS
+instructions followed an additional Newton-Raphson step instead of
+doing a floating point division.
+
+@item arch=@var{ARCH}
+@cindex @code{target("arch=@var{ARCH}")} attribute
+Specify the architecture to generate code for in compiling the function.
+
+@item tune=@var{TUNE}
+@cindex @code{target("tune=@var{TUNE}")} attribute
+Specify the architecture to tune for in compiling the function.
+
+@item fpmath=@var{FPMATH}
+@cindex @code{target("fpmath=@var{FPMATH}")} attribute
+Specify which floating point unit to use. The
+@code{target("fpmath=sse,387")} option must be specified as
+@code{target("fpmath=sse+387")} because the comma would separate
+different options.
+@end table
+
+On the 386, you can use either multiple strings to specify multiple
+options, or you can separate the option with a comma (@code{,}).
+
+On the 386, the inliner will not inline a function that has different
+target options than the caller, unless the callee has a subset of the
+target options of the caller. For example a function declared with
+@code{target("sse3")} can inline a function with
+@code{target("sse2")}, since @code{-msse3} implies @code{-msse2}.
+
+The @code{target} attribute is not implemented in GCC versions earlier
+than 4.4, and at present only the 386 uses it.
+
@item tiny_data
@cindex tiny data section on the H8/300H and H8S
Use this attribute on the H8/300H and H8S to indicate that the specified
inline assembly.
@item version_id
-@cindex @code{version_id} attribute on IA64 HP-UX
-This attribute, attached to a global variable or function, renames a
+@cindex @code{version_id} attribute
+This IA64 HP-UX attribute, attached to a global variable or function, renames a
symbol to contain a version string, thus allowing for function level
versioning. HP-UX system header files may use version level functioning
for some system calls.
of its type.
In C++, you can mark member functions and static member variables of a
-class with the visibility attribute. This is useful if if you know a
+class with the visibility attribute. This is useful if you know a
particular method or static member variable should only be used from
one shared object; then you can mark it hidden while the rest of the
class has default visibility. Care must be taken to avoid breaking
If both the template and enclosing class have explicit visibility, the
visibility from the template is used.
+@item vliw
+@cindex @code{vliw} attribute
+On MeP, the @code{vliw} attribute tells the compiler to emit
+instructions in VLIW mode instead of core mode. Note that this
+attribute is not allowed unless a VLIW coprocessor has been configured
+and enabled through command line options.
+
@item warn_unused_result
@cindex @code{warn_unused_result} attribute
The @code{warn_unused_result} attribute causes a warning to be emitted
A weak reference is an alias that does not by itself require a
definition to be given for the target symbol. If the target symbol is
-only referenced through weak references, then the becomes a @code{weak}
+only referenced through weak references, then it becomes a @code{weak}
undefined symbol. If it is directly referenced, however, then such
strong references prevail, and a definition will be required for the
symbol, not necessarily in the same translation unit.
At present, a declaration to which @code{weakref} is attached can
only be @code{static}.
-@item externally_visible
-@cindex @code{externally_visible} attribute.
-This attribute, attached to a global variable or function nullify
-effect of @option{-fwhole-program} command line option, so the object
-remain visible outside the current compilation unit
-
@end table
You can specify multiple attributes in a declaration by separating them
that may be unused but which is compiled with @option{-Wall}. It would
not normally be appropriate to use in it human-written code, though it
could be useful in cases where the code that jumps to the label is
-contained within an @code{#ifdef} conditional. GNU C++ does not permit
-such placement of attribute lists, as it is permissible for a
-declaration, which could begin with an attribute list, to be labelled in
-C++. Declarations cannot be labelled in C90 or C99, so the ambiguity
-does not arise there.
+contained within an @code{#ifdef} conditional. GNU C++ only permits
+attributes on labels if the attribute specifier is immediately
+followed by a semicolon (i.e., the label applies to an empty
+statement). If the semicolon is missing, C++ label attributes are
+ambiguous, as it is permissible for a declaration, which could begin
+with an attribute list, to be labelled in C++. Declarations cannot be
+labelled in C90 or C99, so the ambiguity does not arise there.
An attribute specifier list may appear as part of a @code{struct},
@code{union} or @code{enum} specifier. It may go either immediately
such comments, and they are included in the 1999 C standard. However,
C++ style comments are not recognized if you specify an @option{-std}
option specifying a version of ISO C before C99, or @option{-ansi}
-(equivalent to @option{-std=c89}).
+(equivalent to @option{-std=c90}).
@node Dollar Signs
@section Dollar Signs in Identifier Names
As in the preceding examples, you can explicitly specify the alignment
(in bytes) that you wish the compiler to use for a given variable or
structure field. Alternatively, you can leave out the alignment factor
-and just ask the compiler to align a variable or field to the maximum
-useful alignment for the target machine you are compiling for. For
-example, you could write:
+and just ask the compiler to align a variable or field to the
+default alignment for the target architecture you are compiling for.
+The default alignment is sufficient for all scalar types, but may not be
+enough for all vector types on a target which supports vector operations.
+The default alignment is fixed for a particular target ABI.
+
+Gcc also provides a target specific macro @code{__BIGGEST_ALIGNMENT__},
+which is the largest alignment ever used for any data type on the
+target machine you are compiling for. For example, you could write:
@smallexample
-short array[3] __attribute__ ((aligned));
+short array[3] __attribute__ ((aligned (__BIGGEST_ALIGNMENT__)));
@end smallexample
-Whenever you leave out the alignment factor in an @code{aligned} attribute
-specification, the compiler automatically sets the alignment for the declared
-variable or field to the largest alignment which is ever used for any data
-type on the target machine you are compiling for. Doing this can often make
-copy operations more efficient, because the compiler can use whatever
-instructions copy the biggest chunks of memory when performing copies to
-or from the variables or fields that you have aligned this way.
+The compiler automatically sets the alignment for the declared
+variable or field to @code{__BIGGEST_ALIGNMENT__}. Doing this can
+often make copy operations more efficient, because the compiler can
+use whatever instructions copy the biggest chunks of memory when
+performing copies to or from the variables or fields that you have
+aligned this way. Note that the value of @code{__BIGGEST_ALIGNMENT__}
+may change depending on command line options.
When used on a struct, or struct member, the @code{aligned} attribute can
only increase the alignment; in order to decrease it, the @code{packed}
@option{-fno-common} and @option{-fcommon} flags respectively.
@item deprecated
+@itemx deprecated (@var{msg})
@cindex @code{deprecated} attribute
The @code{deprecated} attribute results in a warning if the variable
is used anywhere in the source file. This is useful when identifying
int new_fn () @{ return old_var; @}
@end smallexample
-results in a warning on line 3 but not line 2.
+results in a warning on line 3 but not line 2. The optional msg
+argument, which must be a string, will be printed in the warning if
+present.
The @code{deprecated} attribute can also be used for functions and
types (@pxref{Function Attributes}, @pxref{Type Attributes}.)
@};
@end smallexample
+@emph{Note:} The 4.1, 4.2 and 4.3 series of GCC ignore the
+@code{packed} attribute on bit-fields of type @code{char}. This has
+been fixed in GCC 4.4 but the change can lead to differences in the
+structure layout. See the documentation of
+@option{-Wpacked-bitfield-compat} for more information.
+
@item section ("@var{section-name}")
@cindex @code{section} variable attribute
Normally, the compiler places the objects it generates in sections like
struct duart a __attribute__ ((section ("DUART_A"))) = @{ 0 @};
struct duart b __attribute__ ((section ("DUART_B"))) = @{ 0 @};
char stack[10000] __attribute__ ((section ("STACK"))) = @{ 0 @};
-int init_data __attribute__ ((section ("INITDATA"))) = 0;
+int init_data __attribute__ ((section ("INITDATA")));
main()
@{
@end smallexample
@noindent
-Use the @code{section} attribute with an @emph{initialized} definition
-of a @emph{global} variable, as shown in the example. GCC issues
-a warning and otherwise ignores the @code{section} attribute in
-uninitialized variable declarations.
+Use the @code{section} attribute with
+@emph{global} variables and not @emph{local} variables,
+as shown in the example.
-You may only use the @code{section} attribute with a fully initialized
-global definition because of the way linkers work. The linker requires
+You may use the @code{section} attribute with initialized or
+uninitialized global variables but the linker requires
each object be defined once, with the exception that uninitialized
variables tentatively go in the @code{common} (or @code{bss}) section
-and can be multiply ``defined''. You can force a variable to be
-initialized with the @option{-fno-common} flag or the @code{nocommon}
-attribute.
+and can be multiply ``defined''. Using the @code{section} attribute
+will change what section the variable goes into and may cause the
+linker to issue an error if an uninitialized variable has multiple
+definitions. You can force a variable to be initialized with the
+@option{-fno-common} flag or the @code{nocommon} attribute.
Some file formats do not support arbitrary sections so the @code{section}
attribute is not available on all platforms.
@cindex @code{tls_model} attribute
The @code{tls_model} attribute sets thread-local storage model
(@pxref{Thread-Local}) of a particular @code{__thread} variable,
-overriding @option{-ftls-model=} command line switch on a per-variable
+overriding @option{-ftls-model=} command-line switch on a per-variable
basis.
The @var{tls_model} argument should be one of @code{global-dynamic},
@code{local-dynamic}, @code{initial-exec} or @code{local-exec}.
compilers.
@item weak
-The @code{weak} attribute is described in @xref{Function Attributes}.
+The @code{weak} attribute is described in @ref{Function Attributes}.
@item dllimport
-The @code{dllimport} attribute is described in @xref{Function Attributes}.
+The @code{dllimport} attribute is described in @ref{Function Attributes}.
@item dllexport
-The @code{dllexport} attribute is described in @xref{Function Attributes}.
+The @code{dllexport} attribute is described in @ref{Function Attributes}.
@end table
@table @code
@item l1_data
-@item l1_data_A
-@item l1_data_B
+@itemx l1_data_A
+@itemx l1_data_B
@cindex @code{l1_data} variable attribute
@cindex @code{l1_data_A} variable attribute
@cindex @code{l1_data_B} variable attribute
named @code{.l1.data}. Those with @code{l1_data_A} attribute will be put into
the specific section named @code{.l1.data.A}. Those with @code{l1_data_B}
attribute will be put into the specific section named @code{.l1.data.B}.
+
+@item l2
+@cindex @code{l2} variable attribute
+Use this attribute on the Blackfin to place the variable into L2 SRAM.
+Variables with @code{l2} attribute will be put into the specific section
+named @code{.l2.data}.
@end table
@subsection M32R/D Variable Attributes
addresses).
@end table
+@anchor{MeP Variable Attributes}
+@subsection MeP Variable Attributes
+
+The MeP target has a number of addressing modes and busses. The
+@code{near} space spans the standard memory space's first 16 megabytes
+(24 bits). The @code{far} space spans the entire 32-bit memory space.
+The @code{based} space is a 128 byte region in the memory space which
+is addressed relative to the @code{$tp} register. The @code{tiny}
+space is a 65536 byte region relative to the @code{$gp} register. In
+addition to these memory regions, the MeP target has a separate 16-bit
+control bus which is specified with @code{cb} attributes.
+
+@table @code
+
+@item based
+Any variable with the @code{based} attribute will be assigned to the
+@code{.based} section, and will be accessed with relative to the
+@code{$tp} register.
+
+@item tiny
+Likewise, the @code{tiny} attribute assigned variables to the
+@code{.tiny} section, relative to the @code{$gp} register.
+
+@item near
+Variables with the @code{near} attribute are assumed to have addresses
+that fit in a 24-bit addressing mode. This is the default for large
+variables (@code{-mtiny=4} is the default) but this attribute can
+override @code{-mtiny=} for small variables, or override @code{-ml}.
+
+@item far
+Variables with the @code{far} attribute are addressed using a full
+32-bit address. Since this covers the entire memory space, this
+allows modules to make no assumptions about where variables might be
+stored.
+
+@item io
+@itemx io (@var{addr})
+Variables with the @code{io} attribute are used to address
+memory-mapped peripherals. If an address is specified, the variable
+is assigned that address, else it is not assigned an address (it is
+assumed some other module will assign an address). Example:
+
+@example
+int timer_count __attribute__((io(0x123)));
+@end example
+
+@item cb
+@itemx cb (@var{addr})
+Variables with the @code{cb} attribute are used to access the control
+bus, using special instructions. @code{addr} indicates the control bus
+address. Example:
+
+@example
+int cpu_clock __attribute__((cb(0x123)));
+@end example
+
+@end table
+
@anchor{i386 Variable Attributes}
@subsection i386 Variable Attributes
@code{altivec}, @code{ms_struct} and @code{gcc_struct}.
For full documentation of the struct attributes please see the
-documentation in the @xref{i386 Variable Attributes}, section.
+documentation in @ref{i386 Variable Attributes}.
For documentation of @code{altivec} attribute please see the
-documentation in the @xref{PowerPC Type Attributes}, section.
+documentation in @ref{PowerPC Type Attributes}.
@subsection SPU Variable Attributes
The SPU supports the @code{spu_vector} attribute for variables. For
-documentation of this attribute please see the documentation in the
-@xref{SPU Type Attributes}, section.
+documentation of this attribute please see the documentation in
+@ref{SPU Type Attributes}.
@subsection Xstormy16 Variable Attributes
One attribute is currently defined for xstormy16 configurations:
-@code{below100}
+@code{below100}.
@table @code
@item below100
@};
@end smallexample
-You may only specify this attribute on the definition of a @code{enum},
+You may only specify this attribute on the definition of an @code{enum},
@code{struct} or @code{union}, not on a @code{typedef} which does not
also define the enumerated type, structure or union.
nontrivial bookkeeping functions.
@item deprecated
+@itemx deprecated (@var{msg})
The @code{deprecated} attribute results in a warning if the type
is used anywhere in the source file. This is useful when identifying
types that are expected to be removed in a future version of a program.
results in a warning on line 2 and 3 but not lines 4, 5, or 6. No
warning is issued for line 4 because T2 is not explicitly
deprecated. Line 5 has no warning because T3 is explicitly
-deprecated. Similarly for line 6.
+deprecated. Similarly for line 6. The optional msg
+argument, which must be a string, will be printed in the warning if
+present.
The @code{deprecated} attribute can also be used for functions and
variables (@pxref{Function Attributes}, @pxref{Variable Attributes}.)
@item may_alias
-Accesses to objects with types with this attribute are not subjected to
-type-based alias analysis, but are instead assumed to be able to alias
-any other type of objects, just like the @code{char} type. See
-@option{-fstrict-aliasing} for more information on aliasing issues.
+Accesses through pointers to types with this attribute are not subject
+to type-based alias analysis, but are instead assumed to be able to alias
+any other type of objects. In the context of 6.5/7 an lvalue expression
+dereferencing such a pointer is treated like having a character type.
+See @option{-fstrict-aliasing} for more information on aliasing issues.
+This extension exists to support some vector APIs, in which pointers to
+one vector type are permitted to alias pointers to a different vector type.
+
+Note that an object of a type with this attribute does not have any
+special semantics.
Example of use:
Otherwise the two shared objects will be unable to use the same
typeinfo node and exception handling will break.
+@end table
+
@subsection ARM Type Attributes
On those ARM targets that support @code{dllimport} (such as Symbian
@code{__attribute__} instead of @code{__declspec} if you prefer, but
most Symbian OS code uses @code{__declspec}.)
+@anchor{MeP Type Attributes}
+@subsection MeP Type Attributes
+
+Many of the MeP variable attributes may be applied to types as well.
+Specifically, the @code{based}, @code{tiny}, @code{near}, and
+@code{far} attributes may be applied to either. The @code{io} and
+@code{cb} attributes may not be applied to types.
+
@anchor{i386 Type Attributes}
@subsection i386 Type Attributes
Two attributes are currently defined for i386 configurations:
-@code{ms_struct} and @code{gcc_struct}
+@code{ms_struct} and @code{gcc_struct}.
+
+@table @code
@item ms_struct
@itemx gcc_struct
Three attributes currently are defined for PowerPC configurations:
@code{altivec}, @code{ms_struct} and @code{gcc_struct}.
-For full documentation of the struct attributes please see the
-documentation in the @xref{i386 Type Attributes}, section.
+For full documentation of the @code{ms_struct} and @code{gcc_struct}
+attributes please see the documentation in @ref{i386 Type Attributes}.
The @code{altivec} attribute allows one to declare AltiVec vector data
types supported by the AltiVec Programming Interface Manual. The
GCC implements three different semantics of declaring a function
inline. One is available with @option{-std=gnu89} or
@option{-fgnu89-inline} or when @code{gnu_inline} attribute is present
-on all inline declarations, another when @option{-std=c99} or
-@option{-std=gnu99} (without @option{-fgnu89-inline}), and the third
+on all inline declarations, another when
+@option{-std=c99}, @option{-std=c1x},
+@option{-std=gnu99} or @option{-std=gnu1x}
+(without @option{-fgnu89-inline}), and the third
is used when compiling C++.
To declare a function inline, use the @code{inline} keyword in its
static inline int
inc (int *a)
@{
- (*a)++;
+ return (*a)++;
@}
@end smallexample
-If you are writing a header file to be included in ISO C89 programs, write
+If you are writing a header file to be included in ISO C90 programs, write
@code{__inline__} instead of @code{inline}. @xref{Alternate Keywords}.
The three types of inlining behave similarly in two important cases:
inline int
inc (int *a)
@{
- (*a)++;
+ return (*a)++;
@}
@end smallexample
inline void foo (const char) __attribute__((always_inline));
@end smallexample
-The remainder of this section is specific to GNU C89 inlining.
+The remainder of this section is specific to GNU C90 inlining.
@cindex non-static inline function
When an inline function is not @code{static}, then the compiler must assume
In the above example, beware that a register that is call-clobbered by
the target ABI will be overwritten by any function call in the
assignment, including library calls for arithmetic operators.
+Also a register may be clobbered when generating some operations,
+like variable shift, memory copy or memory move on x86.
Assuming it is a call-clobbered register, this may happen to @code{r0}
above by the assignment to @code{p2}. If you have to use such a
register, use temporary variables for expressions between the register
Speaking of labels, jumps from one @code{asm} to another are not
supported. The compiler's optimizers do not know about these jumps, and
therefore they cannot take account of them when deciding how to
-optimize.
+optimize. @xref{Extended asm with goto}.
@cindex macros containing @code{asm}
Usually the most convenient way to use these @code{asm} instructions is to
an assembler instruction access to the condition code left by previous
instructions.
+@anchor{Extended asm with goto}
+As of GCC version 4.5, @code{asm goto} may be used to have the assembly
+jump to one or more C labels. In this form, a fifth section after the
+clobber list contains a list of all C labels to which the assembly may jump.
+Each label operand is implicitly self-named. The @code{asm} is also assumed
+to fall through to the next statement.
+
+This form of @code{asm} is restricted to not have outputs. This is due
+to a internal restriction in the compiler that control transfer instructions
+cannot have outputs. This restriction on @code{asm goto} may be lifted
+in some future version of the compiler. In the mean time, @code{asm goto}
+may include a memory clobber, and so leave outputs in memory.
+
+@smallexample
+int frob(int x)
+@{
+ int y;
+ asm goto ("frob %%r5, %1; jc %l[error]; mov (%2), %%r5"
+ : : "r"(x), "r"(&y) : "r5", "memory" : error);
+ return y;
+ error:
+ return -1;
+@}
+@end smallexample
+
+In this (inefficient) example, the @code{frob} instruction sets the
+carry bit to indicate an error. The @code{jc} instruction detects
+this and branches to the @code{error} label. Finally, the output
+of the @code{frob} instruction (@code{%r5}) is stored into the memory
+for variable @code{y}, which is later read by the @code{return} statement.
+
+@smallexample
+void doit(void)
+@{
+ int i = 0;
+ asm goto ("mfsr %%r1, 123; jmp %%r1;"
+ ".pushsection doit_table;"
+ ".long %l0, %l1, %l2, %l3;"
+ ".popsection"
+ : : : "r1" : label1, label2, label3, label4);
+ __builtin_unreachable ();
+
+ label1:
+ f1();
+ return;
+ label2:
+ f2();
+ return;
+ label3:
+ i = 1;
+ label4:
+ f3(i);
+@}
+@end smallexample
+
+In this (also inefficient) example, the @code{mfsr} instruction reads
+an address from some out-of-band machine register, and the following
+@code{jmp} instruction branches to that address. The address read by
+the @code{mfsr} instruction is assumed to have been previously set via
+some application-specific mechanism to be one of the four values stored
+in the @code{doit_table} section. Finally, the @code{asm} is followed
+by a call to @code{__builtin_unreachable} to indicate that the @code{asm}
+does not in fact fall through.
+
+@smallexample
+#define TRACE1(NUM) \
+ do @{ \
+ asm goto ("0: nop;" \
+ ".pushsection trace_table;" \
+ ".long 0b, %l0;" \
+ ".popsection" \
+ : : : : trace#NUM); \
+ if (0) @{ trace#NUM: trace(); @} \
+ @} while (0)
+#define TRACE TRACE1(__COUNTER__)
+@end smallexample
+
+In this example (which in fact inspired the @code{asm goto} feature)
+we want on rare occasions to call the @code{trace} function; on other
+occasions we'd like to keep the overhead to the absolute minimum.
+The normal code path consists of a single @code{nop} instruction.
+However, we record the address of this @code{nop} together with the
+address of a label that calls the @code{trace} function. This allows
+the @code{nop} instruction to be patched at runtime to be an
+unconditional branch to the stored label. It is assumed that an
+optimizing compiler will move the labeled block out of line, to
+optimize the fall through path from the @code{asm}.
+
If you are writing a header file that should be includable in ISO C
programs, write @code{__asm__} instead of @code{asm}. @xref{Alternate
Keywords}.
including ISO C programs. The keywords @code{asm}, @code{typeof} and
@code{inline} are not available in programs compiled with
@option{-ansi} or @option{-std} (although @code{inline} can be used in a
-program compiled with @option{-std=c99}). The ISO C99 keyword
+program compiled with @option{-std=c99} or @option{-std=c1x}). The
+ISO C99 keyword
@code{restrict} is only available when @option{-std=gnu99} (which will
eventually be the default) or @option{-std=c99} (or the equivalent
-@option{-std=iso9899:1999}) is used.
+@option{-std=iso9899:1999}), or an option for a later standard
+version, is used.
The way to solve these problems is to put @samp{__} at the beginning and
end of each problematical keyword. For example, use @code{__asm__}
function, as a string. The first of these is @code{__func__}, which
is part of the C99 standard:
-@display
The identifier @code{__func__} is implicitly declared by the translator
as if, immediately following the opening brace of each function
definition, the declaration
static const char __func__[] = "function-name";
@end smallexample
+@noindent
appeared, where function-name is the name of the lexically-enclosing
function. This name is the unadorned name of the function.
-@end display
@code{__FUNCTION__} is another name for @code{__func__}. Older
versions of GCC recognize only this name. However, it is not
random value. In addition, @code{__builtin_frame_address} may be used
to determine if the top of the stack has been reached.
+Additional post-processing of the returned value may be needed, see
+@code{__builtin_extract_return_address}.
+
This function should only be used with a nonzero argument for debugging
purposes.
@end deftypefn
+@deftypefn {Built-in Function} {void *} __builtin_extract_return_address (void *@var{addr})
+The address as returned by @code{__builtin_return_address} may have to be fed
+through this function to get the actual encoded address. For example, on the
+31-bit S/390 platform the highest bit has to be masked out, or on SPARC
+platforms an offset has to be added for the true next instruction to be
+executed.
+
+If no fixup is needed, this function simply passes through @var{addr}.
+@end deftypefn
+
+@deftypefn {Built-in Function} {void *} __builtin_frob_return_address (void *@var{addr})
+This function does the reverse of @code{__builtin_extract_return_address}.
+@end deftypefn
+
@deftypefn {Built-in Function} {void *} __builtin_frame_address (unsigned int @var{level})
This function is similar to @code{__builtin_return_address}, but it
returns the address of the function frame rather than the return address
On some targets, the instruction set contains SIMD vector instructions that
operate on multiple values contained in one large register at the same time.
-For example, on the i386 the MMX, 3Dnow! and SSE extensions can be used
+For example, on the i386 the MMX, 3DNow!@: and SSE extensions can be used
this way.
The first step in using these extensions is to provide the necessary data
The types defined in this manner can be used with a subset of normal C
operations. Currently, GCC will allow using the following operators
-on these types: @code{+, -, *, /, unary minus, ^, |, &, ~}@.
+on these types: @code{+, -, *, /, unary minus, ^, |, &, ~, %}@.
The operations behave like C++ @code{valarrays}. Addition is defined as
the addition of the corresponding elements of the operands. For
@smallexample
primary:
- "__builtin_offsetof" "(" @code{typename} "," offsetof_member_designator ")"
+ "__builtin_offsetof" "(" @code{typename} "," offsetof_member_designator ")"
offsetof_member_designator:
- @code{identifier}
- | offsetof_member_designator "." @code{identifier}
- | offsetof_member_designator "[" @code{expr} "]"
+ @code{identifier}
+ | offsetof_member_designator "." @code{identifier}
+ | offsetof_member_designator "[" @code{expr} "]"
@end smallexample
This extension is sufficient such that
processor from speculating loads across the operation and from queuing stores
after the operation.
-All of the routines are are described in the Intel documentation to take
+All of the routines are described in the Intel documentation to take
``an optional list of variables protected by the memory barrier''. It's
not clear what is meant by that; it could mean that @emph{only} the
following variables are protected, or it could mean that these variables
@smallexample
@{ tmp = *ptr; *ptr @var{op}= value; return tmp; @}
-@{ tmp = *ptr; *ptr = ~tmp & value; return tmp; @} // nand
+@{ tmp = *ptr; *ptr = ~(tmp & value); return tmp; @} // nand
@end smallexample
+@emph{Note:} GCC 4.4 and later implement @code{__sync_fetch_and_nand}
+builtin as @code{*ptr = ~(tmp & value)} instead of @code{*ptr = ~tmp & value}.
+
@item @var{type} __sync_add_and_fetch (@var{type} *ptr, @var{type} value, ...)
@itemx @var{type} __sync_sub_and_fetch (@var{type} *ptr, @var{type} value, ...)
@itemx @var{type} __sync_or_and_fetch (@var{type} *ptr, @var{type} value, ...)
@smallexample
@{ *ptr @var{op}= value; return *ptr; @}
-@{ *ptr = ~*ptr & value; return *ptr; @} // nand
+@{ *ptr = ~(*ptr & value); return *ptr; @} // nand
@end smallexample
+@emph{Note:} GCC 4.4 and later implement @code{__sync_nand_and_fetch}
+builtin as @code{*ptr = ~(*ptr & value)} instead of
+@code{*ptr = ~*ptr & value}.
+
@item bool __sync_bool_compare_and_swap (@var{type} *ptr, @var{type} oldval @var{type} newval, ...)
@itemx @var{type} __sync_val_compare_and_swap (@var{type} *ptr, @var{type} oldval @var{type} newval, ...)
@findex __sync_bool_compare_and_swap
assert (__builtin_object_size (p, 1) == sizeof (var.buf1) - 1);
/* The object q points to is var. */
assert (__builtin_object_size (q, 0)
- == (char *) (&var + 1) - (char *) &var.b);
+ == (char *) (&var + 1) - (char *) &var.b);
/* The subobject q points to is var.b. */
assert (__builtin_object_size (q, 1) == sizeof (var.b));
@end smallexample
@smallexample
int __builtin___sprintf_chk (char *s, int flag, size_t os, const char *fmt, ...);
int __builtin___snprintf_chk (char *s, size_t maxlen, int flag, size_t os,
- const char *fmt, ...);
+ const char *fmt, ...);
int __builtin___vsprintf_chk (char *s, int flag, size_t os, const char *fmt,
- va_list ap);
+ va_list ap);
int __builtin___vsnprintf_chk (char *s, size_t maxlen, int flag, size_t os,
- const char *fmt, va_list ap);
+ const char *fmt, va_list ap);
@end smallexample
The added @var{flag} argument is passed unchanged to @code{__sprintf_chk}
@opindex ansi
@opindex std
-Outside strict ISO C mode (@option{-ansi}, @option{-std=c89} or
-@option{-std=c99}), the functions
+Outside strict ISO C mode (@option{-ansi}, @option{-std=c90},
+@option{-std=c99} or @option{-std=c1x}), the functions
@code{_exit}, @code{alloca}, @code{bcmp}, @code{bzero},
@code{dcgettext}, @code{dgettext}, @code{dremf}, @code{dreml},
@code{drem}, @code{exp10f}, @code{exp10l}, @code{exp10}, @code{ffsll},
@code{yn}
may be handled as built-in functions.
All these functions have corresponding versions
-prefixed with @code{__builtin_}, which may be used even in strict C89
+prefixed with @code{__builtin_}, which may be used even in strict C90
mode.
The ISO C99 functions
@code{tgamma}, @code{truncf}, @code{truncl}, @code{trunc},
@code{vfscanf}, @code{vscanf}, @code{vsnprintf} and @code{vsscanf}
are handled as built-in functions
-except in strict ISO C90 mode (@option{-ansi} or @option{-std=c89}).
+except in strict ISO C90 mode (@option{-ansi} or @option{-std=c90}).
There are also built-in versions of the ISO C99 functions
@code{acosf}, @code{acosl}, @code{asinf}, @code{asinl}, @code{atan2f},
@code{iswspace}, @code{iswupper}, @code{iswxdigit}, @code{towlower} and
@code{towupper}
are handled as built-in functions
-except in strict ISO C90 mode (@option{-ansi} or @option{-std=c89}).
+except in strict ISO C90 mode (@option{-ansi} or @option{-std=c90}).
The ISO C90 functions
@code{abort}, @code{abs}, @code{acos}, @code{asin}, @code{atan2},
You can use the built-in function @code{__builtin_choose_expr} to
evaluate code depending on the value of a constant expression. This
-built-in function returns @var{exp1} if @var{const_exp}, which is a
-constant expression that must be able to be determined at compile time,
-is nonzero. Otherwise it returns 0.
+built-in function returns @var{exp1} if @var{const_exp}, which is an
+integer constant expression, is nonzero. Otherwise it returns 0.
This built-in function is analogous to the @samp{? :} operator in C,
except that the expression returned has its type unaltered by promotion
@noindent
This is an acceptable initializer even if @var{EXPRESSION} is not a
-constant expression. GCC must be more conservative about evaluating the
+constant expression, including the case where
+@code{__builtin_constant_p} returns 1 because @var{EXPRESSION} can be
+folded to a constant but @var{EXPRESSION} contains operands that would
+not otherwise be permitted in a static initializer (for example,
+@code{0 && foo ()}). GCC must be more conservative about evaluating the
built-in in this case, because it has no opportunity to perform
optimization.
you should not rely on any particular implementation.
@end deftypefn
+@deftypefn {Built-in Function} void __builtin_unreachable (void)
+If control flow reaches the point of the @code{__builtin_unreachable},
+the program is undefined. It is useful in situations where the
+compiler cannot deduce the unreachability of the code.
+
+One such case is immediately following an @code{asm} statement that
+will either never terminate, or one that transfers control elsewhere
+and never returns. In this example, without the
+@code{__builtin_unreachable}, GCC would issue a warning that control
+reaches the end of a non-void function. It would also generate code
+to return after the @code{asm}.
+
+@smallexample
+int f (int c, int v)
+@{
+ if (c)
+ @{
+ return v;
+ @}
+ else
+ @{
+ asm("jmp error_handler");
+ __builtin_unreachable ();
+ @}
+@}
+@end smallexample
+
+Because the @code{asm} statement unconditionally transfers control out
+of the function, control will never reach the end of the function
+body. The @code{__builtin_unreachable} is in fact unreachable and
+communicates this fact to the compiler.
+
+Another use for @code{__builtin_unreachable} is following a call a
+function that never returns but that is not declared
+@code{__attribute__((noreturn))}, as in this example:
+
+@smallexample
+void function_that_never_returns (void);
+
+int g (int c)
+@{
+ if (c)
+ @{
+ return 1;
+ @}
+ else
+ @{
+ function_that_never_returns ();
+ __builtin_unreachable ();
+ @}
+@}
+@end smallexample
+
+@end deftypefn
+
@deftypefn {Built-in Function} void __builtin___clear_cache (char *@var{begin}, char *@var{end})
This function is used to flush the processor's instruction cache for
the region of memory between @var{begin} inclusive and @var{end}
* X86 Built-in Functions::
* MIPS DSP Built-in Functions::
* MIPS Paired-Single Support::
-* PowerPC AltiVec Built-in Functions::
+* MIPS Loongson Built-in Functions::
+* Other MIPS Built-in Functions::
+* picoChip Built-in Functions::
+* PowerPC AltiVec/VSX Built-in Functions::
+* RX Built-in Functions::
* SPARC VIS Built-in Functions::
* SPU Built-in Functions::
@end menu
vector of eight 8-bit integers. Some of the built-in functions operate on
MMX registers as a whole 64-bit entity, these use @code{V1DI} as their mode.
-If 3Dnow extensions are enabled, @code{V2SF} is used as a mode for a vector
+If 3DNow!@: extensions are enabled, @code{V2SF} is used as a mode for a vector
of two 32-bit floating point values.
If SSE extensions are enabled, @code{V4SF} is used for a vector of four 32-bit
@table @code
@item __float128 __builtin_infq (void)
Similar to @code{__builtin_inf}, except the return type is @code{__float128}.
+@findex __builtin_infq
+
+@item __float128 __builtin_huge_valq (void)
+Similar to @code{__builtin_huge_val}, except the return type is @code{__float128}.
+@findex __builtin_huge_valq
@end table
The following built-in functions are made available by @option{-mmmx}.
v8hi __builtin_ia32_psrawi128 (v8hi, int)
v4si __builtin_ia32_psradi128 (v4si, int)
v4si __builtin_ia32_pmaddwd128 (v8hi, v8hi)
+v2di __builtin_ia32_movq128 (v2di)
@end smallexample
The following built-in functions are available when @option{-msse3} is used.
@item unsigned int __builtin_ia32_crc32si (unsigned int, unsigned int)
Generates the @code{crc32l} machine instruction.
@item unsigned long long __builtin_ia32_crc32di (unsigned long long, unsigned long long)
+Generates the @code{crc32q} machine instruction.
@end table
The following built-in functions are changed to generate new SSE4.2
Generates the @code{popcntq} machine instruction.
@end table
+The following built-in functions are available when @option{-mavx} is
+used. All of them generate the machine instruction that is part of the
+name.
+
+@smallexample
+v4df __builtin_ia32_addpd256 (v4df,v4df)
+v8sf __builtin_ia32_addps256 (v8sf,v8sf)
+v4df __builtin_ia32_addsubpd256 (v4df,v4df)
+v8sf __builtin_ia32_addsubps256 (v8sf,v8sf)
+v4df __builtin_ia32_andnpd256 (v4df,v4df)
+v8sf __builtin_ia32_andnps256 (v8sf,v8sf)
+v4df __builtin_ia32_andpd256 (v4df,v4df)
+v8sf __builtin_ia32_andps256 (v8sf,v8sf)
+v4df __builtin_ia32_blendpd256 (v4df,v4df,int)
+v8sf __builtin_ia32_blendps256 (v8sf,v8sf,int)
+v4df __builtin_ia32_blendvpd256 (v4df,v4df,v4df)
+v8sf __builtin_ia32_blendvps256 (v8sf,v8sf,v8sf)
+v2df __builtin_ia32_cmppd (v2df,v2df,int)
+v4df __builtin_ia32_cmppd256 (v4df,v4df,int)
+v4sf __builtin_ia32_cmpps (v4sf,v4sf,int)
+v8sf __builtin_ia32_cmpps256 (v8sf,v8sf,int)
+v2df __builtin_ia32_cmpsd (v2df,v2df,int)
+v4sf __builtin_ia32_cmpss (v4sf,v4sf,int)
+v4df __builtin_ia32_cvtdq2pd256 (v4si)
+v8sf __builtin_ia32_cvtdq2ps256 (v8si)
+v4si __builtin_ia32_cvtpd2dq256 (v4df)
+v4sf __builtin_ia32_cvtpd2ps256 (v4df)
+v8si __builtin_ia32_cvtps2dq256 (v8sf)
+v4df __builtin_ia32_cvtps2pd256 (v4sf)
+v4si __builtin_ia32_cvttpd2dq256 (v4df)
+v8si __builtin_ia32_cvttps2dq256 (v8sf)
+v4df __builtin_ia32_divpd256 (v4df,v4df)
+v8sf __builtin_ia32_divps256 (v8sf,v8sf)
+v8sf __builtin_ia32_dpps256 (v8sf,v8sf,int)
+v4df __builtin_ia32_haddpd256 (v4df,v4df)
+v8sf __builtin_ia32_haddps256 (v8sf,v8sf)
+v4df __builtin_ia32_hsubpd256 (v4df,v4df)
+v8sf __builtin_ia32_hsubps256 (v8sf,v8sf)
+v32qi __builtin_ia32_lddqu256 (pcchar)
+v32qi __builtin_ia32_loaddqu256 (pcchar)
+v4df __builtin_ia32_loadupd256 (pcdouble)
+v8sf __builtin_ia32_loadups256 (pcfloat)
+v2df __builtin_ia32_maskloadpd (pcv2df,v2df)
+v4df __builtin_ia32_maskloadpd256 (pcv4df,v4df)
+v4sf __builtin_ia32_maskloadps (pcv4sf,v4sf)
+v8sf __builtin_ia32_maskloadps256 (pcv8sf,v8sf)
+void __builtin_ia32_maskstorepd (pv2df,v2df,v2df)
+void __builtin_ia32_maskstorepd256 (pv4df,v4df,v4df)
+void __builtin_ia32_maskstoreps (pv4sf,v4sf,v4sf)
+void __builtin_ia32_maskstoreps256 (pv8sf,v8sf,v8sf)
+v4df __builtin_ia32_maxpd256 (v4df,v4df)
+v8sf __builtin_ia32_maxps256 (v8sf,v8sf)
+v4df __builtin_ia32_minpd256 (v4df,v4df)
+v8sf __builtin_ia32_minps256 (v8sf,v8sf)
+v4df __builtin_ia32_movddup256 (v4df)
+int __builtin_ia32_movmskpd256 (v4df)
+int __builtin_ia32_movmskps256 (v8sf)
+v8sf __builtin_ia32_movshdup256 (v8sf)
+v8sf __builtin_ia32_movsldup256 (v8sf)
+v4df __builtin_ia32_mulpd256 (v4df,v4df)
+v8sf __builtin_ia32_mulps256 (v8sf,v8sf)
+v4df __builtin_ia32_orpd256 (v4df,v4df)
+v8sf __builtin_ia32_orps256 (v8sf,v8sf)
+v2df __builtin_ia32_pd_pd256 (v4df)
+v4df __builtin_ia32_pd256_pd (v2df)
+v4sf __builtin_ia32_ps_ps256 (v8sf)
+v8sf __builtin_ia32_ps256_ps (v4sf)
+int __builtin_ia32_ptestc256 (v4di,v4di,ptest)
+int __builtin_ia32_ptestnzc256 (v4di,v4di,ptest)
+int __builtin_ia32_ptestz256 (v4di,v4di,ptest)
+v8sf __builtin_ia32_rcpps256 (v8sf)
+v4df __builtin_ia32_roundpd256 (v4df,int)
+v8sf __builtin_ia32_roundps256 (v8sf,int)
+v8sf __builtin_ia32_rsqrtps_nr256 (v8sf)
+v8sf __builtin_ia32_rsqrtps256 (v8sf)
+v4df __builtin_ia32_shufpd256 (v4df,v4df,int)
+v8sf __builtin_ia32_shufps256 (v8sf,v8sf,int)
+v4si __builtin_ia32_si_si256 (v8si)
+v8si __builtin_ia32_si256_si (v4si)
+v4df __builtin_ia32_sqrtpd256 (v4df)
+v8sf __builtin_ia32_sqrtps_nr256 (v8sf)
+v8sf __builtin_ia32_sqrtps256 (v8sf)
+void __builtin_ia32_storedqu256 (pchar,v32qi)
+void __builtin_ia32_storeupd256 (pdouble,v4df)
+void __builtin_ia32_storeups256 (pfloat,v8sf)
+v4df __builtin_ia32_subpd256 (v4df,v4df)
+v8sf __builtin_ia32_subps256 (v8sf,v8sf)
+v4df __builtin_ia32_unpckhpd256 (v4df,v4df)
+v8sf __builtin_ia32_unpckhps256 (v8sf,v8sf)
+v4df __builtin_ia32_unpcklpd256 (v4df,v4df)
+v8sf __builtin_ia32_unpcklps256 (v8sf,v8sf)
+v4df __builtin_ia32_vbroadcastf128_pd256 (pcv2df)
+v8sf __builtin_ia32_vbroadcastf128_ps256 (pcv4sf)
+v4df __builtin_ia32_vbroadcastsd256 (pcdouble)
+v4sf __builtin_ia32_vbroadcastss (pcfloat)
+v8sf __builtin_ia32_vbroadcastss256 (pcfloat)
+v2df __builtin_ia32_vextractf128_pd256 (v4df,int)
+v4sf __builtin_ia32_vextractf128_ps256 (v8sf,int)
+v4si __builtin_ia32_vextractf128_si256 (v8si,int)
+v4df __builtin_ia32_vinsertf128_pd256 (v4df,v2df,int)
+v8sf __builtin_ia32_vinsertf128_ps256 (v8sf,v4sf,int)
+v8si __builtin_ia32_vinsertf128_si256 (v8si,v4si,int)
+v4df __builtin_ia32_vperm2f128_pd256 (v4df,v4df,int)
+v8sf __builtin_ia32_vperm2f128_ps256 (v8sf,v8sf,int)
+v8si __builtin_ia32_vperm2f128_si256 (v8si,v8si,int)
+v2df __builtin_ia32_vpermil2pd (v2df,v2df,v2di,int)
+v4df __builtin_ia32_vpermil2pd256 (v4df,v4df,v4di,int)
+v4sf __builtin_ia32_vpermil2ps (v4sf,v4sf,v4si,int)
+v8sf __builtin_ia32_vpermil2ps256 (v8sf,v8sf,v8si,int)
+v2df __builtin_ia32_vpermilpd (v2df,int)
+v4df __builtin_ia32_vpermilpd256 (v4df,int)
+v4sf __builtin_ia32_vpermilps (v4sf,int)
+v8sf __builtin_ia32_vpermilps256 (v8sf,int)
+v2df __builtin_ia32_vpermilvarpd (v2df,v2di)
+v4df __builtin_ia32_vpermilvarpd256 (v4df,v4di)
+v4sf __builtin_ia32_vpermilvarps (v4sf,v4si)
+v8sf __builtin_ia32_vpermilvarps256 (v8sf,v8si)
+int __builtin_ia32_vtestcpd (v2df,v2df,ptest)
+int __builtin_ia32_vtestcpd256 (v4df,v4df,ptest)
+int __builtin_ia32_vtestcps (v4sf,v4sf,ptest)
+int __builtin_ia32_vtestcps256 (v8sf,v8sf,ptest)
+int __builtin_ia32_vtestnzcpd (v2df,v2df,ptest)
+int __builtin_ia32_vtestnzcpd256 (v4df,v4df,ptest)
+int __builtin_ia32_vtestnzcps (v4sf,v4sf,ptest)
+int __builtin_ia32_vtestnzcps256 (v8sf,v8sf,ptest)
+int __builtin_ia32_vtestzpd (v2df,v2df,ptest)
+int __builtin_ia32_vtestzpd256 (v4df,v4df,ptest)
+int __builtin_ia32_vtestzps (v4sf,v4sf,ptest)
+int __builtin_ia32_vtestzps256 (v8sf,v8sf,ptest)
+void __builtin_ia32_vzeroall (void)
+void __builtin_ia32_vzeroupper (void)
+v4df __builtin_ia32_xorpd256 (v4df,v4df)
+v8sf __builtin_ia32_xorps256 (v8sf,v8sf)
+@end smallexample
+
The following built-in functions are available when @option{-maes} is
used. All of them generate the machine instruction that is part of the
name.
v2di __builtin_ia32_insertqi (v2di, v2di, const unsigned int, const unsigned int)
@end smallexample
-The following built-in functions are available when @option{-msse5} is used.
+The following built-in functions are available when @option{-mxop} is used.
+@smallexample
+v2df __builtin_ia32_vfrczpd (v2df)
+v4sf __builtin_ia32_vfrczps (v4sf)
+v2df __builtin_ia32_vfrczsd (v2df, v2df)
+v4sf __builtin_ia32_vfrczss (v4sf, v4sf)
+v4df __builtin_ia32_vfrczpd256 (v4df)
+v8sf __builtin_ia32_vfrczps256 (v8sf)
+v2di __builtin_ia32_vpcmov (v2di, v2di, v2di)
+v2di __builtin_ia32_vpcmov_v2di (v2di, v2di, v2di)
+v4si __builtin_ia32_vpcmov_v4si (v4si, v4si, v4si)
+v8hi __builtin_ia32_vpcmov_v8hi (v8hi, v8hi, v8hi)
+v16qi __builtin_ia32_vpcmov_v16qi (v16qi, v16qi, v16qi)
+v2df __builtin_ia32_vpcmov_v2df (v2df, v2df, v2df)
+v4sf __builtin_ia32_vpcmov_v4sf (v4sf, v4sf, v4sf)
+v4di __builtin_ia32_vpcmov_v4di256 (v4di, v4di, v4di)
+v8si __builtin_ia32_vpcmov_v8si256 (v8si, v8si, v8si)
+v16hi __builtin_ia32_vpcmov_v16hi256 (v16hi, v16hi, v16hi)
+v32qi __builtin_ia32_vpcmov_v32qi256 (v32qi, v32qi, v32qi)
+v4df __builtin_ia32_vpcmov_v4df256 (v4df, v4df, v4df)
+v8sf __builtin_ia32_vpcmov_v8sf256 (v8sf, v8sf, v8sf)
+v16qi __builtin_ia32_vpcomeqb (v16qi, v16qi)
+v8hi __builtin_ia32_vpcomeqw (v8hi, v8hi)
+v4si __builtin_ia32_vpcomeqd (v4si, v4si)
+v2di __builtin_ia32_vpcomeqq (v2di, v2di)
+v16qi __builtin_ia32_vpcomequb (v16qi, v16qi)
+v4si __builtin_ia32_vpcomequd (v4si, v4si)
+v2di __builtin_ia32_vpcomequq (v2di, v2di)
+v8hi __builtin_ia32_vpcomequw (v8hi, v8hi)
+v8hi __builtin_ia32_vpcomeqw (v8hi, v8hi)
+v16qi __builtin_ia32_vpcomfalseb (v16qi, v16qi)
+v4si __builtin_ia32_vpcomfalsed (v4si, v4si)
+v2di __builtin_ia32_vpcomfalseq (v2di, v2di)
+v16qi __builtin_ia32_vpcomfalseub (v16qi, v16qi)
+v4si __builtin_ia32_vpcomfalseud (v4si, v4si)
+v2di __builtin_ia32_vpcomfalseuq (v2di, v2di)
+v8hi __builtin_ia32_vpcomfalseuw (v8hi, v8hi)
+v8hi __builtin_ia32_vpcomfalsew (v8hi, v8hi)
+v16qi __builtin_ia32_vpcomgeb (v16qi, v16qi)
+v4si __builtin_ia32_vpcomged (v4si, v4si)
+v2di __builtin_ia32_vpcomgeq (v2di, v2di)
+v16qi __builtin_ia32_vpcomgeub (v16qi, v16qi)
+v4si __builtin_ia32_vpcomgeud (v4si, v4si)
+v2di __builtin_ia32_vpcomgeuq (v2di, v2di)
+v8hi __builtin_ia32_vpcomgeuw (v8hi, v8hi)
+v8hi __builtin_ia32_vpcomgew (v8hi, v8hi)
+v16qi __builtin_ia32_vpcomgtb (v16qi, v16qi)
+v4si __builtin_ia32_vpcomgtd (v4si, v4si)
+v2di __builtin_ia32_vpcomgtq (v2di, v2di)
+v16qi __builtin_ia32_vpcomgtub (v16qi, v16qi)
+v4si __builtin_ia32_vpcomgtud (v4si, v4si)
+v2di __builtin_ia32_vpcomgtuq (v2di, v2di)
+v8hi __builtin_ia32_vpcomgtuw (v8hi, v8hi)
+v8hi __builtin_ia32_vpcomgtw (v8hi, v8hi)
+v16qi __builtin_ia32_vpcomleb (v16qi, v16qi)
+v4si __builtin_ia32_vpcomled (v4si, v4si)
+v2di __builtin_ia32_vpcomleq (v2di, v2di)
+v16qi __builtin_ia32_vpcomleub (v16qi, v16qi)
+v4si __builtin_ia32_vpcomleud (v4si, v4si)
+v2di __builtin_ia32_vpcomleuq (v2di, v2di)
+v8hi __builtin_ia32_vpcomleuw (v8hi, v8hi)
+v8hi __builtin_ia32_vpcomlew (v8hi, v8hi)
+v16qi __builtin_ia32_vpcomltb (v16qi, v16qi)
+v4si __builtin_ia32_vpcomltd (v4si, v4si)
+v2di __builtin_ia32_vpcomltq (v2di, v2di)
+v16qi __builtin_ia32_vpcomltub (v16qi, v16qi)
+v4si __builtin_ia32_vpcomltud (v4si, v4si)
+v2di __builtin_ia32_vpcomltuq (v2di, v2di)
+v8hi __builtin_ia32_vpcomltuw (v8hi, v8hi)
+v8hi __builtin_ia32_vpcomltw (v8hi, v8hi)
+v16qi __builtin_ia32_vpcomneb (v16qi, v16qi)
+v4si __builtin_ia32_vpcomned (v4si, v4si)
+v2di __builtin_ia32_vpcomneq (v2di, v2di)
+v16qi __builtin_ia32_vpcomneub (v16qi, v16qi)
+v4si __builtin_ia32_vpcomneud (v4si, v4si)
+v2di __builtin_ia32_vpcomneuq (v2di, v2di)
+v8hi __builtin_ia32_vpcomneuw (v8hi, v8hi)
+v8hi __builtin_ia32_vpcomnew (v8hi, v8hi)
+v16qi __builtin_ia32_vpcomtrueb (v16qi, v16qi)
+v4si __builtin_ia32_vpcomtrued (v4si, v4si)
+v2di __builtin_ia32_vpcomtrueq (v2di, v2di)
+v16qi __builtin_ia32_vpcomtrueub (v16qi, v16qi)
+v4si __builtin_ia32_vpcomtrueud (v4si, v4si)
+v2di __builtin_ia32_vpcomtrueuq (v2di, v2di)
+v8hi __builtin_ia32_vpcomtrueuw (v8hi, v8hi)
+v8hi __builtin_ia32_vpcomtruew (v8hi, v8hi)
+v4si __builtin_ia32_vphaddbd (v16qi)
+v2di __builtin_ia32_vphaddbq (v16qi)
+v8hi __builtin_ia32_vphaddbw (v16qi)
+v2di __builtin_ia32_vphadddq (v4si)
+v4si __builtin_ia32_vphaddubd (v16qi)
+v2di __builtin_ia32_vphaddubq (v16qi)
+v8hi __builtin_ia32_vphaddubw (v16qi)
+v2di __builtin_ia32_vphaddudq (v4si)
+v4si __builtin_ia32_vphadduwd (v8hi)
+v2di __builtin_ia32_vphadduwq (v8hi)
+v4si __builtin_ia32_vphaddwd (v8hi)
+v2di __builtin_ia32_vphaddwq (v8hi)
+v8hi __builtin_ia32_vphsubbw (v16qi)
+v2di __builtin_ia32_vphsubdq (v4si)
+v4si __builtin_ia32_vphsubwd (v8hi)
+v4si __builtin_ia32_vpmacsdd (v4si, v4si, v4si)
+v2di __builtin_ia32_vpmacsdqh (v4si, v4si, v2di)
+v2di __builtin_ia32_vpmacsdql (v4si, v4si, v2di)
+v4si __builtin_ia32_vpmacssdd (v4si, v4si, v4si)
+v2di __builtin_ia32_vpmacssdqh (v4si, v4si, v2di)
+v2di __builtin_ia32_vpmacssdql (v4si, v4si, v2di)
+v4si __builtin_ia32_vpmacsswd (v8hi, v8hi, v4si)
+v8hi __builtin_ia32_vpmacssww (v8hi, v8hi, v8hi)
+v4si __builtin_ia32_vpmacswd (v8hi, v8hi, v4si)
+v8hi __builtin_ia32_vpmacsww (v8hi, v8hi, v8hi)
+v4si __builtin_ia32_vpmadcsswd (v8hi, v8hi, v4si)
+v4si __builtin_ia32_vpmadcswd (v8hi, v8hi, v4si)
+v16qi __builtin_ia32_vpperm (v16qi, v16qi, v16qi)
+v16qi __builtin_ia32_vprotb (v16qi, v16qi)
+v4si __builtin_ia32_vprotd (v4si, v4si)
+v2di __builtin_ia32_vprotq (v2di, v2di)
+v8hi __builtin_ia32_vprotw (v8hi, v8hi)
+v16qi __builtin_ia32_vpshab (v16qi, v16qi)
+v4si __builtin_ia32_vpshad (v4si, v4si)
+v2di __builtin_ia32_vpshaq (v2di, v2di)
+v8hi __builtin_ia32_vpshaw (v8hi, v8hi)
+v16qi __builtin_ia32_vpshlb (v16qi, v16qi)
+v4si __builtin_ia32_vpshld (v4si, v4si)
+v2di __builtin_ia32_vpshlq (v2di, v2di)
+v8hi __builtin_ia32_vpshlw (v8hi, v8hi)
+@end smallexample
+
+The following built-in functions are available when @option{-mfma4} is used.
All of them generate the machine instruction that is part of the name
with MMX registers.
@smallexample
-v2df __builtin_ia32_comeqpd (v2df, v2df)
-v2df __builtin_ia32_comeqps (v2df, v2df)
-v4sf __builtin_ia32_comeqsd (v4sf, v4sf)
-v4sf __builtin_ia32_comeqss (v4sf, v4sf)
-v2df __builtin_ia32_comfalsepd (v2df, v2df)
-v2df __builtin_ia32_comfalseps (v2df, v2df)
-v4sf __builtin_ia32_comfalsesd (v4sf, v4sf)
-v4sf __builtin_ia32_comfalsess (v4sf, v4sf)
-v2df __builtin_ia32_comgepd (v2df, v2df)
-v2df __builtin_ia32_comgeps (v2df, v2df)
-v4sf __builtin_ia32_comgesd (v4sf, v4sf)
-v4sf __builtin_ia32_comgess (v4sf, v4sf)
-v2df __builtin_ia32_comgtpd (v2df, v2df)
-v2df __builtin_ia32_comgtps (v2df, v2df)
-v4sf __builtin_ia32_comgtsd (v4sf, v4sf)
-v4sf __builtin_ia32_comgtss (v4sf, v4sf)
-v2df __builtin_ia32_comlepd (v2df, v2df)
-v2df __builtin_ia32_comleps (v2df, v2df)
-v4sf __builtin_ia32_comlesd (v4sf, v4sf)
-v4sf __builtin_ia32_comless (v4sf, v4sf)
-v2df __builtin_ia32_comltpd (v2df, v2df)
-v2df __builtin_ia32_comltps (v2df, v2df)
-v4sf __builtin_ia32_comltsd (v4sf, v4sf)
-v4sf __builtin_ia32_comltss (v4sf, v4sf)
-v2df __builtin_ia32_comnepd (v2df, v2df)
-v2df __builtin_ia32_comneps (v2df, v2df)
-v4sf __builtin_ia32_comnesd (v4sf, v4sf)
-v4sf __builtin_ia32_comness (v4sf, v4sf)
-v2df __builtin_ia32_comordpd (v2df, v2df)
-v2df __builtin_ia32_comordps (v2df, v2df)
-v4sf __builtin_ia32_comordsd (v4sf, v4sf)
-v4sf __builtin_ia32_comordss (v4sf, v4sf)
-v2df __builtin_ia32_comtruepd (v2df, v2df)
-v2df __builtin_ia32_comtrueps (v2df, v2df)
-v4sf __builtin_ia32_comtruesd (v4sf, v4sf)
-v4sf __builtin_ia32_comtruess (v4sf, v4sf)
-v2df __builtin_ia32_comueqpd (v2df, v2df)
-v2df __builtin_ia32_comueqps (v2df, v2df)
-v4sf __builtin_ia32_comueqsd (v4sf, v4sf)
-v4sf __builtin_ia32_comueqss (v4sf, v4sf)
-v2df __builtin_ia32_comugepd (v2df, v2df)
-v2df __builtin_ia32_comugeps (v2df, v2df)
-v4sf __builtin_ia32_comugesd (v4sf, v4sf)
-v4sf __builtin_ia32_comugess (v4sf, v4sf)
-v2df __builtin_ia32_comugtpd (v2df, v2df)
-v2df __builtin_ia32_comugtps (v2df, v2df)
-v4sf __builtin_ia32_comugtsd (v4sf, v4sf)
-v4sf __builtin_ia32_comugtss (v4sf, v4sf)
-v2df __builtin_ia32_comulepd (v2df, v2df)
-v2df __builtin_ia32_comuleps (v2df, v2df)
-v4sf __builtin_ia32_comulesd (v4sf, v4sf)
-v4sf __builtin_ia32_comuless (v4sf, v4sf)
-v2df __builtin_ia32_comultpd (v2df, v2df)
-v2df __builtin_ia32_comultps (v2df, v2df)
-v4sf __builtin_ia32_comultsd (v4sf, v4sf)
-v4sf __builtin_ia32_comultss (v4sf, v4sf)
-v2df __builtin_ia32_comunepd (v2df, v2df)
-v2df __builtin_ia32_comuneps (v2df, v2df)
-v4sf __builtin_ia32_comunesd (v4sf, v4sf)
-v4sf __builtin_ia32_comuness (v4sf, v4sf)
-v2df __builtin_ia32_comunordpd (v2df, v2df)
-v2df __builtin_ia32_comunordps (v2df, v2df)
-v4sf __builtin_ia32_comunordsd (v4sf, v4sf)
-v4sf __builtin_ia32_comunordss (v4sf, v4sf)
v2df __builtin_ia32_fmaddpd (v2df, v2df, v2df)
v4sf __builtin_ia32_fmaddps (v4sf, v4sf, v4sf)
v2df __builtin_ia32_fmaddsd (v2df, v2df, v2df)
v4sf __builtin_ia32_fnmsubps (v4sf, v4sf, v4sf)
v2df __builtin_ia32_fnmsubsd (v2df, v2df, v2df)
v4sf __builtin_ia32_fnmsubss (v4sf, v4sf, v4sf)
-v2df __builtin_ia32_frczpd (v2df)
-v4sf __builtin_ia32_frczps (v4sf)
-v2df __builtin_ia32_frczsd (v2df, v2df)
-v4sf __builtin_ia32_frczss (v4sf, v4sf)
-v2di __builtin_ia32_pcmov (v2di, v2di, v2di)
-v2di __builtin_ia32_pcmov_v2di (v2di, v2di, v2di)
-v4si __builtin_ia32_pcmov_v4si (v4si, v4si, v4si)
-v8hi __builtin_ia32_pcmov_v8hi (v8hi, v8hi, v8hi)
-v16qi __builtin_ia32_pcmov_v16qi (v16qi, v16qi, v16qi)
-v2df __builtin_ia32_pcmov_v2df (v2df, v2df, v2df)
-v4sf __builtin_ia32_pcmov_v4sf (v4sf, v4sf, v4sf)
-v16qi __builtin_ia32_pcomeqb (v16qi, v16qi)
-v8hi __builtin_ia32_pcomeqw (v8hi, v8hi)
-v4si __builtin_ia32_pcomeqd (v4si, v4si)
-v2di __builtin_ia32_pcomeqq (v2di, v2di)
-v16qi __builtin_ia32_pcomequb (v16qi, v16qi)
-v4si __builtin_ia32_pcomequd (v4si, v4si)
-v2di __builtin_ia32_pcomequq (v2di, v2di)
-v8hi __builtin_ia32_pcomequw (v8hi, v8hi)
-v8hi __builtin_ia32_pcomeqw (v8hi, v8hi)
-v16qi __builtin_ia32_pcomfalseb (v16qi, v16qi)
-v4si __builtin_ia32_pcomfalsed (v4si, v4si)
-v2di __builtin_ia32_pcomfalseq (v2di, v2di)
-v16qi __builtin_ia32_pcomfalseub (v16qi, v16qi)
-v4si __builtin_ia32_pcomfalseud (v4si, v4si)
-v2di __builtin_ia32_pcomfalseuq (v2di, v2di)
-v8hi __builtin_ia32_pcomfalseuw (v8hi, v8hi)
-v8hi __builtin_ia32_pcomfalsew (v8hi, v8hi)
-v16qi __builtin_ia32_pcomgeb (v16qi, v16qi)
-v4si __builtin_ia32_pcomged (v4si, v4si)
-v2di __builtin_ia32_pcomgeq (v2di, v2di)
-v16qi __builtin_ia32_pcomgeub (v16qi, v16qi)
-v4si __builtin_ia32_pcomgeud (v4si, v4si)
-v2di __builtin_ia32_pcomgeuq (v2di, v2di)
-v8hi __builtin_ia32_pcomgeuw (v8hi, v8hi)
-v8hi __builtin_ia32_pcomgew (v8hi, v8hi)
-v16qi __builtin_ia32_pcomgtb (v16qi, v16qi)
-v4si __builtin_ia32_pcomgtd (v4si, v4si)
-v2di __builtin_ia32_pcomgtq (v2di, v2di)
-v16qi __builtin_ia32_pcomgtub (v16qi, v16qi)
-v4si __builtin_ia32_pcomgtud (v4si, v4si)
-v2di __builtin_ia32_pcomgtuq (v2di, v2di)
-v8hi __builtin_ia32_pcomgtuw (v8hi, v8hi)
-v8hi __builtin_ia32_pcomgtw (v8hi, v8hi)
-v16qi __builtin_ia32_pcomleb (v16qi, v16qi)
-v4si __builtin_ia32_pcomled (v4si, v4si)
-v2di __builtin_ia32_pcomleq (v2di, v2di)
-v16qi __builtin_ia32_pcomleub (v16qi, v16qi)
-v4si __builtin_ia32_pcomleud (v4si, v4si)
-v2di __builtin_ia32_pcomleuq (v2di, v2di)
-v8hi __builtin_ia32_pcomleuw (v8hi, v8hi)
-v8hi __builtin_ia32_pcomlew (v8hi, v8hi)
-v16qi __builtin_ia32_pcomltb (v16qi, v16qi)
-v4si __builtin_ia32_pcomltd (v4si, v4si)
-v2di __builtin_ia32_pcomltq (v2di, v2di)
-v16qi __builtin_ia32_pcomltub (v16qi, v16qi)
-v4si __builtin_ia32_pcomltud (v4si, v4si)
-v2di __builtin_ia32_pcomltuq (v2di, v2di)
-v8hi __builtin_ia32_pcomltuw (v8hi, v8hi)
-v8hi __builtin_ia32_pcomltw (v8hi, v8hi)
-v16qi __builtin_ia32_pcomneb (v16qi, v16qi)
-v4si __builtin_ia32_pcomned (v4si, v4si)
-v2di __builtin_ia32_pcomneq (v2di, v2di)
-v16qi __builtin_ia32_pcomneub (v16qi, v16qi)
-v4si __builtin_ia32_pcomneud (v4si, v4si)
-v2di __builtin_ia32_pcomneuq (v2di, v2di)
-v8hi __builtin_ia32_pcomneuw (v8hi, v8hi)
-v8hi __builtin_ia32_pcomnew (v8hi, v8hi)
-v16qi __builtin_ia32_pcomtrueb (v16qi, v16qi)
-v4si __builtin_ia32_pcomtrued (v4si, v4si)
-v2di __builtin_ia32_pcomtrueq (v2di, v2di)
-v16qi __builtin_ia32_pcomtrueub (v16qi, v16qi)
-v4si __builtin_ia32_pcomtrueud (v4si, v4si)
-v2di __builtin_ia32_pcomtrueuq (v2di, v2di)
-v8hi __builtin_ia32_pcomtrueuw (v8hi, v8hi)
-v8hi __builtin_ia32_pcomtruew (v8hi, v8hi)
-v4df __builtin_ia32_permpd (v2df, v2df, v16qi)
-v4sf __builtin_ia32_permps (v4sf, v4sf, v16qi)
-v4si __builtin_ia32_phaddbd (v16qi)
-v2di __builtin_ia32_phaddbq (v16qi)
-v8hi __builtin_ia32_phaddbw (v16qi)
-v2di __builtin_ia32_phadddq (v4si)
-v4si __builtin_ia32_phaddubd (v16qi)
-v2di __builtin_ia32_phaddubq (v16qi)
-v8hi __builtin_ia32_phaddubw (v16qi)
-v2di __builtin_ia32_phaddudq (v4si)
-v4si __builtin_ia32_phadduwd (v8hi)
-v2di __builtin_ia32_phadduwq (v8hi)
-v4si __builtin_ia32_phaddwd (v8hi)
-v2di __builtin_ia32_phaddwq (v8hi)
-v8hi __builtin_ia32_phsubbw (v16qi)
-v2di __builtin_ia32_phsubdq (v4si)
-v4si __builtin_ia32_phsubwd (v8hi)
-v4si __builtin_ia32_pmacsdd (v4si, v4si, v4si)
-v2di __builtin_ia32_pmacsdqh (v4si, v4si, v2di)
-v2di __builtin_ia32_pmacsdql (v4si, v4si, v2di)
-v4si __builtin_ia32_pmacssdd (v4si, v4si, v4si)
-v2di __builtin_ia32_pmacssdqh (v4si, v4si, v2di)
-v2di __builtin_ia32_pmacssdql (v4si, v4si, v2di)
-v4si __builtin_ia32_pmacsswd (v8hi, v8hi, v4si)
-v8hi __builtin_ia32_pmacssww (v8hi, v8hi, v8hi)
-v4si __builtin_ia32_pmacswd (v8hi, v8hi, v4si)
-v8hi __builtin_ia32_pmacsww (v8hi, v8hi, v8hi)
-v4si __builtin_ia32_pmadcsswd (v8hi, v8hi, v4si)
-v4si __builtin_ia32_pmadcswd (v8hi, v8hi, v4si)
-v16qi __builtin_ia32_pperm (v16qi, v16qi, v16qi)
-v16qi __builtin_ia32_protb (v16qi, v16qi)
-v4si __builtin_ia32_protd (v4si, v4si)
-v2di __builtin_ia32_protq (v2di, v2di)
-v8hi __builtin_ia32_protw (v8hi, v8hi)
-v16qi __builtin_ia32_pshab (v16qi, v16qi)
-v4si __builtin_ia32_pshad (v4si, v4si)
-v2di __builtin_ia32_pshaq (v2di, v2di)
-v8hi __builtin_ia32_pshaw (v8hi, v8hi)
-v16qi __builtin_ia32_pshlb (v16qi, v16qi)
-v4si __builtin_ia32_pshld (v4si, v4si)
-v2di __builtin_ia32_pshlq (v2di, v2di)
-v8hi __builtin_ia32_pshlw (v8hi, v8hi)
-@end smallexample
-
-The following builtin-in functions are available when @option{-msse5}
-is used. The second argument must be an integer constant and generate
-the machine instruction that is part of the name with the @samp{_imm}
-suffix removed.
-
-@smallexample
-v16qi __builtin_ia32_protb_imm (v16qi, int)
-v4si __builtin_ia32_protd_imm (v4si, int)
-v2di __builtin_ia32_protq_imm (v2di, int)
-v8hi __builtin_ia32_protw_imm (v8hi, int)
+v2df __builtin_ia32_fmaddsubpd (v2df, v2df, v2df)
+v4sf __builtin_ia32_fmaddsubps (v4sf, v4sf, v4sf)
+v2df __builtin_ia32_fmsubaddpd (v2df, v2df, v2df)
+v4sf __builtin_ia32_fmsubaddps (v4sf, v4sf, v4sf)
+v4df __builtin_ia32_fmaddpd256 (v4df, v4df, v4df)
+v8sf __builtin_ia32_fmaddps256 (v8sf, v8sf, v8sf)
+v4df __builtin_ia32_fmsubpd256 (v4df, v4df, v4df)
+v8sf __builtin_ia32_fmsubps256 (v8sf, v8sf, v8sf)
+v4df __builtin_ia32_fnmaddpd256 (v4df, v4df, v4df)
+v8sf __builtin_ia32_fnmaddps256 (v8sf, v8sf, v8sf)
+v4df __builtin_ia32_fnmsubpd256 (v4df, v4df, v4df)
+v8sf __builtin_ia32_fnmsubps256 (v8sf, v8sf, v8sf)
+v4df __builtin_ia32_fmaddsubpd256 (v4df, v4df, v4df)
+v8sf __builtin_ia32_fmaddsubps256 (v8sf, v8sf, v8sf)
+v4df __builtin_ia32_fmsubaddpd256 (v4df, v4df, v4df)
+v8sf __builtin_ia32_fmsubaddps256 (v8sf, v8sf, v8sf)
+
+@end smallexample
+
+The following built-in functions are available when @option{-mlwp} is used.
+
+@smallexample
+void __builtin_ia32_llwpcb16 (void *);
+void __builtin_ia32_llwpcb32 (void *);
+void __builtin_ia32_llwpcb64 (void *);
+void * __builtin_ia32_llwpcb16 (void);
+void * __builtin_ia32_llwpcb32 (void);
+void * __builtin_ia32_llwpcb64 (void);
+void __builtin_ia32_lwpval16 (unsigned short, unsigned int, unsigned short)
+void __builtin_ia32_lwpval32 (unsigned int, unsigned int, unsigned int)
+void __builtin_ia32_lwpval64 (unsigned __int64, unsigned int, unsigned int)
+unsigned char __builtin_ia32_lwpins16 (unsigned short, unsigned int, unsigned short)
+unsigned char __builtin_ia32_lwpins32 (unsigned int, unsigned int, unsigned int)
+unsigned char __builtin_ia32_lwpins64 (unsigned __int64, unsigned int, unsigned int)
@end smallexample
The following built-in functions are available when @option{-m3dnow} is used.
using the command-line option @option{-mdspr2}; this option implies
@option{-mdsp}.
+The SCOUNT and POS bits of the DSP control register are global. The
+WRDSP, EXTPDP, EXTPDPV and MTHLIP instructions modify the SCOUNT and
+POS bits. During optimization, the compiler will not delete these
+instructions and it will not delete calls to functions containing
+these instructions.
+
At present, GCC only provides support for operations on 32-bit
vectors. The vector type associated with 8-bit integer data is
usually called @code{v4i8}, the vector type associated with Q7
For example, the code above will set the lower half of @code{a} to
@code{1.5} on little-endian targets and @code{9.1} on big-endian targets.
+@node MIPS Loongson Built-in Functions
+@subsection MIPS Loongson Built-in Functions
+
+GCC provides intrinsics to access the SIMD instructions provided by the
+ST Microelectronics Loongson-2E and -2F processors. These intrinsics,
+available after inclusion of the @code{loongson.h} header file,
+operate on the following 64-bit vector types:
+
+@itemize
+@item @code{uint8x8_t}, a vector of eight unsigned 8-bit integers;
+@item @code{uint16x4_t}, a vector of four unsigned 16-bit integers;
+@item @code{uint32x2_t}, a vector of two unsigned 32-bit integers;
+@item @code{int8x8_t}, a vector of eight signed 8-bit integers;
+@item @code{int16x4_t}, a vector of four signed 16-bit integers;
+@item @code{int32x2_t}, a vector of two signed 32-bit integers.
+@end itemize
+
+The intrinsics provided are listed below; each is named after the
+machine instruction to which it corresponds, with suffixes added as
+appropriate to distinguish intrinsics that expand to the same machine
+instruction yet have different argument types. Refer to the architecture
+documentation for a description of the functionality of each
+instruction.
+
+@smallexample
+int16x4_t packsswh (int32x2_t s, int32x2_t t);
+int8x8_t packsshb (int16x4_t s, int16x4_t t);
+uint8x8_t packushb (uint16x4_t s, uint16x4_t t);
+uint32x2_t paddw_u (uint32x2_t s, uint32x2_t t);
+uint16x4_t paddh_u (uint16x4_t s, uint16x4_t t);
+uint8x8_t paddb_u (uint8x8_t s, uint8x8_t t);
+int32x2_t paddw_s (int32x2_t s, int32x2_t t);
+int16x4_t paddh_s (int16x4_t s, int16x4_t t);
+int8x8_t paddb_s (int8x8_t s, int8x8_t t);
+uint64_t paddd_u (uint64_t s, uint64_t t);
+int64_t paddd_s (int64_t s, int64_t t);
+int16x4_t paddsh (int16x4_t s, int16x4_t t);
+int8x8_t paddsb (int8x8_t s, int8x8_t t);
+uint16x4_t paddush (uint16x4_t s, uint16x4_t t);
+uint8x8_t paddusb (uint8x8_t s, uint8x8_t t);
+uint64_t pandn_ud (uint64_t s, uint64_t t);
+uint32x2_t pandn_uw (uint32x2_t s, uint32x2_t t);
+uint16x4_t pandn_uh (uint16x4_t s, uint16x4_t t);
+uint8x8_t pandn_ub (uint8x8_t s, uint8x8_t t);
+int64_t pandn_sd (int64_t s, int64_t t);
+int32x2_t pandn_sw (int32x2_t s, int32x2_t t);
+int16x4_t pandn_sh (int16x4_t s, int16x4_t t);
+int8x8_t pandn_sb (int8x8_t s, int8x8_t t);
+uint16x4_t pavgh (uint16x4_t s, uint16x4_t t);
+uint8x8_t pavgb (uint8x8_t s, uint8x8_t t);
+uint32x2_t pcmpeqw_u (uint32x2_t s, uint32x2_t t);
+uint16x4_t pcmpeqh_u (uint16x4_t s, uint16x4_t t);
+uint8x8_t pcmpeqb_u (uint8x8_t s, uint8x8_t t);
+int32x2_t pcmpeqw_s (int32x2_t s, int32x2_t t);
+int16x4_t pcmpeqh_s (int16x4_t s, int16x4_t t);
+int8x8_t pcmpeqb_s (int8x8_t s, int8x8_t t);
+uint32x2_t pcmpgtw_u (uint32x2_t s, uint32x2_t t);
+uint16x4_t pcmpgth_u (uint16x4_t s, uint16x4_t t);
+uint8x8_t pcmpgtb_u (uint8x8_t s, uint8x8_t t);
+int32x2_t pcmpgtw_s (int32x2_t s, int32x2_t t);
+int16x4_t pcmpgth_s (int16x4_t s, int16x4_t t);
+int8x8_t pcmpgtb_s (int8x8_t s, int8x8_t t);
+uint16x4_t pextrh_u (uint16x4_t s, int field);
+int16x4_t pextrh_s (int16x4_t s, int field);
+uint16x4_t pinsrh_0_u (uint16x4_t s, uint16x4_t t);
+uint16x4_t pinsrh_1_u (uint16x4_t s, uint16x4_t t);
+uint16x4_t pinsrh_2_u (uint16x4_t s, uint16x4_t t);
+uint16x4_t pinsrh_3_u (uint16x4_t s, uint16x4_t t);
+int16x4_t pinsrh_0_s (int16x4_t s, int16x4_t t);
+int16x4_t pinsrh_1_s (int16x4_t s, int16x4_t t);
+int16x4_t pinsrh_2_s (int16x4_t s, int16x4_t t);
+int16x4_t pinsrh_3_s (int16x4_t s, int16x4_t t);
+int32x2_t pmaddhw (int16x4_t s, int16x4_t t);
+int16x4_t pmaxsh (int16x4_t s, int16x4_t t);
+uint8x8_t pmaxub (uint8x8_t s, uint8x8_t t);
+int16x4_t pminsh (int16x4_t s, int16x4_t t);
+uint8x8_t pminub (uint8x8_t s, uint8x8_t t);
+uint8x8_t pmovmskb_u (uint8x8_t s);
+int8x8_t pmovmskb_s (int8x8_t s);
+uint16x4_t pmulhuh (uint16x4_t s, uint16x4_t t);
+int16x4_t pmulhh (int16x4_t s, int16x4_t t);
+int16x4_t pmullh (int16x4_t s, int16x4_t t);
+int64_t pmuluw (uint32x2_t s, uint32x2_t t);
+uint8x8_t pasubub (uint8x8_t s, uint8x8_t t);
+uint16x4_t biadd (uint8x8_t s);
+uint16x4_t psadbh (uint8x8_t s, uint8x8_t t);
+uint16x4_t pshufh_u (uint16x4_t dest, uint16x4_t s, uint8_t order);
+int16x4_t pshufh_s (int16x4_t dest, int16x4_t s, uint8_t order);
+uint16x4_t psllh_u (uint16x4_t s, uint8_t amount);
+int16x4_t psllh_s (int16x4_t s, uint8_t amount);
+uint32x2_t psllw_u (uint32x2_t s, uint8_t amount);
+int32x2_t psllw_s (int32x2_t s, uint8_t amount);
+uint16x4_t psrlh_u (uint16x4_t s, uint8_t amount);
+int16x4_t psrlh_s (int16x4_t s, uint8_t amount);
+uint32x2_t psrlw_u (uint32x2_t s, uint8_t amount);
+int32x2_t psrlw_s (int32x2_t s, uint8_t amount);
+uint16x4_t psrah_u (uint16x4_t s, uint8_t amount);
+int16x4_t psrah_s (int16x4_t s, uint8_t amount);
+uint32x2_t psraw_u (uint32x2_t s, uint8_t amount);
+int32x2_t psraw_s (int32x2_t s, uint8_t amount);
+uint32x2_t psubw_u (uint32x2_t s, uint32x2_t t);
+uint16x4_t psubh_u (uint16x4_t s, uint16x4_t t);
+uint8x8_t psubb_u (uint8x8_t s, uint8x8_t t);
+int32x2_t psubw_s (int32x2_t s, int32x2_t t);
+int16x4_t psubh_s (int16x4_t s, int16x4_t t);
+int8x8_t psubb_s (int8x8_t s, int8x8_t t);
+uint64_t psubd_u (uint64_t s, uint64_t t);
+int64_t psubd_s (int64_t s, int64_t t);
+int16x4_t psubsh (int16x4_t s, int16x4_t t);
+int8x8_t psubsb (int8x8_t s, int8x8_t t);
+uint16x4_t psubush (uint16x4_t s, uint16x4_t t);
+uint8x8_t psubusb (uint8x8_t s, uint8x8_t t);
+uint32x2_t punpckhwd_u (uint32x2_t s, uint32x2_t t);
+uint16x4_t punpckhhw_u (uint16x4_t s, uint16x4_t t);
+uint8x8_t punpckhbh_u (uint8x8_t s, uint8x8_t t);
+int32x2_t punpckhwd_s (int32x2_t s, int32x2_t t);
+int16x4_t punpckhhw_s (int16x4_t s, int16x4_t t);
+int8x8_t punpckhbh_s (int8x8_t s, int8x8_t t);
+uint32x2_t punpcklwd_u (uint32x2_t s, uint32x2_t t);
+uint16x4_t punpcklhw_u (uint16x4_t s, uint16x4_t t);
+uint8x8_t punpcklbh_u (uint8x8_t s, uint8x8_t t);
+int32x2_t punpcklwd_s (int32x2_t s, int32x2_t t);
+int16x4_t punpcklhw_s (int16x4_t s, int16x4_t t);
+int8x8_t punpcklbh_s (int8x8_t s, int8x8_t t);
+@end smallexample
+
@menu
* Paired-Single Arithmetic::
* Paired-Single Built-in Functions::
@end smallexample
@end table
-@node PowerPC AltiVec Built-in Functions
+@node picoChip Built-in Functions
+@subsection picoChip Built-in Functions
+
+GCC provides an interface to selected machine instructions from the
+picoChip instruction set.
+
+@table @code
+@item int __builtin_sbc (int @var{value})
+Sign bit count. Return the number of consecutive bits in @var{value}
+which have the same value as the sign-bit. The result is the number of
+leading sign bits minus one, giving the number of redundant sign bits in
+@var{value}.
+
+@item int __builtin_byteswap (int @var{value})
+Byte swap. Return the result of swapping the upper and lower bytes of
+@var{value}.
+
+@item int __builtin_brev (int @var{value})
+Bit reversal. Return the result of reversing the bits in
+@var{value}. Bit 15 is swapped with bit 0, bit 14 is swapped with bit 1,
+and so on.
+
+@item int __builtin_adds (int @var{x}, int @var{y})
+Saturating addition. Return the result of adding @var{x} and @var{y},
+storing the value 32767 if the result overflows.
+
+@item int __builtin_subs (int @var{x}, int @var{y})
+Saturating subtraction. Return the result of subtracting @var{y} from
+@var{x}, storing the value @minus{}32768 if the result overflows.
+
+@item void __builtin_halt (void)
+Halt. The processor will stop execution. This built-in is useful for
+implementing assertions.
+
+@end table
+
+@node Other MIPS Built-in Functions
+@subsection Other MIPS Built-in Functions
+
+GCC provides other MIPS-specific built-in functions:
+
+@table @code
+@item void __builtin_mips_cache (int @var{op}, const volatile void *@var{addr})
+Insert a @samp{cache} instruction with operands @var{op} and @var{addr}.
+GCC defines the preprocessor macro @code{___GCC_HAVE_BUILTIN_MIPS_CACHE}
+when this function is available.
+@end table
+
+@node PowerPC AltiVec/VSX Built-in Functions
@subsection PowerPC AltiVec Built-in Functions
GCC provides an interface for the PowerPC family of processors to access
vector float
@end smallexample
+If @option{-mvsx} is used the following additional vector types are
+implemented.
+
+@smallexample
+vector unsigned long
+vector signed long
+vector double
+@end smallexample
+
+The long types are only implemented for 64-bit code generation, and
+the long type is only used in the floating point/integer conversion
+instructions.
+
GCC's implementation of the high-level language interface available from
C and C++ code differs from Motorola's documentation in several ways.
@item
Compiling with @option{-maltivec} adds keywords @code{__vector},
-@code{__pixel}, and @code{__bool}. Macros @option{vector},
-@code{pixel}, and @code{bool} are defined in @code{<altivec.h>} and can
-be undefined.
+@code{vector}, @code{__pixel}, @code{pixel}, @code{__bool} and
+@code{bool}. When compiling ISO C, the context-sensitive substitution
+of the keywords @code{vector}, @code{pixel} and @code{bool} is
+disabled. To use them, you must include @code{<altivec.h>} instead.
@item
GCC allows using a @code{typedef} name as the type specifier for a
vector unsigned char vec_vavgub (vector unsigned char,
vector unsigned char);
+vector float vec_copysign (vector float);
+
vector float vec_ceil (vector float);
vector signed int vec_cmpb (vector float, vector float);
int vec_any_out (vector float, vector float);
@end smallexample
+If the vector/scalar (VSX) instruction set is available, the following
+additional functions are available:
+
+@smallexample
+vector double vec_abs (vector double);
+vector double vec_add (vector double, vector double);
+vector double vec_and (vector double, vector double);
+vector double vec_and (vector double, vector bool long);
+vector double vec_and (vector bool long, vector double);
+vector double vec_andc (vector double, vector double);
+vector double vec_andc (vector double, vector bool long);
+vector double vec_andc (vector bool long, vector double);
+vector double vec_ceil (vector double);
+vector bool long vec_cmpeq (vector double, vector double);
+vector bool long vec_cmpge (vector double, vector double);
+vector bool long vec_cmpgt (vector double, vector double);
+vector bool long vec_cmple (vector double, vector double);
+vector bool long vec_cmplt (vector double, vector double);
+vector float vec_div (vector float, vector float);
+vector double vec_div (vector double, vector double);
+vector double vec_floor (vector double);
+vector double vec_madd (vector double, vector double, vector double);
+vector double vec_max (vector double, vector double);
+vector double vec_min (vector double, vector double);
+vector float vec_msub (vector float, vector float, vector float);
+vector double vec_msub (vector double, vector double, vector double);
+vector float vec_mul (vector float, vector float);
+vector double vec_mul (vector double, vector double);
+vector float vec_nearbyint (vector float);
+vector double vec_nearbyint (vector double);
+vector float vec_nmadd (vector float, vector float, vector float);
+vector double vec_nmadd (vector double, vector double, vector double);
+vector double vec_nmsub (vector double, vector double, vector double);
+vector double vec_nor (vector double, vector double);
+vector double vec_or (vector double, vector double);
+vector double vec_or (vector double, vector bool long);
+vector double vec_or (vector bool long, vector double);
+vector double vec_perm (vector double,
+ vector double,
+ vector unsigned char);
+vector float vec_rint (vector float);
+vector double vec_rint (vector double);
+vector double vec_sel (vector double, vector double, vector bool long);
+vector double vec_sel (vector double, vector double, vector unsigned long);
+vector double vec_sub (vector double, vector double);
+vector float vec_sqrt (vector float);
+vector double vec_sqrt (vector double);
+vector double vec_trunc (vector double);
+vector double vec_xor (vector double, vector double);
+vector double vec_xor (vector double, vector bool long);
+vector double vec_xor (vector bool long, vector double);
+int vec_all_eq (vector double, vector double);
+int vec_all_ge (vector double, vector double);
+int vec_all_gt (vector double, vector double);
+int vec_all_le (vector double, vector double);
+int vec_all_lt (vector double, vector double);
+int vec_all_nan (vector double);
+int vec_all_ne (vector double, vector double);
+int vec_all_nge (vector double, vector double);
+int vec_all_ngt (vector double, vector double);
+int vec_all_nle (vector double, vector double);
+int vec_all_nlt (vector double, vector double);
+int vec_all_numeric (vector double);
+int vec_any_eq (vector double, vector double);
+int vec_any_ge (vector double, vector double);
+int vec_any_gt (vector double, vector double);
+int vec_any_le (vector double, vector double);
+int vec_any_lt (vector double, vector double);
+int vec_any_nan (vector double);
+int vec_any_ne (vector double, vector double);
+int vec_any_nge (vector double, vector double);
+int vec_any_ngt (vector double, vector double);
+int vec_any_nle (vector double, vector double);
+int vec_any_nlt (vector double, vector double);
+int vec_any_numeric (vector double);
+@end smallexample
+
+GCC provides a few other builtins on Powerpc to access certain instructions:
+@smallexample
+float __builtin_recipdivf (float, float);
+float __builtin_rsqrtf (float);
+double __builtin_recipdiv (double, double);
+long __builtin_bpermd (long, long);
+int __builtin_bswap16 (int);
+@end smallexample
+
+@node RX Built-in Functions
+@subsection RX Built-in Functions
+GCC supports some of the RX instructions which cannot be expressed in
+the C programming language via the use of built-in functions. The
+following functions are supported:
+
+@deftypefn {Built-in Function} void __builtin_rx_brk (void)
+Generates the @code{brk} machine instruction.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_clrpsw (int)
+Generates the @code{clrpsw} machine instruction to clear the specified
+bit in the processor status word.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_int (int)
+Generates the @code{int} machine instruction to generate an interrupt
+with the specified value.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_machi (int, int)
+Generates the @code{machi} machine instruction to add the result of
+multiplying the top 16-bits of the two arguments into the
+accumulator.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_maclo (int, int)
+Generates the @code{maclo} machine instruction to add the result of
+multiplying the bottom 16-bits of the two arguments into the
+accumulator.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_mulhi (int, int)
+Generates the @code{mulhi} machine instruction to place the result of
+multiplying the top 16-bits of the two arguments into the
+accumulator.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_mullo (int, int)
+Generates the @code{mullo} machine instruction to place the result of
+multiplying the bottom 16-bits of the two arguments into the
+accumulator.
+@end deftypefn
+
+@deftypefn {Built-in Function} int __builtin_rx_mvfachi (void)
+Generates the @code{mvfachi} machine instruction to read the top
+32-bits of the accumulator.
+@end deftypefn
+
+@deftypefn {Built-in Function} int __builtin_rx_mvfacmi (void)
+Generates the @code{mvfacmi} machine instruction to read the middle
+32-bits of the accumulator.
+@end deftypefn
+
+@deftypefn {Built-in Function} int __builtin_rx_mvfc (int)
+Generates the @code{mvfc} machine instruction which reads the control
+register specified in its argument and returns its value.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_mvtachi (int)
+Generates the @code{mvtachi} machine instruction to set the top
+32-bits of the accumulator.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_mvtaclo (int)
+Generates the @code{mvtaclo} machine instruction to set the bottom
+32-bits of the accumulator.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_mvtc (int reg, int val)
+Generates the @code{mvtc} machine instruction which sets control
+register number @code{reg} to @code{val}.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_mvtipl (int)
+Generates the @code{mvtipl} machine instruction set the interrupt
+priority level.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_racw (int)
+Generates the @code{racw} machine instruction to round the accumulator
+according to the specified mode.
+@end deftypefn
+
+@deftypefn {Built-in Function} int __builtin_rx_revw (int)
+Generates the @code{revw} machine instruction which swaps the bytes in
+the argument so that bits 0--7 now occupy bits 8--15 and vice versa,
+and also bits 16--23 occupy bits 24--31 and vice versa.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_rmpa (void)
+Generates the @code{rmpa} machine instruction which initiates a
+repeated multiply and accumulate sequence.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_round (float)
+Generates the @code{round} machine instruction which returns the
+floating point argument rounded according to the current rounding mode
+set in the floating point status word register.
+@end deftypefn
+
+@deftypefn {Built-in Function} int __builtin_rx_sat (int)
+Generates the @code{sat} machine instruction which returns the
+saturated value of the argument.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_setpsw (int)
+Generates the @code{setpsw} machine instruction to set the specified
+bit in the processor status word.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_rx_wait (void)
+Generates the @code{wait} machine instruction.
+@end deftypefn
+
@node SPARC VIS Built-in Functions
@subsection SPARC VIS Built-in Functions
@menu
* ARM Pragmas::
* M32C Pragmas::
+* MeP Pragmas::
* RS/6000 and PowerPC Pragmas::
* Darwin Pragmas::
* Solaris Pragmas::
* Diagnostic Pragmas::
* Visibility Pragmas::
* Push/Pop Macro Pragmas::
+* Function Specific Option Pragmas::
@end menu
@node ARM Pragmas
@table @code
@item memregs @var{number}
@cindex pragma, memregs
-Overrides the command line option @code{-memregs=} for the current
+Overrides the command-line option @code{-memregs=} for the current
file. Use with care! This pragma must be before any function in the
file, and mixing different memregs values in different objects may
make them incompatible. This pragma is useful when a
@end table
+@node MeP Pragmas
+@subsection MeP Pragmas
+
+@table @code
+
+@item custom io_volatile (on|off)
+@cindex pragma, custom io_volatile
+Overrides the command line option @code{-mio-volatile} for the current
+file. Note that for compatibility with future GCC releases, this
+option should only be used once before any @code{io} variables in each
+file.
+
+@item GCC coprocessor available @var{registers}
+@cindex pragma, coprocessor available
+Specifies which coprocessor registers are available to the register
+allocator. @var{registers} may be a single register, register range
+separated by ellipses, or comma-separated list of those. Example:
+
+@example
+#pragma GCC coprocessor available $c0...$c10, $c28
+@end example
+
+@item GCC coprocessor call_saved @var{registers}
+@cindex pragma, coprocessor call_saved
+Specifies which coprocessor registers are to be saved and restored by
+any function using them. @var{registers} may be a single register,
+register range separated by ellipses, or comma-separated list of
+those. Example:
+
+@example
+#pragma GCC coprocessor call_saved $c4...$c6, $c31
+@end example
+
+@item GCC coprocessor subclass '(A|B|C|D)' = @var{registers}
+@cindex pragma, coprocessor subclass
+Creates and defines a register class. These register classes can be
+used by inline @code{asm} constructs. @var{registers} may be a single
+register, register range separated by ellipses, or comma-separated
+list of those. Example:
+
+@example
+#pragma GCC coprocessor subclass 'B' = $c2, $c4, $c6
+
+asm ("cpfoo %0" : "=B" (x));
+@end example
+
+@item GCC disinterrupt @var{name} , @var{name} @dots{}
+@cindex pragma, disinterrupt
+For the named functions, the compiler adds code to disable interrupts
+for the duration of those functions. Any functions so named, which
+are not encountered in the source, cause a warning that the pragma was
+not used. Examples:
+
+@example
+#pragma disinterrupt foo
+#pragma disinterrupt bar, grill
+int foo () @{ @dots{} @}
+@end example
+
+@item GCC call @var{name} , @var{name} @dots{}
+@cindex pragma, call
+For the named functions, the compiler always uses a register-indirect
+call model when calling the named functions. Examples:
+
+@example
+extern int foo ();
+#pragma call foo
+@end example
+
+@end table
+
@node RS/6000 and PowerPC Pragmas
@subsection RS/6000 and PowerPC Pragmas
For compatibility with the Solaris and Tru64 UNIX system headers, GCC
supports two @code{#pragma} directives which change the name used in
-assembly for a given declaration. These pragmas are only available on
-platforms whose system headers need them. To get this effect on all
-platforms supported by GCC, use the asm labels extension (@pxref{Asm
+assembly for a given declaration. @code{#pragma extern_prefix} is only
+available on platforms whose system headers need it. To get this effect
+on all platforms supported by GCC, use the asm labels extension (@pxref{Asm
Labels}).
@table @code
This pragma gives the C function @var{oldname} the assembly symbol
@var{newname}. The preprocessor macro @code{__PRAGMA_REDEFINE_EXTNAME}
-will be defined if this pragma is available (currently only on
-Solaris).
+will be defined if this pragma is available (currently on all platforms).
@item extern_prefix @var{string}
@cindex pragma, extern_prefix
@enumerate
@item @code{#pragma pack(@var{n})} simply sets the new alignment.
@item @code{#pragma pack()} sets the alignment to the one that was in
-effect when compilation started (see also command line option
+effect when compilation started (see also command-line option
@option{-fpack-struct[=<n>]} @pxref{Code Gen Options}).
@item @code{#pragma pack(push[,@var{n}])} pushes the current alignment
setting on an internal stack and then optionally sets the new alignment.
@var{kind} is @samp{error} to treat this diagnostic as an error,
@samp{warning} to treat it like a warning (even if @option{-Werror} is
in effect), or @samp{ignored} if the diagnostic is to be ignored.
-@var{option} is a double quoted string which matches the command line
+@var{option} is a double quoted string which matches the command-line
option.
@example
#pragma GCC diagnostic ignored "-Wformat"
@end example
-Note that these pragmas override any command line options. Also,
+Note that these pragmas override any command-line options. Also,
while it is syntactically valid to put these pragmas anywhere in your
sources, the only supported location for them is before any data or
functions are defined. Doing otherwise may result in unpredictable
results depending on how the optimizer manages your sources. If the
same option is listed multiple times, the last one specified is the
one that is in effect. This pragma is not intended to be a general
-purpose replacement for command line options, but for implementing
+purpose replacement for command-line options, but for implementing
strict control over project policies.
@end table
+GCC also offers a simple mechanism for printing messages during
+compilation.
+
+@table @code
+@item #pragma message @var{string}
+@cindex pragma, diagnostic
+
+Prints @var{string} as a compiler message on compilation. The message
+is informational only, and is neither a compilation warning nor an error.
+
+@smallexample
+#pragma message "Compiling " __FILE__ "..."
+@end smallexample
+
+@var{string} may be parenthesized, and is printed with location
+information. For example,
+
+@smallexample
+#define DO_PRAGMA(x) _Pragma (#x)
+#define TODO(x) DO_PRAGMA(message ("TODO - " #x))
+
+TODO(Remember to fix this)
+@end smallexample
+
+prints @samp{/tmp/file.c:4: note: #pragma message:
+TODO - Remember to fix this}.
+
+@end table
+
@node Visibility Pragmas
@subsection Visibility Pragmas
In this example, the definition of X as 1 is saved by @code{#pragma
push_macro} and restored by @code{#pragma pop_macro}.
+@node Function Specific Option Pragmas
+@subsection Function Specific Option Pragmas
+
+@table @code
+@item #pragma GCC target (@var{"string"}...)
+@cindex pragma GCC target
+
+This pragma allows you to set target specific options for functions
+defined later in the source file. One or more strings can be
+specified. Each function that is defined after this point will be as
+if @code{attribute((target("STRING")))} was specified for that
+function. The parenthesis around the options is optional.
+@xref{Function Attributes}, for more information about the
+@code{target} attribute and the attribute syntax.
+
+The @samp{#pragma GCC target} pragma is not implemented in GCC
+versions earlier than 4.4, and is currently only implemented for the
+386 and x86_64 backends.
+@end table
+
+@table @code
+@item #pragma GCC optimize (@var{"string"}...)
+@cindex pragma GCC optimize
+
+This pragma allows you to set global optimization options for functions
+defined later in the source file. One or more strings can be
+specified. Each function that is defined after this point will be as
+if @code{attribute((optimize("STRING")))} was specified for that
+function. The parenthesis around the options is optional.
+@xref{Function Attributes}, for more information about the
+@code{optimize} attribute and the attribute syntax.
+
+The @samp{#pragma GCC optimize} pragma is not implemented in GCC
+versions earlier than 4.4.
+@end table
+
+@table @code
+@item #pragma GCC push_options
+@itemx #pragma GCC pop_options
+@cindex pragma GCC push_options
+@cindex pragma GCC pop_options
+
+These pragmas maintain a stack of the current target and optimization
+options. It is intended for include files where you temporarily want
+to switch to using a different @samp{#pragma GCC target} or
+@samp{#pragma GCC optimize} and then to pop back to the previous
+options.
+
+The @samp{#pragma GCC push_options} and @samp{#pragma GCC pop_options}
+pragmas are not implemented in GCC versions earlier than 4.4.
+@end table
+
+@table @code
+@item #pragma GCC reset_options
+@cindex pragma GCC reset_options
+
+This pragma clears the current @code{#pragma GCC target} and
+@code{#pragma GCC optimize} to use the default switches as specified
+on the command line.
+
+The @samp{#pragma GCC reset_options} pragma is not implemented in GCC
+versions earlier than 4.4.
+@end table
+
@node Unnamed Fields
@section Unnamed struct/union fields within structs/unions
@cindex struct
@cindex union
-For compatibility with other compilers, GCC allows you to define
+As permitted by ISO C1X and for compatibility with other compilers,
+GCC allows you to define
a structure or union that contains, as fields, structures and unions
without names. For example:
@end smallexample
It is ambiguous which @code{a} is being referred to with @samp{foo.a}.
-Such constructs are not supported and must be avoided. In the future,
-such constructs may be detected and treated as compilation errors.
+The compiler gives errors for such constructs.
@opindex fms-extensions
Unless @option{-fms-extensions} is used, the unnamed field must be a
structure or union definition without a tag (for example, @samp{struct
-@{ int a; @};}). If @option{-fms-extensions} is used, the field may
+@{ int a; @};}), or a @code{typedef} name for such a structure or
+union. If @option{-fms-extensions} is used, the field may
also be a definition with a tag such as @samp{struct foo @{ int a;
@};}, a reference to a previously defined structure or union such as
@samp{struct foo;}, or a reference to a @code{typedef} name for a
-previously defined structure or union type.
+previously defined structure or union type with a tag.
@node Thread-Local
@section Thread-Local Storage
Predefined Macros,cpp,The GNU C Preprocessor}).
@menu
-* Volatiles:: What constitutes an access to a volatile object.
+* Volatiles:: What constitutes an access to a volatile object.
* Restricted Pointers:: C99 restricted pointers and references.
* Vague Linkage:: Where G++ puts inlines, vtables and such.
* C++ Interface:: You can use a single C++ header file for both
@end table
-See also @xref{Namespace Association}.
+See also @ref{Namespace Association}.
@node Namespace Association
@section Namespace Association
@item __is_class (type)
If @code{type} is a cv class type, and not a union type
-([basic.compound]) the the trait is true, else it is false.
+([basic.compound]) the trait is true, else it is false.
@item __is_empty (type)
If @code{__is_class (type)} is false then the trait is false.
Otherwise @code{type} is considered empty if and only if: @code{type}
has no non-static data members, or all non-static data members, if
-any, are bit-fields of lenght 0, and @code{type} has no virtual
+any, are bit-fields of length 0, and @code{type} has no virtual
members, and @code{type} has no virtual base classes, and @code{type}
has no base classes @code{base_type} for which
@code{__is_empty (base_type)} is false. Requires: @code{type} shall
@code{void} type.
@item __is_enum (type)
-If @code{type} is a cv enumeration type ([basic.compound]) the the trait is
+If @code{type} is a cv enumeration type ([basic.compound]) the trait is
true, else it is false.
@item __is_pod (type)
type, an array type of unknown bound, or is a @code{void} type.
@item __is_union (type)
-If @code{type} is a cv union type ([basic.compound]) the the trait is
+If @code{type} is a cv union type ([basic.compound]) the trait is
true, else it is false.
@end table
Previously it was possible to use an empty prototype parameter list to
indicate an unspecified number of parameters (like C), rather than no
parameters, as C++ demands. This feature has been removed, except where
-it is required for backwards compatibility @xref{Backwards Compatibility}.
+it is required for backwards compatibility. @xref{Backwards Compatibility}.
@end table
G++ allows a virtual function returning @samp{void *} to be overridden
compilation of C++ written to such drafts, G++ contains some backwards
compatibilities. @emph{All such backwards compatibility features are
liable to disappear in future versions of G++.} They should be considered
-deprecated @xref{Deprecated Features}.
+deprecated. @xref{Deprecated Features}.
@table @code
@item For scope
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