Add ports for TILE-Gx and TILEPro.

[pf3gnuchains/gcc-fork.git] / gcc / doc / extend.texi

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index ae50ae0..4c71960 100644 (file)
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -8531,6 +8531,8 @@ instructions, but allow the compiler to schedule those calls.
 * SPARC VIS Built-in Functions::
 * SPU Built-in Functions::
 * TI C6X Built-in Functions::
+* TILE-Gx Built-in Functions::
+* TILEPro Built-in Functions::
 @end menu
 
 @node Alpha Built-in Functions
@@ -13718,6 +13720,78 @@ int _abs2 (int)
 
 @end smallexample
 
+@node TILE-Gx Built-in Functions
+@subsection TILE-Gx Built-in Functions
+
+GCC provides intrinsics to access every instruction of the TILE-Gx
+processor.  The intrinsics are of the form:
+
+@smallexample
+
+unsigned long long __insn_@var{op} (...)
+
+@end smallexample
+
+Where @var{op} is the name of the instruction.  Refer to the ISA manual
+for the complete list of instructions.
+
+GCC also provides intrinsics to directly access the network registers.
+The intrinsics are:
+
+@smallexample
+
+unsigned long long __tile_idn0_receive (void)
+unsigned long long __tile_idn1_receive (void)
+unsigned long long __tile_udn0_receive (void)
+unsigned long long __tile_udn1_receive (void)
+unsigned long long __tile_udn2_receive (void)
+unsigned long long __tile_udn3_receive (void)
+void __tile_idn_send (unsigned long long)
+void __tile_udn_send (unsigned long long)
+
+@end smallexample
+
+The intrinsic @code{void __tile_network_barrier (void)} is used to
+guarantee that no network operatons before it will be reordered with
+those after it.
+
+@node TILEPro Built-in Functions
+@subsection TILEPro Built-in Functions
+
+GCC provides intrinsics to access every instruction of the TILEPro
+processor.  The intrinsics are of the form:
+
+@smallexample
+
+unsigned __insn_@var{op} (...)
+
+@end smallexample
+
+Where @var{op} is the name of the instruction.  Refer to the ISA manual
+for the complete list of instructions.
+
+GCC also provides intrinsics to directly access the network registers.
+The intrinsics are:
+
+@smallexample
+
+unsigned __tile_idn0_receive (void)
+unsigned __tile_idn1_receive (void)
+unsigned __tile_sn_receive (void)
+unsigned __tile_udn0_receive (void)
+unsigned __tile_udn1_receive (void)
+unsigned __tile_udn2_receive (void)
+unsigned __tile_udn3_receive (void)
+void __tile_idn_send (unsigned)
+void __tile_sn_send (unsigned)
+void __tile_udn_send (unsigned)
+
+@end smallexample
+
+The intrinsic @code{void __tile_network_barrier (void)} is used to
+guarantee that no network operatons before it will be reordered with
+those after it.
+
 @node Target Format Checks
 @section Format Checks Specific to Particular Target Machines