/* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
- Copyright (C) 2001 Free Software Foundation, Inc.
+ Copyright 2001,2002,2003 Free Software Foundation, Inc.
Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
This file is part of GCC.
#include "config.h"
#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
#include "rtl.h"
#include "regs.h"
-#include "machmode.h"
#include "hard-reg-set.h"
#include "basic-block.h"
#include "real.h"
/* Enumeration for all of the relational tests, so that we can build
arrays indexed by the test type, and not worry about the order
- of EQ, NE, etc. */
+ of EQ, NE, etc. */
enum internal_test {
ITEST_EQ,
struct machine_function GTY(())
{
int accesses_prev_frame;
+ bool incoming_a7_copied;
};
/* Vector, indexed by hard register number, which contains 1 for a
register that is allowable in a candidate for leaf function
- treatment. */
+ treatment. */
const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] =
{
/* Map hard register number to register class */
const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER] =
{
- GR_REGS, SP_REG, GR_REGS, GR_REGS,
- GR_REGS, GR_REGS, GR_REGS, GR_REGS,
- GR_REGS, GR_REGS, GR_REGS, GR_REGS,
- GR_REGS, GR_REGS, GR_REGS, GR_REGS,
+ RL_REGS, SP_REG, RL_REGS, RL_REGS,
+ RL_REGS, RL_REGS, RL_REGS, GR_REGS,
+ RL_REGS, RL_REGS, RL_REGS, RL_REGS,
+ RL_REGS, RL_REGS, RL_REGS, RL_REGS,
AR_REGS, AR_REGS, BR_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
static enum machine_mode xtensa_find_mode_for_size PARAMS ((unsigned));
static struct machine_function * xtensa_init_machine_status PARAMS ((void));
static void printx PARAMS ((FILE *, signed int));
-static void xtensa_select_rtx_section PARAMS ((enum machine_mode, rtx,
- unsigned HOST_WIDE_INT));
-static void xtensa_encode_section_info PARAMS ((tree, int));
+static unsigned int xtensa_multibss_section_type_flags
+ PARAMS ((tree, const char *, int));
+static void xtensa_select_rtx_section
+ PARAMS ((enum machine_mode, rtx, unsigned HOST_WIDE_INT));
+static bool xtensa_rtx_costs PARAMS ((rtx, int, int, int *));
static rtx frame_size_const;
static int current_function_arg_words;
#undef TARGET_ASM_SELECT_RTX_SECTION
#define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
-#undef TARGET_ENCODE_SECTION_INFO
-#define TARGET_ENCODE_SECTION_INFO xtensa_encode_section_info
+
+#undef TARGET_RTX_COSTS
+#define TARGET_RTX_COSTS xtensa_rtx_costs
+#undef TARGET_ADDRESS_COST
+#define TARGET_ADDRESS_COST hook_int_rtx_0
struct gcc_target targetm = TARGET_INITIALIZER;
\f
/* This is just like the standard true_regnum() function except that it
- works even when reg_renumber is not initialized. */
+ works even when reg_renumber is not initialized. */
int
xt_true_regnum (x)
int
add_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+ rtx op;
+ enum machine_mode mode;
{
- if (GET_CODE (op) == CONST_INT)
- return (xtensa_simm8 (INTVAL (op)) ||
- xtensa_simm8x256 (INTVAL (op)));
+ if (GET_CODE (op) == CONST_INT)
+ return (xtensa_simm8 (INTVAL (op)) ||
+ xtensa_simm8x256 (INTVAL (op)));
- return register_operand (op, mode);
+ return register_operand (op, mode);
}
int
arith_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+ rtx op;
+ enum machine_mode mode;
{
- if (GET_CODE (op) == CONST_INT)
- return xtensa_simm8 (INTVAL (op));
+ if (GET_CODE (op) == CONST_INT)
+ return xtensa_simm8 (INTVAL (op));
- return register_operand (op, mode);
+ return register_operand (op, mode);
}
int
nonimmed_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+ rtx op;
+ enum machine_mode mode;
{
- /* We cannot use the standard nonimmediate_operand() predicate because
- it includes constant pool memory operands. */
+ /* We cannot use the standard nonimmediate_operand() predicate because
+ it includes constant pool memory operands. */
- if (memory_operand (op, mode))
- return !constantpool_address_p (XEXP (op, 0));
+ if (memory_operand (op, mode))
+ return !constantpool_address_p (XEXP (op, 0));
- return register_operand (op, mode);
+ return register_operand (op, mode);
}
int
mem_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+ rtx op;
+ enum machine_mode mode;
{
- /* We cannot use the standard memory_operand() predicate because
- it includes constant pool memory operands. */
+ /* We cannot use the standard memory_operand() predicate because
+ it includes constant pool memory operands. */
- if (memory_operand (op, mode))
- return !constantpool_address_p (XEXP (op, 0));
+ if (memory_operand (op, mode))
+ return !constantpool_address_p (XEXP (op, 0));
- return FALSE;
+ return FALSE;
}
{
int dst_regnum = xt_true_regnum (operands[0]);
- /* The stack pointer can only be assigned with a MOVSP opcode. */
+ /* The stack pointer can only be assigned with a MOVSP opcode. */
if (dst_regnum == STACK_POINTER_REGNUM)
return (mode == SImode
&& register_operand (operands[1], mode)
if (CONSTANT_ADDRESS_P (op))
{
/* Direct calls only allowed to static functions with PIC. */
- return (!flag_pic || (GET_CODE (op) == SYMBOL_REF
- && SYMBOL_REF_FLAG (op)));
+ return (!flag_pic
+ || (GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op)));
}
return FALSE;
return TRUE;
/* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and
- result in 0/1. */
+ result in 0/1. */
if (GET_CODE (op) == CONSTANT_P_RTX)
return TRUE;
where we emit an optimized block move operation if the block can be
moved in < "move_ratio" pieces. The worst case is when the block is
aligned but has a size of (3 mod 4) (does this happen?) so that the
- last piece requires a byte load/store. */
+ last piece requires a byte load/store. */
return (xtensa_uimm8 (v) &&
xtensa_uimm8 (v + MOVE_MAX * LARGEST_MOVE_RATIO));
/* Generate the code to compare two integer values. The return value is
- the comparison expression. */
+ the comparison expression. */
static rtx
gen_int_relational (test_code, cmp0, cmp1, p_invert)
/* Generate the code to compare two float values. The return value is
- the comparison expression. */
+ the comparison expression. */
static rtx
gen_float_relational (test_code, cmp0, cmp1)
comparison supported in Xtensa. We shouldn't have to
transform <LE x const> comparisons, because neither
xtensa_expand_conditional_branch() nor get_condition() will
- produce them. */
+ produce them. */
if ((code == GT) && (op1 == constm1_rtx))
{
if (!xtensa_valid_move (mode, operands))
operands[1] = force_reg (mode, operands[1]);
- /* Check if this move is copying an incoming argument in a7. If
- so, emit the move, followed by the special "set_frame_ptr"
- unspec_volatile insn, at the very beginning of the function.
- This is necessary because the register allocator will ignore
- conflicts with a7 and may assign some other pseudo to a7. If
- that pseudo was assigned prior to this move, it would clobber
- the incoming argument in a7. By copying the argument out of
- a7 as the very first thing, and then immediately following
- that with an unspec_volatile to keep the scheduler away, we
- should avoid any problems. */
-
- if (a7_overlap_mentioned_p (operands[1]))
- {
- rtx mov;
- switch (mode)
- {
- case SImode:
- mov = gen_movsi_internal (operands[0], operands[1]);
- break;
- case HImode:
- mov = gen_movhi_internal (operands[0], operands[1]);
- break;
- case QImode:
- mov = gen_movqi_internal (operands[0], operands[1]);
- break;
- default:
- abort ();
- }
-
- /* Insert the instructions before any other argument copies.
- (The set_frame_ptr insn comes _after_ the move, so push it
- out first.) */
- push_topmost_sequence ();
- emit_insn_after (gen_set_frame_ptr (), get_insns ());
- emit_insn_after (mov, get_insns ());
- pop_topmost_sequence ();
-
- return 1;
- }
+ if (xtensa_copy_incoming_a7 (operands, mode))
+ return 1;
}
/* During reload we don't want to emit (subreg:X (mem:Y)) since that
- instruction won't be recognized after reload. So we remove the
- subreg and adjust mem accordingly. */
+ instruction won't be recognized after reload, so we remove the
+ subreg and adjust mem accordingly. */
if (reload_in_progress)
{
operands[0] = fixup_subreg_mem (operands[0]);
}
+/* Check if this move is copying an incoming argument in a7. If so,
+ emit the move, followed by the special "set_frame_ptr"
+ unspec_volatile insn, at the very beginning of the function. This
+ is necessary because the register allocator will ignore conflicts
+ with a7 and may assign some other pseudo to a7. If that pseudo was
+ assigned prior to this move, it would clobber the incoming argument
+ in a7. By copying the argument out of a7 as the very first thing,
+ and then immediately following that with an unspec_volatile to keep
+ the scheduler away, we should avoid any problems. */
+
+bool
+xtensa_copy_incoming_a7 (operands, mode)
+ rtx *operands;
+ enum machine_mode mode;
+{
+ if (a7_overlap_mentioned_p (operands[1])
+ && !cfun->machine->incoming_a7_copied)
+ {
+ rtx mov;
+ switch (mode)
+ {
+ case DFmode:
+ mov = gen_movdf_internal (operands[0], operands[1]);
+ break;
+ case SFmode:
+ mov = gen_movsf_internal (operands[0], operands[1]);
+ break;
+ case DImode:
+ mov = gen_movdi_internal (operands[0], operands[1]);
+ break;
+ case SImode:
+ mov = gen_movsi_internal (operands[0], operands[1]);
+ break;
+ case HImode:
+ mov = gen_movhi_internal (operands[0], operands[1]);
+ break;
+ case QImode:
+ mov = gen_movqi_internal (operands[0], operands[1]);
+ break;
+ default:
+ abort ();
+ }
+
+ /* Insert the instructions before any other argument copies.
+ (The set_frame_ptr insn comes _after_ the move, so push it
+ out first.) */
+ push_topmost_sequence ();
+ emit_insn_after (gen_set_frame_ptr (), get_insns ());
+ emit_insn_after (mov, get_insns ());
+ pop_topmost_sequence ();
+
+ /* Ideally the incoming argument in a7 would only be copied
+ once, since propagating a7 into the body of a function
+ will almost certainly lead to errors. However, there is
+ at least one harmless case (in GCSE) where the original
+ copy from a7 is changed to copy into a new pseudo. Thus,
+ we use a flag to only do this special treatment for the
+ first copy of a7. */
+
+ cfun->machine->incoming_a7_copied = true;
+
+ return 1;
+ }
+
+ return 0;
+}
+
+
/* Try to expand a block move operation to an RTL block move instruction.
If not optimizing or if the block size is not a constant or if the
block is small, the expansion fails and GCC falls back to calling
void
xtensa_setup_frame_addresses ()
{
- /* Set flag to cause FRAME_POINTER_REQUIRED to be set. */
+ /* Set flag to cause FRAME_POINTER_REQUIRED to be set. */
cfun->machine->accesses_prev_frame = 1;
emit_library_call
}
-/* Emit the assembly for the end of a zero-cost loop. Normally we just emit
- a comment showing where the end of the loop is. However, if there is a
+/* Emit the assembly for the end of a zero-cost loop. Normally we just emit
+ a comment showing where the end of the loop is. However, if there is a
label or a branch at the end of the loop then we need to place a nop
- there. If the loop ends with a label we need the nop so that branches
+ there. If the loop ends with a label we need the nop so that branches
targetting that label will target the nop (and thus remain in the loop),
instead of targetting the instruction after the loop (and thus exiting
- the loop). If the loop ends with a branch, we need the nop in case the
- branch is targetting a location inside the loop. When the branch
+ the loop). If the loop ends with a branch, we need the nop in case the
+ branch is targetting a location inside the loop. When the branch
executes it will cause the loop count to be decremented even if it is
taken (because it is the last instruction in the loop), so we need to
nop after the branch to prevent the loop count from being decremented
- when the branch is taken. */
+ when the branch is taken. */
void
xtensa_emit_loop_end (insn, operands)
rtx tgt = operands[callop];
if (GET_CODE (tgt) == CONST_INT)
- sprintf (result, "call8\t0x%x", INTVAL (tgt));
+ sprintf (result, "call8\t0x%lx", INTVAL (tgt));
else if (register_operand (tgt, VOIDmode))
sprintf (result, "callx8\t%%%d", callop);
else
}
-/* Return the stabs register number to use for 'regno'. */
+/* Return the stabs register number to use for 'regno'. */
int
xtensa_dbx_register_number (regno)
numbered in libcc order beginning with 256. We can't guarantee
that the FP registers will come first, so the following is just
a guess. It seems like we should make a special case for FP
- registers and give them fixed numbers < 256. */
+ registers and give them fixed numbers < 256. */
first = 256;
}
else if (ACC_REG_P (regno))
}
/* When optimizing, we sometimes get asked about pseudo-registers
- that don't represent hard registers. Return 0 for these. */
+ that don't represent hard registers. Return 0 for these. */
if (first == -1)
return 0;
rtx that is not equal to hard_frame_pointer_rtx. For BLKmode and
modes bigger than 2 words (because we only have patterns for
modes of 2 words or smaller), we can't control the expansion
- unless we explicitly list the individual registers in a PARALLEL. */
+ unless we explicitly list the individual registers in a PARALLEL. */
if ((mode == BLKmode || words > 2)
&& regno < A7_REG
xtensa_char_to_class['D'] = ((TARGET_DENSITY) ? GR_REGS: NO_REGS);
xtensa_char_to_class['d'] = ((TARGET_DENSITY) ? AR_REGS: NO_REGS);
- /* Set up array giving whether a given register can hold a given mode. */
+ /* Set up array giving whether a given register can hold a given mode. */
for (mode = VOIDmode;
mode != MAX_MACHINE_MODE;
mode = (enum machine_mode) ((int) mode + 1))
/* Check PIC settings. There's no need for -fPIC on Xtensa and
some targets need to always use PIC. */
- if (XTENSA_ALWAYS_PIC)
- {
- if (flag_pic)
- warning ("-f%s ignored (all code is position independent)",
- (flag_pic > 1 ? "PIC" : "pic"));
- flag_pic = 1;
- }
- if (flag_pic > 1)
+ if (flag_pic > 1 || (XTENSA_ALWAYS_PIC))
flag_pic = 1;
}
}
case 'L':
- fprintf (file, "%d", (32 - INTVAL (op)) & 0x1f);
+ fprintf (file, "%ld", (32 - INTVAL (op)) & 0x1f);
break;
case 'R':
- fprintf (file, "%d", INTVAL (op) & 0x1f);
+ fprintf (file, "%ld", INTVAL (op) & 0x1f);
break;
case 'x':
case 'd':
default:
- fprintf (file, "%d", INTVAL (op));
+ fprintf (file, "%ld", INTVAL (op));
break;
}
}
-/* Emit either a label, .comm, or .lcomm directive. */
-
-void
-xtensa_declare_object (file, name, init_string, final_string, size)
- FILE *file;
- char *name;
- char *init_string;
- char *final_string;
- int size;
-{
- fputs (init_string, file); /* "", "\t.comm\t", or "\t.lcomm\t" */
- assemble_name (file, name);
- fprintf (file, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
-}
-
-
void
xtensa_output_literal (file, x, mode, labelno)
FILE *file;
/* Return the bytes needed to compute the frame pointer from the current
- stack pointer. */
+ stack pointer. */
#define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
#define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
/* The code to expand builtin_frame_addr and builtin_return_addr
currently uses the hard_frame_pointer instead of frame_pointer.
This seems wrong but maybe it's necessary for other architectures.
- This function is derived from the i386 code. */
+ This function is derived from the i386 code. */
if (cfun->machine->accesses_prev_frame)
return 1;
frame pointer. This search will fail if the function does not
have an incoming argument in $a7, but in that case, we can just
set up the frame pointer at the very beginning of the
- function. */
+ function. */
for (insn = first; insn; insn = NEXT_INSN (insn))
{
continue;
pat = PATTERN (insn);
- if (GET_CODE (pat) == UNSPEC_VOLATILE
- && (XINT (pat, 1) == UNSPECV_SET_FP))
+ if (GET_CODE (pat) == SET
+ && GET_CODE (SET_SRC (pat)) == UNSPEC_VOLATILE
+ && (XINT (SET_SRC (pat), 1) == UNSPECV_SET_FP))
{
set_frame_ptr_insn = insn;
break;
void
xtensa_function_prologue (file, size)
FILE *file;
- int size ATTRIBUTE_UNUSED;
+ HOST_WIDE_INT size ATTRIBUTE_UNUSED;
{
unsigned long tsize = compute_frame_size (get_frame_size ());
/* Do any necessary cleanup after a function to restore
- stack, frame, and regs. */
+ stack, frame, and regs. */
void
xtensa_function_epilogue (file, size)
FILE *file;
- int size ATTRIBUTE_UNUSED;
+ HOST_WIDE_INT size ATTRIBUTE_UNUSED;
{
rtx insn = get_last_insn ();
- /* If the last insn was a BARRIER, we don't have to write anything. */
+ /* If the last insn was a BARRIER, we don't have to write anything. */
if (GET_CODE (insn) == NOTE)
insn = prev_nonnote_insn (insn);
if (insn == 0 || GET_CODE (insn) != BARRIER)
}
+rtx
+xtensa_return_addr (count, frame)
+ int count;
+ rtx frame;
+{
+ rtx result, retaddr;
+
+ if (count == -1)
+ retaddr = gen_rtx_REG (Pmode, 0);
+ else
+ {
+ rtx addr = plus_constant (frame, -4 * UNITS_PER_WORD);
+ addr = memory_address (Pmode, addr);
+ retaddr = gen_reg_rtx (Pmode);
+ emit_move_insn (retaddr, gen_rtx_MEM (Pmode, addr));
+ }
+
+ /* The 2 most-significant bits of the return address on Xtensa hold
+ the register window size. To get the real return address, these
+ bits must be replaced with the high bits from the current PC. */
+
+ result = gen_reg_rtx (Pmode);
+ emit_insn (gen_fix_return_addr (result, retaddr));
+ return result;
+}
+
+
/* Create the va_list data type.
This structure is set up by __builtin_saveregs. The __va_reg
field points to a stack-allocated region holding the contents of the
registers. E.G., if there are 6 argument registers, and each register is
4 bytes, then __va_stk is set to $sp - (6 * 4); then __va_reg[N*4]
references argument word N for 0 <= N < 6, and __va_stk[N*4] references
- argument word N for N >= 6. */
+ argument word N for N >= 6. */
tree
-xtensa_build_va_list (void)
+xtensa_build_va_list ()
{
tree f_stk, f_reg, f_ndx, record, type_decl;
/* Save the incoming argument registers on the stack. Returns the
- address of the saved registers. */
+ address of the saved registers. */
rtx
xtensa_builtin_saveregs ()
/* Note: Don't use move_block_from_reg() here because the incoming
argument in a7 cannot be represented by hard_frame_pointer_rtx.
Instead, call gen_raw_REG() directly so that we get a distinct
- instance of (REG:SI 7). */
+ instance of (REG:SI 7). */
for (i = 0; i < gp_left; i++)
{
emit_move_insn (operand_subword (dest, i, 1, BLKmode),
/* Implement `va_start' for varargs and stdarg. We look at the
- current function to fill in an initial va_list. */
+ current function to fill in an initial va_list. */
void
-xtensa_va_start (stdarg_p, valist, nextarg)
- int stdarg_p ATTRIBUTE_UNUSED;
+xtensa_va_start (valist, nextarg)
tree valist;
rtx nextarg ATTRIBUTE_UNUSED;
{
TREE_SIDE_EFFECTS (t) = 1;
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
- /* Set the __va_ndx member. */
+ /* Set the __va_ndx member. */
u = build_int_2 (arg_words * UNITS_PER_WORD, 0);
t = build (MODIFY_EXPR, integer_type_node, ndx, u);
TREE_SIDE_EFFECTS (t) = 1;
enum reg_class
-xtensa_preferred_reload_class (x, class)
+xtensa_preferred_reload_class (x, class, isoutput)
rtx x;
enum reg_class class;
+ int isoutput;
{
- if (CONSTANT_P (x) && GET_CODE (x) == CONST_DOUBLE)
+ if (!isoutput && CONSTANT_P (x) && GET_CODE (x) == CONST_DOUBLE)
return NO_REGS;
- /* Don't use sp for reloads! */
- if (class == AR_REGS)
- return GR_REGS;
+ /* Don't use the stack pointer or hard frame pointer for reloads!
+ The hard frame pointer would normally be OK except that it may
+ briefly hold an incoming argument in the prologue, and reload
+ won't know that it is live because the hard frame pointer is
+ treated specially. */
+
+ if (class == AR_REGS || class == GR_REGS)
+ return RL_REGS;
return class;
}
if (!isoutput)
{
if (class == FP_REGS && constantpool_mem_p (x))
- return GR_REGS;
+ return RL_REGS;
}
if (ACC_REG_P (regno))
- return (class == GR_REGS ? NO_REGS : GR_REGS);
+ return ((class == GR_REGS || class == RL_REGS) ? NO_REGS : RL_REGS);
if (class == ACC_REG)
- return (GP_REG_P (regno) ? NO_REGS : GR_REGS);
+ return (GP_REG_P (regno) ? NO_REGS : RL_REGS);
return NO_REGS;
}
for (i = 0; i < num_arg_regs; i++)
reg_alloc_order[nxt++] = GP_ARG_FIRST + i;
+ /* list the coprocessor registers in order */
+ for (i = 0; i < BR_REG_NUM; i++)
+ reg_alloc_order[nxt++] = BR_REG_FIRST + i;
+
/* list the FP registers in order for now */
for (i = 0; i < 16; i++)
reg_alloc_order[nxt++] = FP_REG_FIRST + i;
- /* GCC requires that we list *all* the registers.... */
+ /* GCC requires that we list *all* the registers.... */
reg_alloc_order[nxt++] = 0; /* a0 = return address */
reg_alloc_order[nxt++] = 1; /* a1 = stack pointer */
reg_alloc_order[nxt++] = 16; /* pseudo frame pointer */
reg_alloc_order[nxt++] = 17; /* pseudo arg pointer */
- /* list the coprocessor registers in order */
- for (i = 0; i < BR_REG_NUM; i++)
- reg_alloc_order[nxt++] = BR_REG_FIRST + i;
-
reg_alloc_order[nxt++] = ACC_REG_FIRST; /* MAC16 accumulator */
}
}
/* A customized version of reg_overlap_mentioned_p that only looks for
- references to a7 (as opposed to hard_frame_pointer_rtx). */
+ references to a7 (as opposed to hard_frame_pointer_rtx). */
int
a7_overlap_mentioned_p (x)
return 0;
}
+
+/* Some Xtensa targets support multiple bss sections. If the section
+ name ends with ".bss", add SECTION_BSS to the flags. */
+
+static unsigned int
+xtensa_multibss_section_type_flags (decl, name, reloc)
+ tree decl;
+ const char *name;
+ int reloc;
+{
+ unsigned int flags = default_section_type_flags (decl, name, reloc);
+ const char *suffix;
+
+ suffix = strrchr (name, '.');
+ if (suffix && strcmp (suffix, ".bss") == 0)
+ {
+ if (!decl || (TREE_CODE (decl) == VAR_DECL
+ && DECL_INITIAL (decl) == NULL_TREE))
+ flags |= SECTION_BSS; /* @nobits */
+ else
+ warning ("only uninitialized variables can be placed in a "
+ ".bss section");
+ }
+
+ return flags;
+}
+
+
/* The literal pool stays with the function. */
static void
function_section (current_function_decl);
}
-/* If we are referencing a function that is static, make the SYMBOL_REF
- special so that we can generate direct calls to it even with -fpic. */
+/* Compute a (partial) cost for rtx X. Return true if the complete
+ cost has been computed, and false if subexpressions should be
+ scanned. In either case, *TOTAL contains the cost result. */
-static void
-xtensa_encode_section_info (decl, first)
- tree decl;
- int first ATTRIBUTE_UNUSED;
+static bool
+xtensa_rtx_costs (x, code, outer_code, total)
+ rtx x;
+ int code, outer_code;
+ int *total;
{
- if (TREE_CODE (decl) == FUNCTION_DECL && ! TREE_PUBLIC (decl))
- SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
+ switch (code)
+ {
+ case CONST_INT:
+ switch (outer_code)
+ {
+ case SET:
+ if (xtensa_simm12b (INTVAL (x)))
+ {
+ *total = 4;
+ return true;
+ }
+ break;
+ case PLUS:
+ if (xtensa_simm8 (INTVAL (x))
+ || xtensa_simm8x256 (INTVAL (x)))
+ {
+ *total = 0;
+ return true;
+ }
+ break;
+ case AND:
+ if (xtensa_mask_immediate (INTVAL (x)))
+ {
+ *total = 0;
+ return true;
+ }
+ break;
+ case COMPARE:
+ if ((INTVAL (x) == 0) || xtensa_b4const (INTVAL (x)))
+ {
+ *total = 0;
+ return true;
+ }
+ break;
+ case ASHIFT:
+ case ASHIFTRT:
+ case LSHIFTRT:
+ case ROTATE:
+ case ROTATERT:
+ /* no way to tell if X is the 2nd operand so be conservative */
+ default: break;
+ }
+ if (xtensa_simm12b (INTVAL (x)))
+ *total = 5;
+ else
+ *total = 6;
+ return true;
+
+ case CONST:
+ case LABEL_REF:
+ case SYMBOL_REF:
+ *total = 5;
+ return true;
+
+ case CONST_DOUBLE:
+ *total = 7;
+ return true;
+
+ case MEM:
+ {
+ int num_words =
+ (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) ? 2 : 1;
+
+ if (memory_address_p (GET_MODE (x), XEXP ((x), 0)))
+ *total = COSTS_N_INSNS (num_words);
+ else
+ *total = COSTS_N_INSNS (2*num_words);
+ return true;
+ }
+
+ case FFS:
+ *total = COSTS_N_INSNS (TARGET_NSA ? 5 : 50);
+ return true;
+
+ case NOT:
+ *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 3 : 2);
+ return true;
+
+ case AND:
+ case IOR:
+ case XOR:
+ if (GET_MODE (x) == DImode)
+ *total = COSTS_N_INSNS (2);
+ else
+ *total = COSTS_N_INSNS (1);
+ return true;
+
+ case ASHIFT:
+ case ASHIFTRT:
+ case LSHIFTRT:
+ if (GET_MODE (x) == DImode)
+ *total = COSTS_N_INSNS (50);
+ else
+ *total = COSTS_N_INSNS (1);
+ return true;
+
+ case ABS:
+ {
+ enum machine_mode xmode = GET_MODE (x);
+ if (xmode == SFmode)
+ *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
+ else if (xmode == DFmode)
+ *total = COSTS_N_INSNS (50);
+ else
+ *total = COSTS_N_INSNS (4);
+ return true;
+ }
+
+ case PLUS:
+ case MINUS:
+ {
+ enum machine_mode xmode = GET_MODE (x);
+ if (xmode == SFmode)
+ *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
+ else if (xmode == DFmode || xmode == DImode)
+ *total = COSTS_N_INSNS (50);
+ else
+ *total = COSTS_N_INSNS (1);
+ return true;
+ }
+
+ case NEG:
+ *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 4 : 2);
+ return true;
+
+ case MULT:
+ {
+ enum machine_mode xmode = GET_MODE (x);
+ if (xmode == SFmode)
+ *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50);
+ else if (xmode == DFmode || xmode == DImode)
+ *total = COSTS_N_INSNS (50);
+ else if (TARGET_MUL32)
+ *total = COSTS_N_INSNS (4);
+ else if (TARGET_MAC16)
+ *total = COSTS_N_INSNS (16);
+ else if (TARGET_MUL16)
+ *total = COSTS_N_INSNS (12);
+ else
+ *total = COSTS_N_INSNS (50);
+ return true;
+ }
+
+ case DIV:
+ case MOD:
+ {
+ enum machine_mode xmode = GET_MODE (x);
+ if (xmode == SFmode)
+ {
+ *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50);
+ return true;
+ }
+ else if (xmode == DFmode)
+ {
+ *total = COSTS_N_INSNS (50);
+ return true;
+ }
+ }
+ /* fall through */
+
+ case UDIV:
+ case UMOD:
+ {
+ enum machine_mode xmode = GET_MODE (x);
+ if (xmode == DImode)
+ *total = COSTS_N_INSNS (50);
+ else if (TARGET_DIV32)
+ *total = COSTS_N_INSNS (32);
+ else
+ *total = COSTS_N_INSNS (50);
+ return true;
+ }
+
+ case SQRT:
+ if (GET_MODE (x) == SFmode)
+ *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50);
+ else
+ *total = COSTS_N_INSNS (50);
+ return true;
+
+ case SMIN:
+ case UMIN:
+ case SMAX:
+ case UMAX:
+ *total = COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50);
+ return true;
+
+ case SIGN_EXTRACT:
+ case SIGN_EXTEND:
+ *total = COSTS_N_INSNS (TARGET_SEXT ? 1 : 2);
+ return true;
+
+ case ZERO_EXTRACT:
+ case ZERO_EXTEND:
+ *total = COSTS_N_INSNS (1);
+ return true;
+
+ default:
+ return false;
+ }
}
#include "gt-xtensa.h"
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