/* Subroutines for insn-output.c for VAX.
- Copyright (C) 1987, 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002
+ Copyright (C) 1987, 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002,
+ 2004, 2005
Free Software Foundation, Inc.
This file is part of GCC.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
+the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+Boston, MA 02110-1301, USA. */
#include "config.h"
#include "system.h"
#include "optabs.h"
#include "flags.h"
#include "debug.h"
+#include "toplev.h"
#include "tm_p.h"
#include "target.h"
#include "target-def.h"
HOST_WIDE_INT, tree);
static int vax_address_cost_1 (rtx);
static int vax_address_cost (rtx);
-static int vax_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
static bool vax_rtx_costs (rtx, int, int, int *);
+static rtx vax_struct_value_rtx (tree, int);
\f
/* Initialize the GCC target structure. */
#undef TARGET_ASM_ALIGNED_HI_OP
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
+#undef TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
+
#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS vax_rtx_costs
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST vax_address_cost
+#undef TARGET_PROMOTE_PROTOTYPES
+#define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
+
+#undef TARGET_STRUCT_VALUE_RTX
+#define TARGET_STRUCT_VALUE_RTX vax_struct_value_rtx
+
struct gcc_target targetm = TARGET_INITIALIZER;
\f
/* Set global variables as needed for the options enabled. */
override_options (void)
{
/* We're VAX floating point, not IEEE floating point. */
- memset (real_format_for_mode, 0, sizeof real_format_for_mode);
- real_format_for_mode[SFmode - QFmode] = &vax_f_format;
- real_format_for_mode[DFmode - QFmode]
- = (TARGET_G_FLOAT ? &vax_g_format : &vax_d_format);
+ if (TARGET_G_FLOAT)
+ REAL_MODE_FORMAT (DFmode) = &vax_g_format;
}
/* Generate the assembly code for function entry. FILE is a stdio
static void
vax_output_function_prologue (FILE * file, HOST_WIDE_INT size)
{
- register int regno;
- register int mask = 0;
+ int regno;
+ int mask = 0;
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
if (regs_ever_live[regno] && !call_used_regs[regno])
vax_init_libfuncs (void)
{
set_optab_libfunc (udiv_optab, SImode, TARGET_ELF ? "*__udiv" : "*udiv");
- set_optab_libfunc (umod_optab, SImode, TARGET_ELF ? "*__umod" : "*umod");
+ set_optab_libfunc (umod_optab, SImode, TARGET_ELF ? "*__urem" : "*urem");
}
/* This is like nonimmediate_operand with a restriction on the type of MEM. */
{
if (low[i])
/* it's already been figured out */;
- else if (GET_CODE (operands[i]) == MEM
+ else if (MEM_P (operands[i])
&& (GET_CODE (XEXP (operands[i], 0)) == POST_INC))
{
rtx addr = XEXP (operands[i], 0);
}
\f
void
-print_operand_address (FILE * file, register rtx addr)
+print_operand_address (FILE * file, rtx addr)
{
- register rtx reg1, breg, ireg;
+ rtx reg1, breg, ireg;
rtx offset;
retry:
reg1 = 0; ireg = 0; breg = 0; offset = 0;
if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
- || GET_CODE (XEXP (addr, 0)) == MEM)
+ || MEM_P (XEXP (addr, 0)))
{
offset = XEXP (addr, 0);
addr = XEXP (addr, 1);
}
else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
- || GET_CODE (XEXP (addr, 1)) == MEM)
+ || MEM_P (XEXP (addr, 1)))
{
offset = XEXP (addr, 1);
addr = XEXP (addr, 0);
ireg = XEXP (addr, 0);
addr = XEXP (addr, 1);
}
- else if (GET_CODE (XEXP (addr, 1)) == REG)
+ else if (REG_P (XEXP (addr, 1)))
{
reg1 = XEXP (addr, 1);
addr = XEXP (addr, 0);
}
- else if (GET_CODE (XEXP (addr, 0)) == REG)
+ else if (REG_P (XEXP (addr, 0)))
{
reg1 = XEXP (addr, 0);
addr = XEXP (addr, 1);
}
else
- abort ();
+ gcc_unreachable ();
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
{
if (reg1)
ireg = addr;
}
else if (GET_CODE (addr) == MULT)
ireg = addr;
- else if (GET_CODE (addr) == PLUS)
+ else
{
+ gcc_assert (GET_CODE (addr) == PLUS);
if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
- || GET_CODE (XEXP (addr, 0)) == MEM)
+ || MEM_P (XEXP (addr, 0)))
{
if (offset)
{
if (GET_CODE (offset) == CONST_INT)
offset = plus_constant (XEXP (addr, 0), INTVAL (offset));
- else if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
- offset = plus_constant (offset, INTVAL (XEXP (addr, 0)));
else
- abort ();
+ {
+ gcc_assert (GET_CODE (XEXP (addr, 0)) == CONST_INT);
+ offset = plus_constant (offset, INTVAL (XEXP (addr, 0)));
+ }
}
offset = XEXP (addr, 0);
}
- else if (GET_CODE (XEXP (addr, 0)) == REG)
+ else if (REG_P (XEXP (addr, 0)))
{
if (reg1)
ireg = reg1, breg = XEXP (addr, 0), reg1 = 0;
else
reg1 = XEXP (addr, 0);
}
- else if (GET_CODE (XEXP (addr, 0)) == MULT)
+ else
{
- if (ireg)
- abort ();
+ gcc_assert (GET_CODE (XEXP (addr, 0)) == MULT);
+ gcc_assert (!ireg);
ireg = XEXP (addr, 0);
}
- else
- abort ();
if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
- || GET_CODE (XEXP (addr, 1)) == MEM)
+ || MEM_P (XEXP (addr, 1)))
{
if (offset)
{
if (GET_CODE (offset) == CONST_INT)
offset = plus_constant (XEXP (addr, 1), INTVAL (offset));
- else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
- offset = plus_constant (offset, INTVAL (XEXP (addr, 1)));
else
- abort ();
+ {
+ gcc_assert (GET_CODE (XEXP (addr, 1)) == CONST_INT);
+ offset = plus_constant (offset, INTVAL (XEXP (addr, 1)));
+ }
}
offset = XEXP (addr, 1);
}
- else if (GET_CODE (XEXP (addr, 1)) == REG)
+ else if (REG_P (XEXP (addr, 1)))
{
if (reg1)
ireg = reg1, breg = XEXP (addr, 1), reg1 = 0;
else
reg1 = XEXP (addr, 1);
}
- else if (GET_CODE (XEXP (addr, 1)) == MULT)
+ else
{
- if (ireg)
- abort ();
+ gcc_assert (GET_CODE (XEXP (addr, 1)) == MULT);
+ gcc_assert (!ireg);
ireg = XEXP (addr, 1);
}
- else
- abort ();
}
- else
- abort ();
/* If REG1 is nonzero, figure out if it is a base or index register. */
if (reg1)
{
- if (breg != 0 || (offset && GET_CODE (offset) == MEM))
+ if (breg != 0 || (offset && MEM_P (offset)))
{
- if (ireg)
- abort ();
+ gcc_assert (!ireg);
ireg = reg1;
}
else
{
if (GET_CODE (ireg) == MULT)
ireg = XEXP (ireg, 0);
- if (GET_CODE (ireg) != REG)
- abort ();
+ gcc_assert (REG_P (ireg));
fprintf (file, "[%s]", reg_names[REGNO (ireg)]);
}
break;
return "lssu";
default:
- abort ();
+ gcc_unreachable ();
}
}
int
-vax_float_literal(register rtx c)
+vax_float_literal(rtx c)
{
- register enum machine_mode mode;
+ enum machine_mode mode;
REAL_VALUE_TYPE r, s;
int i;
for (i = 0; i < 7; i++)
{
int x = 1 << i;
+ bool ok;
REAL_VALUE_FROM_INT (s, x, 0, mode);
if (REAL_VALUES_EQUAL (r, s))
return 1;
- if (!exact_real_inverse (mode, &s))
- abort ();
+ ok = exact_real_inverse (mode, &s);
+ gcc_assert (ok);
if (REAL_VALUES_EQUAL (r, s))
return 1;
}
static int
-vax_address_cost_1 (register rtx addr)
+vax_address_cost_1 (rtx addr)
{
int reg = 0, indexed = 0, indir = 0, offset = 0, predec = 0;
rtx plus_op0 = 0, plus_op1 = 0;
case CONST_INT:
/* byte offsets cost nothing (on a VAX 2, they cost 1 cycle) */
if (offset == 0)
- offset = (unsigned)(INTVAL(addr)+128) > 256;
+ offset = (unsigned HOST_WIDE_INT)(INTVAL(addr)+128) > 256;
break;
case CONST:
case SYMBOL_REF:
static int
vax_address_cost (rtx x)
{
- return (1 + (GET_CODE (x) == REG ? 0 : vax_address_cost_1 (x)));
+ return (1 + (REG_P (x) ? 0 : vax_address_cost_1 (x)));
}
/* Cost of an expression on a VAX. This version has costs tuned for the
CVAX chip (found in the VAX 3 series) with comments for variations on
- other models. */
+ other models.
-static int
-vax_rtx_costs_1 (register rtx x, enum rtx_code code, enum rtx_code outer_code)
+ FIXME: The costs need review, particularly for TRUNCATE, FLOAT_EXTEND
+ and FLOAT_TRUNCATE. We need a -mcpu option to allow provision of
+ costs on a per cpu basis. */
+
+static bool
+vax_rtx_costs (rtx x, int code, int outer_code, int *total)
{
enum machine_mode mode = GET_MODE (x);
- register int c;
- int i = 0; /* may be modified in switch */
+ int i = 0; /* may be modified in switch */
const char *fmt = GET_RTX_FORMAT (code); /* may be modified in switch */
switch (code)
{
/* On a VAX, constants from 0..63 are cheap because they can use the
- 1 byte literal constant format. compare to -1 should be made cheap
- so that decrement-and-branch insns can be formed more easily (if
- the value -1 is copied to a register some decrement-and-branch
+ 1 byte literal constant format. Compare to -1 should be made cheap
+ so that decrement-and-branch insns can be formed more easily (if
+ the value -1 is copied to a register some decrement-and-branch
patterns will not match). */
case CONST_INT:
if (INTVAL (x) == 0)
- return 0;
+ return true;
if (outer_code == AND)
- return ((unsigned HOST_WIDE_INT) ~INTVAL (x) <= 077) ? 1 : 2;
- if ((unsigned HOST_WIDE_INT) INTVAL (x) <= 077)
- return 1;
- if (outer_code == COMPARE && INTVAL (x) == -1)
- return 1;
- if (outer_code == PLUS && (unsigned HOST_WIDE_INT) -INTVAL (x) <= 077)
- return 1;
+ {
+ *total = ((unsigned HOST_WIDE_INT) ~INTVAL (x) <= 077) ? 1 : 2;
+ return true;
+ }
+ if ((unsigned HOST_WIDE_INT) INTVAL (x) <= 077
+ || (outer_code == COMPARE
+ && INTVAL (x) == -1)
+ || ((outer_code == PLUS || outer_code == MINUS)
+ && (unsigned HOST_WIDE_INT) -INTVAL (x) <= 077))
+ {
+ *total = 1;
+ return true;
+ }
/* FALLTHRU */
case CONST:
case LABEL_REF:
case SYMBOL_REF:
- return 3;
+ *total = 3;
+ return true;
case CONST_DOUBLE:
if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
- return vax_float_literal (x) ? 5 : 8;
+ *total = vax_float_literal (x) ? 5 : 8;
else
- return (((CONST_DOUBLE_HIGH (x) == 0
- && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (x) < 64)
- || (outer_code == PLUS
- && CONST_DOUBLE_HIGH (x) == -1 \
- && (unsigned HOST_WIDE_INT)-CONST_DOUBLE_LOW (x) < 64))
- ? 2 : 5);
-
+ *total = ((CONST_DOUBLE_HIGH (x) == 0
+ && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (x) < 64)
+ || (outer_code == PLUS
+ && CONST_DOUBLE_HIGH (x) == -1
+ && (unsigned HOST_WIDE_INT)-CONST_DOUBLE_LOW (x) < 64))
+ ? 2 : 5;
+ return true;
+
case POST_INC:
- return 2;
+ *total = 2;
+ return true; /* Implies register operand. */
+
case PRE_DEC:
- return 3;
+ *total = 3;
+ return true; /* Implies register operand. */
+
case MULT:
switch (mode)
{
case DFmode:
- c = 16; /* 4 on VAX 9000 */
+ *total = 16; /* 4 on VAX 9000 */
break;
case SFmode:
- c = 9; /* 4 on VAX 9000, 12 on VAX 2 */
+ *total = 9; /* 4 on VAX 9000, 12 on VAX 2 */
break;
case DImode:
- c = 16; /* 6 on VAX 9000, 28 on VAX 2 */
+ *total = 16; /* 6 on VAX 9000, 28 on VAX 2 */
break;
case SImode:
case HImode:
case QImode:
- c = 10; /* 3-4 on VAX 9000, 20-28 on VAX 2 */
+ *total = 10; /* 3-4 on VAX 9000, 20-28 on VAX 2 */
break;
default:
- return MAX_COST; /* Mode is not supported. */
+ *total = MAX_COST; /* Mode is not supported. */
+ return true;
}
break;
+
case UDIV:
if (mode != SImode)
- return MAX_COST; /* Mode is not supported. */
- c = 17;
+ {
+ *total = MAX_COST; /* Mode is not supported. */
+ return true;
+ }
+ *total = 17;
break;
+
case DIV:
if (mode == DImode)
- c = 30; /* highly variable */
+ *total = 30; /* Highly variable. */
else if (mode == DFmode)
/* divide takes 28 cycles if the result is not zero, 13 otherwise */
- c = 24;
+ *total = 24;
else
- c = 11; /* 25 on VAX 2 */
+ *total = 11; /* 25 on VAX 2 */
break;
+
case MOD:
- c = 23;
+ *total = 23;
break;
+
case UMOD:
if (mode != SImode)
- return MAX_COST; /* Mode is not supported. */
- c = 29;
+ {
+ *total = MAX_COST; /* Mode is not supported. */
+ return true;
+ }
+ *total = 29;
break;
+
case FLOAT:
- c = 6 + (mode == DFmode) + (GET_MODE (XEXP (x, 0)) != SImode);
- /* 4 on VAX 9000 */
+ *total = (6 /* 4 on VAX 9000 */
+ + (mode == DFmode) + (GET_MODE (XEXP (x, 0)) != SImode));
break;
+
case FIX:
- c = 7; /* 17 on VAX 2 */
+ *total = 7; /* 17 on VAX 2 */
break;
+
case ASHIFT:
case LSHIFTRT:
case ASHIFTRT:
if (mode == DImode)
- c = 12;
+ *total = 12;
else
- c = 10; /* 6 on VAX 9000 */
+ *total = 10; /* 6 on VAX 9000 */
break;
+
case ROTATE:
case ROTATERT:
- c = 6; /* 5 on VAX 2, 4 on VAX 9000 */
+ *total = 6; /* 5 on VAX 2, 4 on VAX 9000 */
if (GET_CODE (XEXP (x, 1)) == CONST_INT)
- fmt = "e"; /* all constant rotate counts are short */
+ fmt = "e"; /* all constant rotate counts are short */
break;
+
case PLUS:
- /* Check for small negative integer operand: subl2 can be used with
- a short positive constant instead. */
- if (GET_CODE (XEXP (x, 1)) == CONST_INT)
- if ((unsigned)(INTVAL (XEXP (x, 1)) + 63) < 127)
- fmt = "e";
case MINUS:
- c = (mode == DFmode) ? 13 : 8; /* 6/8 on VAX 9000, 16/15 on VAX 2 */
+ *total = (mode == DFmode) ? 13 : 8; /* 6/8 on VAX 9000, 16/15 on VAX 2 */
+ /* Small integer operands can use subl2 and addl2. */
+ if ((GET_CODE (XEXP (x, 1)) == CONST_INT)
+ && (unsigned HOST_WIDE_INT)(INTVAL (XEXP (x, 1)) + 63) < 127)
+ fmt = "e";
+ break;
+
case IOR:
case XOR:
- c = 3;
+ *total = 3;
break;
+
case AND:
/* AND is special because the first operand is complemented. */
- c = 3;
+ *total = 3;
if (GET_CODE (XEXP (x, 0)) == CONST_INT)
{
- if ((unsigned)~INTVAL (XEXP (x, 0)) > 63)
- c = 4;
+ if ((unsigned HOST_WIDE_INT)~INTVAL (XEXP (x, 0)) > 63)
+ *total = 4;
fmt = "e";
i = 1;
}
break;
+
case NEG:
if (mode == DFmode)
- return 9;
+ *total = 9;
else if (mode == SFmode)
- return 6;
+ *total = 6;
else if (mode == DImode)
- return 4;
+ *total = 4;
+ else
+ *total = 2;
+ break;
+
case NOT:
- return 2;
+ *total = 2;
+ break;
+
case ZERO_EXTRACT:
case SIGN_EXTRACT:
- c = 15;
+ *total = 15;
break;
+
case MEM:
if (mode == DImode || mode == DFmode)
- c = 5; /* 7 on VAX 2 */
+ *total = 5; /* 7 on VAX 2 */
else
- c = 3; /* 4 on VAX 2 */
+ *total = 3; /* 4 on VAX 2 */
x = XEXP (x, 0);
- if (GET_CODE (x) == REG || GET_CODE (x) == POST_INC)
- return c;
- return c + vax_address_cost_1 (x);
- default:
- c = 3;
+ if (!REG_P (x) && GET_CODE (x) != POST_INC)
+ *total += vax_address_cost_1 (x);
+ return true;
+
+ case FLOAT_EXTEND:
+ case FLOAT_TRUNCATE:
+ case TRUNCATE:
+ *total = 3; /* FIXME: Costs need to be checked */
break;
+
+ default:
+ return false;
}
/* Now look inside the expression. Operands which are not registers or
short constants add to the cost.
FMT and I may have been adjusted in the switch above for instructions
- which require special handling */
+ which require special handling. */
while (*fmt++ == 'e')
{
- register rtx op = XEXP (x, i++);
+ rtx op = XEXP (x, i);
+
+ i += 1;
code = GET_CODE (op);
/* A NOT is likely to be found as the first operand of an AND
switch (code)
{
case CONST_INT:
- if ((unsigned)INTVAL (op) > 63 && GET_MODE (x) != QImode)
- c += 1; /* 2 on VAX 2 */
+ if ((unsigned HOST_WIDE_INT)INTVAL (op) > 63
+ && GET_MODE (x) != QImode)
+ *total += 1; /* 2 on VAX 2 */
break;
case CONST:
case LABEL_REF:
case SYMBOL_REF:
- c += 1; /* 2 on VAX 2 */
+ *total += 1; /* 2 on VAX 2 */
break;
case CONST_DOUBLE:
if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
/* Registers are faster than floating point constants -- even
those constants which can be encoded in a single byte. */
if (vax_float_literal (op))
- c++;
+ *total += 1;
else
- c += (GET_MODE (x) == DFmode) ? 3 : 2;
+ *total += (GET_MODE (x) == DFmode) ? 3 : 2;
}
else
{
if (CONST_DOUBLE_HIGH (op) != 0
|| (unsigned)CONST_DOUBLE_LOW (op) > 63)
- c += 2;
+ *total += 2;
}
break;
case MEM:
- c += 1; /* 2 on VAX 2 */
- if (GET_CODE (XEXP (op, 0)) != REG)
- c += vax_address_cost_1 (XEXP (op, 0));
+ *total += 1; /* 2 on VAX 2 */
+ if (!REG_P (XEXP (op, 0)))
+ *total += vax_address_cost_1 (XEXP (op, 0));
break;
case REG:
case SUBREG:
break;
default:
- c += 1;
+ *total += 1;
break;
}
}
- return c;
-}
-
-static bool
-vax_rtx_costs (rtx x, int code, int outer_code, int * total)
-{
- *total = vax_rtx_costs_1 (x, code, outer_code);
return true;
}
\f
static void
vax_output_mi_thunk (FILE * file,
- tree thunk ATTRIBUTE_UNUSED,
+ tree thunk ATTRIBUTE_UNUSED,
HOST_WIDE_INT delta,
HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
tree function)
{
fprintf (file, "\t.word 0x0ffc\n\taddl2 $" HOST_WIDE_INT_PRINT_DEC, delta);
asm_fprintf (file, ",4(%Rap)\n");
- fprintf (file, "\tjmp ");
- assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
- fprintf (file, "+2\n");
+ fprintf (file, "\tjmp ");
+ assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
+ fprintf (file, "+2\n");
+}
+\f
+static rtx
+vax_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
+ int incoming ATTRIBUTE_UNUSED)
+{
+ return gen_rtx_REG (Pmode, VAX_STRUCT_VALUE_REGNUM);
+}
+
+/* Worker function for NOTICE_UPDATE_CC. */
+
+void
+vax_notice_update_cc (rtx exp, rtx insn ATTRIBUTE_UNUSED)
+{
+ if (GET_CODE (exp) == SET)
+ {
+ if (GET_CODE (SET_SRC (exp)) == CALL)
+ CC_STATUS_INIT;
+ else if (GET_CODE (SET_DEST (exp)) != ZERO_EXTRACT
+ && GET_CODE (SET_DEST (exp)) != PC)
+ {
+ cc_status.flags = 0;
+ /* The integer operations below don't set carry or
+ set it in an incompatible way. That's ok though
+ as the Z bit is all we need when doing unsigned
+ comparisons on the result of these insns (since
+ they're always with 0). Set CC_NO_OVERFLOW to
+ generate the correct unsigned branches. */
+ switch (GET_CODE (SET_SRC (exp)))
+ {
+ case NEG:
+ if (GET_MODE_CLASS (GET_MODE (exp)) == MODE_FLOAT)
+ break;
+ case AND:
+ case IOR:
+ case XOR:
+ case NOT:
+ case MEM:
+ case REG:
+ cc_status.flags = CC_NO_OVERFLOW;
+ break;
+ default:
+ break;
+ }
+ cc_status.value1 = SET_DEST (exp);
+ cc_status.value2 = SET_SRC (exp);
+ }
+ }
+ else if (GET_CODE (exp) == PARALLEL
+ && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
+ {
+ if (GET_CODE (SET_SRC (XVECEXP (exp, 0, 0))) == CALL)
+ CC_STATUS_INIT;
+ else if (GET_CODE (SET_DEST (XVECEXP (exp, 0, 0))) != PC)
+ {
+ cc_status.flags = 0;
+ cc_status.value1 = SET_DEST (XVECEXP (exp, 0, 0));
+ cc_status.value2 = SET_SRC (XVECEXP (exp, 0, 0));
+ }
+ else
+ /* PARALLELs whose first element sets the PC are aob,
+ sob insns. They do change the cc's. */
+ CC_STATUS_INIT;
+ }
+ else
+ CC_STATUS_INIT;
+ if (cc_status.value1 && REG_P (cc_status.value1)
+ && cc_status.value2
+ && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
+ cc_status.value2 = 0;
+ if (cc_status.value1 && MEM_P (cc_status.value1)
+ && cc_status.value2
+ && MEM_P (cc_status.value2))
+ cc_status.value2 = 0;
+ /* Actual condition, one line up, should be that value2's address
+ depends on value1, but that is too much of a pain. */
+}
+
+/* Output integer move instructions. */
+
+const char *
+vax_output_int_move (rtx insn ATTRIBUTE_UNUSED, rtx *operands,
+ enum machine_mode mode)
+{
+ switch (mode)
+ {
+ case SImode:
+ if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
+ {
+ if (push_operand (operands[0], SImode))
+ return "pushab %a1";
+ return "movab %a1,%0";
+ }
+ if (operands[1] == const0_rtx)
+ return "clrl %0";
+ if (GET_CODE (operands[1]) == CONST_INT
+ && (unsigned) INTVAL (operands[1]) >= 64)
+ {
+ int i = INTVAL (operands[1]);
+ if ((unsigned)(~i) < 64)
+ return "mcoml %N1,%0";
+ if ((unsigned)i < 0x100)
+ return "movzbl %1,%0";
+ if (i >= -0x80 && i < 0)
+ return "cvtbl %1,%0";
+ if ((unsigned)i < 0x10000)
+ return "movzwl %1,%0";
+ if (i >= -0x8000 && i < 0)
+ return "cvtwl %1,%0";
+ }
+ if (push_operand (operands[0], SImode))
+ return "pushl %1";
+ return "movl %1,%0";
+
+ case HImode:
+ if (GET_CODE (operands[1]) == CONST_INT)
+ {
+ int i = INTVAL (operands[1]);
+ if (i == 0)
+ return "clrw %0";
+ else if ((unsigned int)i < 64)
+ return "movw %1,%0";
+ else if ((unsigned int)~i < 64)
+ return "mcomw %H1,%0";
+ else if ((unsigned int)i < 256)
+ return "movzbw %1,%0";
+ }
+ return "movw %1,%0";
+
+ case QImode:
+ if (GET_CODE (operands[1]) == CONST_INT)
+ {
+ int i = INTVAL (operands[1]);
+ if (i == 0)
+ return "clrb %0";
+ else if ((unsigned int)~i < 64)
+ return "mcomb %B1,%0";
+ }
+ return "movb %1,%0";
+
+ default:
+ gcc_unreachable ();
+ }
+}
+
+/* Output integer add instructions.
+
+ The space-time-opcode tradeoffs for addition vary by model of VAX.
+
+ On a VAX 3 "movab (r1)[r2],r3" is faster than "addl3 r1,r2,r3",
+ but it not faster on other models.
+
+ "movab #(r1),r2" is usually shorter than "addl3 #,r1,r2", and is
+ faster on a VAX 3, but some VAXen (e.g. VAX 9000) will stall if
+ a register is used in an address too soon after it is set.
+ Compromise by using movab only when it is shorter than the add
+ or the base register in the address is one of sp, ap, and fp,
+ which are not modified very often. */
+
+const char *
+vax_output_int_add (rtx insn ATTRIBUTE_UNUSED, rtx *operands,
+ enum machine_mode mode)
+{
+ switch (mode)
+ {
+ case SImode:
+ if (rtx_equal_p (operands[0], operands[1]))
+ {
+ if (operands[2] == const1_rtx)
+ return "incl %0";
+ if (operands[2] == constm1_rtx)
+ return "decl %0";
+ if (GET_CODE (operands[2]) == CONST_INT
+ && (unsigned) (- INTVAL (operands[2])) < 64)
+ return "subl2 $%n2,%0";
+ if (GET_CODE (operands[2]) == CONST_INT
+ && (unsigned) INTVAL (operands[2]) >= 64
+ && REG_P (operands[1])
+ && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
+ || REGNO (operands[1]) > 11))
+ return "movab %c2(%1),%0";
+ return "addl2 %2,%0";
+ }
+
+ if (rtx_equal_p (operands[0], operands[2]))
+ return "addl2 %1,%0";
+
+ if (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) < 32767
+ && INTVAL (operands[2]) > -32768
+ && REG_P (operands[1])
+ && push_operand (operands[0], SImode))
+ return "pushab %c2(%1)";
+
+ if (GET_CODE (operands[2]) == CONST_INT
+ && (unsigned) (- INTVAL (operands[2])) < 64)
+ return "subl3 $%n2,%1,%0";
+
+ if (GET_CODE (operands[2]) == CONST_INT
+ && (unsigned) INTVAL (operands[2]) >= 64
+ && REG_P (operands[1])
+ && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
+ || REGNO (operands[1]) > 11))
+ return "movab %c2(%1),%0";
+
+ /* Add this if using gcc on a VAX 3xxx:
+ if (REG_P (operands[1]) && REG_P (operands[2]))
+ return "movab (%1)[%2],%0";
+ */
+ return "addl3 %1,%2,%0";
+
+ case HImode:
+ if (rtx_equal_p (operands[0], operands[1]))
+ {
+ if (operands[2] == const1_rtx)
+ return "incw %0";
+ if (operands[2] == constm1_rtx)
+ return "decw %0";
+ if (GET_CODE (operands[2]) == CONST_INT
+ && (unsigned) (- INTVAL (operands[2])) < 64)
+ return "subw2 $%n2,%0";
+ return "addw2 %2,%0";
+ }
+ if (rtx_equal_p (operands[0], operands[2]))
+ return "addw2 %1,%0";
+ if (GET_CODE (operands[2]) == CONST_INT
+ && (unsigned) (- INTVAL (operands[2])) < 64)
+ return "subw3 $%n2,%1,%0";
+ return "addw3 %1,%2,%0";
+
+ case QImode:
+ if (rtx_equal_p (operands[0], operands[1]))
+ {
+ if (operands[2] == const1_rtx)
+ return "incb %0";
+ if (operands[2] == constm1_rtx)
+ return "decb %0";
+ if (GET_CODE (operands[2]) == CONST_INT
+ && (unsigned) (- INTVAL (operands[2])) < 64)
+ return "subb2 $%n2,%0";
+ return "addb2 %2,%0";
+ }
+ if (rtx_equal_p (operands[0], operands[2]))
+ return "addb2 %1,%0";
+ if (GET_CODE (operands[2]) == CONST_INT
+ && (unsigned) (- INTVAL (operands[2])) < 64)
+ return "subb3 $%n2,%1,%0";
+ return "addb3 %1,%2,%0";
+
+ default:
+ gcc_unreachable ();
+ }
+}
+
+/* Output a conditional branch. */
+const char *
+vax_output_conditional_branch (enum rtx_code code)
+{
+ switch (code)
+ {
+ case EQ: return "jeql %l0";
+ case NE: return "jneq %l0";
+ case GT: return "jgtr %l0";
+ case LT: return "jlss %l0";
+ case GTU: return "jgtru %l0";
+ case LTU: return "jlssu %l0";
+ case GE: return "jgeq %l0";
+ case LE: return "jleq %l0";
+ case GEU: return "jgequ %l0";
+ case LEU: return "jlequ %l0";
+ default:
+ gcc_unreachable ();
+ }
+}
+
+/* 1 if X is an rtx for a constant that is a valid address. */
+
+int
+legitimate_constant_address_p (rtx x)
+{
+ return (GET_CODE (x) == LABEL_REF || GET_CODE (x) == SYMBOL_REF
+ || GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST
+ || GET_CODE (x) == HIGH);
+}
+
+/* Nonzero if the constant value X is a legitimate general operand.
+ It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
+
+int
+legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
+{
+ return 1;
+}
+
+/* The other macros defined here are used only in legitimate_address_p (). */
+
+/* Nonzero if X is a hard reg that can be used as an index
+ or, if not strict, if it is a pseudo reg. */
+#define INDEX_REGISTER_P(X, STRICT) \
+(REG_P (X) && (!(STRICT) || REGNO_OK_FOR_INDEX_P (REGNO (X))))
+
+/* Nonzero if X is a hard reg that can be used as a base reg
+ or, if not strict, if it is a pseudo reg. */
+#define BASE_REGISTER_P(X, STRICT) \
+(REG_P (X) && (!(STRICT) || REGNO_OK_FOR_BASE_P (REGNO (X))))
+
+#ifdef NO_EXTERNAL_INDIRECT_ADDRESS
+
+/* Re-definition of CONSTANT_ADDRESS_P, which is true only when there
+ are no SYMBOL_REFs for external symbols present. */
+
+static int
+indirectable_constant_address_p (rtx x)
+{
+ if (!CONSTANT_ADDRESS_P (x))
+ return 0;
+ if (GET_CODE (x) == CONST && GET_CODE (XEXP ((x), 0)) == PLUS)
+ x = XEXP (XEXP (x, 0), 0);
+ if (GET_CODE (x) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x))
+ return 0;
+
+ return 1;
+}
+
+#else /* not NO_EXTERNAL_INDIRECT_ADDRESS */
+
+static int
+indirectable_constant_address_p (rtx x)
+{
+ return CONSTANT_ADDRESS_P (x);
+}
+
+#endif /* not NO_EXTERNAL_INDIRECT_ADDRESS */
+
+/* Nonzero if X is an address which can be indirected. External symbols
+ could be in a sharable image library, so we disallow those. */
+
+static int
+indirectable_address_p(rtx x, int strict)
+{
+ if (indirectable_constant_address_p (x))
+ return 1;
+ if (BASE_REGISTER_P (x, strict))
+ return 1;
+ if (GET_CODE (x) == PLUS
+ && BASE_REGISTER_P (XEXP (x, 0), strict)
+ && indirectable_constant_address_p (XEXP (x, 1)))
+ return 1;
+ return 0;
+}
+
+/* Return 1 if x is a valid address not using indexing.
+ (This much is the easy part.) */
+static int
+nonindexed_address_p (rtx x, int strict)
+{
+ rtx xfoo0;
+ if (REG_P (x))
+ {
+ extern rtx *reg_equiv_mem;
+ if (! reload_in_progress
+ || reg_equiv_mem[REGNO (x)] == 0
+ || indirectable_address_p (reg_equiv_mem[REGNO (x)], strict))
+ return 1;
+ }
+ if (indirectable_constant_address_p (x))
+ return 1;
+ if (indirectable_address_p (x, strict))
+ return 1;
+ xfoo0 = XEXP (x, 0);
+ if (MEM_P (x) && indirectable_address_p (xfoo0, strict))
+ return 1;
+ if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC)
+ && BASE_REGISTER_P (xfoo0, strict))
+ return 1;
+ return 0;
+}
+
+/* 1 if PROD is either a reg times size of mode MODE and MODE is less
+ than or equal 8 bytes, or just a reg if MODE is one byte. */
+
+static int
+index_term_p (rtx prod, enum machine_mode mode, int strict)
+{
+ rtx xfoo0, xfoo1;
+
+ if (GET_MODE_SIZE (mode) == 1)
+ return BASE_REGISTER_P (prod, strict);
+
+ if (GET_CODE (prod) != MULT || GET_MODE_SIZE (mode) > 8)
+ return 0;
+
+ xfoo0 = XEXP (prod, 0);
+ xfoo1 = XEXP (prod, 1);
+
+ if (GET_CODE (xfoo0) == CONST_INT
+ && INTVAL (xfoo0) == (int)GET_MODE_SIZE (mode)
+ && INDEX_REGISTER_P (xfoo1, strict))
+ return 1;
+
+ if (GET_CODE (xfoo1) == CONST_INT
+ && INTVAL (xfoo1) == (int)GET_MODE_SIZE (mode)
+ && INDEX_REGISTER_P (xfoo0, strict))
+ return 1;
+
+ return 0;
+}
+
+/* Return 1 if X is the sum of a register
+ and a valid index term for mode MODE. */
+static int
+reg_plus_index_p (rtx x, enum machine_mode mode, int strict)
+{
+ rtx xfoo0, xfoo1;
+
+ if (GET_CODE (x) != PLUS)
+ return 0;
+
+ xfoo0 = XEXP (x, 0);
+ xfoo1 = XEXP (x, 1);
+
+ if (BASE_REGISTER_P (xfoo0, strict) && index_term_p (xfoo1, mode, strict))
+ return 1;
+
+ if (BASE_REGISTER_P (xfoo1, strict) && index_term_p (xfoo0, mode, strict))
+ return 1;
+
+ return 0;
+}
+
+/* legitimate_address_p returns 1 if it recognizes an RTL expression "x"
+ that is a valid memory address for an instruction.
+ The MODE argument is the machine mode for the MEM expression
+ that wants to use this address. */
+int
+legitimate_address_p (enum machine_mode mode, rtx x, int strict)
+{
+ rtx xfoo0, xfoo1;
+
+ if (nonindexed_address_p (x, strict))
+ return 1;
+
+ if (GET_CODE (x) != PLUS)
+ return 0;
+
+ /* Handle <address>[index] represented with index-sum outermost */
+
+ xfoo0 = XEXP (x, 0);
+ xfoo1 = XEXP (x, 1);
+
+ if (index_term_p (xfoo0, mode, strict)
+ && nonindexed_address_p (xfoo1, strict))
+ return 1;
+
+ if (index_term_p (xfoo1, mode, strict)
+ && nonindexed_address_p (xfoo0, strict))
+ return 1;
+
+ /* Handle offset(reg)[index] with offset added outermost */
+
+ if (indirectable_constant_address_p (xfoo0)
+ && (BASE_REGISTER_P (xfoo1, strict)
+ || reg_plus_index_p (xfoo1, mode, strict)))
+ return 1;
+
+ if (indirectable_constant_address_p (xfoo1)
+ && (BASE_REGISTER_P (xfoo0, strict)
+ || reg_plus_index_p (xfoo0, mode, strict)))
+ return 1;
+
+ return 0;
+}
+
+/* Return 1 if x (a legitimate address expression) has an effect that
+ depends on the machine mode it is used for. On the VAX, the predecrement
+ and postincrement address depend thus (the amount of decrement or
+ increment being the length of the operand) and all indexed address depend
+ thus (because the index scale factor is the length of the operand). */
+
+int
+vax_mode_dependent_address_p (rtx x)
+{
+ rtx xfoo0, xfoo1;
+
+ if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
+ return 1;
+ if (GET_CODE (x) != PLUS)
+ return 0;
+
+ xfoo0 = XEXP (x, 0);
+ xfoo1 = XEXP (x, 1);
+
+ if (CONSTANT_ADDRESS_P (xfoo0) && REG_P (xfoo1))
+ return 0;
+ if (CONSTANT_ADDRESS_P (xfoo1) && REG_P (xfoo0))
+ return 0;
+
+ return 1;
}
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