[(UNSPEC_MOVE_PIC 0)
(UNSPEC_UPDATE_RETURN 1)
(UNSPEC_LOAD_PCREL_SYM 2)
+ (UNSPEC_FRAME_BLOCKAGE 3)
(UNSPEC_MOVE_PIC_LABEL 5)
(UNSPEC_SETH44 6)
(UNSPEC_SETM44 7)
(UNSPEC_MOVE_GOTDATA 19)
(UNSPEC_MEMBAR 20)
+ (UNSPEC_ATOMIC 21)
(UNSPEC_TLSGD 30)
(UNSPEC_TLSLDM 31)
(UNSPEC_MUL8 86)
(UNSPEC_MUL8SU 87)
(UNSPEC_MULDSU 88)
- (UNSPEC_SHORT_LOAD 89)
])
(define_constants
(match_operand:SI 2 "arith_operand" "rI,rI,rI")))
(clobber (match_scratch:SI 3 "=X,X,&h"))]
"TARGET_V8PLUS"
- "* return output_v8plus_shift (operands, insn, \"sllx\");"
+ "* return output_v8plus_shift (insn ,operands, \"sllx\");"
[(set_attr "type" "multi")
(set_attr "length" "5,5,6")])
(match_operand:SI 2 "arith_operand" "rI,rI,rI")))
(clobber (match_scratch:SI 3 "=X,X,&h"))]
"TARGET_V8PLUS"
- "* return output_v8plus_shift (operands, insn, \"srax\");"
+ "* return output_v8plus_shift (insn, operands, \"srax\");"
[(set_attr "type" "multi")
(set_attr "length" "5,5,6")])
(match_operand:SI 2 "arith_operand" "rI,rI,rI")))
(clobber (match_scratch:SI 3 "=X,X,&h"))]
"TARGET_V8PLUS"
- "* return output_v8plus_shift (operands, insn, \"srlx\");"
+ "* return output_v8plus_shift (insn, operands, \"srlx\");"
[(set_attr "type" "multi")
(set_attr "length" "5,5,6")])
""
[(set_attr "length" "0")])
+;; Do not schedule instructions accessing memory before this point.
+
+(define_expand "frame_blockage"
+ [(set (match_dup 0)
+ (unspec:BLK [(match_dup 1)] UNSPEC_FRAME_BLOCKAGE))]
+ ""
+{
+ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ MEM_VOLATILE_P (operands[0]) = 1;
+ operands[1] = stack_pointer_rtx;
+})
+
+(define_insn "*frame_blockage<P:mode>"
+ [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(match_operand:P 1 "" "")] UNSPEC_FRAME_BLOCKAGE))]
+ ""
+ ""
+ [(set_attr "length" "0")])
+
(define_expand "probe_stack"
[(set (match_operand 0 "memory_operand" "") (const_int 0))]
""
DONE;
})
-(define_expand "zero_extend_v8qi_vis"
- [(set (match_operand:V8QI 0 "register_operand" "")
- (unspec:V8QI [(match_operand:QI 1 "memory_operand" "")]
- UNSPEC_SHORT_LOAD))]
- "TARGET_VIS"
-{
- if (! REG_P (XEXP (operands[1], 0)))
- {
- rtx addr = force_reg (Pmode, XEXP (operands[1], 0));
- operands[1] = replace_equiv_address (operands[1], addr);
- }
-})
-
-(define_expand "zero_extend_v4hi_vis"
- [(set (match_operand:V4HI 0 "register_operand" "")
- (unspec:V4HI [(match_operand:HI 1 "memory_operand" "")]
- UNSPEC_SHORT_LOAD))]
- "TARGET_VIS"
-{
- if (! REG_P (XEXP (operands[1], 0)))
- {
- rtx addr = force_reg (Pmode, XEXP (operands[1], 0));
- operands[1] = replace_equiv_address (operands[1], addr);
- }
-})
-
-(define_insn "*zero_extend_v8qi_<P:mode>_insn"
- [(set (match_operand:V8QI 0 "register_operand" "=e")
- (unspec:V8QI [(mem:QI
- (match_operand:P 1 "register_operand" "r"))]
- UNSPEC_SHORT_LOAD))]
- "TARGET_VIS"
- "ldda\t[%1] 0xd0, %0")
-
-(define_insn "*zero_extend_v4hi_<P:mode>_insn"
- [(set (match_operand:V4HI 0 "register_operand" "=e")
- (unspec:V4HI [(mem:HI
- (match_operand:P 1 "register_operand" "r"))]
- UNSPEC_SHORT_LOAD))]
- "TARGET_VIS"
- "ldda\t[%1] 0xd2, %0")
-
(define_expand "vec_init<mode>"
[(match_operand:VMALL 0 "register_operand" "")
(match_operand:VMALL 1 "" "")]