/* Definitions of target machine for GNU compiler, for Sun SPARC.
Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
- Free Software Foundation, Inc.
+ 2000, 2001, 2002 Free Software Foundation, Inc.
Contributed by Michael Tiemann (tiemann@cygnus.com).
64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
at Cygnus Support.
#define TARGET_CPU_sparcv9 7 /* alias */
#define TARGET_CPU_sparc64 7 /* alias */
#define TARGET_CPU_ultrasparc 8
+#define TARGET_CPU_ultrasparc3 9
#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
- || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
+ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
+ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
#define CPP_CPU32_DEFAULT_SPEC ""
#define ASM_CPU32_DEFAULT_SPEC ""
#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
#define ASM_CPU64_DEFAULT_SPEC "-Av9a"
#endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
+#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
+#define ASM_CPU64_DEFAULT_SPEC "-Av9b"
+#endif
#else
#endif /* !SPARC_BI_ARCH */
-/* Names to predefine in the preprocessor for this target machine.
- ??? It would be nice to not include any subtarget specific values here,
- however there's no way to portably provide subtarget values to
- CPP_PREFINES. Also, -D values in CPP_SUBTARGET_SPEC don't get turned into
- foo, __foo and __foo__. */
-
-#define CPP_PREDEFINES "-Dsparc -Dsun -Dunix -Asystem(unix) -Asystem(bsd)"
-
/* Define macros to distinguish architectures. */
/* Common CPP definitions used by CPP_SPEC amongst the various targets
for handling -mcpu=xxx switches. */
#define CPP_CPU_SPEC "\
+%{msoft-float:-D_SOFT_FLOAT} \
%{mcypress:} \
%{msparclite:-D__sparclite__} \
%{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
%{mcpu=sparclite86x:-D__sparclite86x__} \
%{mcpu=v9:-D__sparc_v9__} \
%{mcpu=ultrasparc:-D__sparc_v9__} \
+%{mcpu=ultrasparc3:-D__sparc_v9__} \
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
"
#ifdef SPARC_BI_ARCH
#define CPP_ARCH32_SPEC "-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \
--D__GCC_NEW_VARARGS__ -Acpu(sparc) -Amachine(sparc)"
+-D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
#define CPP_ARCH64_SPEC "-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \
--D__arch64__ -Acpu(sparc64) -Amachine(sparc64)"
+-D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
#else
-#define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu(sparc) -Amachine(sparc)"
-#define CPP_ARCH64_SPEC "-D__arch64__ -Acpu(sparc64) -Amachine(sparc64)"
+#define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
+#define CPP_ARCH64_SPEC "-D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
#endif
%{mv8plus:-Av8plus} \
%{mcpu=v9:-Av9} \
%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
+%{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
"
%{!m32:%{!m64:%(asm_arch_default)}} \
"
+#ifdef HAVE_AS_RELAX_OPTION
+#define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
+#else
+#define ASM_RELAX_SPEC ""
+#endif
+
/* Special flags to the Sun-4 assembler when using pipe for input. */
#define ASM_SPEC "\
%| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \
-%(asm_cpu) \
-"
-
-#define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}"
-
-/* Provide required defaults for linker -e and -d switches. */
-
-#define LINK_SPEC \
- "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \
- %{assert*} %{shared:%{!mimpure-text:-assert pure-text}}"
+%(asm_cpu) %(asm_relax)"
/* This macro defines names of additional specifications to put in the specs
that can be used in various specifications like CC1_SPEC. Its definition
{ "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
{ "asm_arch32", ASM_ARCH32_SPEC }, \
{ "asm_arch64", ASM_ARCH64_SPEC }, \
+ { "asm_relax", ASM_RELAX_SPEC }, \
{ "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
{ "asm_arch", ASM_ARCH_SPEC }, \
SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS
+
+/* Because libgcc can generate references back to libc (via .umul etc.) we have
+ to list libc again after the second libgcc. */
+#define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L"
+
\f
#ifdef SPARC_BI_ARCH
#define NO_BUILTIN_PTRDIFF_TYPE
/* ??? This should be 32 bits for v9 but what can we do? */
#define WCHAR_TYPE "short unsigned int"
#define WCHAR_TYPE_SIZE 16
-#define MAX_WCHAR_TYPE_SIZE 16
/* Show we can debug even without a frame pointer. */
#define CAN_DEBUG_WITHOUT_FP
-/* To make profiling work with -f{pic,PIC}, we need to emit the profiling
- code into the rtl. Also, if we are profiling, we cannot eliminate
- the frame pointer (because the return address will get smashed). */
-
-#define OVERRIDE_OPTIONS \
- do { \
- if (profile_flag || profile_block_flag || profile_arc_flag) \
- { \
- if (flag_pic) \
- { \
- const char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC";\
- warning ("%s and profiling conflict: disabling %s", \
- pic_string, pic_string); \
- flag_pic = 0; \
- } \
- flag_omit_frame_pointer = 0; \
- } \
- sparc_override_options (); \
- SUBTARGET_OVERRIDE_OPTIONS; \
- } while (0)
-
-/* This is meant to be redefined in the host dependent files. */
-#define SUBTARGET_OVERRIDE_OPTIONS
-
-/* These compiler options take an argument. We ignore -target for now. */
-
-#define WORD_SWITCH_TAKES_ARG(STR) \
- (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \
- || !strcmp (STR, "target") || !strcmp (STR, "assert"))
-
-/* Print subsidiary information on the compiler version in use. */
-
-#define TARGET_VERSION fprintf (stderr, " (sparc)");
+#define OVERRIDE_OPTIONS sparc_override_options ()
/* Generate DBX debugging information. */
#define MASK_FPU 1
#define TARGET_FPU (target_flags & MASK_FPU)
-/* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
- use fast return insns, but lose some generality. */
-#define MASK_EPILOGUE 2
-#define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)
-
/* Nonzero if we should assume that double pointers might be unaligned.
This can happen when linking gcc compiled code with other compilers,
because the ABI only guarantees 4 byte alignment. */
/* 0x2000, 0x4000 are unused */
-/* Nonzero if pointers are 64 bits.
- At the moment it must follow architecture size flag. */
+/* Nonzero if pointers are 64 bits. */
#define MASK_PTR64 0x8000
#define TARGET_PTR64 (target_flags & MASK_PTR64)
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
- { {"fpu", MASK_FPU | MASK_FPU_SET, "Use hardware fp" }, \
- {"no-fpu", -MASK_FPU, "Do not use hardware fp" }, \
+ { {"fpu", MASK_FPU | MASK_FPU_SET, \
+ N_("Use hardware fp") }, \
+ {"no-fpu", -MASK_FPU, \
+ N_("Do not use hardware fp") }, \
{"no-fpu", MASK_FPU_SET, NULL, }, \
- {"hard-float", MASK_FPU | MASK_FPU_SET, "Use hardware fp" }, \
- {"soft-float", -MASK_FPU, "Do not use hardware fp" }, \
- {"soft-float", MASK_FPU_SET, NULL }, \
- {"epilogue", MASK_EPILOGUE, "Use FUNCTION_EPILOGUE" }, \
- {"no-epilogue", -MASK_EPILOGUE, "Do not use FUNCTION_EPILOGUE" }, \
- {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, "Assume possible double misalignment" },\
- {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, "Assume all doubles are aligned" }, \
- {"impure-text", MASK_IMPURE_TEXT, "Pass -assert pure-text to linker" }, \
- {"no-impure-text", -MASK_IMPURE_TEXT, "Do not pass -assert pure-text to linker" }, \
- {"flat", MASK_FLAT, "Use flat register window model" }, \
- {"no-flat", -MASK_FLAT, "Do not use flat register window model" }, \
- {"app-regs", MASK_APP_REGS, "Use ABI reserved registers" }, \
- {"no-app-regs", -MASK_APP_REGS, "Do not use ABI reserved registers" }, \
- {"hard-quad-float", MASK_HARD_QUAD, "Use hardware quad fp instructions" }, \
- {"soft-quad-float", -MASK_HARD_QUAD, "Do not use hardware quad fp instructions" }, \
- {"v8plus", MASK_V8PLUS, "Compile for v8plus ABI" }, \
- {"no-v8plus", -MASK_V8PLUS, "Do not compile for v8plus ABI" }, \
- {"vis", MASK_VIS, "Utilize Visual Instruction Set" }, \
- {"no-vis", -MASK_VIS, "Do not utilize Visual Instruction Set" }, \
+ {"hard-float", MASK_FPU | MASK_FPU_SET, \
+ N_("Use hardware fp") }, \
+ {"soft-float", -MASK_FPU, \
+ N_("Do not use hardware fp") }, \
+ {"soft-float", MASK_FPU_SET, NULL }, \
+ {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
+ N_("Assume possible double misalignment") }, \
+ {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
+ N_("Assume all doubles are aligned") }, \
+ {"impure-text", MASK_IMPURE_TEXT, \
+ N_("Pass -assert pure-text to linker") }, \
+ {"no-impure-text", -MASK_IMPURE_TEXT, \
+ N_("Do not pass -assert pure-text to linker") }, \
+ {"flat", MASK_FLAT, \
+ N_("Use flat register window model") }, \
+ {"no-flat", -MASK_FLAT, \
+ N_("Do not use flat register window model") }, \
+ {"app-regs", MASK_APP_REGS, \
+ N_("Use ABI reserved registers") }, \
+ {"no-app-regs", -MASK_APP_REGS, \
+ N_("Do not use ABI reserved registers") }, \
+ {"hard-quad-float", MASK_HARD_QUAD, \
+ N_("Use hardware quad fp instructions") }, \
+ {"soft-quad-float", -MASK_HARD_QUAD, \
+ N_("Do not use hardware quad fp instructions") }, \
+ {"v8plus", MASK_V8PLUS, \
+ N_("Compile for v8plus ABI") }, \
+ {"no-v8plus", -MASK_V8PLUS, \
+ N_("Do not compile for v8plus ABI") }, \
+ {"vis", MASK_VIS, \
+ N_("Utilize Visual Instruction Set") }, \
+ {"no-vis", -MASK_VIS, \
+ N_("Do not utilize Visual Instruction Set") }, \
/* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \
- {"cypress", 0, "Optimize for Cypress processors" }, \
- {"sparclite", 0, "Optimize for SparcLite processors" }, \
- {"f930", 0, "Optimize for F930 processors" }, \
- {"f934", 0, "Optimize for F934 processors" }, \
- {"v8", 0, "Use V8 Sparc ISA" }, \
- {"supersparc", 0, "Optimize for SuperSparc processors" }, \
- /* End of deprecated options. */ \
- {"ptr64", MASK_PTR64, "Pointers are 64-bit" }, \
- {"ptr32", -MASK_PTR64, "Pointers are 32-bit" }, \
- {"32", -MASK_64BIT, "Use 32-bit ABI" }, \
- {"64", MASK_64BIT, "Use 64-bit ABI" }, \
- {"stack-bias", MASK_STACK_BIAS, "Use stack bias" }, \
- {"no-stack-bias", -MASK_STACK_BIAS, "Do not use stack bias" }, \
- {"faster-structs", MASK_FASTER_STRUCTS, "Use structs on stronger alignment for double-word copies" }, \
- {"no-faster-structs", -MASK_FASTER_STRUCTS, "Do not use structs on stronger alignment for double-word copies" }, \
+ {"cypress", 0, \
+ N_("Optimize for Cypress processors") }, \
+ {"sparclite", 0, \
+ N_("Optimize for SparcLite processors") }, \
+ {"f930", 0, \
+ N_("Optimize for F930 processors") }, \
+ {"f934", 0, \
+ N_("Optimize for F934 processors") }, \
+ {"v8", 0, \
+ N_("Use V8 Sparc ISA") }, \
+ {"supersparc", 0, \
+ N_("Optimize for SuperSparc processors") }, \
+ /* End of deprecated options. */ \
+ {"ptr64", MASK_PTR64, \
+ N_("Pointers are 64-bit") }, \
+ {"ptr32", -MASK_PTR64, \
+ N_("Pointers are 32-bit") }, \
+ {"32", -MASK_64BIT, \
+ N_("Use 32-bit ABI") }, \
+ {"64", MASK_64BIT, \
+ N_("Use 64-bit ABI") }, \
+ {"stack-bias", MASK_STACK_BIAS, \
+ N_("Use stack bias") }, \
+ {"no-stack-bias", -MASK_STACK_BIAS, \
+ N_("Do not use stack bias") }, \
+ {"faster-structs", MASK_FASTER_STRUCTS, \
+ N_("Use structs on stronger alignment for double-word copies") }, \
+ {"no-faster-structs", -MASK_FASTER_STRUCTS, \
+ N_("Do not use structs on stronger alignment for double-word copies") }, \
+ {"relax", 0, \
+ N_("Optimize tail call instructions in assembler and linker") }, \
+ {"no-relax", 0, \
+ N_("Do not optimize tail call instructions in assembler or linker") }, \
SUBTARGET_SWITCHES \
{ "", TARGET_DEFAULT, ""}}
/* MASK_APP_REGS must always be the default because that's what
FIXED_REGISTERS is set to and -ffixed- is processed before
CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
-#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
+#define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
/* This is meant to be redefined in target specific files. */
#define SUBTARGET_SWITCHES
PROCESSOR_SPARCLET,
PROCESSOR_TSC701,
PROCESSOR_V9,
- PROCESSOR_ULTRASPARC
+ PROCESSOR_ULTRASPARC,
+ PROCESSOR_ULTRASPARC3
};
/* This is set from -m{cpu,tune}=xxx. */
Every file includes us, but not every file includes insn-attr.h. */
#define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
-/* This macro is similar to `TARGET_SWITCHES' but defines names of
- command options that have values. Its definition is an
- initializer with a subgrouping for each command option.
-
- Each subgrouping contains a string constant, that defines the
- fixed part of the option name, and the address of a variable.
- The variable, type `char *', is set to the variable part of the
- given option if the fixed part matches. The actual option name
- is made by appending `-m' to the specified name.
-
- Here is an example which defines `-mshort-data-NUMBER'. If the
- given option is `-mshort-data-512', the variable `m88k_short_data'
- will be set to the string `"512"'.
-
- extern char *m88k_short_data;
- #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
-
#define TARGET_OPTIONS \
-{ \
- { "cpu=", &sparc_select[1].string, "Use features of and schedule code for given CPU" }, \
- { "tune=", &sparc_select[2].string, "Schedule code for given CPU" }, \
- { "cmodel=", &sparc_cmodel_string, "Use given Sparc code model" }, \
- SUBTARGET_OPTIONS \
+{ \
+ { "cpu=", &sparc_select[1].string, \
+ N_("Use features of and schedule code for given CPU") }, \
+ { "tune=", &sparc_select[2].string, \
+ N_("Schedule code for given CPU") }, \
+ { "cmodel=", &sparc_cmodel_string, \
+ N_("Use given Sparc code model") }, \
+ SUBTARGET_OPTIONS \
}
/* This is meant to be redefined in target specific files. */
struct sparc_cpu_select
{
const char *string;
- const char *name;
- int set_tune_p;
- int set_arch_p;
+ const char *const name;
+ const int set_tune_p;
+ const int set_arch_p;
};
extern struct sparc_cpu_select sparc_select[];
\f
/* target machine storage layout */
-/* Define for cross-compilation to a sparc target with no TFmode from a host
- with a different float format (e.g. VAX). */
-#define REAL_ARITHMETIC
-
/* Define this if most significant bit is lowest numbered
in instructions that operate on numbered bit-fields. */
#define BITS_BIG_ENDIAN 1
#define LIBGCC2_WORDS_BIG_ENDIAN 1
#endif
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
- Note that this is not necessarily the width of data type `int';
- if using 16-bit ints on a 68000, this would still be 32.
- But on a machine with 16-bit registers, this would be 16. */
-#define BITS_PER_WORD (TARGET_ARCH64 ? 64 : 32)
#define MAX_BITS_PER_WORD 64
/* Width of a word, in units (bytes). */
#define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
+#ifdef IN_LIBGCC2
+#define MIN_UNITS_PER_WORD UNITS_PER_WORD
+#else
#define MIN_UNITS_PER_WORD 4
+#endif
/* Now define the sizes of the C data types. */
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
-#if defined (SPARC_BI_ARCH)
+#ifdef SPARC_BI_ARCH
#define MAX_LONG_TYPE_SIZE 64
#endif
#if 0
/* ??? This does not work in SunOS 4.x, so it is not enabled here.
Instead, it is enabled in sol2.h, because it does work under Solaris. */
-/* Define for support of TFmode long double and REAL_ARITHMETIC.
+/* Define for support of TFmode long double.
Sparc ABI says that long double is 4 words. */
#define LONG_DOUBLE_TYPE_SIZE 128
#endif
See also the macro `Pmode' defined below. */
#define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
+/* If we have to extend pointers (only when TARGET_ARCH64 and not
+ TARGET_PTR64), we want to do it unsigned. This macro does nothing
+ if ptr_mode and Pmode are the same. */
+#define POINTERS_EXTEND_UNSIGNED 1
+
/* A macro to update MODE and UNSIGNEDP when an object whose type
is TYPE and which has the specified mode and signedness is to be
stored in a register. This macro is only called when TYPE is a
if (TARGET_ARCH64 \
&& GET_MODE_CLASS (MODE) == MODE_INT \
&& GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
-{ \
- (MODE) = DImode; \
-}
+ (MODE) = DImode;
/* Define this macro if the promotion described by PROMOTE_MODE
should also be done for outgoing function arguments. */
#define SUNOS4_SHARED_LIBRARIES 0
#endif
-/* This is defined differently for v9 in a cover file. */
-#define SELECT_SECTION(T,RELOC) \
-{ \
- if (TREE_CODE (T) == VAR_DECL) \
- { \
- if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
- && DECL_INITIAL (T) \
- && (DECL_INITIAL (T) == error_mark_node \
- || TREE_CONSTANT (DECL_INITIAL (T))) \
- && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
- && ! (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \
- text_section (); \
- else \
- data_section (); \
- } \
- else if (TREE_CODE (T) == CONSTRUCTOR) \
- { \
- if (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES)) \
- data_section (); \
- } \
- else if (TREE_CODE_CLASS (TREE_CODE (T)) == 'c') \
- { \
- if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
- || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN \
- || (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \
- data_section (); \
- else \
- text_section (); \
- } \
-}
/* Use text section for a constant
unless we need more alignment than that offers. */
/* This is defined differently for v9 in a cover file. */
-#define SELECT_RTX_SECTION(MODE, X) \
+#define SELECT_RTX_SECTION(MODE, X, ALIGN) \
{ \
if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
&& ! (flag_pic && (symbolic_operand ((X), (MODE)) || SUNOS4_SHARED_LIBRARIES))) \
accessible. We still account for them to simplify register computations
(eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
32+32+32+4 == 100.
- Register 100 is used as the integer condition code register. */
+ Register 100 is used as the integer condition code register.
+ Register 101 is used as the soft frame pointer register. */
-#define FIRST_PSEUDO_REGISTER 101
+#define FIRST_PSEUDO_REGISTER 102
#define SPARC_FIRST_FP_REG 32
/* Additional V9 fp regs. */
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
\
- 0, 0, 0, 0, 0}
+ 0, 0, 0, 0, 0, 1}
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, \
\
- 1, 1, 1, 1, 1}
+ 1, 1, 1, 1, 1, 1}
/* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
they won't be allocated. */
#define CONDITIONAL_REGISTER_USAGE \
do \
{ \
- if (flag_pic) \
+ if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
{ \
fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
/* Let the compiler believe the frame pointer is still \
%fp, but output it as %i7. */ \
fixed_regs[31] = 1; \
- reg_names[FRAME_POINTER_REGNUM] = "%i7"; \
+ reg_names[HARD_FRAME_POINTER_REGNUM] = "%i7"; \
/* Disable leaf functions */ \
- bzero (sparc_leaf_regs, FIRST_PSEUDO_REGISTER); \
- } \
- if (profile_block_flag) \
- { \
- /* %g1 and %g2 (sparc32) resp. %g4 (sparc64) must be \
- fixed, because BLOCK_PROFILER uses them. */ \
- fixed_regs[1] = 1; \
- fixed_regs[TARGET_ARCH64 ? 4 : 2] = 1; \
+ memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER); \
} \
} \
while (0)
#define HARD_REGNO_NREGS(REGNO, MODE) \
(TARGET_ARCH64 \
- ? ((REGNO) < 32 \
- ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
- : (GET_MODE_SIZE (MODE) + 3) / 4) \
+ ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
+ ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
+ : (GET_MODE_SIZE (MODE) + 3) / 4) \
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-/* A subreg in 64 bit mode will have the wrong offset for a floating point
- register. The least significant part is at offset 1, compared to 0 for
- integer registers. This only applies when FMODE is a larger mode.
- We also need to handle a special case of TF-->DF conversions. */
-#define ALTER_HARD_SUBREG(TMODE, WORD, FMODE, REGNO) \
- (TARGET_ARCH64 \
- && (REGNO) >= SPARC_FIRST_FP_REG \
- && (REGNO) <= SPARC_LAST_V9_FP_REG \
- && (TMODE) == SImode \
- && !((FMODE) == QImode || (FMODE) == HImode) \
- ? ((REGNO) + 1) \
- : ((TMODE) == DFmode && (FMODE) == TFmode) \
- ? ((REGNO) + ((WORD) * 2)) \
- : ((REGNO) + (WORD)))
+/* Due to the ARCH64 descrepancy above we must override this next
+ macro too. */
+#define REGMODE_NATURAL_SIZE(MODE) \
+ ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
See sparc.c for how we initialize this. */
-extern int *hard_regno_mode_classes;
+extern const int *hard_regno_mode_classes;
extern int sparc_mode_class[];
+
+/* ??? Because of the funny way we pass parameters we should allow certain
+ ??? types of float/complex values to be in integer registers during
+ ??? RTL generation. This only matters on arch32. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
/* Register to use for pushing function arguments. */
#define STACK_POINTER_REGNUM 14
+/* The stack bias (amount by which the hardware register is offset by). */
+#define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
+
/* Actual top-of-stack address is 92/176 greater than the contents of the
stack pointer register for !v9/v9. That is:
- !v9: 64 bytes for the in and local registers, 4 bytes for structure return
address, and 6*4 bytes for the 6 register parameters.
- v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
parameter regs. */
-#define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
-
-/* The stack bias (amount by which the hardware register is offset by). */
-#define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
-
-/* Is stack biased? */
-#define STACK_BIAS SPARC_STACK_BIAS
+#define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
/* Base register for access to local variables of the function. */
-#define FRAME_POINTER_REGNUM 30
-
-#if 0
-/* Register that is used for the return address for the flat model. */
-#define RETURN_ADDR_REGNUM 15
-#endif
+#define HARD_FRAME_POINTER_REGNUM 30
+
+/* The soft frame pointer does not have the stack bias applied. */
+#define FRAME_POINTER_REGNUM 101
+
+/* Given the stack bias, the stack pointer isn't actually aligned. */
+#define INIT_EXPANDERS \
+ do { \
+ if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \
+ { \
+ REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
+ REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
+ } \
+ } while (0)
/* Value should be nonzero if functions must have frame pointers.
Zero means the frame pointer need not be set up (and parms
Being a non-leaf function does not mean a frame pointer is needed in the
flat window model. However, the debugger won't be able to backtrace through
us with out it. */
-#define FRAME_POINTER_REQUIRED \
- (TARGET_FLAT ? (current_function_calls_alloca || current_function_varargs \
- || !leaf_function_p ()) \
+#define FRAME_POINTER_REQUIRED \
+ (TARGET_FLAT \
+ ? (current_function_calls_alloca \
+ || current_function_varargs \
+ || !leaf_function_p ()) \
: ! (leaf_function_p () && only_leaf_regs_used ()))
-/* C statement to store the difference between the frame pointer
- and the stack pointer values immediately after the function prologue.
-
- Note, we always pretend that this is a leaf function because if
- it's not, there's no point in trying to eliminate the
- frame pointer. If it is a leaf function, we guessed right! */
-#define INITIAL_FRAME_POINTER_OFFSET(VAR) \
- ((VAR) = (TARGET_FLAT ? sparc_flat_compute_frame_size (get_frame_size ()) \
- : compute_frame_size (get_frame_size (), 1)))
-
/* Base register for access to arguments of the function. */
#define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
/* Register which holds offset table for position-independent
data references. */
-#define PIC_OFFSET_TABLE_REGNUM 23
-
-#define FINALIZE_PIC finalize_pic ()
+#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
/* Pick a default value we can notice from override_options:
!v9: Default is on.
|| TYPE_MODE (TYPE) == TFmode \
|| TYPE_MODE (TYPE) == TCmode) \
: (TYPE_MODE (TYPE) == BLKmode \
- && int_size_in_bytes (TYPE) > 32))
+ && (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 32))
/* Functions which return large structures get the address
to place the wanted value at offset 64 from the frame.
#define N_REG_CLASSES (int) LIM_REG_CLASSES
-/* Give names of register classes as strings for dump file. */
+/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
{ "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. */
-#define REG_CLASS_CONTENTS \
- {{0, 0, 0, 0}, {0, 0, 0, 0xf}, {0xffff, 0, 0, 0}, \
- {-1, 0, 0, 0}, {0, -1, 0, 0}, {0, -1, -1, 0}, \
- {-1, -1, 0, 0}, {-1, -1, -1, 0}, {-1, -1, -1, 0x1f}}
+#define REG_CLASS_CONTENTS \
+ {{0, 0, 0, 0}, /* NO_REGS */ \
+ {0, 0, 0, 0xf}, /* FPCC_REGS */ \
+ {0xffff, 0, 0, 0}, /* I64_REGS */ \
+ {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
+ {0, -1, 0, 0}, /* FP_REGS */ \
+ {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
+ {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
+ {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
+ {-1, -1, -1, 0x3f}} /* ALL_REGS */
/* The same information, inverted:
Return the class number of the smallest class containing
reg number REGNO. This could be a conditional expression
or could index an array. */
-extern enum reg_class sparc_regno_reg_class[];
+extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
#define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
32, 33, /* %f0,%f1 */ \
96, 97, 98, 99, 100, /* %fcc0-3, %icc */ \
- 1, 4, 5, 6, 7, 0, 14, 30}
+ 1, 4, 5, 6, 7, 0, 14, 30, 101}
/* This is the order in which to allocate registers for
leaf functions. If all registers can fit in the "gi" registers,
88, 89, 90, 91, 92, 93, 94, 95, \
32, 33, \
96, 97, 98, 99, 100, \
- 0, 14, 30, 31}
+ 0, 14, 30, 31, 101}
#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
extern char sparc_leaf_regs[];
#define LEAF_REGISTERS sparc_leaf_regs
-extern char leaf_reg_remap[];
+extern const char leaf_reg_remap[];
#define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
/* The class value for index registers, and the one for base regs. */
.md file for v8 and v9.
'd' and 'b' are used for single and double precision VIS operations,
if TARGET_VIS.
- 'h' is used for V8+ 64 bit global and out registers. */
+ 'h' is used for V8+ 64 bit global and out registers. */
#define REG_CLASS_FROM_LETTER(C) \
(TARGET_V9 \
`J' is used for the range which is just zero (since that is R0).
`K' is used for constants which can be loaded with a single sethi insn.
`L' is used for the range of constants supported by the movcc insns.
- `M' is used for the range of constants supported by the movrcc insns. */
+ `M' is used for the range of constants supported by the movrcc insns.
+ `N' is like K, but for constants wider than 32 bits. */
#define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
#define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
SMALL_INT is used throughout the port so we continue to use it. */
#define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
/* 13 bit immediate, considering only the low 32 bits */
-#define SMALL_INT32(X) (SPARC_SIMM13_P ((int)INTVAL (X) & 0xffffffff))
+#define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \
+ (INTVAL (X), SImode)))
#define SPARC_SETHI_P(X) \
-(((unsigned HOST_WIDE_INT) (X) & \
- (TARGET_ARCH64 ? ~(unsigned HOST_WIDE_INT) 0xfffffc00 : 0x3ff)) == 0)
+ (((unsigned HOST_WIDE_INT) (X) \
+ & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
+#define SPARC_SETHI32_P(X) \
+ (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
: (C) == 'J' ? (VALUE) == 0 \
- : (C) == 'K' ? SPARC_SETHI_P (VALUE) \
+ : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
: (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
: (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
+ : (C) == 'N' ? SPARC_SETHI_P (VALUE) \
: 0)
/* Similar, but for floating constants, and defining letters G and H.
/* - We can't load constants into FP registers.
- We can't load FP constants into integer registers when soft-float,
because there is no soft-float pattern with a r/F constraint.
+ - We can't load FP constants into integer registers for TFmode unless
+ it is 0.0L, because there is no movtf pattern with a r/F constraint.
- Try and reload integer constants (symbolic or otherwise) back into
registers directly, rather than having them dumped to memory. */
(CONSTANT_P (X) \
? ((FP_REG_CLASS_P (CLASS) \
|| (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
- && ! TARGET_FPU)) \
+ && ! TARGET_FPU) \
+ || (GET_MODE (X) == TFmode \
+ && ! fp_zero_operand (X, TFmode))) \
? NO_REGS \
: (!FP_REG_CLASS_P (CLASS) \
&& GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
We need a temporary when loading/storing a HImode/QImode value
between memory and the FPU registers. This can happen when combine puts
- a paradoxical subreg in a float/fix conversion insn. */
+ a paradoxical subreg in a float/fix conversion insn.
+
+ We need a temporary when loading/storing a DFmode value between
+ unaligned memory and the upper FPU registers. */
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
((FP_REG_CLASS_P (CLASS) \
|| ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
&& true_regnum (IN) == -1))) \
? GENERAL_REGS \
- : (((TARGET_CM_MEDANY \
- && symbolic_operand ((IN), (MODE))) \
- || (TARGET_CM_EMBMEDANY \
- && text_segment_operand ((IN), (MODE)))) \
- && !flag_pic) \
- ? GENERAL_REGS \
- : NO_REGS)
+ : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
+ && GET_CODE (IN) == MEM && TARGET_ARCH32 \
+ && ! mem_min_alignment ((IN), 8)) \
+ ? FP_REGS \
+ : (((TARGET_CM_MEDANY \
+ && symbolic_operand ((IN), (MODE))) \
+ || (TARGET_CM_EMBMEDANY \
+ && text_segment_operand ((IN), (MODE)))) \
+ && !flag_pic) \
+ ? GENERAL_REGS \
+ : NO_REGS)
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
- ((FP_REG_CLASS_P (CLASS) \
+ ((FP_REG_CLASS_P (CLASS) \
&& ((MODE) == HImode || (MODE) == QImode) \
&& (GET_CODE (IN) == MEM \
|| ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
&& true_regnum (IN) == -1))) \
- ? GENERAL_REGS \
- : (((TARGET_CM_MEDANY \
- && symbolic_operand ((IN), (MODE))) \
- || (TARGET_CM_EMBMEDANY \
- && text_segment_operand ((IN), (MODE)))) \
- && !flag_pic) \
- ? GENERAL_REGS \
- : NO_REGS)
+ ? GENERAL_REGS \
+ : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
+ && GET_CODE (IN) == MEM && TARGET_ARCH32 \
+ && ! mem_min_alignment ((IN), 8)) \
+ ? FP_REGS \
+ : (((TARGET_CM_MEDANY \
+ && symbolic_operand ((IN), (MODE))) \
+ || (TARGET_CM_EMBMEDANY \
+ && text_segment_operand ((IN), (MODE)))) \
+ && !flag_pic) \
+ ? GENERAL_REGS \
+ : NO_REGS)
/* On SPARC it is not possible to directly move data between
GENERAL_REGS and FP_REGS. */
of the first local allocated. */
/* This allows space for one TFmode floating point value. */
#define STARTING_FRAME_OFFSET \
- (TARGET_ARCH64 ? (SPARC_STACK_BIAS - 16) \
+ (TARGET_ARCH64 ? -16 \
: (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
/* If we generate an insn to push BYTES bytes,
even if this function isn't going to use it.
v9: This is 128 for the ins and locals. */
#define FIRST_PARM_OFFSET(FNDECL) \
- (TARGET_ARCH64 ? (SPARC_STACK_BIAS + 16 * UNITS_PER_WORD) \
- : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD))
+ (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
/* Offset from the argument pointer register value to the CFA.
This is different from FIRST_PARM_OFFSET because the register window
comes between the CFA and the arguments. */
-
-#define ARG_POINTER_CFA_OFFSET(FNDECL) SPARC_STACK_BIAS
+#define ARG_POINTER_CFA_OFFSET(FNDECL) 0
/* When a parameter is passed in a register, stack space is still
allocated for it.
!v9: All 6 possible integer registers have backing store allocated.
- v9: Only space for the arguments passed is allocated. */
+ v9: Only space for the arguments passed is allocated. */
/* ??? Ideally, we'd use zero here (as the minimum), but zero has special
meaning to the backend. Further, we need to be able to detect if a
varargs/unprototyped function is called, as they may want to spill more
all 6 slots even for v9. */
#define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
+/* Definitions for register elimination. */
+/* ??? In TARGET_FLAT mode we needn't have a hard frame pointer. */
+
+#define ELIMINABLE_REGS \
+ {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
+ { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
+
+/* The way this is structured, we can't eliminate SFP in favor of SP
+ if the frame pointer is required: we want to use the SFP->HFP elimination
+ in that case. But the test in update_eliminables doesn't know we are
+ assuming below that we only do the former elimination. */
+#define CAN_ELIMINATE(FROM, TO) \
+ ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED)
+
+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
+ do { \
+ (OFFSET) = 0; \
+ if ((TO) == STACK_POINTER_REGNUM) \
+ { \
+ /* Note, we always pretend that this is a leaf function \
+ because if it's not, there's no point in trying to \
+ eliminate the frame pointer. If it is a leaf \
+ function, we guessed right! */ \
+ if (TARGET_FLAT) \
+ (OFFSET) = \
+ sparc_flat_compute_frame_size (get_frame_size ()); \
+ else \
+ (OFFSET) = compute_frame_size (get_frame_size (), 1); \
+ } \
+ (OFFSET) += SPARC_STACK_BIAS; \
+ } while (0)
+
/* Keep the stack pointer constant throughout the function.
This is both an optimization and a necessity: longjmp
doesn't behave itself when the stack pointer moves within
the function! */
-#define ACCUMULATE_OUTGOING_ARGS
+#define ACCUMULATE_OUTGOING_ARGS 1
/* Value is the number of bytes of arguments automatically
popped when returning from a subroutine call.
? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
: 8)
-/* ??? FIXME -- seems wrong for v9 structure passing... */
+/* ??? FIXME -- seems wrong for v9 structure passing... */
#define BASE_INCOMING_ARG_REG(MODE) \
(TARGET_ARCH64 \
? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
#define OUTGOING_REGNO(IN) \
((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
+/* Define this macro if the target machine has register windows. This
+ C expression returns true if the register is call-saved but is in the
+ register window. */
+
+#define LOCAL_REGNO(REGNO) \
+ (TARGET_FLAT ? 0 : (REGNO) >= 16 && (REGNO) <= 31)
+
/* Define how to find the value returned by a function.
VALTYPE is the data type of the value (as a tree).
If the precise function being called is known, FUNC is its FUNCTION_DECL;
#define ASM_DECLARE_RESULT(FILE, RESULT) \
fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
-/* Output the label for a function definition. */
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
-do { \
- ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
- ASM_OUTPUT_LABEL (FILE, NAME); \
-} while (0)
-
/* Output the special assembly code needed to tell the assembler some
register is used as global register variable.
} while (0)
#endif
-/* This macro generates the assembly code for function entry.
- FILE is a stdio stream to output the code to.
- SIZE is an int: how many units of temporary storage to allocate.
- Refer to the array `regs_ever_live' to determine which registers
- to save; `regs_ever_live[I]' is nonzero if register number I
- is ever used in the function. This macro is responsible for
- knowing which registers should not be saved even if used. */
-
-/* On SPARC, move-double insns between fpu and cpu need an 8-byte block
- of memory. If any fpu reg is used in the function, we allocate
- such a block here, at the bottom of the frame, just in case it's needed.
-
- If this function is a leaf procedure, then we may choose not
- to do a "save" insn. The decision about whether or not
- to do this is made in regclass.c. */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE) \
- (TARGET_FLAT ? sparc_flat_output_function_prologue (FILE, (int)SIZE) \
- : output_function_prologue (FILE, (int)SIZE, \
- current_function_uses_only_leaf_regs))
\f
-/* Output assembler code to FILE to increment profiler label # LABELNO
- for profiling a function entry. */
+/* Emit rtl for profiling. */
+#define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- sparc_function_profiler(FILE, LABELNO)
+/* All the work done in PROFILE_HOOK, but still required. */
+#define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
/* Set the name of the mcount function for the system. */
-
#define MCOUNT_FUNCTION "*mcount"
-
-/* The following macro shall output assembler code to FILE
- to initialize basic-block profiling. */
-
-#define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
- sparc_function_block_profiler(FILE, BLOCK_OR_LABEL)
-
-/* The following macro shall output assembler code to FILE
- to increment a counter associated with basic block number BLOCKNO. */
-
-#define BLOCK_PROFILER(FILE, BLOCKNO) \
- sparc_block_profiler (FILE, BLOCKNO)
-
-/* The following macro shall output assembler code to FILE
- to indicate a return from function during basic-block profiling. */
-
-#define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
- sparc_function_block_profiler_exit(FILE)
-
-#ifdef IN_LIBGCC2
-
-/* The function `__bb_trace_func' is called in every basic block
- and is not allowed to change the machine state. Saving (restoring)
- the state can either be done in the BLOCK_PROFILER macro,
- before calling function (rsp. after returning from function)
- `__bb_trace_func', or it can be done inside the function by
- defining the macros:
-
- MACHINE_STATE_SAVE(ID)
- MACHINE_STATE_RESTORE(ID)
-
- In the latter case care must be taken, that the prologue code
- of function `__bb_trace_func' does not already change the
- state prior to saving it with MACHINE_STATE_SAVE.
-
- The parameter `ID' is a string identifying a unique macro use.
-
- On sparc it is sufficient to save the psw register to memory.
- Unfortunately the psw register can be read in supervisor mode only,
- so we read only the condition codes by using branch instructions
- and hope that this is enough.
-
- On V9, life is much sweater: there is a user accessible %ccr
- register, but we use it for 64bit libraries only. */
-
-#if TARGET_ARCH32
-
-#define MACHINE_STATE_SAVE(ID) \
- int ms_flags, ms_saveret; \
- asm volatile( \
- "mov %%g2,%1\n\
- mov %%g0,%0\n\
- be,a LFLGNZ"ID"\n\
- or %0,4,%0\n\
-LFLGNZ"ID":\n\
- bcs,a LFLGNC"ID"\n\
- or %0,1,%0\n\
-LFLGNC"ID":\n\
- bvs,a LFLGNV"ID"\n\
- or %0,2,%0\n\
-LFLGNV"ID":\n\
- bneg,a LFLGNN"ID"\n\
- or %0,8,%0\n\
-LFLGNN"ID":" \
- : "=r"(ms_flags), "=r"(ms_saveret));
-
-#else
-
-#define MACHINE_STATE_SAVE(ID) \
- unsigned long ms_flags, ms_saveret; \
- asm volatile( \
- "mov %%g4,%1\n\
- rd %%ccr,%0" \
- : "=r"(ms_flags), "=r"(ms_saveret));
-
-#endif
-
-/* On sparc MACHINE_STATE_RESTORE restores the psw register from memory.
- The psw register can be written in supervisor mode only,
- which is true even for simple condition codes.
- We use some combination of instructions to produce the
- proper condition codes, but some flag combinations can not
- be generated in this way. If this happens an unimplemented
- instruction will be executed to abort the program. */
-
-#if TARGET_ARCH32
-
-#define MACHINE_STATE_RESTORE(ID) \
-{ extern char flgtab[] __asm__("LFLGTAB"ID); \
- int scratch; \
- asm volatile ( \
- "jmpl %2+%1,%%g0\n\
- ! Do part of VC in the delay slot here, as it needs 3 insns.\n\
- addcc 2,%3,%%g0\n\
-LFLGTAB" ID ":\n\
- ! 0\n\
- ba LFLGRET"ID"\n\
- orcc 1,%%g0,%%g0\n\
- ! C\n\
- ba LFLGRET"ID"\n\
- addcc 2,%3,%%g0\n\
- ! V\n\
- unimp\n\
- nop\n\
- ! VC\n\
- ba LFLGRET"ID"\n\
- addxcc %4,%4,%0\n\
- ! Z\n\
- ba LFLGRET"ID"\n\
- subcc %%g0,%%g0,%%g0\n\
- ! ZC\n\
- ba LFLGRET"ID"\n\
- addcc 1,%3,%0\n\
- ! ZVC\n\
- ba LFLGRET"ID"\n\
- addcc %4,%4,%0\n\
- ! N\n\
- ba LFLGRET"ID"\n\
- orcc %%g0,-1,%%g0\n\
- ! NC\n\
- ba LFLGRET"ID"\n\
- addcc %%g0,%3,%%g0\n\
- ! NV\n\
- unimp\n\
- nop\n\
- ! NVC\n\
- unimp\n\
- nop\n\
- ! NZ\n\
- unimp\n\
- nop\n\
- ! NZC\n\
- unimp\n\
- nop\n\
- ! NZV\n\
- unimp\n\
- nop\n\
- ! NZVC\n\
- unimp\n\
- nop\n\
-LFLGRET"ID":\n\
- mov %5,%%g2" \
- : "=r"(scratch) \
- : "r"(ms_flags*8), "r"(flgtab), "r"(-1), \
- "r"(0x80000000), "r"(ms_saveret) \
- : "cc", "g2"); }
-
-#else
-
-#define MACHINE_STATE_RESTORE(ID) \
- asm volatile ( \
- "wr %0,0,%%ccr\n\
- mov %1,%%g4" \
- : : "r"(ms_flags), "r"(ms_saveret) \
- : "cc", "g4");
-
-#endif
-
-#endif /* IN_LIBGCC2 */
\f
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
the stack pointer does not matter. The value is tested only in
(get_frame_size () != 0 \
|| current_function_calls_alloca || current_function_outgoing_args_size)
-/* This macro generates the assembly code for function exit,
- on machines that need it. If FUNCTION_EPILOGUE is not defined
- then individual return instructions are generated for each
- return statement. Args are same as for FUNCTION_PROLOGUE.
-
- The function epilogue should not depend on the current stack pointer!
- It should use the frame pointer only. This is mandatory because
- of alloca; we also take advantage of it to omit stack adjustments
- before returning. */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) \
- (TARGET_FLAT ? sparc_flat_output_function_epilogue (FILE, (int)SIZE) \
- : output_function_epilogue (FILE, (int)SIZE, \
- current_function_uses_only_leaf_regs))
-
#define DELAY_SLOTS_FOR_EPILOGUE \
(TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1)
#define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
#define STRICT_ARGUMENT_NAMING TARGET_V9
/* We do not allow sibling calls if -mflat, nor
- we do not allow indirect calls to be optimized into sibling calls. */
-#define FUNCTION_OK_FOR_SIBCALL(DECL) (DECL && ! TARGET_FLAT)
+ we do not allow indirect calls to be optimized into sibling calls.
+
+ Also, on sparc 32-bit we cannot emit a sibling call when the
+ current function returns a structure. This is because the "unimp
+ after call" convention would cause the callee to return to the
+ wrong place. The generic code already disallows cases where the
+ function being called returns a structure.
+
+ It may seem strange how this last case could occur. Usually there
+ is code after the call which jumps to epilogue code which dumps the
+ return value into the struct return area. That ought to invalidate
+ the sibling call right? Well, in the c++ case we can end up passing
+ the pointer to the struct return area to a constructor (which returns
+ void) and then nothing else happens. Such a sibling call would look
+ valid without the added check here. */
+#define FUNCTION_OK_FOR_SIBCALL(DECL) \
+ (DECL \
+ && ! TARGET_FLAT \
+ && (TARGET_ARCH64 || ! current_function_returns_struct))
/* Generate RTL to flush the register windows so as to make arbitrary frames
available. */
#define RETURN_ADDR_IN_PREVIOUS_FRAME
/* This is the offset of the return address to the true next instruction to be
- executed for the current function. */
+ executed for the current function. */
#define RETURN_ADDR_OFFSET \
(8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
? gen_rtx_REG (Pmode, 31) \
: gen_rtx_MEM (Pmode, \
memory_address (Pmode, plus_constant (frame, \
- 15 * UNITS_PER_WORD))))
+ 15 * UNITS_PER_WORD \
+ + SPARC_STACK_BIAS))))
/* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
+12, but always using +8 is close enough for frame unwind purposes.
bias if present. */
#define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
-#define DOESNT_NEED_UNWINDER (! TARGET_FLAT)
+/* Describe how we implement __builtin_eh_return. */
+#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
+#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
+#define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
+
+/* Select a format to encode pointers in exception handling data. CODE
+ is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
+ true if the symbol may be affected by dynamic relocations.
+
+ If assembler and linker properly support .uaword %r_disp32(foo),
+ then use PC relative 32-bit relocations instead of absolute relocs
+ for shared libraries. On sparc64, use pc relative 32-bit relocs even
+ for binaries, to save memory.
+
+ binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
+ symbol %r_disp32() is against was not local, but .hidden. In that
+ case, we have to use DW_EH_PE_absptr for pic personality. */
+#ifdef HAVE_AS_SPARC_UA_PCREL
+#ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
+#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
+ (flag_pic \
+ ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
+ : ((TARGET_ARCH64 && ! GLOBAL) \
+ ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
+ : DW_EH_PE_absptr))
+#else
+#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
+ (flag_pic \
+ ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
+ : ((TARGET_ARCH64 && ! GLOBAL) \
+ ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
+ : DW_EH_PE_absptr))
+#endif
+
+/* Emit a PC-relative relocation. */
+#define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
+ do { \
+ fputs (integer_asm_op (SIZE, FALSE), FILE); \
+ fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
+ assemble_name (FILE, LABEL); \
+ fputc (')', FILE); \
+ } while (0)
+#endif
\f
/* Addressing modes, and classification of registers for them. */
has been allocated, which happens in local-alloc.c. */
#define REGNO_OK_FOR_INDEX_P(REGNO) \
-((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32)
-#define REGNO_OK_FOR_BASE_P(REGNO) \
-((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32)
+((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
+ || (REGNO) == FRAME_POINTER_REGNUM \
+ || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
+
+#define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
+
#define REGNO_OK_FOR_FP_P(REGNO) \
(((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
|| ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
be at least 8 bytes.
`U' handles all pseudo registers or a hard even numbered
- integer register, needed for ldd/std instructions. */
+ integer register, needed for ldd/std instructions.
-#define EXTRA_CONSTRAINT_BASE(OP, C) \
- ((C) == 'Q' ? fp_sethi_p(OP) \
- : (C) == 'R' ? fp_mov_p(OP) \
- : (C) == 'S' ? fp_high_losum_p(OP) \
- : 0)
+ 'W' handles the memory operand when moving operands in/out
+ of 'e' constraint floating point registers. */
#ifndef REG_OK_STRICT
/* Nonzero if X is a hard reg that can be used as an index
or if it is a pseudo reg. */
#define REG_OK_FOR_INDEX_P(X) \
- (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
+ (REGNO (X) < 32 \
+ || REGNO (X) == FRAME_POINTER_REGNUM \
+ || REGNO (X) >= FIRST_PSEUDO_REGISTER)
+
/* Nonzero if X is a hard reg that can be used as a base reg
or if it is a pseudo reg. */
-#define REG_OK_FOR_BASE_P(X) \
- (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
+#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
-/* 'T', 'U' are for aligned memory loads which aren't needed for v9. */
+/* 'T', 'U' are for aligned memory loads which aren't needed for arch64.
+ 'W' is like 'T' but is assumed true on arch64.
-#define EXTRA_CONSTRAINT(OP, C) \
- (EXTRA_CONSTRAINT_BASE(OP, C) \
- || ((! TARGET_ARCH64 && (C) == 'T') \
- ? (mem_min_alignment (OP, 8)) \
- : ((! TARGET_ARCH64 && (C) == 'U') \
- ? (register_ok_for_ldd (OP)) \
- : 0)))
+ Remember to accept pseudo-registers for memory constraints if reload is
+ in progress. */
+
+#define EXTRA_CONSTRAINT(OP, C) \
+ sparc_extra_constraint_check(OP, C, 0)
#else
/* Nonzero if X is a hard reg that can be used as a base reg. */
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-#define EXTRA_CONSTRAINT(OP, C) \
- (EXTRA_CONSTRAINT_BASE(OP, C) \
- || ((! TARGET_ARCH64 && (C) == 'T') \
- ? mem_min_alignment (OP, 8) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
- : ((! TARGET_ARCH64 && (C) == 'U') \
- ? (GET_CODE (OP) == REG \
- && (REGNO (OP) < FIRST_PSEUDO_REGISTER \
- || reg_renumber[REGNO (OP)] >= 0) \
- && register_ok_for_ldd (OP)) \
- : 0)))
+#define EXTRA_CONSTRAINT(OP, C) \
+ sparc_extra_constraint_check(OP, C, 1)
#endif
\f
&& REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
#define RTX_OK_FOR_OFFSET_P(X) \
- (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
+ (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
#define RTX_OK_FOR_OLO10_P(X) \
(GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
of a movtf pattern are both MEMs with \
REG+REG address, then only one of them \
gets converted to an offsetable \
- address. */ \
- && (MODE != TFmode \
- || (TARGET_FPU && TARGET_ARCH64 \
- && TARGET_V9 \
- && TARGET_HARD_QUAD))) \
+ address. */ \
+ && (MODE != TFmode \
+ || (TARGET_FPU && TARGET_ARCH64 \
+ && TARGET_V9 \
+ && TARGET_HARD_QUAD)) \
+ /* We prohibit REG + REG on ARCH32 if \
+ not optimizing for DFmode/DImode \
+ because then mem_min_alignment is \
+ likely to be zero after reload and the \
+ forced split would lack a matching \
+ splitter pattern. */ \
+ && (TARGET_ARCH64 || optimize \
+ || (MODE != DFmode \
+ && MODE != DImode))) \
|| RTX_OK_FOR_OFFSET_P (op1)) \
goto ADDR; \
} \
else if (RTX_OK_FOR_BASE_P (op1)) \
{ \
if ((RTX_OK_FOR_INDEX_P (op0) \
- /* See the previous comment. */ \
- && (MODE != TFmode \
+ /* See the previous comment. */ \
+ && (MODE != TFmode \
|| (TARGET_FPU && TARGET_ARCH64 \
&& TARGET_V9 \
- && TARGET_HARD_QUAD))) \
+ && TARGET_HARD_QUAD)) \
+ && (TARGET_ARCH64 || optimize \
+ || (MODE != DFmode \
+ && MODE != DImode))) \
|| RTX_OK_FOR_OFFSET_P (op0)) \
goto ADDR; \
} \
&& CONSTANT_P (op1) \
/* We can't allow TFmode, because an offset \
greater than or equal to the alignment (8) \
- may cause the LO_SUM to overflow if !v9. */\
+ may cause the LO_SUM to overflow if !v9. */\
&& (MODE != TFmode || TARGET_V9)) \
goto ADDR; \
} \
/* Decompose SImode constants into hi+lo_sum. We do have to \
rerecognize what we produce, so be careful. */ \
if (CONSTANT_P (X) \
- && (MODE != TFmode || TARGET_V9) \
+ && (MODE != TFmode || TARGET_ARCH64) \
&& GET_MODE (X) == SImode \
&& GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
&& ! (flag_pic \
&& (symbolic_operand (X, Pmode) \
- || pic_address_needs_scratch (X)))) \
+ || pic_address_needs_scratch (X))) \
+ && sparc_cmodel <= CM_MEDLOW) \
{ \
X = gen_rtx_LO_SUM (GET_MODE (X), \
gen_rtx_HIGH (GET_MODE (X), X), X); \
- push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
+ push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
OPNUM, TYPE); \
goto WIN; \
In the Embedded Medium/Anywhere code model, %g4 points to the data segment
so we must not add it to function addresses. */
-#define ENCODE_SECTION_INFO(DECL) \
- do { \
- if (TARGET_CM_EMBMEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
- SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
+#define ENCODE_SECTION_INFO(DECL, FIRST) \
+ do { \
+ if (TARGET_CM_EMBMEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
+ SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
} while (0)
\f
/* Specify the machine mode that this machine uses
(! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
#else
/* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
- we have to sign extend which slows things down. */
+ we have to sign extend which slows things down. */
#define CASE_VECTOR_MODE \
(! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
#endif
/* Define as C expression which evaluates to nonzero if the tablejump
instruction expects the table to contain offsets from the address of the
table.
- Do not define this if the table should contain absolute addresses. */
+ Do not define this if the table should contain absolute addresses. */
/* #define CASE_VECTOR_PC_RELATIVE 1 */
-/* Specify the tree operation to be used to convert reals to integers. */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case. */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
/* Define this as 1 if `char' should by default be signed; else as 0. */
#define DEFAULT_SIGNED_CHAR 1
#define PROMOTE_PROTOTYPES (TARGET_ARCH32)
/* Define this to be nonzero if shift instructions ignore all but the low-order
- few bits. */
+ few bits. */
#define SHIFT_COUNT_TRUNCATED 1
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
/* Specify the machine mode that pointers have.
After generation of rtl, the compiler makes no further distinction
between pointers and any other objects of this machine mode. */
-#define Pmode (TARGET_PTR64 ? DImode : SImode)
+#define Pmode (TARGET_ARCH64 ? DImode : SImode)
/* Generate calls to memcpy, memcmp and memset. */
#define TARGET_MEM_FUNCTIONS
/* Return non-zero if MODE implies a floating point inequality can be
reversed. For Sparc this is always true because we have a full
- compliment of ordered and unordered comparisons. */
-#define REVERSIBLE_CC_MODE(MODE) 1
+ compliment of ordered and unordered comparisons, but until generic
+ code knows how to reverse it correctly we keep the old definition. */
+#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
-/* A function address in a call instruction
- is a byte address (for indexing purposes)
- so give the MEM rtx a byte's mode. */
-#define FUNCTION_MODE SImode
+/* A function address in a call instruction for indexing purposes. */
+#define FUNCTION_MODE Pmode
/* Define this if addresses of constant functions
shouldn't be put through pseudo regs where they can be cse'd.
= init_one_libfunc (NEGTF2_LIBCALL); \
smul_optab->handlers[(int) TFmode].libfunc \
= init_one_libfunc (MULTF3_LIBCALL); \
- flodiv_optab->handlers[(int) TFmode].libfunc \
+ sdiv_optab->handlers[(int) TFmode].libfunc \
= init_one_libfunc (DIVTF3_LIBCALL); \
eqtf2_libfunc = init_one_libfunc (EQTF2_LIBCALL); \
netf2_libfunc = init_one_libfunc (NETF2_LIBCALL); \
/* Compute extra cost of moving data between one register class
and another. */
#define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
-#define REGISTER_MOVE_COST(CLASS1, CLASS2) \
+#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
(((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
|| (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
|| (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
- ? (sparc_cpu == PROCESSOR_ULTRASPARC ? 12 : 6) : 2)
+ ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
+ || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2)
+
+/* Provide the cost of a branch. For pre-v9 processors we use
+ a value of 3 to take into account the potential annulling of
+ the delay slot (which ends up being a bubble in the pipeline slot)
+ plus a cycle to take into consideration the instruction cache
+ effects.
+
+ On v9 and later, which have branch prediction facilities, we set
+ it to the depth of the pipeline as that is the cost of a
+ mispredicted branch. */
+
+#define BRANCH_COST \
+ ((sparc_cpu == PROCESSOR_V9 \
+ || sparc_cpu == PROCESSOR_ULTRASPARC) \
+ ? 7 \
+ : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
+ ? 9 : 3))
/* Provide the costs of a rtl expression. This is in the body of a
switch on CODE. The purpose for the cost of MULT is to encourage
if (sparc_cpu == PROCESSOR_ULTRASPARC) \
return (GET_MODE (X) == DImode ? \
COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); \
+ if (sparc_cpu == PROCESSOR_ULTRASPARC3) \
+ return COSTS_N_INSNS (6); \
return TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
case DIV: \
case UDIV: \
if (sparc_cpu == PROCESSOR_ULTRASPARC) \
return (GET_MODE (X) == DImode ? \
COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); \
+ if (sparc_cpu == PROCESSOR_ULTRASPARC3) \
+ return (GET_MODE (X) == DImode ? \
+ COSTS_N_INSNS (71) : COSTS_N_INSNS (40)); \
return COSTS_N_INSNS (25); \
/* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
so that cse will favor the latter. */ \
case FIX: \
return 19;
-#define ISSUE_RATE sparc_issue_rate()
-
-/* Adjust the cost of dependencies. */
-#define ADJUST_COST(INSN,LINK,DEP,COST) \
- (COST) = sparc_adjust_cost(INSN, LINK, DEP, COST)
+#define PREFETCH_BLOCK \
+ ((sparc_cpu == PROCESSOR_ULTRASPARC \
+ || sparc_cpu == PROCESSOR_ULTRASPARC3) \
+ ? 64 : 32)
-#define MD_SCHED_INIT(DUMP, SCHED_VERBOSE) \
- if (sparc_cpu == PROCESSOR_ULTRASPARC) \
- ultrasparc_sched_init (DUMP, SCHED_VERBOSE)
-
-#define MD_SCHED_REORDER(DUMP, SCHED_VERBOSE, READY, N_READY, CLOCK, CIM) \
-do { \
- if (sparc_cpu == PROCESSOR_ULTRASPARC) \
- ultrasparc_sched_reorder (DUMP, SCHED_VERBOSE, READY, N_READY); \
- CIM = issue_rate; \
-} while (0)
-
-#define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \
-do { \
- if (sparc_cpu == PROCESSOR_ULTRASPARC) \
- (CAN_ISSUE_MORE) = ultrasparc_variable_issue (INSN); \
- else \
- (CAN_ISSUE_MORE)--; \
-} while (0)
-
-/* Conditional branches with empty delay slots have a length of two. */
-#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
-do { \
- if (GET_CODE (INSN) == CALL_INSN \
- || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
- LENGTH += 1; \
-} while (0)
+#define SIMULTANEOUS_PREFETCHES \
+ ((sparc_cpu == PROCESSOR_ULTRASPARC) \
+ ? 2 \
+ : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
+ ? 8 : 3))
\f
/* Control the assembler format that we output. */
/* ??? Try to make the style consistent here (_OP?). */
-#define ASM_LONGLONG ".xword"
-#define ASM_LONG ".word"
-#define ASM_SHORT ".half"
-#define ASM_BYTE_OP ".byte"
#define ASM_FLOAT ".single"
#define ASM_DOUBLE ".double"
-#define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
-
-/* Output before read-only data. */
-
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* Output before writable data. */
-
-#define DATA_SECTION_ASM_OP ".data"
+#define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
/* How to refer to registers in assembler output.
This sequence is indexed by compiler's hard-register-number (see above). */
"%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
"%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
"%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
- "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc"}
+ "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
/* Define additional names for use in asm clobbers and asm declarations. */
#define ADDITIONAL_REGISTER_NAMES \
{{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
-/* How to renumber registers for dbx and gdb. In the flat model, the frame
- pointer is really %i7. */
-
-#define DBX_REGISTER_NUMBER(REGNO) \
- (TARGET_FLAT && REGNO == FRAME_POINTER_REGNUM ? 31 : REGNO)
-
/* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
can run past this up to a continuation point. Once we used 1500, but
a single entry in C++ can run more than 500 bytes, due to the length of
guess... */
#define DBX_CONTIN_LENGTH 1000
-/* This is how to output a note to DBX telling it the line number
- to which the following sequence of instructions corresponds.
-
- This is needed for SunOS 4.0, and should not hurt for 3.2
- versions either. */
-#define ASM_OUTPUT_SOURCE_LINE(file, line) \
- { static int sym_lineno = 1; \
- fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
- line, sym_lineno, sym_lineno); \
- sym_lineno += 1; }
-
/* This is how to output the definition of a user-level label named NAME,
such as the label on a static function or variable NAME. */
#define ASM_GLOBALIZE_LABEL(FILE,NAME) \
do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-/* The prefix to add to user-visible assembler symbols. */
+/* The prefix to add to user-visible assembler symbols. */
#define USER_LABEL_PREFIX "_"
#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
-/* This is how to output an assembler line defining a `float' constant.
- We always have to use a .long pseudo-op to do this because the native
- SVR4 ELF assembler is buggy and it generates incorrect values when we
- try to use the .float pseudo-op instead. */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE) \
- { \
- long t; \
- char str[30]; \
- REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
- REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
- fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t, \
- ASM_COMMENT_START, str); \
- } \
-
-/* This is how to output an assembler line defining a `double' constant.
- We always have to use a .long pseudo-op to do this because the native
- SVR4 ELF assembler is buggy and it generates incorrect values when we
- try to use the .float pseudo-op instead. */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
- { \
- long t[2]; \
- char str[30]; \
- REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
- REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
- fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t[0], \
- ASM_COMMENT_START, str); \
- fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[1]); \
- }
-
-/* This is how to output an assembler line defining a `long double'
- constant. */
-
-#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
- { \
- long t[4]; \
- char str[30]; \
- REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
- REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
- fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t[0], \
- ASM_COMMENT_START, str); \
- fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[1]); \
- fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[2]); \
- fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[3]); \
- }
-
-/* This is how to output an assembler line defining an `int' constant. */
-
-#define ASM_OUTPUT_INT(FILE,VALUE) \
-( fprintf (FILE, "\t%s\t", ASM_LONG), \
- output_addr_const (FILE, (VALUE)), \
- fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line defining a DImode constant. */
-#define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
- output_double_int (FILE, VALUE)
-
-/* Likewise for `char' and `short' constants. */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE) \
-( fprintf (FILE, "\t%s\t", ASM_SHORT), \
- output_addr_const (FILE, (VALUE)), \
- fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE) \
-( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \
- output_addr_const (FILE, (VALUE)), \
- fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte. */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE) \
- fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
-
/* This is how we hook in and defer the case-vector until the end of
the function. */
#define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-#define IDENT_ASM_OP ".ident"
+#define IDENT_ASM_OP "\t.ident\t"
/* Output #ident as a .ident. */
#define ASM_OUTPUT_IDENT(FILE, NAME) \
- fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
+ fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
/* Output code to add DELTA to the first argument, and then jump to FUNCTION.
Used for C++ multiple inheritance. */
#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
do { \
- int big_delta = (DELTA) >= 4096 || (DELTA) < -4096; \
- if (big_delta) \
- fprintf (FILE, "\tset %d,%%g1\n\tadd %%o0,%%g1,%%o0\n", (DELTA)); \
- /* Don't use the jmp solution unless we know the target is local to \
- the application or shared object. \
- XXX: Wimp out and don't actually check anything except if this is \
- an embedded target where we assume there are no shared libs. */ \
- if (!TARGET_CM_EMBMEDANY || flag_pic) \
- { \
- if (! big_delta) \
- fprintf (FILE, "\tadd %%o0,%d,%%o0\n", DELTA); \
- fprintf (FILE, "\tmov %%o7,%%g1\n"); \
- fprintf (FILE, "\tcall "); \
- assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
- fprintf (FILE, ",0\n"); \
- } \
- else if (TARGET_CM_EMBMEDANY) \
- { \
- fprintf (FILE, "\tsetx "); \
- assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
- fprintf (FILE, ",%%g5,%%g1\n\tjmp %%g1\n"); \
- } \
- else \
- { \
- fprintf (FILE, "\tsethi %%hi("); \
- assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
- fprintf (FILE, "),%%g1\n\tjmp %%g1+%%lo("); \
- assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
- fprintf (FILE, ")\n"); \
- } \
- if (!TARGET_CM_EMBMEDANY || flag_pic) \
- fprintf (FILE, "\tmov %%g1,%%o7\n"); \
- else if (big_delta) \
- fprintf (FILE, "\tnop\n"); \
+ int reg = 0; \
+ \
+ if (TARGET_ARCH64 \
+ && aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION)))) \
+ reg = 1; \
+ if ((DELTA) >= 4096 || (DELTA) < -4096) \
+ fprintf (FILE, "\tset\t%d, %%g1\n\tadd\t%%o%d, %%g1, %%o%d\n", \
+ (int)(DELTA), reg, reg); \
else \
- fprintf (FILE, "\tadd %%o0,%d,%%o0\n", DELTA); \
+ fprintf (FILE, "\tadd\t%%o%d, %d, %%o%d\n", reg, (int)(DELTA), reg);\
+ fprintf (FILE, "\tor\t%%o7, %%g0, %%g1\n"); \
+ fprintf (FILE, "\tcall\t"); \
+ assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
+ fprintf (FILE, ", 0\n"); \
+ fprintf (FILE, "\t or\t%%g1, %%g0, %%o7\n"); \
} while (0)
-/* Define the parentheses used to group arithmetic operations
- in assembler code. */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences. */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_')
#define PREDICATE_CODES \
{"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
{"fp_zero_operand", {CONST_DOUBLE}}, \
-{"fp_sethi_p", {CONST_DOUBLE}}, \
-{"fp_mov_p", {CONST_DOUBLE}}, \
-{"fp_high_losum_p", {CONST_DOUBLE}}, \
+{"fp_register_operand", {SUBREG, REG}}, \
{"intreg_operand", {SUBREG, REG}}, \
{"fcc_reg_operand", {REG}}, \
+{"fcc0_reg_operand", {REG}}, \
{"icc_or_fcc_reg_operand", {REG}}, \
{"restore_operand", {REG}}, \
{"call_operand", {MEM}}, \
{"eq_or_neq", {EQ, NE}}, \
{"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
{"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
+{"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
{"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
{"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
{"cc_arithop", {AND, IOR, XOR}}, \
#define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic)
-/* Defined in flags.h, but insn-emit.c does not include flags.h. */
-
-extern int flag_pic;
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