/* Definitions of target machine for GNU compiler, for Sun SPARC.
Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
- 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
+ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
+ Free Software Foundation, Inc.
Contributed by Michael Tiemann (tiemann@cygnus.com).
64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
at Cygnus Support.
/* ??? This should be 32 bits for v9 but what can we do? */
#define WCHAR_TYPE "short unsigned int"
#define WCHAR_TYPE_SIZE 16
-
-/* Show we can debug even without a frame pointer. */
-#define CAN_DEBUG_WITHOUT_FP
-
-/* Option handling. */
-
-#define OVERRIDE_OPTIONS sparc_override_options ()
\f
/* Mask of all CPU selection flags. */
#define MASK_ISA \
numbered. */
#define WORDS_BIG_ENDIAN 1
-/* Define this to set the endianness to use in libgcc2.c, which can
- not depend on target_flags. */
-#if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
-#define LIBGCC2_WORDS_BIG_ENDIAN 0
-#else
-#define LIBGCC2_WORDS_BIG_ENDIAN 1
-#endif
-
#define MAX_BITS_PER_WORD 64
/* Width of a word, in units (bytes). */
#define MIN_UNITS_PER_WORD 4
#endif
-#define UNITS_PER_SIMD_WORD (TARGET_VIS ? 8 : UNITS_PER_WORD)
-
/* Now define the sizes of the C data types. */
#define SHORT_TYPE_SIZE 16
#define LONG_LONG_TYPE_SIZE 64
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
+
/* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the
SPARC ABI says that it is 128-bit wide. */
/* #define LONG_DOUBLE_TYPE_SIZE 128 */
-/* Width in bits of a pointer.
- See also the macro `Pmode' defined below. */
+/* The widest floating-point format really supported by the hardware. */
+#define WIDEST_HARDWARE_FP_SIZE 64
+
+/* Width in bits of a pointer. This is the size of ptr_mode. */
#define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
+/* This is the machine mode used for addresses. */
+#define Pmode (TARGET_ARCH64 ? DImode : SImode)
+
/* If we have to extend pointers (only when TARGET_ARCH64 and not
TARGET_PTR64), we want to do it unsigned. This macro does nothing
if ptr_mode and Pmode are the same. */
#define POINTERS_EXTEND_UNSIGNED 1
-/* For TARGET_ARCH64 we need this, as we don't have instructions
- for arithmetic operations which do zero/sign extension at the same time,
- so without this we end up with a srl/sra after every assignment to an
- user variable, which means very very bad code. */
-#define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
-if (TARGET_ARCH64 \
- && GET_MODE_CLASS (MODE) == MODE_INT \
- && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
- (MODE) = word_mode;
-
/* Allocation boundary (in *bits*) for storing arguments in argument list. */
#define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
} \
} while (0)
-/* Value should be nonzero if functions must have frame pointers.
- Zero means the frame pointer need not be set up (and parms
- may be accessed via the stack pointer) in functions that seem suitable.
- Used in flow.c, global.c, ra.c and reload1.c. */
-#define FRAME_POINTER_REQUIRED \
- (! (leaf_function_p () && only_leaf_regs_used ()))
-
/* Base register for access to arguments of the function. */
#define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
/* Pick a default value we can notice from override_options:
!v9: Default is on.
- v9: Default is off. */
+ v9: Default is off.
+ Originally it was -1, but later on the container of options changed to
+ unsigned byte, so we decided to pick 127 as default value, which does
+ reflect an undefined default value in case of 0/1. */
-#define DEFAULT_PCC_STRUCT_RETURN -1
+#define DEFAULT_PCC_STRUCT_RETURN 127
/* Functions which return large structures get the address
to place the wanted value at offset 64 from the frame.
{-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
{-1, -1, -1, 0x3f}} /* ALL_REGS */
+/* The same information, inverted:
+ Return the class number of the smallest class containing
+ reg number REGNO. This could be a conditional expression
+ or could index an array. */
+
+extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
+
+#define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
+
+/* The following macro defines cover classes for Integrated Register
+ Allocator. Cover classes is a set of non-intersected register
+ classes covering all hard registers used for register allocation
+ purpose. Any move between two registers of a cover class should be
+ cheaper than load or store of the registers. The macro value is
+ array of register classes with LIM_REG_CLASSES used as the end
+ marker. */
+
+#define IRA_COVER_CLASSES \
+{ \
+ GENERAL_REGS, EXTRA_FP_REGS, FPCC_REGS, LIM_REG_CLASSES \
+}
+
/* Defines invalid mode changes. Borrowed from pa64-regs.h.
SImode loads to floating-point registers are not zero-extended.
&& GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
-/* The same information, inverted:
- Return the class number of the smallest class containing
- reg number REGNO. This could be a conditional expression
- or could index an array. */
-
-extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
-
-#define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
-
/* This is the order in which to allocate registers normally.
We put %f0-%f7 last among the float registers, so as to make it more
96, 97, 98, 99, /* %fcc0-3 */ \
100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */
-#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
+#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
extern char sparc_leaf_regs[];
#define LEAF_REGISTERS sparc_leaf_regs
/* Local macro to handle the two v9 classes of FP regs. */
#define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
-/* Get reg_class from a letter such as appears in the machine description.
- In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
- .md file for v8 and v9.
- 'd' and 'b' are used for single and double precision VIS operations,
- if TARGET_VIS.
- 'h' is used for V8+ 64 bit global and out registers. */
-
-#define REG_CLASS_FROM_LETTER(C) \
-(TARGET_V9 \
- ? ((C) == 'f' ? FP_REGS \
- : (C) == 'e' ? EXTRA_FP_REGS \
- : (C) == 'c' ? FPCC_REGS \
- : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
- : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
- : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
- : NO_REGS) \
- : ((C) == 'f' ? FP_REGS \
- : (C) == 'e' ? FP_REGS \
- : (C) == 'c' ? FPCC_REGS \
- : NO_REGS))
-
-/* The letters I, J, K, L, M, N, O, P in a register constraint string
- can be used to stand for particular ranges of CONST_INTs.
- This macro defines what the ranges are.
- C is the letter, and VALUE is a constant value.
- Return 1 if VALUE is in the range specified by C.
-
- `I' is used for the range of constants an insn can actually contain.
- `J' is used for the range which is just zero (since that is R0).
- `K' is used for constants which can be loaded with a single sethi insn.
- `L' is used for the range of constants supported by the movcc insns.
- `M' is used for the range of constants supported by the movrcc insns.
- `N' is like K, but for constants wider than 32 bits.
- `O' is used for the range which is just 4096.
- `P' is free. */
-
/* Predicates for 10-bit, 11-bit and 13-bit signed constants. */
#define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
#define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
#define SPARC_SETHI32_P(X) \
(SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
- : (C) == 'J' ? (VALUE) == 0 \
- : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
- : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
- : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
- : (C) == 'N' ? SPARC_SETHI_P (VALUE) \
- : (C) == 'O' ? (VALUE) == 4096 \
- : 0)
-
-/* Similar, but for CONST_DOUBLEs, and defining letters G and H.
- Here VALUE is the CONST_DOUBLE rtx itself. */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'G' ? const_zero_operand (VALUE, GET_MODE (VALUE)) \
- : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
- : 0)
-
/* Given an rtx X being reloaded into a reg required to be
in class CLASS, return the class of reg to actually use.
In general this is just CLASS; but on some machines
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
(FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
-/* Return the stack location to use for secondary memory needed reloads.
- We want to use the reserved location just below the frame pointer.
- However, we must ensure that there is a frame, so use assign_stack_local
- if the frame size is zero. */
-#define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
- (get_frame_size () == 0 \
- ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
- : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
- STARTING_FRAME_OFFSET)))
-
/* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
because the movsi and movsf patterns don't handle r/f moves.
For v8 we copy the default definition. */
If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
first local allocated. Otherwise, it is the offset to the BEGINNING
of the first local allocated. */
-/* This allows space for one TFmode floating point value, which is used
- by SECONDARY_MEMORY_NEEDED_RTX. */
-#define STARTING_FRAME_OFFSET \
- (TARGET_ARCH64 ? -16 \
- : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
+#define STARTING_FRAME_OFFSET 0
/* Offset of first parameter from the argument pointer register value.
!v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
-/* The way this is structured, we can't eliminate SFP in favor of SP
- if the frame pointer is required: we want to use the SFP->HFP elimination
- in that case. But the test in update_eliminables doesn't know we are
- assuming below that we only do the former elimination. */
-#define CAN_ELIMINATE(FROM, TO) \
- ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED)
-
/* We always pretend that this is a leaf function because if it's not,
there's no point in trying to eliminate the frame pointer. If it
is a leaf function, we guessed right! */
the function! */
#define ACCUMULATE_OUTGOING_ARGS 1
-/* Value is the number of bytes of arguments automatically
- popped when returning from a subroutine call.
- FUNDECL is the declaration node of the function (as a tree),
- FUNTYPE is the data type of the function (as a tree),
- or for a library call it is an identifier node for the subroutine name.
- SIZE is the number of bytes of arguments passed on the stack. */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
/* Define this macro if the target machine has "register windows". This
C expression returns the register number as seen by the called function
corresponding to register number OUT as seen by the calling function.
#define LOCAL_REGNO(REGNO) \
((REGNO) >= 16 && (REGNO) <= 31)
-/* Define how to find the value returned by a function.
- VALTYPE is the data type of the value (as a tree).
- If the precise function being called is known, FUNC is its FUNCTION_DECL;
- otherwise, FUNC is 0. */
-
-/* On SPARC the value is found in the first "output" register. */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
- function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
-
-/* But the called function leaves it in the first "input" register. */
-
-#define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
- function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
-
-/* Define how to find the value returned by a library function
- assuming the value has mode MODE. */
-
-#define LIBCALL_VALUE(MODE) \
- function_value (NULL_TREE, (MODE), 1)
-
-/* 1 if N is a possible register number for a function value
- as seen by the caller.
- On SPARC, the first "output" reg is used for integer values,
- and the first floating point register is used for floating point values. */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
-
/* Define the size of space to allocate for the return value of an
untyped_call. */
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL));
-/* Update the data in CUM to advance over an argument
- of mode MODE and data type TYPE.
- TYPE is null for libcalls where that information may not be available. */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
-function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
-
-/* Determine where to put an argument to a function.
- Value is zero to push the argument on the stack,
- or a hard register in which to store the argument.
-
- MODE is the argument's machine mode.
- TYPE is the data type of the argument (as a tree).
- This is null for libcalls where that information may
- not be available.
- CUM is a variable of type CUMULATIVE_ARGS which gives info about
- the preceding args and about the function being called.
- NAMED is nonzero if this argument is a named parameter
- (otherwise it is an extra parameter matching an ellipsis). */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
-
-/* Define where a function finds its arguments.
- This is different from FUNCTION_ARG because of register windows. */
-
-#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
-function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
-
/* If defined, a C expression which determines whether, and in which direction,
to pad out an argument with extra space. The value should be of type
`enum direction': either `upward' to pad above the argument,
&& (GET_MODE_ALIGNMENT (MODE) == 128 \
|| ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
? 128 : PARM_BOUNDARY)
-\f
-/* Define the information needed to generate branch and scc insns. This is
- stored from the compare operation. Note that we can't use "rtx" here
- since it hasn't been defined! */
-
-extern GTY(()) rtx sparc_compare_op0;
-extern GTY(()) rtx sparc_compare_op1;
-extern GTY(()) rtx sparc_compare_emitted;
\f
/* Generate the special assembly code needed to tell the assembler whatever
#define EXIT_IGNORE_STACK \
(get_frame_size () != 0 \
- || current_function_calls_alloca || current_function_outgoing_args_size)
+ || cfun->calls_alloca || crtl->outgoing_args_size)
/* Define registers used by the epilogue and return instruction. */
#define EPILOGUE_USES(REGNO) ((REGNO) == 31 \
- || (current_function_calls_eh_return && (REGNO) == 1))
+ || (crtl->calls_eh_return && (REGNO) == 1))
\f
/* Length in units of the trampoline for entering a nested function. */
#define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
#define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
- FNADDR is an RTX for the address of the function's pure code.
- CXT is an RTX for the static chain value for the function. */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
- if (TARGET_ARCH64) \
- sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
- else \
- sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
\f
/* Generate RTL to flush the register windows so as to make arbitrary frames
available. */
/* This is the offset of the return address to the true next instruction to be
executed for the current function. */
#define RETURN_ADDR_OFFSET \
- (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
+ (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct))
/* The current return address is in %i7. The return address of anything
farther back is in the register window save area at [%fp+60]. */
After reload, it makes no difference, since pseudo regs have
been eliminated by then. */
-/* Optional extra constraints for this machine.
-
- 'Q' handles floating point constants which can be moved into
- an integer register with a single sethi instruction.
-
- 'R' handles floating point constants which can be moved into
- an integer register with a single mov instruction.
-
- 'S' handles floating point constants which can be moved into
- an integer register using a high/lo_sum sequence.
-
- 'T' handles memory addresses where the alignment is known to
- be at least 8 bytes.
-
- `U' handles all pseudo registers or a hard even numbered
- integer register, needed for ldd/std instructions.
-
- 'W' handles the memory operand when moving operands in/out
- of 'e' constraint floating point registers.
-
- 'Y' handles the zero vector constant. */
-
#ifndef REG_OK_STRICT
/* Nonzero if X is a hard reg that can be used as an index
or if it is a pseudo reg. */
#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
-/* 'T', 'U' are for aligned memory loads which aren't needed for arch64.
- 'W' is like 'T' but is assumed true on arch64.
-
- Remember to accept pseudo-registers for memory constraints if reload is
- in progress. */
-
-#define EXTRA_CONSTRAINT(OP, C) \
- sparc_extra_constraint_check(OP, C, 0)
-
#else
/* Nonzero if X is a hard reg that can be used as an index. */
/* Nonzero if X is a hard reg that can be used as a base reg. */
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-#define EXTRA_CONSTRAINT(OP, C) \
- sparc_extra_constraint_check(OP, C, 1)
-
#endif
\f
/* Should gcc use [%reg+%lo(xx)+offset] addresses? */
#define USE_AS_OFFSETABLE_LO10 0
#endif
\f
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
- that is a valid memory address for an instruction.
- The MODE argument is the machine mode for the MEM expression
- that wants to use this address.
-
- On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
- ordinarily. This changes a bit when generating PIC.
-
- If you change this, execute "rm explow.o recog.o reload.o". */
+/* On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
+ ordinarily. This changes a bit when generating PIC. The details are
+ in sparc.c's implementation of TARGET_LEGITIMATE_ADDRESS_P. */
#define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode)
#define RTX_OK_FOR_OLO10_P(X) \
(GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
-#ifdef REG_OK_STRICT
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
-{ \
- if (legitimate_address_p (MODE, X, 1)) \
- goto ADDR; \
-}
-#else
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
-{ \
- if (legitimate_address_p (MODE, X, 0)) \
- goto ADDR; \
-}
-#endif
-
-/* Go to LABEL if ADDR (a legitimate address expression)
- has an effect that depends on the machine mode it is used for.
-
- In PIC mode,
-
- (mem:HI [%l7+a])
-
- is not equivalent to
-
- (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
-
- because [%l7+a+1] is interpreted as the address of (a+1). */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
-{ \
- if (flag_pic == 1) \
- { \
- if (GET_CODE (ADDR) == PLUS) \
- { \
- rtx op0 = XEXP (ADDR, 0); \
- rtx op1 = XEXP (ADDR, 1); \
- if (op0 == pic_offset_table_rtx \
- && SYMBOLIC_CONST (op1)) \
- goto LABEL; \
- } \
- } \
-}
\f
-/* Try machine-dependent ways of modifying an illegitimate address
- to be legitimate. If we find one, return the new, valid address.
- This macro is used in only one place: `memory_address' in explow.c.
-
- OLDX is the address as it was before break_out_memory_refs was called.
- In some cases it is useful to look at this to decide what needs to be done.
-
- MODE and WIN are passed so that this macro can use
- GO_IF_LEGITIMATE_ADDRESS.
-
- It is always safe for this macro to do nothing. It exists to recognize
- opportunities to optimize the output. */
-
-/* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
-{ \
- (X) = legitimize_address (X, OLDX, MODE); \
- if (memory_address_p (MODE, X)) \
- goto WIN; \
-}
-
/* Try a machine-dependent way of reloading an illegitimate address
operand. If we find one, push the reload and jump to WIN. This
- macro is used in only one place: `find_reloads_address' in reload.c.
-
- For SPARC 32, we wish to handle addresses by splitting them into
- HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
- This cuts the number of extra insns by one.
-
- Do nothing when generating PIC code and the address is a
- symbolic operand or requires a scratch register. */
-
-#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
-do { \
- /* Decompose SImode constants into hi+lo_sum. We do have to \
- rerecognize what we produce, so be careful. */ \
- if (CONSTANT_P (X) \
- && (MODE != TFmode || TARGET_ARCH64) \
- && GET_MODE (X) == SImode \
- && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
- && ! (flag_pic \
- && (symbolic_operand (X, Pmode) \
- || pic_address_needs_scratch (X))) \
- && sparc_cmodel <= CM_MEDLOW) \
- { \
- X = gen_rtx_LO_SUM (GET_MODE (X), \
- gen_rtx_HIGH (GET_MODE (X), X), X); \
- push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
- BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
- OPNUM, TYPE); \
- goto WIN; \
- } \
- /* ??? 64-bit reloads. */ \
+ macro is used in only one place: `find_reloads_address' in reload.c. */
+#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
+do { \
+ int win; \
+ (X) = sparc_legitimize_reload_address ((X), (MODE), (OPNUM), \
+ (int)(TYPE), (IND_LEVELS), &win); \
+ if (win) \
+ goto WIN; \
} while (0)
\f
/* Specify the machine mode that this machine uses
/* If a memory-to-memory move would take MOVE_RATIO or more simple
move-instruction pairs, we will do a movmem or libcall instead. */
-#define MOVE_RATIO (optimize_size ? 3 : 8)
+#define MOVE_RATIO(speed) ((speed) ? 8 : 3)
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
is done just by pretending it is already truncated. */
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-/* Specify the machine mode used for addresses. */
-#define Pmode (TARGET_ARCH64 ? DImode : SImode)
-
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
return the mode to be used for the comparison. For floating-point,
CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
On Niagara-2, a not-taken branch costs 1 cycle whereas a taken
branch costs 6 cycles. */
-#define BRANCH_COST \
+#define BRANCH_COST(speed_p, predictable_p) \
((sparc_cpu == PROCESSOR_V9 \
|| sparc_cpu == PROCESSOR_ULTRASPARC) \
? 7 \
} \
} while (0)
-#define SPARC_SYMBOL_REF_TLS_P(RTX) \
- (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
-
#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '(' \
|| (CHAR) == ')' || (CHAR) == '_' || (CHAR) == '&')
/* The number of Pmode words for the setjmp buffer. */
#define JMP_BUF_SIZE 12
+
+/* We use gcc _mcount for profiling. */
+#define NO_PROFILE_COUNTERS 0