-;;- Machine description for Hitachi / SuperH SH.
-;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
+;;- Machine description for Renesas / SuperH SH.
+;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
;; Free Software Foundation, Inc.
;; Contributed by Steve Chamberlain (sac@cygnus.com).
;; Improved by Jim Wilson (wilson@cygnus.com).
-;; This file is part of GNU CC.
+;; This file is part of GCC.
-;; GNU CC is free software; you can redistribute it and/or modify
+;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.
-;; GNU CC is distributed in the hope that it will be useful,
+;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING. If not, write to
+;; along with GCC; see the file COPYING. If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.
(R8_REG 8)
(R9_REG 9)
(R10_REG 10)
+ (R20_REG 20)
+ (R21_REG 21)
+ (R22_REG 22)
+ (R23_REG 23)
(DR0_REG 64)
(DR2_REG 66)
(DR4_REG 68)
+ (FR23_REG 87)
(TR0_REG 128)
(TR1_REG 129)
(UNSPEC_CALLER 10)
(UNSPEC_GOTPLT 11)
(UNSPEC_ICACHE 12)
+ (UNSPEC_INIT_TRAMP 13)
+ (UNSPEC_FCOSA 14)
+ (UNSPEC_FSRRA 15)
+ (UNSPEC_FSINA 16)
+ (UNSPEC_NSB 17)
+ (UNSPEC_ALLOCO 18)
+ (UNSPEC_EH_RETURN 19)
+ (UNSPEC_TLSGD 20)
+ (UNSPEC_TLSLDM 21)
+ (UNSPEC_TLSIE 22)
+ (UNSPEC_DTPOFF 23)
+ (UNSPEC_GOTTPOFF 24)
+ (UNSPEC_TPOFF 25)
+ (UNSPEC_RA 26)
;; These are used with unspec_volatile.
(UNSPECV_BLOCKAGE 0)
(UNSPECV_CONST8 6)
(UNSPECV_WINDOW_END 10)
(UNSPECV_CONST_END 11)
-])
+])
;; -------------------------------------------------------------------------
;; Attributes
;; Target CPU.
(define_attr "cpu"
- "sh1,sh2,sh3,sh3e,sh4,sh5"
+ "sh1,sh2,sh2e,sh3,sh3e,sh4,sh5"
(const (symbol_ref "sh_cpu_attr")))
(define_attr "endian" "big,little"
(define_attr "fmovd" "yes,no"
(const (if_then_else (symbol_ref "TARGET_FMOVD")
(const_string "yes") (const_string "no"))))
-;; issues/clock
-(define_attr "issues" "1,2"
- (const (if_then_else (symbol_ref "TARGET_SUPERSCALAR") (const_string "2") (const_string "1"))))
+;; pipeline model
+(define_attr "pipe_model" "sh1,sh4,sh5media"
+ (const
+ (cond [(symbol_ref "TARGET_SHMEDIA") (const_string "sh5media")
+ (symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
+ (const_string "sh1"))))
;; cbranch conditional branch instructions
;; jump unconditional jumps
;; arith3b like above, but might end with a redirected branch
;; load from memory
;; load_si Likewise, SImode variant for general register.
+;; fload Likewise, but load to fp register.
;; store to memory
-;; move register to register
+;; move general purpose register to register
+;; mt_group other sh4 mt instructions
;; fmove register to register, floating point
;; smpy word precision integer multiply
;; dmpy longword or doublelongword precision integer multiply
;; pstore store of pr reg, which can't be put into delay slot of jsr
;; prget copy pr to register, ditto
;; pcload pc relative load of constant value
+;; pcfload Likewise, but load to fp register.
;; pcload_si Likewise, SImode variant for general register.
;; rte return from exception
;; sfunc special function call with known used registers
;; call function call
;; fp floating point
;; fdiv floating point divide (or square root)
-;; gp_fpul move between general purpose register and fpul
+;; gp_fpul move from general purpose register to fpul
+;; fpul_gp move from fpul to general purpose register
+;; mac_gp move from mac[lh] to general purpose register
;; dfp_arith, dfp_cmp,dfp_conv
+;; ftrc_s fix_truncsfsi2_i4
;; dfdiv double precision floating point divide (or square root)
+;; cwb ic_invalidate_line_i
+;; tls_load load TLS related address
+;; arith_media SHmedia arithmetic, logical, and shift instructions
+;; cbranch_media SHmedia conditional branch instructions
+;; cmp_media SHmedia compare instructions
+;; dfdiv_media SHmedia double precision divide and square root
+;; dfmul_media SHmedia double precision multiply instruction
+;; dfparith_media SHmedia double precision floating point arithmetic
+;; dfpconv_media SHmedia double precision floating point conversions
+;; dmpy_media SHmedia longword multiply
+;; fcmp_media SHmedia floating point compare instructions
+;; fdiv_media SHmedia single precision divide and square root
+;; fload_media SHmedia floating point register load instructions
+;; fmove_media SHmedia floating point register moves (inc. fabs and fneg)
+;; fparith_media SHmedia single precision floating point arithmetic
+;; fpconv_media SHmedia single precision floating point conversions
+;; fstore_media SHmedia floating point register store instructions
+;; gettr_media SHmedia gettr instruction
+;; invalidate_line_media SHmedia invalidate_line sequence
+;; jump_media SHmedia unconditional branch instructions
+;; load_media SHmedia general register load instructions
+;; pt_media SHmedia pt instruction (expanded by assembler)
+;; ptabs_media SHmedia ptabs instruction
+;; store_media SHmedia general register store instructions
+;; mcmp_media SHmedia multimedia compare, absolute, saturating ops
+;; mac_media SHmedia mac-style fixed point operations
+;; d2mpy_media SHmedia: two 32 bit integer multiplies
+;; atrans SHmedia approximate transcendental functions
+;; ustore_media SHmedia unaligned stores
;; nil no-op move, will be deleted.
(define_attr "type"
- "cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,other,load,load_si,store,move,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload,pcload_si,pt,ptabs,rte,sfunc,call,fp,fdiv,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,nil"
+ "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,fload,store,move,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fdiv,ftrc_s,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,mem_fpscr,gp_fpscr,cwb,tls_load,arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media,nil,other"
(const_string "other"))
;; We define a new attribute namely "insn_class".We use
-;; this for DFA based pipeline description.
-;; Although the "type" attribute covers almost all insn
-;; classes,it is more convenient to define new attribute
-;; for certain reservations.
+;; this for the DFA based pipeline description.
;;
;; mt_group SH4 "mt" group instructions.
;;
-;; ex_group SH4 "ex" group instructions.They mostly
-;; overlap with arithmetic instructions but
-;; new attribute defined to distinguish from
-;; mt group instructions.
+;; ex_group SH4 "ex" group instructions.
+;;
+;; ls_group SH4 "ls" group instructions.
;;
-;; lds_to_fpscr The "type" attribute couldn't sufficiently
-;; distinguish it from others.It is part of
-;; new attribute.Similar case with ldsmem_to_fpscr
-;; and cwb.
(define_attr "insn_class"
- "mt_group,ex_group,lds_to_fpscr,ldsmem_to_fpscr,cwb,none"
- (const_string "none"))
+ "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
+ (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
+ (eq_attr "type" "arith,dyn_shift") (const_string "ex_group")
+ (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,store,gp_fpul,fpul_gp") (const_string "ls_group")
+ (eq_attr "type" "cbranch,jump") (const_string "br_group")
+ (eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_conv,dfdiv")
+ (const_string "fe_group")
+ (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb") (const_string "co_group")]
+ (const_string "none")))
+;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
+;; so these do not belong in an insn group, although they are modeled
+;; with their own define_insn_reservations.
;; Indicate what precision must be selected in fpscr for this insn, if any.
(define_attr "fp_mode" "single,double,none" (const_string "none"))
+;; Indicate if the fpu mode is set by this instruction
+;; "unknown" must have the value as "none" in fp_mode, and means
+;; that the instruction/abi has left the processor in an unknown
+;; state.
+;; "none" means that nothing has changed and no mode is set.
+;; This attribute is only used for the Renesas ABI.
+(define_attr "fp_set" "single,double,unknown,none" (const_string "none"))
+
; If a conditional branch destination is within -252..258 bytes away
; from the instruction it can be 2 bytes long. Something in the
; range -4090..4100 bytes can be 6 bytes long. All other conditional
(eq_attr "type" "jump")
(cond [(eq_attr "med_branch_p" "yes")
(const_int 2)
- (and (eq (symbol_ref "GET_CODE (PREV_INSN (insn))")
+ (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
(symbol_ref "INSN"))
- (eq (symbol_ref "INSN_CODE (PREV_INSN (insn))")
+ (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
(symbol_ref "code_for_indirect_jump_scratch")))
(if_then_else (eq_attr "braf_branch_p" "yes")
(const_int 6)
(ne (symbol_ref ("flag_pic")) (const_int 0))
(const_int 22)
] (const_int 14))
- (eq_attr "type" "pt")
+ (eq_attr "type" "pt_media")
(if_then_else (ne (symbol_ref "TARGET_SHMEDIA64") (const_int 0))
(const_int 20) (const_int 12))
] (if_then_else (ne (symbol_ref "TARGET_SHMEDIA") (const_int 0))
;; We only do this for SImode loads of general registers, to make the work
;; for ADJUST_COST easier.
(define_function_unit "memory" 1 0
- (and (eq_attr "issues" "1")
+ (and (eq_attr "pipe_model" "sh1")
(eq_attr "type" "load_si,pcload_si"))
3 2)
(define_function_unit "memory" 1 0
- (and (eq_attr "issues" "1")
+ (and (eq_attr "pipe_model" "sh1")
(eq_attr "type" "load,pcload,pload,store,pstore"))
2 2)
(define_function_unit "int" 1 0
- (and (eq_attr "issues" "1") (eq_attr "type" "arith3,arith3b")) 3 3)
+ (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "arith3,arith3b")) 3 3)
(define_function_unit "int" 1 0
- (and (eq_attr "issues" "1") (eq_attr "type" "dyn_shift")) 2 2)
+ (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "dyn_shift")) 2 2)
(define_function_unit "int" 1 0
- (and (eq_attr "issues" "1") (eq_attr "type" "!arith3,arith3b,dyn_shift")) 1 1)
+ (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "!arith3,arith3b,dyn_shift")) 1 1)
;; ??? These are approximations.
(define_function_unit "mpy" 1 0
- (and (eq_attr "issues" "1") (eq_attr "type" "smpy")) 2 2)
+ (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "smpy")) 2 2)
(define_function_unit "mpy" 1 0
- (and (eq_attr "issues" "1") (eq_attr "type" "dmpy")) 3 3)
+ (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "dmpy")) 3 3)
(define_function_unit "fp" 1 0
- (and (eq_attr "issues" "1") (eq_attr "type" "fp,fmove")) 2 1)
+ (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "fp,fmove")) 2 1)
(define_function_unit "fp" 1 0
- (and (eq_attr "issues" "1") (eq_attr "type" "fdiv")) 13 12)
-
-
-;; SH4 scheduling
-;; The SH4 is a dual-issue implementation, thus we have to multiply all
-;; costs by at least two.
-;; There will be single increments of the modeled that don't correspond
-;; to the actual target ;; whenever two insns to be issued depend one a
-;; single resource, and the scheduler picks to be the first one.
-;; If we multiplied the costs just by two, just two of these single
-;; increments would amount to an actual cycle. By picking a larger
-;; factor, we can ameliorate the effect; However, we then have to make sure
-;; that only two insns are modeled as issued per actual cycle.
-;; Moreover, we need a way to specify the latency of insns that don't
-;; use an actual function unit.
-;; We use an 'issue' function unit to do that, and a cost factor of 10.
-
-(define_function_unit "issue" 2 0
- (and (eq_attr "issues" "2") (eq_attr "type" "!nil,arith3"))
- 10 10)
-
-(define_function_unit "issue" 2 0
- (and (eq_attr "issues" "2") (eq_attr "type" "arith3"))
- 30 30)
-
-;; There is no point in providing exact scheduling information about branches,
-;; because they are at the starts / ends of basic blocks anyways.
-
-;; Some insns cannot be issued before/after another insn in the same cycle,
-;; irrespective of the type of the other insn.
-
-;; default is dual-issue, but can't be paired with an insn that
-;; uses multiple function units.
-(define_function_unit "single_issue" 1 0
- (and (eq_attr "issues" "2")
- (eq_attr "type" "!smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul,call,sfunc,arith3,arith3b"))
- 1 10
- [(eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul")])
-
-(define_function_unit "single_issue" 1 0
- (and (eq_attr "issues" "2")
- (eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul"))
- 10 10
- [(const_int 1)])
-
-;; arith3 insns are always pairable at the start, but not inecessarily at
-;; the end; however, there doesn't seem to be a way to express that.
-(define_function_unit "single_issue" 1 0
- (and (eq_attr "issues" "2")
- (eq_attr "type" "arith3"))
- 30 20
- [(const_int 1)])
-
-;; arith3b insn are pairable at the end and have latency that prevents pairing
-;; with the following branch, but we don't want this latency be respected;
-;; When the following branch is immediately adjacent, we can redirect the
-;; internal branch, which is likly to be a larger win.
-(define_function_unit "single_issue" 1 0
- (and (eq_attr "issues" "2")
- (eq_attr "type" "arith3b"))
- 20 20
- [(const_int 1)])
-
-;; calls introduce a longisch delay that is likely to flush the pipelines.
-(define_function_unit "single_issue" 1 0
- (and (eq_attr "issues" "2")
- (eq_attr "type" "call,sfunc"))
- 160 160
- [(eq_attr "type" "!call") (eq_attr "type" "call")])
+ (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "fdiv")) 13 12)
-;; Load and store instructions have no alignment peculiarities for the SH4,
-;; but they use the load-store unit, which they share with the fmove type
-;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
-;; Loads have a latency of two.
-;; However, call insns can only paired with a preceding insn, and have
-;; a delay slot, so that we want two more insns to be scheduled between the
-;; load of the function address and the call. This is equivalent to a
-;; latency of three.
-;; We cannot use a conflict list for this, because we need to distinguish
-;; between the actual call address and the function arguments.
-;; ADJUST_COST can only properly handle reductions of the cost, so we
-;; use a latency of three here, which gets multiplied by 10 to yield 30.
-;; We only do this for SImode loads of general registers, to make the work
-;; for ADJUST_COST easier.
-;; When specifying different latencies for different insns using the
-;; the same function unit, genattrtab.c assumes a 'FIFO constraint'
-;; so that the blockage is at least READY-COST (E) + 1 - READY-COST (C)
-;; for an executing insn E and a candidate insn C.
-;; Therefore, we define three different function units for load_store:
-;; load_store, load and load_si.
-
-(define_function_unit "load_si" 1 0
- (and (eq_attr "issues" "2")
- (eq_attr "type" "load_si,pcload_si")) 30 10)
-(define_function_unit "load" 1 0
- (and (eq_attr "issues" "2")
- (eq_attr "type" "load,pcload,pload")) 20 10)
-(define_function_unit "load_store" 1 0
- (and (eq_attr "issues" "2")
- (eq_attr "type" "load_si,pcload_si,load,pcload,pload,store,pstore,fmove"))
- 10 10)
+;; SH-5 SHmedia scheduling
+;; When executing SHmedia code, the SH-5 is a fairly straightforward
+;; single-issue machine. It has four pipelines, the branch unit (br),
+;; the integer and multimedia unit (imu), the load/store unit (lsu), and
+;; the floating point unit (fpu).
+;; Here model the instructions with a latency greater than one cycle.
-(define_function_unit "int" 1 0
- (and (eq_attr "issues" "2") (eq_attr "type" "arith,dyn_shift")) 10 10)
+;; Every instruction on SH-5 occupies the issue resource for at least one
+;; cycle.
+(define_function_unit "sh5issue" 1 0
+ (and (eq_attr "pipe_model" "sh5media")
+ (eq_attr "type" "!pt_media,ptabs_media,invalidate_line_media,dmpy_media,load_media,fload_media,fcmp_media,fmove_media,fparith_media,dfparith_media,fpconv_media,dfpconv_media,dfmul_media,store_media,fstore_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media")) 1 1)
-;; Again, we have to pretend a lower latency for the "int" unit to avoid a
-;; spurious FIFO constraint; the multiply instructions use the "int"
-;; unit actually only for two cycles.
-(define_function_unit "int" 1 0
- (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 20 20)
+;; Specify the various types of instruction which have latency > 1
+(define_function_unit "sh5issue" 1 0
+ (and (eq_attr "pipe_model" "sh5media")
+ (eq_attr "type" "mcmp_media")) 2 1)
-;; We use a fictous "mpy" unit to express the actual latency.
-(define_function_unit "mpy" 1 0
- (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 20)
-
-;; Again, we have to pretend a lower latency for the "int" unit to avoid a
-;; spurious FIFO constraint.
-(define_function_unit "int" 1 0
- (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 10 10)
-
-;; We use a fictous "gp_fpul" unit to express the actual latency.
-(define_function_unit "gp_fpul" 1 0
- (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 20 10)
-
-;; ??? multiply uses the floating point unit, but with a two cycle delay.
-;; Thus, a simple single-precision fp operation could finish if issued in
-;; the very next cycle, but stalls when issued two or three cycles later.
-;; Similarily, a divide / sqrt can work without stalls if issued in
-;; the very next cycle, while it would have to block if issued two or
-;; three cycles later.
-;; There is no way to model this with gcc's function units. This problem is
-;; actually mentioned in md.texi. Tackling this problem requires first that
-;; it is possible to speak about the target in an open discussion.
-;;
-;; However, simple double-precision operations always conflict.
-
-(define_function_unit "fp" 1 0
- (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 40
- [(eq_attr "type" "dfp_cmp,dfp_conv,dfp_arith")])
-
-;; The "fp" unit is for pipeline stages F1 and F2.
+(define_function_unit "sh5issue" 1 0
+ (and (eq_attr "pipe_model" "sh5media")
+ (eq_attr "type" "dmpy_media,load_media,fcmp_media,mac_media")) 3 1)
+;; but see sh_adjust_cost for mac_media exception.
-(define_function_unit "fp" 1 0
- (and (eq_attr "issues" "2") (eq_attr "type" "fp")) 30 10)
+(define_function_unit "sh5issue" 1 0
+ (and (eq_attr "pipe_model" "sh5media")
+ (eq_attr "type" "fload_media,fmove_media")) 4 1)
-;; Again, we have to pretend a lower latency for the "fp" unit to avoid a
-;; spurious FIFO constraint; the bulk of the fdiv type insns executes in
-;; the F3 stage.
-(define_function_unit "fp" 1 0
- (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 30 10)
+(define_function_unit "sh5issue" 1 0
+ (and (eq_attr "pipe_model" "sh5media")
+ (eq_attr "type" "d2mpy_media")) 4 2)
-;; The "fdiv" function unit models the aggregate effect of the F1, F2 and F3
-;; pipeline stages on the pipelining of fdiv/fsqrt insns.
-;; We also use it to give the actual latency here.
-;; fsqrt is actually one cycle faster than fdiv (and the value used here),
-;; but that will hardly matter in practice for scheduling.
-(define_function_unit "fdiv" 1 0
- (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 120 100)
+(define_function_unit "sh5issue" 1 0
+ (and (eq_attr "pipe_model" "sh5media")
+ (eq_attr "type" "pt_media,ptabs_media")) 5 1)
-;; There is again a late use of the "fp" unit by [d]fdiv type insns
-;; that we can't express.
+(define_function_unit "sh5issue" 1 0
+ (and (eq_attr "pipe_model" "sh5media")
+ (eq_attr "type" "fparith_media,dfparith_media,fpconv_media,dfpconv_media")) 6 1)
-(define_function_unit "fp" 1 0
- (and (eq_attr "issues" "2") (eq_attr "type" "dfp_cmp,dfp_conv")) 40 20)
+(define_function_unit "sh5issue" 1 0
+ (and (eq_attr "pipe_model" "sh5media")
+ (eq_attr "type" "invalidate_line_media")) 7 7)
-(define_function_unit "fp" 1 0
- (and (eq_attr "issues" "2") (eq_attr "type" "dfp_arith")) 80 60)
+(define_function_unit "sh5issue" 1 0
+ (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfmul_media")) 9 4)
-(define_function_unit "fp" 1 0
- (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 10)
+(define_function_unit "sh5issue" 1 0
+ (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "atrans_media")) 10 5)
-(define_function_unit "fdiv" 1 0
- (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 210)
+;; Floating-point divide and square-root occupy an additional resource,
+;; which is not internally pipelined. However, other instructions
+;; can continue to issue.
+(define_function_unit "sh5fds" 1 0
+ (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "fdiv_media")) 19 19)
-;; This should be enough for pt insns to be moved 5 insns ahead of
-;; corresponding branches.
-(define_function_unit "pt" 1 0
- (eq_attr "type" "pt,ptabs") 10 2)
+(define_function_unit "sh5fds" 1 0
+ (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfdiv_media")) 35 35)
; Definitions for filling branch delay slots.
(eq_attr "length" "2") (const_string "yes")
] (const_string "no")))
+(define_attr "cond_delay_slot" "yes,no"
+ (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes")
+ ] (const_string "no")))
+
(define_attr "is_sfunc" ""
(if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
+(define_attr "is_mac_media" ""
+ (if_then_else (eq_attr "type" "mac_media") (const_int 1) (const_int 0)))
+
+(define_attr "branch_zero" "yes,no"
+ (cond [(eq_attr "type" "!cbranch") (const_string "no")
+ (ne (symbol_ref "(next_active_insn (insn)\
+ == (prev_active_insn\
+ (XEXP (SET_SRC (PATTERN (insn)), 1))))\
+ && get_attr_length (next_active_insn (insn)) == 2")
+ (const_int 0))
+ (const_string "yes")]
+ (const_string "no")))
+
+;; SH4 Double-precision computation with double-precision result -
+;; the two halves are ready at different times.
+(define_attr "dfp_comp" "yes,no"
+ (cond [(eq_attr "type" "dfp_arith,dfp_conv,dfdiv") (const_string "yes")]
+ (const_string "no")))
+
+;; Insns for which the latency of a preceding fp insn is decreased by one.
+(define_attr "late_fp_use" "yes,no" (const_string "no"))
+;; And feeding insns for which this relevant.
+(define_attr "any_fp_comp" "yes,no"
+ (cond [(eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_conv,dfdiv")
+ (const_string "yes")]
+ (const_string "no")))
+
+(define_attr "any_int_load" "yes,no"
+ (cond [(eq_attr "type" "load,load_si,pcload,pcload_si")
+ (const_string "yes")]
+ (const_string "no")))
+
(define_delay
(eq_attr "needs_delay_slot" "yes")
[(eq_attr "in_delay_slot" "yes") (nil) (nil)])
(define_delay
(and (eq_attr "type" "cbranch")
(ne (symbol_ref "TARGET_SH2") (const_int 0)))
- [(eq_attr "in_delay_slot" "yes") (eq_attr "in_delay_slot" "yes") (nil)])
+ ;; SH2e has a hardware bug that pretty much prohibits the use of
+ ;; annuled delay slots.
+ [(eq_attr "in_delay_slot" "yes") (and (eq_attr "cond_delay_slot" "yes")
+ (not (eq_attr "cpu" "sh2e"))) (nil)])
\f
;; -------------------------------------------------------------------------
;; SImode signed integer comparisons
(define_insn ""
[(set (reg:SI T_REG)
(eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
- (match_operand:SI 1 "arith_operand" "L,r"))
+ (match_operand:SI 1 "arith_operand" "K08,r"))
(const_int 0)))]
"TARGET_SH1"
"tst %1,%0"
- [(set_attr "insn_class" "mt_group")])
+ [(set_attr "type" "mt_group")])
;; ??? Perhaps should only accept reg/constant if the register is reg 0.
;; That would still allow reload to create cmpi instructions, but would
(define_insn "cmpeqsi_t"
[(set (reg:SI T_REG)
(eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
- (match_operand:SI 1 "arith_operand" "N,rI,r")))]
+ (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
"TARGET_SH1"
"@
tst %0,%0
cmp/eq %1,%0
cmp/eq %1,%0"
- [(set_attr "insn_class" "mt_group,mt_group,mt_group")])
+ [(set_attr "type" "mt_group")])
(define_insn "cmpgtsi_t"
[(set (reg:SI T_REG)
"@
cmp/gt %1,%0
cmp/pl %0"
- [(set_attr "insn_class" "mt_group,mt_group")])
+ [(set_attr "type" "mt_group")])
(define_insn "cmpgesi_t"
[(set (reg:SI T_REG)
"@
cmp/ge %1,%0
cmp/pz %0"
- [(set_attr "insn_class" "mt_group,mt_group")])
+ [(set_attr "type" "mt_group")])
;; -------------------------------------------------------------------------
;; SImode unsigned integer comparisons
(match_operand:SI 1 "arith_reg_operand" "r")))]
"TARGET_SH1"
"cmp/hs %1,%0"
- [(set_attr "insn_class" "mt_group")])
+ [(set_attr "type" "mt_group")])
(define_insn "cmpgtusi_t"
[(set (reg:SI T_REG)
(match_operand:SI 1 "arith_reg_operand" "r")))]
"TARGET_SH1"
"cmp/hi %1,%0"
- [(set_attr "insn_class" "mt_group")])
+ [(set_attr "type" "mt_group")])
;; We save the compare operands in the cmpxx patterns and use them when
;; we generate the branch.
(define_split
[(set (reg:SI T_REG)
- (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
- (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
+ (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
+ (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
;; If we applied this split when not optimizing, it would only be
;; applied during the machine-dependent reorg, when no new basic blocks
;; may be created.
cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
cmp/pz\\t%S0"
[(set_attr "length" "8,2")
- (set_attr "type" "arith3,arith")])
+ (set_attr "type" "arith3,mt_group")])
\f
;; -------------------------------------------------------------------------
;; DImode unsigned integer comparisons
(set_attr "type" "arith3")])
(define_insn "cmpeqdi_media"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (eq:DI (match_operand:DI 1 "register_operand" "%r,r")
- (match_operand:DI 2 "arith_reg_or_0_operand" "N,r")))]
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (eq:DI (match_operand:DI 1 "register_operand" "%r")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "Nr")))]
"TARGET_SHMEDIA"
- "@
- cmpeq %1, r63, %0
- cmpeq %1, %2, %0")
+ "cmpeq %1, %N2, %0"
+ [(set_attr "type" "cmp_media")])
(define_insn "cmpgtdi_media"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
- (gt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "N,r,r")
- (match_operand:DI 2 "arith_reg_or_0_operand" "r,N,r")))]
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (gt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
"TARGET_SHMEDIA"
- "@
- cmpgt r63, %2, %0
- cmpgt %1, r63, %0
- cmpgt %1, %2, %0")
+ "cmpgt %N1, %N2, %0"
+ [(set_attr "type" "cmp_media")])
(define_insn "cmpgtudi_media"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
- (gtu:DI (match_operand:DI 1 "arith_reg_or_0_operand" "N,r,r")
- (match_operand:DI 2 "arith_reg_or_0_operand" "r,N,r")))]
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (gtu:DI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
"TARGET_SHMEDIA"
- "@
- cmpgtu r63, %2, %0
- cmpgtu %1, r63, %0
- cmpgtu %1, %2, %0")
+ "cmpgtu %N1, %N2, %0"
+ [(set_attr "type" "cmp_media")])
;; We save the compare operands in the cmpxx patterns and use them when
;; we generate the branch.
;; if op1 == 0, and cmvne does it if op1 != 0.
(define_insn "movdicc_false"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (if_then_else:DI (eq (match_operand:DI 1 "register_operand" "r")
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (if_then_else:DI (eq (match_operand:DI 1 "arith_reg_operand" "r")
(const_int 0))
- (match_operand:DI 2 "register_operand" "r")
- (match_operand:DI 3 "register_operand" "0")))]
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
+ (match_operand:DI 3 "arith_reg_operand" "0")))]
"TARGET_SHMEDIA"
- "cmveq %1, %2, %0")
+ "cmveq %1, %N2, %0"
+ [(set_attr "type" "arith_media")])
(define_insn "movdicc_true"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (if_then_else:DI (ne (match_operand:DI 1 "register_operand" "r")
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (if_then_else:DI (ne (match_operand:DI 1 "arith_reg_operand" "r")
(const_int 0))
- (match_operand:DI 2 "register_operand" "r")
- (match_operand:DI 3 "register_operand" "0")))]
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
+ (match_operand:DI 3 "arith_reg_operand" "0")))]
"TARGET_SHMEDIA"
- "cmvne %1, %2, %0")
+ "cmvne %1, %N2, %0"
+ [(set_attr "type" "arith_media")])
(define_expand "movdicc"
[(set (match_operand:DI 0 "register_operand" "")
(define_insn "*adddi3_media"
[(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
(plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
- (match_operand:DI 2 "arith_operand" "r,P")))]
+ (match_operand:DI 2 "arith_operand" "r,I10")))]
"TARGET_SHMEDIA"
"@
add %1, %2, %0
- addi %1, %2, %0")
+ addi %1, %2, %0"
+ [(set_attr "type" "arith_media")])
-(define_insn "*adddi3z_media"
- [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
+(define_insn "adddi3z_media"
+ [(set (match_operand:DI 0 "arith_reg_operand" "=r")
(zero_extend:DI
- (plus:SI (match_operand:SI 1 "arith_reg_operand" "r,r")
- (match_operand:SI 2 "arith_reg_or_0_operand" "r,n"))))]
+ (plus:SI (match_operand:SI 1 "extend_reg_operand" "r")
+ (match_operand:SI 2 "extend_reg_or_0_operand" "rN"))))]
"TARGET_SHMEDIA"
- "@
- addz.l %1, %2, %0
- addz.l %1, r63, %0")
-
+ "addz.l %1, %N2, %0"
+ [(set_attr "type" "arith_media")])
+
(define_insn "adddi3_compact"
- [(set (match_operand:DI 0 "arith_reg_operand" "=r")
+ [(set (match_operand:DI 0 "arith_reg_operand" "=&r")
(plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
(match_operand:DI 2 "arith_reg_operand" "r")))
(clobber (reg:SI T_REG))]
[(set_attr "length" "6")])
(define_split
- [(set (match_operand:DI 0 "arith_reg_operand" "=r")
- (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
- (match_operand:DI 2 "arith_reg_operand" "r")))
+ [(set (match_operand:DI 0 "arith_reg_operand" "")
+ (plus:DI (match_operand:DI 1 "arith_reg_operand" "")
+ (match_operand:DI 2 "arith_reg_operand" "")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(const_int 0)]
(ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
"TARGET_SH1"
"addc %2,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_insn "addc1"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(clobber (reg:SI T_REG))]
"TARGET_SH1"
"addc %2,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_expand "addsi3"
[(set (match_operand:SI 0 "arith_reg_operand" "")
(define_insn "addsi3_media"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
- (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r")
- (match_operand:SI 2 "arith_operand" "r,P")))]
+ (plus:SI (match_operand:SI 1 "extend_reg_operand" "%r,r")
+ (match_operand:SI 2 "arith_operand" "r,I10")))]
"TARGET_SHMEDIA"
"@
add.l %1, %2, %0
- addi.l %1, %2, %0")
-
+ addi.l %1, %2, %0"
+ [(set_attr "type" "arith_media")])
+
(define_insn "*addsi3_compact"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(plus:SI (match_operand:SI 1 "arith_operand" "%0")
- (match_operand:SI 2 "arith_operand" "rI")))]
+ (match_operand:SI 2 "arith_operand" "rI08")))]
"TARGET_SH1"
"add %2,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
;; -------------------------------------------------------------------------
;; Subtraction instructions
(define_expand "subdi3"
[(set (match_operand:DI 0 "arith_reg_operand" "")
- (minus:DI (match_operand:DI 1 "arith_reg_operand" "")
+ (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "")
(match_operand:DI 2 "arith_reg_operand" "")))]
""
"
{
if (TARGET_SH1)
{
+ operands[1] = force_reg (DImode, operands[1]);
emit_insn (gen_subdi3_compact (operands[0], operands[1], operands[2]));
DONE;
}
}")
-
+
(define_insn "*subdi3_media"
[(set (match_operand:DI 0 "arith_reg_operand" "=r")
- (minus:DI (match_operand:DI 1 "arith_reg_operand" "r")
+ (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
(match_operand:DI 2 "arith_reg_operand" "r")))]
"TARGET_SHMEDIA"
- "sub %1, %2, %0")
-
+ "sub %N1, %2, %0"
+ [(set_attr "type" "arith_media")])
+
(define_insn "subdi3_compact"
- [(set (match_operand:DI 0 "arith_reg_operand" "=r")
+ [(set (match_operand:DI 0 "arith_reg_operand" "=&r")
(minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
(match_operand:DI 2 "arith_reg_operand" "r")))
(clobber (reg:SI T_REG))]
[(set_attr "length" "6")])
(define_split
- [(set (match_operand:DI 0 "arith_reg_operand" "=r")
- (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
- (match_operand:DI 2 "arith_reg_operand" "r")))
+ [(set (match_operand:DI 0 "arith_reg_operand" "")
+ (minus:DI (match_operand:DI 1 "arith_reg_operand" "")
+ (match_operand:DI 2 "arith_reg_operand" "")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(const_int 0)]
(gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
"TARGET_SH1"
"subc %2,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_insn "subc1"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(clobber (reg:SI T_REG))]
"TARGET_SH1"
"subc %2,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_insn "*subsi3_internal"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(match_operand:SI 2 "arith_reg_operand" "r")))]
"TARGET_SH1"
"sub %2,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_insn "*subsi3_media"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
- (minus:SI (match_operand:SI 1 "arith_reg_operand" "r")
- (match_operand:SI 2 "arith_reg_operand" "r")))]
+ (minus:SI (match_operand:SI 1 "extend_reg_or_0_operand" "rN")
+ (match_operand:SI 2 "extend_reg_operand" "r")))]
"TARGET_SHMEDIA"
- "sub.l %1, %2, %0")
+ "sub.l %N1, %2, %0"
+ [(set_attr "type" "arith_media")])
;; Convert `constant - reg' to `neg rX; add rX, #const' since this
;; will sometimes save one instruction. Otherwise we might get
}
if (TARGET_SHMEDIA)
{
- if (no_new_pseudos && ! arith_reg_operand (operands[1], SImode))
+ if (no_new_pseudos && ! arith_reg_or_0_operand (operands[1], SImode))
FAIL;
- operands[1] = force_reg (SImode, operands[1]);
+ if (operands[1] != const0_rtx)
+ operands[1] = force_reg (SImode, operands[1]);
}
}")
\f
;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
;; also has an effect on the register that holds the address of the sfunc.
-;; To make this work, we have an extra dummy insns that shows the use
+;; To make this work, we have an extra dummy insn that shows the use
;; of this register for reorg.
(define_insn "use_sfunc_addr"
[(set (reg:SI PR_REG)
- (unspec [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
+ (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
"TARGET_SH1"
""
[(set_attr "length" "0")])
[(set_attr "type" "sfunc")
(set_attr "needs_delay_slot" "yes")])
+; Since shmedia-nofpu code could be linked against shcompact code, and
+; the udivsi3 libcall has the same name, we must consider all registers
+; clobbered that are in the union of the registers clobbered by the
+; shmedia and the shcompact implementation. Note, if the shcompact
+; implementation actually used shcompact code, we'd need to clobber
+; also r23 and fr23.
(define_insn "udivsi3_i1_media"
[(set (match_operand:SI 0 "register_operand" "=z")
(udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
(clobber (reg:SI T_MEDIA_REG))
(clobber (reg:SI PR_MEDIA_REG))
- (clobber (reg:SI R4_REG))
+ (clobber (reg:SI R20_REG))
+ (clobber (reg:SI R21_REG))
+ (clobber (reg:SI R22_REG))
(clobber (reg:DI TR0_REG))
(clobber (reg:DI TR1_REG))
(clobber (reg:DI TR2_REG))
(set_attr "needs_delay_slot" "yes")])
(define_expand "udivsi3_i4_media"
- [(set (match_dup 2) (zero_extend:DI (reg:SI R4_REG)))
- (set (match_dup 3) (zero_extend:DI (reg:SI R5_REG)))
- (set (match_dup 4) (float:DF (match_dup 2)))
+ [(set (match_dup 3)
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
+ (set (match_dup 4)
+ (zero_extend:DI (match_operand:SI 2 "register_operand" "")))
(set (match_dup 5) (float:DF (match_dup 3)))
- (set (match_dup 6) (div:DF (match_dup 4) (match_dup 5)))
- (set (subreg:DI (match_operand:SI 0 "register_operand" "=r") 0)
- (fix:DI (match_dup 6)))]
+ (set (match_dup 6) (float:DF (match_dup 4)))
+ (set (match_dup 7) (div:DF (match_dup 5) (match_dup 6)))
+ (set (match_dup 8) (fix:DI (match_dup 7)))
+ (set (match_operand:SI 0 "register_operand" "")
+ (truncate:SI (match_dup 8)))]
"TARGET_SHMEDIA_FPU"
"
{
- operands[2] = gen_reg_rtx (DImode);
operands[3] = gen_reg_rtx (DImode);
- operands[4] = gen_reg_rtx (DFmode);
+ operands[4] = gen_reg_rtx (DImode);
operands[5] = gen_reg_rtx (DFmode);
operands[6] = gen_reg_rtx (DFmode);
+ operands[7] = gen_reg_rtx (DFmode);
+ operands[8] = gen_reg_rtx (DImode);
}")
(define_insn "udivsi3_i4"
operands[3] = gen_reg_rtx (Pmode);
/* Emit the move of the address to a pseudo outside of the libcall. */
- if (TARGET_HARD_SH4 && TARGET_SH3E)
+ if (TARGET_HARD_SH4 && TARGET_SH2E)
{
- emit_move_insn (operands[3],
- gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
+ emit_move_insn (operands[3], function_symbol (\"__udivsi3_i4\"));
if (TARGET_FPU_SINGLE)
last = gen_udivsi3_i4_single (operands[0], operands[3]);
else
last = gen_udivsi3_i4 (operands[0], operands[3]);
}
else if (TARGET_SHMEDIA_FPU)
- last = gen_udivsi3_i4_media (operands[0]);
+ {
+ operands[1] = force_reg (SImode, operands[1]);
+ operands[2] = force_reg (SImode, operands[2]);
+ emit_insn (gen_udivsi3_i4_media (operands[0], operands[1], operands[2]));
+ DONE;
+ }
else if (TARGET_SH5)
{
emit_move_insn (operands[3],
- gen_rtx_SYMBOL_REF (Pmode,
- (TARGET_FPU_ANY
- ? \"__udivsi3_i4\"
- : \"__udivsi3\")));
+ function_symbol (TARGET_FPU_ANY
+ ? \"__udivsi3_i4\"
+ : \"__udivsi3\"));
if (TARGET_SHMEDIA)
last = gen_udivsi3_i1_media (operands[0],
}
else
{
- emit_move_insn (operands[3],
- gen_rtx_SYMBOL_REF (SImode, \"__udivsi3\"));
+ emit_move_insn (operands[3], function_symbol (\"__udivsi3\"));
last = gen_udivsi3_i1 (operands[0], operands[3]);
}
first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
[(set_attr "type" "sfunc")
(set_attr "needs_delay_slot" "yes")])
+; Since shmedia-nofpu code could be linked against shcompact code, and
+; the sdivsi3 libcall has the same name, we must consider all registers
+; clobbered that are in the union of the registers clobbered by the
+; shmedia and the shcompact implementation. Note, if the shcompact
+; implementation actually used shcompact code, we'd need to clobber
+; also r22, r23 and fr23.
(define_insn "divsi3_i1_media"
[(set (match_operand:SI 0 "register_operand" "=z")
(div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
(clobber (reg:SI R1_REG))
(clobber (reg:SI R2_REG))
(clobber (reg:SI R3_REG))
+ (clobber (reg:SI R20_REG))
+ (clobber (reg:SI R21_REG))
(clobber (reg:DI TR0_REG))
(clobber (reg:DI TR1_REG))
(clobber (reg:DI TR2_REG))
(use (match_operand:DI 1 "target_operand" "b"))]
"TARGET_SHMEDIA && ! TARGET_SHMEDIA_FPU"
- "blink %1, r18")
+ "blink %1, r18"
+ [(set_attr "type" "sfunc")])
(define_expand "divsi3_i4_media"
[(set (match_dup 3) (float:DF (match_operand:SI 1 "register_operand" "r")))
""
"
{
- rtx first = 0, last;
+ rtx first, last;
operands[3] = gen_reg_rtx (Pmode);
/* Emit the move of the address to a pseudo outside of the libcall. */
- if (TARGET_HARD_SH4 && TARGET_SH3E)
+ if (TARGET_HARD_SH4 && TARGET_SH2E)
{
- emit_move_insn (operands[3],
- gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
+ emit_move_insn (operands[3], function_symbol (\"__sdivsi3_i4\"));
if (TARGET_FPU_SINGLE)
last = gen_divsi3_i4_single (operands[0], operands[3]);
else
{
operands[1] = force_reg (SImode, operands[1]);
operands[2] = force_reg (SImode, operands[2]);
- last = gen_divsi3_i4_media (operands[0], operands[1], operands[2]);
- first = XVECEXP (last, 0, 0);
+ emit_insn (gen_divsi3_i4_media (operands[0], operands[1], operands[2]));
+ DONE;
}
else if (TARGET_SH5)
{
emit_move_insn (operands[3],
- gen_rtx_SYMBOL_REF (Pmode,
- (TARGET_FPU_ANY
- ? \"__sdivsi3_i4\"
- : \"__sdivsi3\")));
+ function_symbol (TARGET_FPU_ANY
+ ? \"__sdivsi3_i4\"
+ : \"__sdivsi3\"));
if (TARGET_SHMEDIA)
- last = gen_divsi3_i1_media (operands[0],
+ last = gen_divsi3_i1_media (operands[0],
Pmode == DImode
? operands[3]
: gen_rtx_SUBREG (DImode, operands[3],
}
else
{
- emit_move_insn (operands[3], gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3\"));
+ emit_move_insn (operands[3], function_symbol (\"__sdivsi3\"));
last = gen_divsi3_i1 (operands[0], operands[3]);
}
- if (! first)
- {
- first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
- emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
- }
+ first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
+ emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
last = emit_insn (last);
/* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
invariant code motion can move it. */
invariant code motion can move it. */
REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
+ /* expand_binop can't find a suitable code in umul_widen_optab to
+ make a REG_EQUAL note from, so make one here.
+ See also smulsi3_highpart.
+ ??? Alternatively, we could put this at the calling site of expand_binop,
+ i.e. expand_expr. */
+ REG_NOTES (last)
+ = gen_rtx_EXPR_LIST (REG_EQUAL, copy_rtx (SET_SRC (single_set (first))),
+ REG_NOTES (last));
DONE;
}")
invariant code motion can move it. */
REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
+ /* expand_binop can't find a suitable code in umul_widen_optab to
+ make a REG_EQUAL note from, so make one here.
+ See also smulsi3_highpart.
+ ??? Alternatively, we could put this at the calling site of expand_binop,
+ i.e. expand_expr. */
+ REG_NOTES (last)
+ = gen_rtx_EXPR_LIST (REG_EQUAL, copy_rtx (SET_SRC (single_set (first))),
+ REG_NOTES (last));
DONE;
}")
{
/* The address must be set outside the libcall,
since it goes into a pseudo. */
- rtx sym = gen_rtx_SYMBOL_REF (SImode, \"__mulsi3\");
+ rtx sym = function_symbol (\"__mulsi3\");
rtx addr = force_reg (SImode, sym);
rtx insns = gen_mulsi3_call (operands[0], operands[1],
operands[2], addr);
- first = XVECEXP (insns, 0, 0);
- last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
- emit_insn (insns);
+ first = insns;
+ last = emit_insn (insns);
}
else
{
(define_insn "mulsidi3_media"
[(set (match_operand:DI 0 "arith_reg_operand" "=r")
- (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "%r"))
- (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
+ (mult:DI (sign_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
+ (sign_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
"TARGET_SHMEDIA"
- "muls.l %1, %2, %0")
-
+ "muls.l %1, %2, %0"
+ [(set_attr "type" "dmpy_media")])
+
(define_insn "mulsidi3_compact"
[(set (match_operand:DI 0 "arith_reg_operand" "=r")
(mult:DI
(define_insn "umulsidi3_media"
[(set (match_operand:DI 0 "arith_reg_operand" "=r")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "%r"))
- (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
+ (zero_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
"TARGET_SHMEDIA"
- "mulu.l %1, %2, %0")
-
+ "mulu.l %1, %2, %0"
+ [(set_attr "type" "dmpy_media")])
+
(define_insn "umulsidi3_compact"
[(set (match_operand:DI 0 "arith_reg_operand" "=r")
(mult:DI
REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
/* expand_binop can't find a suitable code in mul_highpart_optab to
make a REG_EQUAL note from, so make one here.
+ See also {,u}mulhisi.
??? Alternatively, we could put this at the calling site of expand_binop,
i.e. expand_mult_highpart. */
REG_NOTES (last)
;; Logical operations
;; -------------------------------------------------------------------------
-(define_insn ""
+(define_insn "*andsi3_compact"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
(and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
- (match_operand:SI 2 "logical_operand" "r,L")))]
+ (match_operand:SI 2 "logical_operand" "r,K08")))]
"TARGET_SH1"
"and %2,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
-;; If the constant is 255, then emit a extu.b instruction instead of an
+;; If the constant is 255, then emit an extu.b instruction instead of an
;; and, since that will give better code.
(define_expand "andsi3"
}
}")
-(define_insn "anddi3"
- [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
- (and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
- (match_operand:DI 2 "logical_operand" "r,P")))]
+(define_insn_and_split "anddi3"
+ [(set (match_operand:DI 0 "arith_reg_operand" "=r,r,r")
+ (and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r")
+ (match_operand:DI 2 "and_operand" "r,I10,J16")))]
"TARGET_SHMEDIA"
"@
and %1, %2, %0
- andi %1, %2, %0")
+ andi %1, %2, %0
+ #"
+ "reload_completed
+ && ! logical_operand (operands[2], DImode)"
+ [(const_int 0)]
+ "
+{
+ if (INTVAL (operands[2]) == (unsigned) 0xffffffff)
+ emit_insn (gen_mshflo_l_di (operands[0], operands[1], CONST0_RTX (DImode)));
+ else
+ emit_insn (gen_mshfhi_l_di (operands[0], CONST0_RTX (DImode), operands[1]));
+ DONE;
+}"
+ [(set_attr "type" "arith_media")])
-(define_insn "*andcdi3"
+(define_insn "andcdi3"
[(set (match_operand:DI 0 "arith_reg_operand" "=r")
(and:DI (match_operand:DI 1 "arith_reg_operand" "r")
(not:DI (match_operand:DI 2 "arith_reg_operand" "r"))))]
"TARGET_SHMEDIA"
- "andc %1,%2,%0")
+ "andc %1,%2,%0"
+ [(set_attr "type" "arith_media")])
(define_insn "iorsi3"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
(ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
- (match_operand:SI 2 "logical_operand" "r,L")))]
+ (match_operand:SI 2 "logical_operand" "r,K08")))]
"TARGET_SH1"
"or %2,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_insn "iordi3"
[(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
(ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
- (match_operand:DI 2 "logical_operand" "r,P")))]
+ (match_operand:DI 2 "logical_operand" "r,I10")))]
"TARGET_SHMEDIA"
"@
or %1, %2, %0
- ori %1, %2, %0")
+ ori %1, %2, %0"
+ [(set_attr "type" "arith_media")])
(define_insn "xorsi3"
[(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
(xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
- (match_operand:SI 2 "logical_operand" "L,r")))]
+ (match_operand:SI 2 "logical_operand" "K08,r")))]
"TARGET_SH1"
"xor %2,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_insn "xordi3"
[(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
(xor:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
- (match_operand:DI 2 "shmedia_6bit_operand" "r,O")))]
+ (match_operand:DI 2 "shmedia_6bit_operand" "r,I06")))]
"TARGET_SHMEDIA"
"@
xor %1, %2, %0
- xori %1, %2, %0")
+ xori %1, %2, %0"
+ [(set_attr "type" "arith_media")])
+
+;; Combiner bridge pattern for 2 * sign extend -> logical op -> truncate.
+;; converts 2 * sign extend -> logical op into logical op -> sign extend
+(define_split
+ [(set (match_operand:DI 0 "arith_reg_operand" "")
+ (sign_extend:DI (match_operator 4 "binary_logical_operator"
+ [(match_operand 1 "any_register_operand" "")
+ (match_operand 2 "any_register_operand" "")])))]
+ "TARGET_SHMEDIA"
+ [(set (match_dup 5) (match_dup 4))
+ (set (match_dup 0) (sign_extend:DI (match_dup 5)))]
+"
+{
+ enum machine_mode inmode = GET_MODE (operands[1]);
+ int offset = 0;
+
+ if (GET_CODE (operands[0]) == SUBREG)
+ {
+ offset = SUBREG_BYTE (operands[0]);
+ operands[0] = SUBREG_REG (operands[0]);
+ }
+ if (GET_CODE (operands[0]) != REG)
+ abort ();
+ if (! TARGET_LITTLE_ENDIAN)
+ offset += 8 - GET_MODE_SIZE (inmode);
+ operands[5] = gen_rtx_SUBREG (inmode, operands[0], offset);
+}")
\f
;; -------------------------------------------------------------------------
;; Shifts and rotates
;; -------------------------------------------------------------------------
+(define_expand "rotldi3"
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
+ (match_operand:HI 2 "mextr_bit_offset" "i")))]
+ "TARGET_SHMEDIA"
+ "if (! mextr_bit_offset (operands[2], HImode)) FAIL;")
+
+(define_insn "rotldi3_mextr"
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
+ (match_operand:HI 2 "mextr_bit_offset" "i")))]
+ "TARGET_SHMEDIA"
+ "*
+{
+ static char templ[16];
+
+ sprintf (templ, \"mextr%d\\t%%1,%%1,%%0\",
+ 8 - (int) (INTVAL (operands[2]) >> 3));
+ return templ;
+}"
+ [(set_attr "type" "arith_media")])
+
+(define_expand "rotrdi3"
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r")
+ (match_operand:HI 2 "mextr_bit_offset" "i")))]
+ "TARGET_SHMEDIA"
+ "if (! mextr_bit_offset (operands[2], HImode)) FAIL;")
+
+(define_insn "rotrdi3_mextr"
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r")
+ (match_operand:HI 2 "mextr_bit_offset" "i")))]
+ "TARGET_SHMEDIA"
+ "*
+{
+ static char templ[16];
+
+ sprintf (templ, \"mextr%d\\t%%1,%%1,%%0\", (int) INTVAL (operands[2]) >> 3);
+ return templ;
+}"
+ [(set_attr "type" "arith_media")])
+
(define_insn "rotlsi3_1"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
(lshiftrt:SI (match_dup 1) (const_int 31)))]
"TARGET_SH1"
"rotl %0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_insn "rotlsi3_31"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(clobber (reg:SI T_REG))]
"TARGET_SH1"
"rotr %0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_insn "rotlsi3_16"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(const_int 16)))]
"TARGET_SH1"
"swap.w %1,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_expand "rotlsi3"
[(set (match_operand:SI 0 "arith_reg_operand" "")
(const_int 8)))]
"TARGET_SH1"
"swap.b %1,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_expand "rotlhi3"
[(set (match_operand:HI 0 "arith_reg_operand" "")
(define_insn_and_split "ashlsi3_std"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,r,r,r")
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0")
- (match_operand:SI 2 "nonmemory_operand" "r,M,K,?ri")))
+ (match_operand:SI 2 "nonmemory_operand" "r,M,P27,?ri")))
(clobber (match_scratch:SI 3 "=X,X,X,&r"))]
"TARGET_SH3
|| (TARGET_SH1 && GET_CODE (operands[2]) == CONST_INT
- && CONST_OK_FOR_K (INTVAL (operands[2])))"
+ && CONST_OK_FOR_P27 (INTVAL (operands[2])))"
"@
shld %2,%0
add %0,%0
"TARGET_SH3
&& reload_completed
&& GET_CODE (operands[2]) == CONST_INT
- && ! CONST_OK_FOR_K (INTVAL (operands[2]))"
+ && ! CONST_OK_FOR_P27 (INTVAL (operands[2]))"
[(set (match_dup 3) (match_dup 2))
(parallel
[(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 3)))
(clobber (match_dup 4))])]
"operands[4] = gen_rtx_SCRATCH (SImode);"
[(set_attr "length" "*,*,*,4")
- (set_attr "type" "dyn_shift,arith,arith,arith")
- (set_attr "insn_class" "ex_group,ex_group,ex_group,ex_group")])
+ (set_attr "type" "dyn_shift,arith,arith,arith")])
(define_insn "ashlhi3_k"
[(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
(ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
- (match_operand:HI 2 "const_int_operand" "M,K")))]
- "TARGET_SH1 && CONST_OK_FOR_K (INTVAL (operands[2]))"
+ (match_operand:HI 2 "const_int_operand" "M,P27")))]
+ "TARGET_SH1 && CONST_OK_FOR_P27 (INTVAL (operands[2]))"
"@
add %0,%0
shll%O2 %0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_insn "ashlsi3_n"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
(const_string "6")]
(const_string "8")))
- (set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ (set_attr "type" "arith")])
(define_split
[(set (match_operand:SI 0 "arith_reg_operand" "")
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
- (match_operand:SI 2 "const_int_operand" "n")))
+ (match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(use (reg:SI R0_REG))]
(define_insn "ashlsi3_media"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
- (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r,r")
+ (ashift:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
(match_operand:SI 2 "nonmemory_operand" "r,n")))]
"TARGET_SHMEDIA"
"@
shlld.l %1, %2, %0
- shlli.l %1, %2, %0")
+ shlli.l %1, %2, %0"
+ [(set_attr "type" "arith_media")])
(define_expand "ashlsi3"
[(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
(define_split
[(set (match_operand:HI 0 "arith_reg_operand" "")
(ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
- (match_operand:HI 2 "const_int_operand" "n")))
+ (match_operand:HI 2 "const_int_operand" "")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(use (reg:SI R0_REG))]
(clobber (reg:SI T_REG))]
"TARGET_SH1 && INTVAL (operands[2]) == 1"
"shar %0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
;; We can't do HImode right shifts correctly unless we start out with an
;; explicit zero / sign extension; doing that would result in worse overall
[(set_attr "length" "4")])
(define_split
- [(set (match_operand:SI 0 "arith_reg_operand" "=r")
- (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
+ [(set (match_operand:SI 0 "arith_reg_operand" "")
+ (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
(const_int 16)))]
"TARGET_SH1"
[(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
[(set_attr "length" "4")])
(define_split
- [(set (match_operand:SI 0 "arith_reg_operand" "=r")
- (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
+ [(set (match_operand:SI 0 "arith_reg_operand" "")
+ (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
(const_int 31)))
(clobber (reg:SI T_REG))]
"TARGET_SH1"
(lt:SI (match_dup 1) (const_int 0)))]
"TARGET_SH1"
"shll %0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_insn "ashrsi3_d"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
"TARGET_SH3"
"shad %2,%0"
- [(set_attr "type" "dyn_shift")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "dyn_shift")])
(define_insn "ashrsi3_n"
[(set (reg:SI R4_REG)
(define_insn "ashrsi3_media"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
- (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r,r")
+ (ashiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
(match_operand:SI 2 "nonmemory_operand" "r,n")))]
"TARGET_SHMEDIA"
"@
shard.l %1, %2, %0
- shari.l %1, %2, %0")
+ shari.l %1, %2, %0"
+ [(set_attr "type" "arith_media")])
(define_expand "ashrsi3"
[(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
(neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
"TARGET_SH3"
"shld %2,%0"
- [(set_attr "type" "dyn_shift")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "dyn_shift")])
;; Only the single bit shift clobbers the T bit.
(clobber (reg:SI T_REG))]
"TARGET_SH1 && CONST_OK_FOR_M (INTVAL (operands[2]))"
"shlr %0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_insn "lshrsi3_k"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
- (match_operand:SI 2 "const_int_operand" "K")))]
- "TARGET_SH1 && CONST_OK_FOR_K (INTVAL (operands[2]))
+ (match_operand:SI 2 "const_int_operand" "P27")))]
+ "TARGET_SH1 && CONST_OK_FOR_P27 (INTVAL (operands[2]))
&& ! CONST_OK_FOR_M (INTVAL (operands[2]))"
"shlr%O2 %0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_insn "lshrsi3_n"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(define_split
[(set (match_operand:SI 0 "arith_reg_operand" "")
(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
- (match_operand:SI 2 "const_int_operand" "n")))
+ (match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(use (reg:SI R0_REG))]
(define_insn "lshrsi3_media"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
- (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r,r")
+ (lshiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
(match_operand:SI 2 "nonmemory_operand" "r,n")))]
"TARGET_SHMEDIA"
"@
shlrd.l %1, %2, %0
- shlri.l %1, %2, %0")
+ shlri.l %1, %2, %0"
+ [(set_attr "type" "arith_media")])
(define_expand "lshrsi3"
[(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
"TARGET_SH1"
"shll %R0\;rotcl %S0"
[(set_attr "length" "4")
- (set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ (set_attr "type" "arith")])
(define_insn "ashldi3_media"
[(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
"TARGET_SHMEDIA"
"@
shlld %1, %2, %0
- shlli %1, %2, %0")
+ shlli %1, %2, %0"
+ [(set_attr "type" "arith_media")])
(define_expand "ashldi3"
[(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
"TARGET_SH1"
"shlr %S0\;rotcr %R0"
[(set_attr "length" "4")
- (set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ (set_attr "type" "arith")])
(define_insn "lshrdi3_media"
[(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
"TARGET_SHMEDIA"
"@
shlrd %1, %2, %0
- shlri %1, %2, %0")
+ shlri %1, %2, %0"
+ [(set_attr "type" "arith_media")])
(define_expand "lshrdi3"
[(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
"TARGET_SH1"
"shar %S0\;rotcr %R0"
[(set_attr "length" "4")
- (set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ (set_attr "type" "arith")])
(define_insn "ashrdi3_media"
[(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
"TARGET_SHMEDIA"
"@
shard %1, %2, %0
- shari %1, %2, %0")
+ shari %1, %2, %0"
+ [(set_attr "type" "arith_media")])
(define_expand "ashrdi3"
[(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "n"))
- (match_operand:SI 3 "const_int_operand" "n")))]
- "TARGET_SH1 && (unsigned)INTVAL (operands[2]) < 32"
+ (match_operand:SI 2 "const_int_operand" ""))
+ (match_operand:SI 3 "const_int_operand" "")))]
+ "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
[(use (reg:SI R0_REG))]
"if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
DONE;")
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "n"))
- (match_operand:SI 3 "const_int_operand" "n")))
+ (match_operand:SI 2 "const_int_operand" ""))
+ (match_operand:SI 3 "const_int_operand" "")))
(clobber (reg:SI T_REG))]
- "TARGET_SH1 && (unsigned)INTVAL (operands[2]) < 32"
+ "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
[(use (reg:SI R0_REG))]
"if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
DONE;")
(set_attr "type" "arith")])
(define_split
- [(set (match_operand:SI 0 "register_operand" "=r,&r")
+ [(set (match_operand:SI 0 "register_operand" "")
(lshiftrt:SI
(ashift:SI
(and:SI
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
- (match_operand:SI 2 "const_int_operand" "N,n"))
- (match_operand:SI 3 "register_operand" "0,r"))
- (match_operand:SI 4 "const_int_operand" "n,n"))
- (match_operand:SI 5 "const_int_operand" "n,n")))
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "const_int_operand" ""))
+ (match_operand:SI 3 "register_operand" ""))
+ (match_operand:SI 4 "const_int_operand" ""))
+ (match_operand:SI 5 "const_int_operand" "")))
(clobber (reg:SI T_REG))]
"TARGET_SH1"
[(use (reg:SI R0_REG))]
;; signed left/right shift combination.
(define_split
- [(set (match_operand:SI 0 "register_operand" "=r")
+ [(set (match_operand:SI 0 "register_operand" "")
(sign_extract:SI
- (ashift:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "const_int_operand" "n"))
- (match_operand:SI 3 "const_int_operand" "n")
+ (ashift:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "const_int_operand" ""))
+ (match_operand:SI 3 "const_int_operand" "")
(const_int 0)))
(clobber (reg:SI T_REG))]
"TARGET_SH1"
(const_int 16))))]
"TARGET_SH1"
"xtrct %1,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_insn "xtrct_right"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(const_int 16))))]
"TARGET_SH1"
"xtrct %2,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
;; -------------------------------------------------------------------------
;; Unary arithmetic
(const_int 0)))]
"TARGET_SH1"
"negc %1,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_insn "*negdi_media"
[(set (match_operand:DI 0 "arith_reg_operand" "=r")
(neg:DI (match_operand:DI 1 "arith_reg_operand" "r")))]
"TARGET_SHMEDIA"
- "sub r63, %1, %0")
+ "sub r63, %1, %0"
+ [(set_attr "type" "arith_media")])
(define_expand "negdi2"
[(set (match_operand:DI 0 "arith_reg_operand" "")
- (neg:DI (match_operand:DI 1 "arith_reg_operand" "")))
- (clobber (reg:SI T_REG))]
+ (neg:DI (match_operand:DI 1 "arith_reg_operand" "")))]
""
"
{
(neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
"TARGET_SH1"
"neg %1,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_insn "one_cmplsi2"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
"TARGET_SH1"
"not %1,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
(define_expand "one_cmpldi2"
[(set (match_operand:DI 0 "arith_reg_operand" "")
(define_insn "zero_extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
+ (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "r")))]
"TARGET_SHMEDIA"
- "addz.l %1, r63, %0")
+ "addz.l %1, r63, %0"
+ [(set_attr "type" "arith_media")])
(define_insn "zero_extendhidi2"
[(set (match_operand:DI 0 "register_operand" "=r,r")
- (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
+ (zero_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
"TARGET_SHMEDIA"
"@
#
- ld%M1.uw %m1, %0")
+ ld%M1.uw %m1, %0"
+ [(set_attr "type" "*,load_media")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
+ [(set (match_operand:DI 0 "register_operand" "")
+ (zero_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
"TARGET_SHMEDIA && reload_completed"
[(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
- (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 48)))])
+ (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 48)))]
+ "
+{
+ if (GET_CODE (operands[1]) == TRUNCATE)
+ operands[1] = XEXP (operands[1], 0);
+}")
+
+;; ??? when a truncated input to a zero_extend is reloaded, reload will
+;; reload the entire truncate expression.
+(define_insn_and_split "*loaddi_trunc"
+ [(set (match_operand 0 "int_gpr_dest" "=r")
+ (truncate (match_operand:DI 1 "memory_operand" "m")))]
+ "TARGET_SHMEDIA && reload_completed"
+ "#"
+ "TARGET_SHMEDIA && reload_completed"
+ [(set (match_dup 0) (match_dup 1))]
+ "operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));")
(define_insn "zero_extendqidi2"
[(set (match_operand:DI 0 "register_operand" "=r,r")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
+ (zero_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
"TARGET_SHMEDIA"
"@
andi %1, 255, %0
- ld%M1.ub %m1, %0")
+ ld%M1.ub %m1, %0"
+ [(set_attr "type" "arith_media,load_media")])
+
+(define_expand "zero_extendhisi2"
+ [(set (match_operand:SI 0 "arith_reg_operand" "")
+ (zero_extend:SI (match_operand:HI 1 "general_extend_operand" "")))]
+ ""
+ "
+{
+ if (! TARGET_SHMEDIA && ! arith_reg_operand (operands[1], HImode))
+ operands[1] = copy_to_mode_reg (HImode, operands[1]);
+}")
-(define_insn "zero_extendhisi2"
+(define_insn "*zero_extendhisi2_compact"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
"TARGET_SH1"
"extu.w %1,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
+
+(define_insn "*zero_extendhisi2_media"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (zero_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
+ "TARGET_SHMEDIA"
+ "@
+ #
+ ld%M1.uw %m1, %0"
+ [(set_attr "type" "arith_media,load_media")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (zero_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
+ "TARGET_SHMEDIA && reload_completed"
+ [(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 16)))
+ (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
+ "
+{
+ if (GET_CODE (operands[1]) == TRUNCATE)
+ operands[1] = XEXP (operands[1], 0);
+}")
+
+(define_expand "zero_extendqisi2"
+ [(set (match_operand:SI 0 "arith_reg_operand" "")
+ (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "")))]
+ ""
+ "
+{
+ if (! TARGET_SHMEDIA && ! arith_reg_operand (operands[1], QImode))
+ operands[1] = copy_to_mode_reg (QImode, operands[1]);
+}")
-(define_insn "zero_extendqisi2"
+(define_insn "*zero_extendqisi2_compact"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
"TARGET_SH1"
"extu.b %1,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
+
+(define_insn "*zero_extendqisi2_media"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
+ "TARGET_SHMEDIA"
+ "@
+ andi %1, 255, %0
+ ld%M1.ub %m1, %0"
+ [(set_attr "type" "arith_media,load_media")])
(define_insn "zero_extendqihi2"
[(set (match_operand:HI 0 "arith_reg_operand" "=r")
(zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
"TARGET_SH1"
"extu.b %1,%0"
- [(set_attr "type" "arith")
- (set_attr "insn_class" "ex_group")])
+ [(set_attr "type" "arith")])
;; -------------------------------------------------------------------------
;; Sign extension instructions
"TARGET_SHMEDIA"
"@
add.l %1, r63, %0
- ld%M1.l %m1, %0")
+ ld%M1.l %m1, %0"
+ [(set_attr "type" "arith_media,load_media")])
(define_insn "extendhidi2"
[(set (match_operand:DI 0 "register_operand" "=r,r")
- (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
+ (sign_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
"TARGET_SHMEDIA"
"@
#
- ld%M1.w %m1, %0")
+ ld%M1.w %m1, %0"
+ [(set_attr "type" "*,load_media")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "=r")
- (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
+ [(set (match_operand:DI 0 "register_operand" "")
+ (sign_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
"TARGET_SHMEDIA && reload_completed"
[(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
- (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 48)))])
+ (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 48)))]
+ "
+{
+ if (GET_CODE (operands[1]) == TRUNCATE)
+ operands[1] = XEXP (operands[1], 0);
+}")
(define_insn "extendqidi2"
[(set (match_operand:DI 0 "register_operand" "=r,r")
- (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
+ (sign_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
"TARGET_SHMEDIA"
"@
#
- ld%M1.b %m1, %0")
+ ld%M1.b %m1, %0"
+ [(set_attr "type" "*,load_media")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "=r")
- (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
+ [(set (match_operand:DI 0 "register_operand" "")
+ (sign_extend:DI (match_operand:QI 1 "extend_reg_operand" "")))]
"TARGET_SHMEDIA && reload_completed"
[(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 56)))
- (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))])
+ (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))]
+ "
+{
+ if (GET_CODE (operands[1]) == TRUNCATE)
+ operands[1] = XEXP (operands[1], 0);
+}")
+
+(define_expand "extendhisi2"
+ [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
+ (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
+ ""
+ "")
-(define_insn "extendhisi2"
+(define_insn "*extendhisi2_compact"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
(sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,m")))]
"TARGET_SH1"
"@
exts.w %1,%0
mov.w %1,%0"
- [(set_attr "type" "arith,load")
- (set_attr "insn_class" "ex_group,*")])
+ [(set_attr "type" "arith,load")])
+
+(define_insn "*extendhisi2_media"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
+ "TARGET_SHMEDIA"
+ "@
+ #
+ ld%M1.w %m1, %0"
+ [(set_attr "type" "arith_media,load_media")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (sign_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
+ "TARGET_SHMEDIA && reload_completed"
+ [(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 16)))
+ (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
+ "
+{
+ if (GET_CODE (operands[1]) == TRUNCATE)
+ operands[1] = XEXP (operands[1], 0);
+}")
+
+(define_expand "extendqisi2"
+ [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
+ (sign_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
+ ""
+ "")
-(define_insn "extendqisi2"
+(define_insn "*extendqisi2_compact"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
(sign_extend:SI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
"TARGET_SH1"
"@
exts.b %1,%0
mov.b %1,%0"
- [(set_attr "type" "arith,load")
- (set_attr "insn_class" "ex_group,*")])
+ [(set_attr "type" "arith,load")])
-(define_insn "extendqihi2"
- [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
- (sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
- "TARGET_SH1"
+(define_insn "*extendqisi2_media"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (sign_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
+ "TARGET_SHMEDIA"
"@
- exts.b %1,%0
+ #
+ ld%M1.b %m1, %0"
+ [(set_attr "type" "arith_media,load_media")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (sign_extend:SI (match_operand:QI 1 "extend_reg_operand" "")))]
+ "TARGET_SHMEDIA && reload_completed"
+ [(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 24)))
+ (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))]
+ "
+{
+ if (GET_CODE (operands[1]) == TRUNCATE)
+ operands[1] = XEXP (operands[1], 0);
+}")
+
+(define_insn "extendqihi2"
+ [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
+ (sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
+ "TARGET_SH1"
+ "@
+ exts.b %1,%0
mov.b %1,%0"
- [(set_attr "type" "arith,load")
- (set_attr "insn_class" "ex_group,*")])
+ [(set_attr "type" "arith,load")])
+
+/* It would seem useful to combine the truncXi patterns into the movXi
+ patterns, but unary operators are ignored when matching constraints,
+ so we need separate patterns. */
+(define_insn "truncdisi2"
+ [(set (match_operand:SI 0 "general_movdst_operand" "=r,m,m,f,r,f")
+ (truncate:SI (match_operand:DI 1 "register_operand" "r,r,f,r,f,f")))]
+ "TARGET_SHMEDIA"
+ "@
+ add.l %1, r63, %0
+ st%M0.l %m0, %1
+ fst%M0.s %m0, %T1
+ fmov.ls %1, %0
+ fmov.sl %T1, %0
+ fmov.s %T1, %0"
+ [(set_attr "type" "arith_media,store_media,fstore_media,fload_media,fpconv_media,fmove_media")])
+
+
+(define_insn "truncdihi2"
+ [(set (match_operand:HI 0 "general_movdst_operand" "=?r,m")
+ (truncate:HI (match_operand:DI 1 "register_operand" "r,r")))]
+ "TARGET_SHMEDIA"
+ "@
+ shlli\\t%1,48,%0\;shlri\\t%0,48,%0
+ st%M0.w %m0, %1"
+ [(set_attr "type" "arith_media,store_media")
+ (set_attr "length" "8,4")])
+
+; N.B. This should agree with LOAD_EXTEND_OP and movqi.
+; Because we use zero extension, we can't provide signed QImode compares
+; using a simple compare or conditional banch insn.
+(define_insn "truncdiqi2"
+ [(set (match_operand:QI 0 "general_movdst_operand" "=r,m")
+ (truncate:QI (match_operand:DI 1 "register_operand" "r,r")))]
+ "TARGET_SHMEDIA"
+ "@
+ and %1, 255, %0
+ st%M0.b %m0, %1"
+ [(set_attr "type" "arith_media,store")])
;; -------------------------------------------------------------------------
;; Move instructions
(define_insn "push_fpul"
[(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
- "TARGET_SH3E && ! TARGET_SH5"
+ "TARGET_SH2E && ! TARGET_SH5"
"sts.l fpul,@-r15"
[(set_attr "type" "store")
+ (set_attr "late_fp_use" "yes")
(set_attr "hit_stack" "yes")])
;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
(define_insn "pop_fpul"
[(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
- "TARGET_SH3E && ! TARGET_SH5"
+ "TARGET_SH2E && ! TARGET_SH5"
"lds.l @r15+,fpul"
[(set_attr "type" "load")
(set_attr "hit_stack" "yes")])
"TARGET_SH1 && ! TARGET_SH5"
"")
+(define_expand "push_fpscr"
+ [(const_int 0)]
+ "TARGET_SH2E"
+ "
+{
+ rtx insn = emit_insn (gen_fpu_switch (gen_rtx (MEM, PSImode,
+ gen_rtx (PRE_DEC, Pmode,
+ stack_pointer_rtx)),
+ get_fpscr_rtx ()));
+ REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
+ DONE;
+}")
+
+(define_expand "pop_fpscr"
+ [(const_int 0)]
+ "TARGET_SH2E"
+ "
+{
+ rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
+ gen_rtx (MEM, PSImode,
+ gen_rtx (POST_INC, Pmode,
+ stack_pointer_rtx))));
+ REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
+ DONE;
+}")
+
;; These two patterns can happen as the result of optimization, when
;; comparisons get simplified to a move of zero or 1 into the T reg.
;; They don't disappear completely, because the T reg is a fixed hard reg.
;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
(define_insn "movsi_i"
- [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
- (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
+ [(set (match_operand:SI 0 "general_movdst_operand"
+ "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
+ (match_operand:SI 1 "general_movsrc_operand"
+ "Q,rI08,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
"TARGET_SH1
- && ! TARGET_SH3E
+ && ! TARGET_SH2E
&& (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
"@
lds.l %1,%0
lds.l %1,%0
fake %1,%0"
- [(set_attr "type" "pcload_si,move,*,load_si,move,prget,move,store,store,pstore,move,prset,load,pload,pcload_si")
- (set_attr "insn_class" "*,*,mt_group,*,*,*,*,*,*,*,*,*,*,*,*")
+ [(set_attr "type" "pcload_si,move,mt_group,load_si,mac_gp,prget,move,store,store,pstore,move,prset,load,pload,pcload_si")
(set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
;; t/r must come after r/r, lest reload will try to reload stuff like
;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
;; ??? This allows moves from macl to fpul to be recognized, but these moves
;; will require a reload.
+;; ??? We can't include f/f because we need the proper FPSCR setting when
+;; TARGET_FMOVD is in effect, and mode switching is done before reload.
(define_insn "movsi_ie"
- [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,y")
- (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y"))]
- "TARGET_SH3E
+ [(set (match_operand:SI 0 "general_movdst_operand"
+ "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
+ (match_operand:SI 1 "general_movsrc_operand"
+ "Q,rI08,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
+ "TARGET_SH2E
&& (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
"@
fake %1,%0
lds %1,%0
sts %1,%0
+ fsts fpul,%0
+ flds %1,fpul
+ fmov %1,%0
! move optimized away"
- [(set_attr "type" "pcload_si,move,*,load_si,move,prget,move,store,store,pstore,move,prset,load,pload,load,store,pcload_si,gp_fpul,gp_fpul,nil")
- (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
+ [(set_attr "type" "pcload_si,move,*,load_si,mac_gp,prget,move,store,store,pstore,move,prset,load,pload,load,store,pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
+ (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
+ (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
(define_insn "movsi_i_lowpart"
[(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
- (match_operand:SI 1 "general_movsrc_operand" "Q,rI,mr,x,l,t,r,i"))]
+ (match_operand:SI 1 "general_movsrc_operand" "Q,rI08,mr,x,l,t,r,i"))]
"TARGET_SH1
&& (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
fake %1,%0"
[(set_attr "type" "pcload,move,load,move,prget,move,store,pcload")])
+(define_insn_and_split "load_ra"
+ [(set (match_operand:SI 0 "general_movdst_operand" "")
+ (unspec:SI [(match_operand 1 "register_operand" "")] UNSPEC_RA))]
+ "TARGET_SH1"
+ "#"
+ "&& ! rtx_equal_function_value_matters"
+ [(set (match_dup 0) (match_dup 1))]
+ "
+{
+ if (TARGET_SHCOMPACT && current_function_has_nonlocal_label)
+ operands[1] = gen_rtx_MEM (SImode, return_address_pointer_rtx);
+}")
+
(define_insn "*movsi_media"
- [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,r,r,m,f,m,f,r,f,*b*k,r,b*k")
- (match_operand:SI 1 "general_movsrc_operand" "r,JS,ns,m,r,m,f,r,f,f,r,*b*k,T"))]
+ [(set (match_operand:SI 0 "general_movdst_operand"
+ "=r,r,r,r,m,f,m,f,r,f,*b,r,b")
+ (match_operand:SI 1 "general_movsrc_operand"
+ "r,I16C16,nCpg,m,rZ,m,f,rZ,f,f,r,*b,Csy"))]
"TARGET_SHMEDIA_FPU
&& (register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode))"
+ || sh_register_operand (operands[1], SImode))"
"@
add.l %1, r63, %0
movi %1, %0
#
ld%M1.l %m1, %0
- st%M0.l %m0, %1
+ st%M0.l %m0, %N1
fld%M1.s %m1, %0
fst%M0.s %m0, %1
- fmov.ls %1, %0
+ fmov.ls %N1, %0
fmov.sl %1, %0
fmov.s %1, %0
ptabs %1, %0
gettr %1, %0
pt %1, %0"
- [(set_attr "type" "move,move,*,load,store,load,store,move,move,move,ptabs,move,pt")
+ [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,fload_media,fstore_media,fload_media,fpconv_media,fmove_media,ptabs_media,gettr_media,pt_media")
(set_attr "length" "4,4,8,4,4,4,4,4,4,4,4,4,12")])
(define_insn "*movsi_media_nofpu"
- [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,r,r,m,*b*k,r,b*k")
- (match_operand:SI 1 "general_movsrc_operand" "r,JS,ns,m,r,r,*b*k,T"))]
+ [(set (match_operand:SI 0 "general_movdst_operand"
+ "=r,r,r,r,m,*b,r,b")
+ (match_operand:SI 1 "general_movsrc_operand"
+ "r,I16C16,nCpg,m,rZ,r,*b,Csy"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode))"
+ || sh_register_operand (operands[1], SImode))"
"@
add.l %1, r63, %0
movi %1, %0
#
ld%M1.l %m1, %0
- st%M0.l %m0, %1
+ st%M0.l %m0, %N1
ptabs %1, %0
gettr %1, %0
pt %1, %0"
- [(set_attr "type" "move,move,*,load,store,ptabs,move,pt")
+ [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,ptabs_media,gettr_media,pt_media")
(set_attr "length" "4,4,8,4,4,4,4,12")])
(define_split
- [(set (match_operand:SI 0 "arith_reg_operand" "=r")
- (match_operand:SI 1 "immediate_operand" "s"))]
+ [(set (match_operand:SI 0 "arith_reg_operand" "")
+ (match_operand:SI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed
&& MOVI_SHORI_BASE_OPERAND_P (operands[1])"
[(set (subreg:DI (match_dup 0) 0) (match_dup 2))]
}")
(define_split
- [(set (match_operand:SI 0 "register_operand" "=r")
- (match_operand:SI 1 "immediate_operand" "n"))]
- "TARGET_SHMEDIA
+ [(set (match_operand:SI 0 "register_operand" "")
+ (match_operand:SI 1 "immediate_operand" ""))]
+ "TARGET_SHMEDIA && reload_completed
&& ((GET_CODE (operands[1]) == CONST_INT
- && ! CONST_OK_FOR_J (INTVAL (operands[1])))
+ && ! CONST_OK_FOR_I16 (INTVAL (operands[1])))
|| GET_CODE (operands[1]) == CONST_DOUBLE)"
[(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
}
else if (TARGET_SHCOMPACT)
{
- operands[1] = gen_rtx_SYMBOL_REF (Pmode, \"__ic_invalidate\");
+ operands[1] = function_symbol (\"__ic_invalidate\");
operands[1] = force_reg (Pmode, operands[1]);
emit_insn (gen_ic_invalidate_line_compact (operands[0], operands[1]));
DONE;
"TARGET_HARD_SH4"
"ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%1,%2\;mov.l\\t%0,@%2"
[(set_attr "length" "8")
- (set_attr "insn_class" "cwb")])
+ (set_attr "type" "cwb")])
+;; ??? could make arg 0 an offsettable memory operand to allow to save
+;; an add in the code that calculates the address.
(define_insn "ic_invalidate_line_media"
[(unspec_volatile [(match_operand 0 "register_operand" "r")]
UNSPEC_ICACHE)]
"TARGET_SHMEDIA"
- "icbi %0, 0\;synci"
- [(set_attr "length" "8")])
+ "ocbwb %0,0\;synco\;icbi %0, 0\;synci"
+ [(set_attr "length" "16")
+ (set_attr "type" "invalidate_line_media")])
(define_insn "ic_invalidate_line_compact"
[(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
[(set_attr "type" "sfunc")
(set_attr "needs_delay_slot" "yes")])
+(define_expand "initialize_trampoline"
+ [(match_operand:SI 0 "" "")
+ (match_operand:SI 1 "" "")
+ (match_operand:SI 2 "" "")]
+ "TARGET_SHCOMPACT"
+ "
+{
+ rtx sfun, tramp;
+
+ tramp = force_reg (Pmode, operands[0]);
+ sfun = force_reg (Pmode, function_symbol (\"__init_trampoline\"));
+ emit_move_insn (gen_rtx_REG (SImode, R2_REG), operands[1]);
+ emit_move_insn (gen_rtx_REG (SImode, R3_REG), operands[2]);
+
+ emit_insn (gen_initialize_trampoline_compact (tramp, sfun));
+ DONE;
+}")
+
+(define_insn "initialize_trampoline_compact"
+ [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
+ (match_operand:SI 1 "register_operand" "r")
+ (reg:SI R2_REG) (reg:SI R3_REG)]
+ UNSPEC_INIT_TRAMP)
+
+ (clobber (reg:SI PR_REG))]
+ "TARGET_SHCOMPACT"
+ "jsr @%1%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
(define_insn "movqi_i"
[(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l")
(match_operand:QI 1 "general_movsrc_operand" "ri,m,r,t,l,r"))]
(define_insn "*movqi_media"
[(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")
- (match_operand:QI 1 "general_movsrc_operand" "r,JS,m,r"))]
+ (match_operand:QI 1 "general_movsrc_operand" "r,I16C16,m,rZ"))]
"TARGET_SHMEDIA
&& (arith_reg_operand (operands[0], QImode)
- || arith_reg_operand (operands[1], QImode))"
+ || arith_reg_or_0_operand (operands[1], QImode))"
"@
add.l %1, r63, %0
movi %1, %0
- ld%M1.b %m1, %0
- st%M0.b %m0, %1")
+ ld%M1.ub %m1, %0
+ st%M0.b %m0, %N1"
+ [(set_attr "type" "arith_media,arith_media,load_media,store_media")])
(define_expand "movqi"
[(set (match_operand:QI 0 "general_operand" "")
""
"{ if (prepare_move_operands (operands, QImode)) DONE; }")
+(define_expand "reload_inqi"
+ [(set (match_operand:SI 2 "" "=&r")
+ (match_operand:QI 1 "inqhi_operand" ""))
+ (set (match_operand:QI 0 "arith_reg_operand" "=r")
+ (truncate:QI (match_dup 3)))]
+ "TARGET_SHMEDIA"
+ "
+{
+ rtx inner = XEXP (operands[1], 0);
+ int regno = REGNO (inner);
+
+ regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
+ operands[1] = gen_rtx_REG (SImode, regno);
+ operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
+}")
+
+/* When storing r0, we have to avoid reg+reg addressing. */
(define_insn "movhi_i"
- [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
- (match_operand:HI 1 "general_movsrc_operand" "Q,rI,m,t,r,l,r,i"))]
+ [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
+ (match_operand:HI 1 "general_movsrc_operand" "Q,rI08,m,t,r,l,r,i"))]
"TARGET_SH1
&& (arith_reg_operand (operands[0], HImode)
- || arith_reg_operand (operands[1], HImode))"
+ || arith_reg_operand (operands[1], HImode))
+ && (GET_CODE (operands[0]) != MEM
+ || GET_CODE (XEXP (operands[0], 0)) != PLUS
+ || GET_CODE (XEXP (XEXP (operands[0], 0), 1)) != REG
+ || ! refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0))"
"@
mov.w %1,%0
mov %1,%0
[(set_attr "type" "pcload,move,load,move,store,move,move,pcload")])
(define_insn "*movhi_media"
- [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m")
- (match_operand:HI 1 "general_movsrc_operand" "r,JS,n,m,r"))]
+ [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m")
+ (match_operand:HI 1 "general_movsrc_operand" "r,I16C16,n,m,rZ"))]
"TARGET_SHMEDIA
&& (arith_reg_operand (operands[0], HImode)
- || arith_reg_operand (operands[1], HImode))"
+ || arith_reg_or_0_operand (operands[1], HImode))"
"@
add.l %1, r63, %0
movi %1, %0
#
ld%M1.w %m1, %0
- st%M0.w %m0, %1")
+ st%M0.w %m0, %N1"
+ [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")])
(define_split
- [(set (match_operand:HI 0 "register_operand" "=r")
- (match_operand:HI 1 "immediate_operand" "n"))]
- "TARGET_SHMEDIA && ! CONST_OK_FOR_J (INTVAL (operands[1]))"
+ [(set (match_operand:HI 0 "register_operand" "")
+ (match_operand:HI 1 "immediate_operand" ""))]
+ "TARGET_SHMEDIA && reload_completed
+ && ! CONST_OK_FOR_I16 (INTVAL (operands[1]))"
[(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
(define_expand "movhi"
""
"{ if (prepare_move_operands (operands, HImode)) DONE; }")
-;; ??? This should be a define expand.
+(define_expand "reload_inhi"
+ [(set (match_operand:SI 2 "" "=&r")
+ (match_operand:HI 1 "inqhi_operand" ""))
+ (set (match_operand:HI 0 "arith_reg_operand" "=r")
+ (truncate:HI (match_dup 3)))]
+ "TARGET_SHMEDIA"
+ "
+{
+ rtx inner = XEXP (operands[1], 0);
+ int regno = REGNO (inner);
+
+ regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
+ operands[1] = gen_rtx_REG (SImode, regno);
+ operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
+}")
;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
;; compiled with -m2 -ml -O3 -funroll-loops
-(define_insn ""
+(define_insn "*movdi_i"
[(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
- (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I,i,x,r"))]
+ (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I08,i,x,r"))]
"TARGET_SH1
&& (arith_reg_operand (operands[0], DImode)
|| arith_reg_operand (operands[1], DImode))"
(set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
;; If the output is a register and the input is memory or a register, we have
-;; to be careful and see which word needs to be loaded first.
+;; to be careful and see which word needs to be loaded first.
(define_split
[(set (match_operand:DI 0 "general_movdst_operand" "")
}")
(define_insn "*movdi_media"
- [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,f,m,f,r,f,*b*k,r,b*k")
- (match_operand:DI 1 "general_movsrc_operand" "r,JS,iF,m,rl,m,f,r,f,f,r,*b*k,T"))]
+ [(set (match_operand:DI 0 "general_movdst_operand"
+ "=r,r,r,rl,m,f,m,f,r,f,*b,r,b")
+ (match_operand:DI 1 "general_movsrc_operand"
+ "r,I16C16,nCpgF,m,rlZ,m,f,rZ,f,f,r,*b,Csy"))]
"TARGET_SHMEDIA_FPU
&& (register_operand (operands[0], DImode)
- || register_operand (operands[1], DImode))"
+ || sh_register_operand (operands[1], DImode))"
"@
add %1, r63, %0
movi %1, %0
#
ld%M1.q %m1, %0
- st%M0.q %m0, %1
+ st%M0.q %m0, %N1
fld%M1.d %m1, %0
fst%M0.d %m0, %1
- fmov.qd %1, %0
+ fmov.qd %N1, %0
fmov.dq %1, %0
fmov.d %1, %0
ptabs %1, %0
gettr %1, %0
pt %1, %0"
- [(set_attr "type" "move,move,*,load,store,load,store,move,move,move,ptabs,move,pt")
+ [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,fload_media,fstore_media,fload_media,dfpconv_media,fmove_media,ptabs_media,gettr_media,pt_media")
(set_attr "length" "4,4,16,4,4,4,4,4,4,4,4,4,*")])
(define_insn "*movdi_media_nofpu"
- [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,*b*k,r,b*k")
- (match_operand:DI 1 "general_movsrc_operand" "r,JS,iF,m,rl,r,*b*k,T"))]
+ [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,*b,r,b")
+ (match_operand:DI 1 "general_movsrc_operand" "r,I16C16,nCpgF,m,rlZ,r,*b,Csy"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], DImode)
- || register_operand (operands[1], DImode))"
+ || sh_register_operand (operands[1], DImode))"
"@
add %1, r63, %0
movi %1, %0
#
ld%M1.q %m1, %0
- st%M0.q %m0, %1
+ st%M0.q %m0, %N1
ptabs %1, %0
gettr %1, %0
pt %1, %0"
- [(set_attr "type" "move,move,*,load,store,ptabs,move,pt")
+ [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,ptabs_media,gettr_media,pt_media")
(set_attr "length" "4,4,16,4,4,4,4,*")])
(define_split
- [(set (match_operand:DI 0 "arith_reg_operand" "=r")
- (match_operand:DI 1 "immediate_operand" "s"))]
+ [(set (match_operand:DI 0 "arith_reg_operand" "")
+ (match_operand:DI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed
&& MOVI_SHORI_BASE_OPERAND_P (operands[1])"
[(set (match_dup 0) (match_dup 1))]
&& MOVI_SHORI_BASE_OPERAND_P (operands[1])"
"
{
- if (GET_CODE (operands[1]) == LABEL_REF
- && GET_CODE (XEXP (operands[1], 0)) == CODE_LABEL)
- LABEL_NUSES (XEXP (operands[1], 0)) += 4;
- else if (GOTOFF_P (operands[1])
- && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == LABEL_REF
- && (GET_CODE (XEXP (XVECEXP (XEXP (operands[1], 0), 0, 0), 0))
- == CODE_LABEL))
- LABEL_NUSES (XEXP (XVECEXP (XEXP (operands[1], 0), 0, 0), 0)) += 4;
+ sh_mark_label (operands[1], 4);
}")
(define_expand "movdi_const_32bit"
&& MOVI_SHORI_BASE_OPERAND_P (operands[1])"
"
{
- if (GET_CODE (operands[1]) == LABEL_REF
- && GET_CODE (XEXP (operands[1], 0)) == CODE_LABEL)
- LABEL_NUSES (XEXP (operands[1], 0)) += 2;
- else if (GOTOFF_P (operands[1])
- && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == LABEL_REF
- && (GET_CODE (XEXP (XVECEXP (XEXP (operands[1], 0), 0, 0), 0))
- == CODE_LABEL))
- LABEL_NUSES (XEXP (XVECEXP (XEXP (operands[1], 0), 0, 0), 0)) += 2;
+ sh_mark_label (operands[1], 2);
}")
(define_expand "movdi_const_16bit"
"")
(define_split
- [(set (match_operand:DI 0 "arith_reg_operand" "=r")
- (match_operand:DI 1 "immediate_operand" "i"))]
+ [(set (match_operand:DI 0 "arith_reg_operand" "")
+ (match_operand:DI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed
&& GET_CODE (operands[1]) == CONST_INT
- && ! CONST_OK_FOR_J (INTVAL (operands[1]))"
+ && ! CONST_OK_FOR_I16 (INTVAL (operands[1]))"
[(set (match_dup 0) (match_dup 2))
- (set (match_dup 0)
- (ior:DI (ashift:DI (match_dup 0) (const_int 16))
- (zero_extend:DI (truncate:HI (match_dup 1)))))]
+ (match_dup 1)]
"
{
- unsigned HOST_WIDE_INT low = INTVAL (operands[1]);
- unsigned HOST_WIDE_INT val = low;
+ unsigned HOST_WIDE_INT val = INTVAL (operands[1]);
+ unsigned HOST_WIDE_INT low = val;
+ unsigned HOST_WIDE_INT high = val;
unsigned HOST_WIDE_INT sign;
+ unsigned HOST_WIDE_INT val2 = val ^ (val-1);
/* Sign-extend the 16 least-significant bits. */
- val &= 0xffff;
- val ^= 0x8000;
- val -= 0x8000;
- operands[1] = GEN_INT (val);
+ low &= 0xffff;
+ low ^= 0x8000;
+ low -= 0x8000;
/* Arithmetic shift right the word by 16 bits. */
- low >>= 16;
+ high >>= 16;
sign = 1;
sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
- low ^= sign;
- low -= sign;
- operands[2] = GEN_INT (low);
+ high ^= sign;
+ high -= sign;
+ do
+ {
+ /* If we can't generate the constant with a two-insn movi / shori
+ sequence, try some other strategies. */
+ if (! CONST_OK_FOR_I16 (high))
+ {
+ /* Try constant load / left shift. We know VAL != 0. */
+ val2 = val ^ (val-1);
+ if (val2 > 0x1ffff)
+ {
+ int trailing_zeroes = exact_log2 ((val2 >> 16) + 1) + 15;
+
+ if (CONST_OK_FOR_I16 (val >> trailing_zeroes)
+ || (! CONST_OK_FOR_I16 (high >> 16)
+ && CONST_OK_FOR_I16 (val >> (trailing_zeroes + 16))))
+ {
+ val2 = (HOST_WIDE_INT) val >> trailing_zeroes;
+ operands[1] = gen_ashldi3_media (operands[0], operands[0],
+ GEN_INT (trailing_zeroes));
+ break;
+ }
+ }
+ /* Try constant load / right shift. */
+ val2 = (val >> 15) + 1;
+ if (val2 == (val2 & -val2))
+ {
+ int shift = 49 - exact_log2 (val2);
+
+ val2 = trunc_int_for_mode (val << shift, DImode);
+ if (CONST_OK_FOR_I16 (val2))
+ {
+ operands[1] = gen_lshrdi3_media (operands[0], operands[0],
+ GEN_INT (shift));
+ break;
+ }
+ }
+ /* Try mperm.w . */
+ val2 = val & 0xffff;
+ if ((val >> 16 & 0xffff) == val2
+ && (val >> 32 & 0xffff) == val2
+ && (val >> 48 & 0xffff) == val2)
+ {
+ val2 = (HOST_WIDE_INT) val >> 48;
+ operands[1] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
+ operands[1] = gen_mperm_w0 (operands[1], operands[1]);
+ break;
+ }
+ /* Try movi / mshflo.l */
+ val2 = (HOST_WIDE_INT) val >> 32;
+ if (val2 == trunc_int_for_mode (val, SImode))
+ {
+ operands[1] = gen_mshflo_l_di (operands[0], operands[0],
+ operands[0]);
+ break;
+ }
+ /* Try movi / mshflo.l w/ r63. */
+ val2 = val + ((HOST_WIDE_INT) -1 << 32);
+ if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_I16 (val2))
+ {
+ operands[1] = gen_mshflo_l_di (operands[0], operands[0],
+ GEN_INT (0));
+ break;
+ }
+ }
+ val2 = high;
+ operands[1] = gen_shori_media (operands[0], operands[0], GEN_INT (low));
+ }
+ while (0);
+ operands[2] = GEN_INT (val2);
}")
(define_split
- [(set (match_operand:DI 0 "arith_reg_operand" "=r")
- (match_operand:DI 1 "immediate_operand" "F"))]
+ [(set (match_operand:DI 0 "arith_reg_operand" "")
+ (match_operand:DI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed
&& GET_CODE (operands[1]) == CONST_DOUBLE"
[(set (match_dup 0) (match_dup 2))
operands[2] = immed_double_const (low, high, DImode);
}")
-(define_insn "*shori_media"
+(define_insn "shori_media"
[(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
(ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0,0")
(const_int 16))
(zero_extend:DI
(truncate:HI
- (match_operand:DI 2 "immediate_operand" "JS,nF")))))]
+ (match_operand:DI 2 "immediate_operand" "I16C16,nF")))))]
"TARGET_SHMEDIA"
"@
shori %u2, %0
- #")
+ #"
+ [(set_attr "type" "arith_media,*")])
(define_expand "movdi"
[(set (match_operand:DI 0 "general_movdst_operand" "")
(define_insn "movdf_media"
[(set (match_operand:DF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
- (match_operand:DF 1 "general_movsrc_operand" "f,r,f,r,F,m,f,m,r"))]
+ (match_operand:DF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
"TARGET_SHMEDIA_FPU
&& (register_operand (operands[0], DFmode)
- || register_operand (operands[1], DFmode))"
+ || sh_register_operand (operands[1], DFmode))"
"@
fmov.d %1, %0
- fmov.qd %1, %0
+ fmov.qd %N1, %0
fmov.dq %1, %0
add %1, r63, %0
#
fld%M1.d %m1, %0
fst%M0.d %m0, %1
ld%M1.q %m1, %0
- st%M0.q %m0, %1"
- [(set_attr "type" "move,move,move,move,*,load,store,load,store")])
+ st%M0.q %m0, %N1"
+ [(set_attr "type" "fmove_media,fload_media,dfpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media")])
(define_insn "movdf_media_nofpu"
[(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
- (match_operand:DF 1 "general_movsrc_operand" "r,F,m,r"))]
+ (match_operand:DF 1 "general_movsrc_operand" "r,F,m,rZ"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], DFmode)
- || register_operand (operands[1], DFmode))"
+ || sh_register_operand (operands[1], DFmode))"
"@
add %1, r63, %0
#
ld%M1.q %m1, %0
- st%M0.q %m0, %1"
- [(set_attr "type" "move,*,load,store")])
+ st%M0.q %m0, %N1"
+ [(set_attr "type" "arith_media,*,load_media,store_media")])
(define_split
[(set (match_operand:DF 0 "arith_reg_operand" "")
(if_then_else
(ne (symbol_ref "TARGET_SHCOMPACT") (const_int 0))
(const_int 10) (const_int 8))])
- (set_attr "type" "fmove,move,pcload,load,store,pcload,load,store,load,load")
+ (set_attr "type" "fmove,move,pcfload,fload,store,pcload,load,store,load,fload")
+ (set_attr "late_fp_use" "*,*,*,*,yes,*,*,*,*,*")
(set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
(const_string "double")
(const_string "none")))])
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "register_operand" ""))
- (use (match_operand:PSI 2 "fpscr_operand" "c"))
+ (use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (match_scratch:SI 3 "=X"))]
"TARGET_SH4 && reload_completed
&& (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
(define_split
[(set (match_operand:DF 0 "general_movdst_operand" "")
(match_operand:DF 1 "general_movsrc_operand" ""))
- (use (match_operand:PSI 2 "fpscr_operand" "c"))
- (clobber (match_scratch:SI 3 "X"))]
+ (use (match_operand:PSI 2 "fpscr_operand" ""))
+ (clobber (match_scratch:SI 3 ""))]
"TARGET_SH4
&& reload_completed
&& true_regnum (operands[0]) < 16
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "memory_operand" ""))
- (use (match_operand:PSI 2 "fpscr_operand" "c"))
+ (use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (reg:SI R0_REG))]
"TARGET_SH4 && reload_completed"
[(parallel [(set (match_dup 0) (match_dup 1))
(match_operand:SF 1 "register_operand" ""))
(use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (match_scratch:SI 3 "X"))]
- "TARGET_SH3E && reload_completed
+ "TARGET_SH2E && reload_completed
&& true_regnum (operands[0]) == true_regnum (operands[1])"
[(set (match_dup 0) (match_dup 0))]
"")
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "register_operand" ""))
- (use (match_operand:PSI 2 "fpscr_operand" "c"))
+ (use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (match_scratch:SI 3 "X"))]
"TARGET_SH4 && ! TARGET_FMOVD && reload_completed
&& FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(mem:DF (match_operand:SI 1 "register_operand" "")))
- (use (match_operand:PSI 2 "fpscr_operand" "c"))
- (clobber (match_scratch:SI 3 "X"))]
+ (use (match_operand:PSI 2 "fpscr_operand" ""))
+ (clobber (match_scratch:SI 3 ""))]
"TARGET_SH4 && ! TARGET_FMOVD && reload_completed
&& FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
&& find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "memory_operand" ""))
- (use (match_operand:PSI 2 "fpscr_operand" "c"))
- (clobber (match_scratch:SI 3 "X"))]
+ (use (match_operand:PSI 2 "fpscr_operand" ""))
+ (clobber (match_scratch:SI 3 ""))]
"TARGET_SH4 && ! TARGET_FMOVD && reload_completed
&& FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
[(const_int 0)]
(define_split
[(set (match_operand:DF 0 "memory_operand" "")
(match_operand:DF 1 "register_operand" ""))
- (use (match_operand:PSI 2 "fpscr_operand" "c"))
- (clobber (match_scratch:SI 3 "X"))]
+ (use (match_operand:PSI 2 "fpscr_operand" ""))
+ (clobber (match_scratch:SI 3 ""))]
"TARGET_SH4 && ! TARGET_FMOVD && reload_completed
&& FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
[(const_int 0)]
}")
;; If the output is a register and the input is memory or a register, we have
-;; to be careful and see which word needs to be loaded first.
+;; to be careful and see which word needs to be loaded first.
(define_split
[(set (match_operand:DF 0 "general_movdst_operand" "")
}
}")
-(define_insn "movv2sf_i"
- [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,m")
- (match_operand:V2SF 1 "nonimmediate_operand" "f,m,f"))]
- "TARGET_SHMEDIA_FPU
- && (fp_arith_reg_operand (operands[0], V2SFmode)
- || fp_arith_reg_operand (operands[1], V2SFmode))"
- "@
- #
- fld%M1.p %m1, %0
- fst%M0.p %m0, %1")
-
-(define_split
- [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f")
- (match_operand:V2SF 1 "nonimmediate_operand" "f"))]
- "TARGET_SHMEDIA_FPU && reload_completed
- && fp_arith_reg_operand (operands[0], V2SFmode)
- && fp_arith_reg_operand (operands[1], V2SFmode)"
- [(set (subreg:DF (match_dup 0) 0) (subreg:DF (match_dup 1) 0))])
+;;This is incompatible with the way gcc uses subregs.
+;;(define_insn "movv2sf_i"
+;; [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,m")
+;; (match_operand:V2SF 1 "nonimmediate_operand" "f,m,f"))]
+;; "TARGET_SHMEDIA_FPU
+;; && (fp_arith_reg_operand (operands[0], V2SFmode)
+;; || fp_arith_reg_operand (operands[1], V2SFmode))"
+;; "@
+;; #
+;; fld%M1.p %m1, %0
+;; fst%M0.p %m0, %1"
+;; [(set_attr "type" "*,fload_media,fstore_media")])
+
+(define_insn_and_split "movv2sf_i"
+ [(set (match_operand:V2SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
+ (match_operand:V2SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
+ "TARGET_SHMEDIA_FPU"
+ "#"
+ "TARGET_SHMEDIA_FPU && reload_completed"
+ [(set (match_dup 0) (match_dup 1))]
+ "
+{
+ operands[0] = simplify_gen_subreg (DFmode, operands[0], V2SFmode, 0);
+ operands[1] = simplify_gen_subreg (DFmode, operands[1], V2SFmode, 0);
+}")
(define_expand "movv2sf"
- [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,m")
- (match_operand:V2SF 1 "nonimmediate_operand" "f,m,f"))]
+ [(set (match_operand:V2SF 0 "general_movdst_operand" "")
+ (match_operand:V2SF 1 "nonimmediate_operand" ""))]
"TARGET_SHMEDIA_FPU"
"
{
DONE;
}")
+(define_expand "addv2sf3"
+ [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
+ (match_operand:V2SF 1 "fp_arith_reg_operand" "")
+ (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
+ "TARGET_SHMEDIA_FPU"
+ "
+{
+ sh_expand_binop_v2sf (PLUS, operands[0], operands[1], operands[2]);
+ DONE;
+}")
+
+(define_expand "subv2sf3"
+ [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
+ (match_operand:V2SF 1 "fp_arith_reg_operand" "")
+ (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
+ "TARGET_SHMEDIA_FPU"
+ "
+{
+ sh_expand_binop_v2sf (MINUS, operands[0], operands[1], operands[2]);
+ DONE;
+}")
+
+(define_expand "mulv2sf3"
+ [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
+ (match_operand:V2SF 1 "fp_arith_reg_operand" "")
+ (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
+ "TARGET_SHMEDIA_FPU"
+ "
+{
+ sh_expand_binop_v2sf (MULT, operands[0], operands[1], operands[2]);
+ DONE;
+}")
+
+(define_expand "divv2sf3"
+ [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
+ (match_operand:V2SF 1 "fp_arith_reg_operand" "")
+ (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
+ "TARGET_SHMEDIA_FPU"
+ "
+{
+ sh_expand_binop_v2sf (DIV, operands[0], operands[1], operands[2]);
+ DONE;
+}")
+
(define_insn_and_split "*movv4sf_i"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=f,f,m")
- (match_operand:V4SF 1 "nonimmediate_operand" "f,m,f"))]
+ (match_operand:V4SF 1 "general_operand" "fZ,m,fZ"))]
"TARGET_SHMEDIA_FPU"
"#"
"&& reload_completed"
plus_constant (XEXP (operands[0], 0),
i * GET_MODE_SIZE (V2SFmode)));
else
- {
- x = gen_rtx_SUBREG (V2SFmode, operands[0], i * 2);
- alter_subreg (&x);
- }
+ x = simplify_gen_subreg (V2SFmode, operands[0], V4SFmode, i * 8);
if (GET_CODE (operands[1]) == MEM)
y = gen_rtx_MEM (V2SFmode,
plus_constant (XEXP (operands[1], 0),
i * GET_MODE_SIZE (V2SFmode)));
else
- {
- y = gen_rtx_SUBREG (V2SFmode, operands[1], i * 2);
- alter_subreg (&y);
- }
+ y = simplify_gen_subreg (V2SFmode, operands[1], V4SFmode, i * 8);
emit_insn (gen_movv2sf_i (x, y));
}
DONE;
}"
[(set_attr "length" "8")])
-
+
(define_expand "movv4sf"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "=f,f,m")
- (match_operand:V4SF 1 "nonimmediate_operand" "f,m,f"))]
+ [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
+ (match_operand:V4SF 1 "general_operand" ""))]
"TARGET_SHMEDIA_FPU"
"
{
DONE;
}"
[(set_attr "length" "32")])
-
+
(define_expand "movv16sf"
[(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
(match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
(define_insn "movsf_media"
[(set (match_operand:SF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
- (match_operand:SF 1 "general_movsrc_operand" "f,r,f,r,F,m,f,m,r"))]
+ (match_operand:SF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
"TARGET_SHMEDIA_FPU
&& (register_operand (operands[0], SFmode)
- || register_operand (operands[1], SFmode))"
+ || sh_register_operand (operands[1], SFmode))"
"@
fmov.s %1, %0
- fmov.ls %1, %0
+ fmov.ls %N1, %0
fmov.sl %1, %0
- add %1, r63, %0
+ add.l %1, r63, %0
#
fld%M1.s %m1, %0
fst%M0.s %m0, %1
ld%M1.l %m1, %0
- st%M0.l %m0, %1"
- [(set_attr "type" "move,move,move,move,*,load,store,load,store")])
+ st%M0.l %m0, %N1"
+ [(set_attr "type" "fmove_media,fload_media,fpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media")])
(define_insn "movsf_media_nofpu"
[(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m")
- (match_operand:SF 1 "general_movsrc_operand" "r,F,m,r"))]
+ (match_operand:SF 1 "general_movsrc_operand" "r,F,m,rZ"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], SFmode)
- || register_operand (operands[1], SFmode))"
+ || sh_register_operand (operands[1], SFmode))"
"@
- add %1, r63, %0
+ add.l %1, r63, %0
#
ld%M1.l %m1, %0
- st%M0.l %m0, %1"
- [(set_attr "type" "move,*,load,store")])
+ st%M0.l %m0, %N1"
+ [(set_attr "type" "arith_media,*,load_media,store_media")])
(define_split
[(set (match_operand:SF 0 "arith_reg_operand" "")
(match_operand:SF 1 "immediate_operand" ""))]
- "TARGET_SHMEDIA && reload_completed"
+ "TARGET_SHMEDIA && reload_completed
+ && ! FP_REGISTER_P (true_regnum (operands[0]))"
[(set (match_dup 3) (match_dup 2))]
"
{
REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
REAL_VALUE_TO_TARGET_SINGLE (value, values);
operands[2] = GEN_INT (values);
-
+
operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
}")
(define_insn "movsf_i"
[(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
- (match_operand:SF 1 "general_movsrc_operand" "r,I,FQ,mr,r,r,l"))]
+ (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))]
"TARGET_SH1
- && (! TARGET_SH3E
+ && (! TARGET_SH2E
/* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
|| (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
|| (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
|| arith_reg_operand (operands[1], SFmode))"
"@
mov %1,%0
- mov %1,%0
+ mov #0,%0
mov.l %1,%0
mov.l %1,%0
mov.l %1,%0
(match_operand:SF 1 "general_movsrc_operand"
"f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
(use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
- (clobber (match_scratch:SI 3 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
+ (clobber (match_scratch:SI 3 "=X,X,Bsc,Bsc,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
- "TARGET_SH3E
+ "TARGET_SH2E
&& (arith_reg_operand (operands[0], SFmode)
|| arith_reg_operand (operands[1], SFmode)
|| arith_reg_operand (operands[3], SImode)
sts.l %1,%0
lds.l %1,%0
! move optimized away"
- [(set_attr "type" "fmove,move,fmove,fmove,pcload,load,store,pcload,load,store,fmove,fmove,load,*,gp_fpul,gp_fpul,store,load,nil")
+ [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,store,pcload,load,store,fmove,fmove,load,*,fpul_gp,gp_fpul,store,load,nil")
+ (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
(set_attr "length" "*,*,*,*,4,*,*,*,*,*,2,2,2,4,2,2,2,2,0")
(set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
(const_string "single")
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(match_operand:SF 1 "register_operand" ""))
- (use (match_operand:PSI 2 "fpscr_operand" "c"))
+ (use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (reg:SI FPUL_REG))]
"TARGET_SH1"
[(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
emit_insn (gen_movsf_media_nofpu (operands[0], operands[1]));
DONE;
}
- if (TARGET_SH3E)
+ if (TARGET_SH2E)
{
emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
DONE;
}")
(define_insn "mov_nop"
- [(set (match_operand 0 "register_operand" "") (match_dup 0))]
- "TARGET_SH3E"
+ [(set (match_operand 0 "any_register_operand" "") (match_dup 0))]
+ "TARGET_SH2E"
""
[(set_attr "length" "0")
(set_attr "type" "nil")])
(define_insn "*movsi_y"
[(set (match_operand:SI 0 "register_operand" "=y,y")
- (match_operand:SI 1 "immediate_operand" "Qi,I"))
+ (match_operand:SI 1 "immediate_operand" "Qi,I08"))
(clobber (match_scratch:SI 2 "=&z,r"))]
- "TARGET_SH3E
+ "TARGET_SH2E
&& (reload_in_progress || reload_completed)"
"#"
[(set_attr "length" "4")
;; This one has the additional purpose to record a possible scratch register
;; for the following branch.
+;; ??? Unfortunately, just setting the scratch register is not good enough,
+;; because the insn then might be deemed dead and deleted. And we can't
+;; make the use in the jump insn explicit because that would disable
+;; delay slot scheduling from the target.
(define_insn "indirect_jump_scratch"
- [(set (match_operand 0 "register_operand" "=r")
- (unspec [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))]
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))
+ (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))]
"TARGET_SH1"
""
[(set_attr "length" "0")])
+
+;; This one is used to preemt an insn from beyond the bra / braf / jmp
+;; being pulled into the delay slot of a condbranch that has been made to
+;; jump around the unconditional jump because it was out of range.
+(define_insn "stuff_delay_slot"
+ [(set (pc)
+ (unspec [(match_operand 0 "const_int_operand" "") (pc)] UNSPEC_BBR))
+ (set (reg:SI T_REG) (match_operand 1 "const_int_operand" ""))]
+ "TARGET_SH1"
+ ""
+ [(set_attr "length" "0")
+ (set_attr "cond_delay_slot" "yes")])
\f
;; Conditional branch insns
(define_expand "beq_media"
[(set (pc)
(if_then_else (eq (match_operand:DI 1 "arith_reg_operand" "r,r")
- (match_operand:DI 2 "arith_operand" "r,O"))
+ (match_operand:DI 2 "arith_operand" "r,I06"))
(label_ref:DI (match_operand 0 "" ""))
(pc)))]
"TARGET_SHMEDIA"
"")
-(define_insn "beq_media_i"
+(define_insn "*beq_media_i"
[(set (pc)
- (if_then_else (eq (match_operand:DI 1 "arith_reg_operand" "r,r")
- (match_operand:DI 2 "arith_operand" "r,O"))
+ (if_then_else (match_operator 3 "equality_comparison_operator"
+ [(match_operand:DI 1 "arith_reg_operand" "r,r")
+ (match_operand:DI 2 "arith_operand" "r,I06")])
(match_operand:DI 0 "target_operand" "b,b")
(pc)))]
"TARGET_SHMEDIA"
"@
- beq %1, %2, %0
- beqi %1, %2, %0")
+ b%o3%' %1, %2, %0
+ b%o3i%' %1, %2, %0"
+ [(set_attr "type" "cbranch_media")])
(define_expand "bne_media"
[(set (pc)
(if_then_else (ne (match_operand:DI 1 "arith_reg_operand" "r,r")
- (match_operand:DI 2 "arith_operand" "r,O"))
+ (match_operand:DI 2 "arith_operand" "r,I06"))
(label_ref:DI (match_operand 0 "" ""))
(pc)))]
"TARGET_SHMEDIA"
"")
-(define_insn "bne_media_i"
- [(set (pc)
- (if_then_else (ne (match_operand:DI 1 "arith_reg_operand" "r,r")
- (match_operand:DI 2 "arith_operand" "r,O"))
- (match_operand:DI 0 "target_operand" "b,b")
- (pc)))]
- "TARGET_SHMEDIA"
- "@
- bne %1, %2, %0
- bnei %1, %2, %0")
-
(define_expand "bgt_media"
[(set (pc)
- (if_then_else (gt (match_operand:DI 1 "arith_reg_operand" "r")
- (match_operand:DI 2 "arith_reg_operand" "r"))
+ (if_then_else (gt (match_operand:DI 1 "arith_reg_or_0_operand" "r")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "r"))
(label_ref:DI (match_operand 0 "" ""))
(pc)))]
"TARGET_SHMEDIA"
"")
-(define_insn "bgt_media_i"
- [(set (pc)
- (if_then_else (gt (match_operand:DI 1 "arith_reg_operand" "r")
- (match_operand:DI 2 "arith_reg_operand" "r"))
- (match_operand:DI 0 "target_operand" "b")
- (pc)))]
- "TARGET_SHMEDIA"
- "bgt %1, %2, %0")
-
(define_expand "bge_media"
[(set (pc)
- (if_then_else (ge (match_operand:DI 1 "arith_reg_operand" "r")
- (match_operand:DI 2 "arith_reg_operand" "r"))
+ (if_then_else (ge (match_operand:DI 1 "arith_reg_or_0_operand" "r")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "r"))
(label_ref:DI (match_operand 0 "" ""))
(pc)))]
"TARGET_SHMEDIA"
"")
-(define_insn "bge_media_i"
- [(set (pc)
- (if_then_else (ge (match_operand:DI 1 "arith_reg_operand" "r")
- (match_operand:DI 2 "arith_reg_operand" "r"))
- (match_operand:DI 0 "target_operand" "b")
- (pc)))]
- "TARGET_SHMEDIA"
- "bge %1, %2, %0")
-
(define_expand "bgtu_media"
[(set (pc)
- (if_then_else (gtu (match_operand:DI 1 "arith_reg_operand" "r")
- (match_operand:DI 2 "arith_reg_operand" "r"))
+ (if_then_else (gtu (match_operand:DI 1 "arith_reg_or_0_operand" "r")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "r"))
(label_ref:DI (match_operand 0 "" ""))
(pc)))]
"TARGET_SHMEDIA"
"")
-(define_insn "bgtu_media_i"
- [(set (pc)
- (if_then_else (gtu (match_operand:DI 1 "arith_reg_operand" "r")
- (match_operand:DI 2 "arith_reg_operand" "r"))
- (match_operand:DI 0 "target_operand" "b")
- (pc)))]
- "TARGET_SHMEDIA"
- "bgtu %1, %2, %0")
-
(define_expand "bgeu_media"
[(set (pc)
- (if_then_else (geu (match_operand:DI 1 "arith_reg_operand" "r")
- (match_operand:DI 2 "arith_reg_operand" "r"))
+ (if_then_else (geu (match_operand:DI 1 "arith_reg_or_0_operand" "r")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "r"))
(label_ref:DI (match_operand 0 "" ""))
(pc)))]
"TARGET_SHMEDIA"
"")
-(define_insn "bgeu_media_i"
+(define_insn "*bgt_media_i"
[(set (pc)
- (if_then_else (geu (match_operand:DI 1 "arith_reg_operand" "r")
- (match_operand:DI 2 "arith_reg_operand" "r"))
+ (if_then_else (match_operator 3 "greater_comparison_operator"
+ [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
(match_operand:DI 0 "target_operand" "b")
(pc)))]
"TARGET_SHMEDIA"
- "bgeu %1, %2, %0")
+ "b%o3%' %N1, %N2, %0"
+ [(set_attr "type" "cbranch_media")])
;; These are only needed to make invert_jump() happy.
-(define_insn "*ble_media_i"
- [(set (pc)
- (if_then_else (le (match_operand:DI 1 "arith_reg_operand" "r")
- (match_operand:DI 2 "arith_reg_operand" "r"))
- (match_operand:DI 0 "target_operand" "b")
- (pc)))]
- "TARGET_SHMEDIA"
- "bge %2, %1, %0")
-
(define_insn "*blt_media_i"
[(set (pc)
- (if_then_else (lt (match_operand:DI 1 "arith_reg_operand" "r")
- (match_operand:DI 2 "arith_reg_operand" "r"))
- (match_operand:DI 0 "target_operand" "b")
- (pc)))]
- "TARGET_SHMEDIA"
- "bgt %2, %1, %0")
-
-(define_insn "*bleu_media_i"
- [(set (pc)
- (if_then_else (leu (match_operand:DI 1 "arith_reg_operand" "r")
- (match_operand:DI 2 "arith_reg_operand" "r"))
- (match_operand:DI 0 "target_operand" "b")
- (pc)))]
- "TARGET_SHMEDIA"
- "bgeu %2, %1, %0")
-
-(define_insn "*bltu_media_i"
- [(set (pc)
- (if_then_else (ltu (match_operand:DI 1 "arith_reg_operand" "r")
- (match_operand:DI 2 "arith_reg_operand" "r"))
+ (if_then_else (match_operator 3 "less_comparison_operator"
+ [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
(match_operand:DI 0 "target_operand" "b")
(pc)))]
"TARGET_SHMEDIA"
- "bgtu %2, %1, %0")
+ "b%o3%' %N2, %N1, %0"
+ [(set_attr "type" "cbranch_media")])
(define_expand "beq"
[(set (pc)
DONE;
}
- sh_compare_op0 = force_reg (DImode, sh_compare_op0);
- sh_compare_op1 = force_reg (DImode, sh_compare_op1);
+ if (sh_compare_op0 != const0_rtx)
+ sh_compare_op0 = force_reg (DImode, sh_compare_op0);
+ if (sh_compare_op1 != const0_rtx)
+ sh_compare_op1 = force_reg (DImode, sh_compare_op1);
emit_jump_insn (gen_bgt_media (operands[0],
sh_compare_op0, sh_compare_op1));
DONE;
DONE;
}
- sh_compare_op0 = force_reg (DImode, sh_compare_op0);
- sh_compare_op1 = force_reg (DImode, sh_compare_op1);
+ if (sh_compare_op0 != const0_rtx)
+ sh_compare_op0 = force_reg (DImode, sh_compare_op0);
+ if (sh_compare_op1 != const0_rtx)
+ sh_compare_op1 = force_reg (DImode, sh_compare_op1);
emit_jump_insn (gen_bgt_media (operands[0],
sh_compare_op1, sh_compare_op0));
DONE;
DONE;
}
- sh_compare_op0 = force_reg (DImode, sh_compare_op0);
- sh_compare_op1 = force_reg (DImode, sh_compare_op1);
+ if (sh_compare_op0 != const0_rtx)
+ sh_compare_op0 = force_reg (DImode, sh_compare_op0);
+ if (sh_compare_op1 != const0_rtx)
+ sh_compare_op1 = force_reg (DImode, sh_compare_op1);
emit_jump_insn (gen_bge_media (operands[0],
sh_compare_op1, sh_compare_op0));
DONE;
}
- if (TARGET_SH3E
+ if (TARGET_SH2E
&& TARGET_IEEE
&& GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
{
DONE;
}
- sh_compare_op0 = force_reg (DImode, sh_compare_op0);
- sh_compare_op1 = force_reg (DImode, sh_compare_op1);
+ if (sh_compare_op0 != const0_rtx)
+ sh_compare_op0 = force_reg (DImode, sh_compare_op0);
+ if (sh_compare_op1 != const0_rtx)
+ sh_compare_op1 = force_reg (DImode, sh_compare_op1);
emit_jump_insn (gen_bge_media (operands[0],
sh_compare_op0, sh_compare_op1));
DONE;
}
- if (TARGET_SH3E
+ if (TARGET_SH2E
&& ! TARGET_IEEE
&& GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
{
{
if (TARGET_SHMEDIA)
{
- sh_compare_op0 = force_reg (DImode, sh_compare_op0);
- sh_compare_op1 = force_reg (DImode, sh_compare_op1);
+ if (sh_compare_op0 != const0_rtx)
+ sh_compare_op0 = force_reg (DImode, sh_compare_op0);
+ if (sh_compare_op1 != const0_rtx)
+ sh_compare_op1 = force_reg (DImode, sh_compare_op1);
emit_jump_insn (gen_bgtu_media (operands[0],
sh_compare_op0, sh_compare_op1));
DONE;
{
if (TARGET_SHMEDIA)
{
- sh_compare_op0 = force_reg (DImode, sh_compare_op0);
- sh_compare_op1 = force_reg (DImode, sh_compare_op1);
+ if (sh_compare_op0 != const0_rtx)
+ sh_compare_op0 = force_reg (DImode, sh_compare_op0);
+ if (sh_compare_op1 != const0_rtx)
+ sh_compare_op1 = force_reg (DImode, sh_compare_op1);
emit_jump_insn (gen_bgtu_media (operands[0],
sh_compare_op1, sh_compare_op0));
DONE;
{
if (TARGET_SHMEDIA)
{
- sh_compare_op0 = force_reg (DImode, sh_compare_op0);
- sh_compare_op1 = force_reg (DImode, sh_compare_op1);
+ if (sh_compare_op0 != const0_rtx)
+ sh_compare_op0 = force_reg (DImode, sh_compare_op0);
+ if (sh_compare_op1 != const0_rtx)
+ sh_compare_op1 = force_reg (DImode, sh_compare_op1);
emit_jump_insn (gen_bgeu_media (operands[0],
sh_compare_op0, sh_compare_op1));
DONE;
{
if (TARGET_SHMEDIA)
{
- sh_compare_op0 = force_reg (DImode, sh_compare_op0);
- sh_compare_op1 = force_reg (DImode, sh_compare_op1);
+ if (sh_compare_op0 != const0_rtx)
+ sh_compare_op0 = force_reg (DImode, sh_compare_op0);
+ if (sh_compare_op1 != const0_rtx)
+ sh_compare_op1 = force_reg (DImode, sh_compare_op1);
emit_jump_insn (gen_bgeu_media (operands[0],
sh_compare_op1, sh_compare_op0));
DONE;
[(set_attr "type" "jump")
(set_attr "needs_delay_slot" "yes")])
+;; ??? It would be much saner to explicitly use the scratch register
+;; in the jump insn, and have indirect_jump_scratch only set it,
+;; but fill_simple_delay_slots would refuse to do delay slot filling
+;; from the target then, as it uses simplejump_p.
+;;(define_insn "jump_compact_far"
+;; [(set (pc)
+;; (label_ref (match_operand 0 "" "")))
+;; (use (match_operand 1 "register_operand" "r")]
+;; "TARGET_SH1"
+;; "* return output_far_jump(insn, operands[0], operands[1]);"
+;; [(set_attr "type" "jump")
+;; (set_attr "needs_delay_slot" "yes")])
+
(define_insn "jump_media"
[(set (pc)
(match_operand:DI 0 "target_operand" "b"))]
"TARGET_SHMEDIA"
- "blink %0, r63")
+ "blink %0, r63"
+ [(set_attr "type" "jump_media")])
(define_expand "jump"
[(set (pc)
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
(const_string "single") (const_string "double")))
- (set_attr "needs_delay_slot" "yes")])
+ (set_attr "needs_delay_slot" "yes")
+ (set_attr "fp_set" "unknown")])
;; This is a pc-rel call, using bsrf, for use with PIC.
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
(const_string "single") (const_string "double")))
- (set_attr "needs_delay_slot" "yes")])
+ (set_attr "needs_delay_slot" "yes")
+ (set_attr "fp_set" "unknown")])
(define_insn_and_split "call_pcrel"
[(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
{
rtx lab = PATTERN (gen_call_site ());
- if (SYMBOL_REF_FLAG (operands[0]))
+ if (SYMBOL_REF_LOCAL_P (operands[0]))
emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
else
emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
(const_string "single") (const_string "double")))
- (set_attr "needs_delay_slot" "yes")])
+ (set_attr "needs_delay_slot" "yes")
+ (set_attr "fp_set" "unknown")])
(define_insn "call_compact"
[(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
(match_operand 1 "" ""))
(clobber (reg:DI PR_MEDIA_REG))]
"TARGET_SHMEDIA"
- "blink %0, r18")
+ "blink %0, r18"
+ [(set_attr "type" "jump_media")])
(define_insn "call_valuei"
[(set (match_operand 0 "" "=rf")
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
(const_string "single") (const_string "double")))
- (set_attr "needs_delay_slot" "yes")])
+ (set_attr "needs_delay_slot" "yes")
+ (set_attr "fp_set" "unknown")])
(define_insn "call_valuei_pcrel"
[(set (match_operand 0 "" "=rf")
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
(const_string "single") (const_string "double")))
- (set_attr "needs_delay_slot" "yes")])
+ (set_attr "needs_delay_slot" "yes")
+ (set_attr "fp_set" "unknown")])
(define_insn_and_split "call_value_pcrel"
[(set (match_operand 0 "" "=rf")
{
rtx lab = PATTERN (gen_call_site ());
- if (SYMBOL_REF_FLAG (operands[1]))
+ if (SYMBOL_REF_LOCAL_P (operands[1]))
emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
else
emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
(const_string "single") (const_string "double")))
- (set_attr "needs_delay_slot" "yes")])
+ (set_attr "needs_delay_slot" "yes")
+ (set_attr "fp_set" "unknown")])
(define_insn "call_value_compact"
[(set (match_operand 0 "" "=rf")
(match_operand 2 "" "")))
(clobber (reg:DI PR_MEDIA_REG))]
"TARGET_SHMEDIA"
- "blink %1, r18")
+ "blink %1, r18"
+ [(set_attr "type" "jump_media")])
(define_expand "call"
[(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
operands[0] = XEXP (operands[0], 0);
if (flag_pic && GET_CODE (operands[0]) == SYMBOL_REF)
{
- if (! SYMBOL_REF_FLAG (operands[0]))
+ if (! SYMBOL_REF_LOCAL_P (operands[0]))
{
rtx reg = gen_reg_rtx (Pmode);
-
+
emit_insn (gen_symGOTPLT2reg (reg, operands[0]));
operands[0] = reg;
}
if (flag_pic)
{
- if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_FLAG (func))
+ if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
{
rtx reg = gen_reg_rtx (Pmode);
run out of registers when adjusting fpscr for the call. */
emit_insn (gen_force_mode_for_call ());
- operands[0] = gen_rtx_SYMBOL_REF (SImode,
- \"__GCC_shcompact_call_trampoline\");
+ operands[0] = function_symbol (\"__GCC_shcompact_call_trampoline\");
if (flag_pic)
{
rtx reg = gen_reg_rtx (Pmode);
}
else if (TARGET_SHCOMPACT && flag_pic
&& GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
- && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
+ && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
{
rtx reg = gen_reg_rtx (Pmode);
DONE;
}
else
+ {
operands[0] = force_reg (SImode, XEXP (operands[0], 0));
+ operands[1] = operands[2];
+ }
emit_call_insn (gen_calli (operands[0], operands[1]));
DONE;
if (flag_pic)
{
- if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_FLAG (func))
+ if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
{
rtx reg = gen_reg_rtx (Pmode);
run out of registers when adjusting fpscr for the call. */
emit_insn (gen_force_mode_for_call ());
- operands[0] = gen_rtx_SYMBOL_REF (SImode,
- \"__GCC_shcompact_call_trampoline\");
+ operands[0] = function_symbol (\"__GCC_shcompact_call_trampoline\");
if (flag_pic)
{
rtx reg = gen_reg_rtx (Pmode);
operands[1] = XEXP (operands[1], 0);
if (flag_pic && GET_CODE (operands[1]) == SYMBOL_REF)
{
- if (! SYMBOL_REF_FLAG (operands[1]))
+ if (! SYMBOL_REF_LOCAL_P (operands[1]))
{
rtx reg = gen_reg_rtx (Pmode);
-
+
emit_insn (gen_symGOTPLT2reg (reg, operands[1]));
operands[1] = reg;
}
if (flag_pic)
{
- if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_FLAG (func))
+ if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
{
rtx reg = gen_reg_rtx (Pmode);
run out of registers when adjusting fpscr for the call. */
emit_insn (gen_force_mode_for_call ());
- operands[1] = gen_rtx_SYMBOL_REF (SImode,
- \"__GCC_shcompact_call_trampoline\");
+ operands[1] = function_symbol (\"__GCC_shcompact_call_trampoline\");
if (flag_pic)
{
rtx reg = gen_reg_rtx (Pmode);
}
else if (TARGET_SHCOMPACT && flag_pic
&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
- && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
+ && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
{
rtx reg = gen_reg_rtx (Pmode);
[(call (mem:SI (match_operand:SI 0 "register_operand" "k,k"))
(match_operand 1 "" ""))
(return)
- (use (match_operand 2 "register_operand" "z,x"))
+ (use (match_operand:SI 2 "register_operand" "z,x"))
(use (reg:SI R1_REG))
(use (reg:PSI FPSCR_REG))
;; We want to make sure the `x' above will only match MACH_REG
(define_insn "sibcall_media"
[(call (mem:DI (match_operand:DI 0 "target_reg_operand" "k"))
(match_operand 1 "" ""))
+ (use (reg:SI PR_MEDIA_REG))
(return)]
"TARGET_SHMEDIA"
- "blink %0, r63")
+ "blink %0, r63"
+ [(set_attr "type" "jump_media")])
(define_expand "sibcall"
[(parallel
operands[0] = XEXP (operands[0], 0);
if (flag_pic && GET_CODE (operands[0]) == SYMBOL_REF)
{
- if (! SYMBOL_REF_FLAG (operands[0]))
+ if (! SYMBOL_REF_LOCAL_P (operands[0]))
{
rtx reg = gen_reg_rtx (Pmode);
-
+
/* We must not use GOTPLT for sibcalls, because PIC_REG
must be restored before the PLT code gets to run. */
emit_insn (gen_symGOT2reg (reg, operands[0]));
if (flag_pic)
{
- if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_FLAG (func))
+ if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
{
rtx reg = gen_reg_rtx (Pmode);
run out of registers when adjusting fpscr for the call. */
emit_insn (gen_force_mode_for_call ());
- operands[0] = gen_rtx_SYMBOL_REF (SImode,
- \"__GCC_shcompact_call_trampoline\");
+ operands[0] = function_symbol (\"__GCC_shcompact_call_trampoline\");
if (flag_pic)
{
rtx reg = gen_reg_rtx (Pmode);
}
else if (TARGET_SHCOMPACT && flag_pic
&& GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
- && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
+ && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
{
rtx reg = gen_reg_rtx (Pmode);
/* The PLT needs the PIC register, but the epilogue would have
to restore it, so we can only use PC-relative PIC calls for
static functions. */
- && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
+ && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
{
emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
DONE;
if (flag_pic)
{
- if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_FLAG (func))
+ if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
{
rtx reg = gen_reg_rtx (Pmode);
run out of registers when adjusting fpscr for the call. */
emit_insn (gen_force_mode_for_call ());
- operands[1] = gen_rtx_SYMBOL_REF (SImode,
- \"__GCC_shcompact_call_trampoline\");
+ operands[1] = function_symbol (\"__GCC_shcompact_call_trampoline\");
if (flag_pic)
{
rtx reg = gen_reg_rtx (Pmode);
[(set (pc) (match_operand:DI 0 "target_reg_operand" "b"))
(use (label_ref (match_operand 1 "" "")))]
"TARGET_SHMEDIA"
- "blink %0, r63")
-
+ "blink %0, r63"
+ [(set_attr "type" "jump_media")])
+
;; Call subroutine returning any type.
;; ??? This probably doesn't work.
(const_int 0))
(match_operand 1 "" "")
(match_operand 2 "" "")])]
- "TARGET_SH3E || TARGET_SHMEDIA"
+ "TARGET_SH2E || TARGET_SHMEDIA"
"
{
int i;
(define_insn "mova"
[(set (reg:SI R0_REG)
- (unspec [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
+ (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
"TARGET_SH1"
"mova %O0,r0"
[(set_attr "in_delay_slot" "no")
(set_attr "type" "arith")])
-;; machine_dependent_reorg() will make this a `mova'.
+;; machine_dependent_reorg will make this a `mova'.
(define_insn "mova_const"
[(set (reg:SI R0_REG)
- (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
+ (unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
"TARGET_SH1"
"#"
[(set_attr "in_delay_slot" "no")
(define_expand "GOTaddr2picreg"
[(set (reg:SI R0_REG)
- (unspec [(const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC))]
- UNSPEC_MOVA))
+ (unspec:SI [(const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC))]
+ UNSPEC_MOVA))
(set (match_dup 0) (const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC)))
(set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
"" "
emit_insn (gen_ptrel (tr, dipic, lab));
if (GET_MODE (operands[0]) != GET_MODE (tr))
- tr = gen_rtx_SUBREG (GET_MODE (operands[0]), tr, 0);
+ tr = gen_lowpart (GET_MODE (operands[0]), tr);
insn = emit_move_insn (operands[0], tr);
-
+
REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, equiv,
REG_NOTES (insn));
}
")
-;; When generating PIC, we must match label_refs especially, because
-;; they do not satisfy LEGITIMATE_PIC_OPERAND_P(), and we don't want
-;; them to do, because they can't be loaded directly into
-;; non-branch-target registers.
-(define_insn "*pt"
- [(set (match_operand:DI 0 "target_reg_operand" "=b*k")
- (match_operand:DI 1 "" "T"))]
- "TARGET_SHMEDIA && flag_pic
- && EXTRA_CONSTRAINT_T (operands[1])"
- "pt %1, %0"
- [(set_attr "type" "pt")
- (set_attr "length" "*")])
-
(define_insn "*ptb"
- [(set (match_operand:DI 0 "target_reg_operand" "=b*k")
- (const:DI (unspec:DI [(match_operand:DI 1 "" "T")]
+ [(set (match_operand:DI 0 "target_reg_operand" "=b")
+ (const:DI (unspec:DI [(match_operand:DI 1 "" "Csy")]
UNSPEC_DATALABEL)))]
"TARGET_SHMEDIA && flag_pic
- && EXTRA_CONSTRAINT_T (operands[1])"
+ && EXTRA_CONSTRAINT_Csy (operands[1])"
"ptb/u datalabel %1, %0"
- [(set_attr "type" "pt")
+ [(set_attr "type" "pt_media")
(set_attr "length" "*")])
(define_insn "ptrel"
- [(set (match_operand:DI 0 "target_reg_operand" "=bk")
- (plus (match_operand:DI 1 "register_operand" "r")
+ [(set (match_operand:DI 0 "target_reg_operand" "=b")
+ (plus:DI (match_operand:DI 1 "register_operand" "r")
(pc)))
(match_operand:DI 2 "" "")]
"TARGET_SHMEDIA"
"%O2: ptrel/u %1, %0"
- [(set_attr "type" "ptabs")])
+ [(set_attr "type" "ptabs_media")])
(define_expand "builtin_setjmp_receiver"
[(match_operand 0 "" "")]
if (TARGET_SHMEDIA)
{
rtx reg = operands[2];
-
+
if (GET_MODE (reg) != DImode)
reg = gen_rtx_SUBREG (DImode, reg, 0);
-
+
if (flag_pic > 1)
emit_insn (gen_movdi_const_32bit (reg, operands[1]));
else
REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, XVECEXP (XEXP (operands[1],
0), 0, 0),
REG_NOTES (insn));
-
+
DONE;
}")
""
"")
+;; TLS code generation.
+;; ??? this should be a define_insn_and_split
+;; See the thread [PATCH/RFA] SH TLS support on gcc-patches
+;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html>
+;; for details.
+
+(define_insn "tls_global_dynamic"
+ [(set (match_operand:SI 0 "register_operand" "=&z")
+ (unspec:SI [(match_operand:SI 1 "" "")]
+ UNSPEC_TLSGD))
+ (use (reg:PSI FPSCR_REG))
+ (use (reg:SI PIC_REG))
+ (clobber (reg:SI PR_REG))
+ (clobber (scratch:SI))]
+ "TARGET_SH1"
+ "*
+{
+ return \"\\
+mov.l\\t1f,r4\\n\\
+\\tmova\\t2f,r0\\n\\
+\\tmov.l\\t2f,r1\\n\\
+\\tadd\\tr0,r1\\n\\
+\\tjsr\\t@r1\\n\\
+\\tadd\\tr12,r4\\n\\
+\\tbra\\t3f\\n\\
+\\tnop\\n\\
+\\t.align\\t2\\n\\
+1:\\t.long\\t%a1@TLSGD\\n\\
+2:\\t.long\\t__tls_get_addr@PLT\\n\\
+3:\";
+}"
+ [(set_attr "type" "tls_load")
+ (set_attr "length" "26")])
+
+(define_insn "tls_local_dynamic"
+ [(set (match_operand:SI 0 "register_operand" "=&z")
+ (unspec:SI [(match_operand:SI 1 "" "")]
+ UNSPEC_TLSLDM))
+ (use (reg:PSI FPSCR_REG))
+ (use (reg:SI PIC_REG))
+ (clobber (reg:SI PR_REG))
+ (clobber (scratch:SI))]
+ "TARGET_SH1"
+ "*
+{
+ return \"\\
+mov.l\\t1f,r4\\n\\
+\\tmova\\t2f,r0\\n\\
+\\tmov.l\\t2f,r1\\n\\
+\\tadd\\tr0,r1\\n\\
+\\tjsr\\t@r1\\n\\
+\\tadd\\tr12,r4\\n\\
+\\tbra\\t3f\\n\\
+\\tnop\\n\\
+\\t.align\\t2\\n\\
+1:\\t.long\\t%a1@TLSLDM\\n\\
+2:\\t.long\\t__tls_get_addr@PLT\\n\\
+3:\";
+}"
+ [(set_attr "type" "tls_load")
+ (set_attr "length" "26")])
+
+(define_expand "sym2DTPOFF"
+ [(const (unspec [(match_operand 0 "" "")] UNSPEC_DTPOFF))]
+ ""
+ "")
+
+(define_expand "symDTPOFF2reg"
+ [(match_operand 0 "" "") (match_operand 1 "" "") (match_operand 2 "" "")]
+ ""
+ "
+{
+ rtx dtpoffsym, insn;
+ rtx t = no_new_pseudos ? operands[0] : gen_reg_rtx (GET_MODE (operands[0]));
+
+ dtpoffsym = gen_sym2DTPOFF (operands[1]);
+ PUT_MODE (dtpoffsym, Pmode);
+ emit_move_insn (t, dtpoffsym);
+ insn = emit_move_insn (operands[0],
+ gen_rtx_PLUS (Pmode, t, operands[2]));
+ DONE;
+}")
+
+(define_expand "sym2GOTTPOFF"
+ [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTTPOFF))]
+ ""
+ "")
+
+(define_insn "tls_initial_exec"
+ [(set (match_operand:SI 0 "register_operand" "=&r")
+ (unspec:SI [(match_operand:SI 1 "" "")]
+ UNSPEC_TLSIE))
+ (use (reg:SI GBR_REG))
+ (use (reg:SI PIC_REG))
+ (clobber (reg:SI R0_REG))]
+ ""
+ "*
+{
+ return \"\\
+mov.l\\t1f,r0\\n\\
+\\tstc\\tgbr,%0\\n\\
+\\tmov.l\\t@(r0,r12),r0\\n\\
+\\tbra\\t2f\\n\\
+\\tadd\\tr0,%0\\n\\
+\\t.align\\t2\\n\\
+1:\\t.long\\t%a1\\n\\
+2:\";
+}"
+ [(set_attr "type" "tls_load")
+ (set_attr "length" "16")])
+
+(define_expand "sym2TPOFF"
+ [(const (unspec [(match_operand 0 "" "")] UNSPEC_TPOFF))]
+ ""
+ "")
+
+(define_expand "symTPOFF2reg"
+ [(match_operand 0 "" "") (match_operand 1 "" "")]
+ ""
+ "
+{
+ rtx tpoffsym, insn;
+
+ tpoffsym = gen_sym2TPOFF (operands[1]);
+ PUT_MODE (tpoffsym, Pmode);
+ insn = emit_move_insn (operands[0], tpoffsym);
+ DONE;
+}")
+
+(define_insn "load_gbr"
+ [(set (match_operand:SI 0 "register_operand" "") (reg:SI GBR_REG))
+ (use (reg:SI GBR_REG))]
+ ""
+ "stc gbr,%0"
+ [(set_attr "type" "tls_load")])
+
;; case instruction for switch statements.
;; Operand 0 is index
(define_insn "casesi_worker_0"
[(set (match_operand:SI 0 "register_operand" "=r,r")
- (unspec:SI [(match_operand 1 "register_operand" "0,r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "0,r")
(label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
(clobber (match_scratch:SI 3 "=X,1"))
(clobber (match_scratch:SI 4 "=&z,z"))]
(define_split
[(set (match_operand:SI 0 "register_operand" "")
- (unspec [(match_operand 1 "register_operand" "")
- (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
+ (unspec:SI [(match_operand:SI 1 "register_operand" "")
+ (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
(clobber (match_scratch:SI 3 ""))
(clobber (match_scratch:SI 4 ""))]
"TARGET_SH1 && ! TARGET_SH2 && reload_completed"
- [(set (reg:SI R0_REG) (unspec [(label_ref (match_dup 2))] UNSPEC_MOVA))
+ [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
(parallel [(set (match_dup 0)
- (unspec [(reg:SI R0_REG) (match_dup 1)
- (label_ref (match_dup 2))] UNSPEC_CASESI))
+ (unspec:SI [(reg:SI R0_REG) (match_dup 1)
+ (label_ref (match_dup 2))] UNSPEC_CASESI))
(clobber (match_dup 3))])
(set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
- "LABEL_NUSES (operands[2])++;")
+ "if (GET_CODE (operands[2]) == CODE_LABEL) LABEL_NUSES (operands[2])++;")
(define_split
[(set (match_operand:SI 0 "register_operand" "")
- (unspec:SI [(match_operand 1 "register_operand" "")
- (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
+ (unspec:SI [(match_operand:SI 1 "register_operand" "")
+ (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
(clobber (match_scratch:SI 3 ""))
(clobber (match_scratch:SI 4 ""))]
"TARGET_SH2 && reload_completed"
- [(set (reg:SI R0_REG) (unspec [(label_ref (match_dup 2))] UNSPEC_MOVA))
+ [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
(parallel [(set (match_dup 0)
(unspec:SI [(reg:SI R0_REG) (match_dup 1)
- (label_ref (match_dup 2))] UNSPEC_CASESI))
+ (label_ref (match_dup 2))] UNSPEC_CASESI))
(clobber (match_dup 3))])]
- "LABEL_NUSES (operands[2])++;")
+ "if (GET_CODE (operands[2]) == CODE_LABEL) LABEL_NUSES (operands[2])++;")
(define_insn "*casesi_worker"
[(set (match_operand:SI 0 "register_operand" "=r,r")
- (unspec [(reg:SI R0_REG) (match_operand 1 "register_operand" "0,r")
- (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
+ (unspec:SI [(reg:SI R0_REG)
+ (match_operand:SI 1 "register_operand" "0,r")
+ (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
(clobber (match_scratch:SI 3 "=X,1"))]
"TARGET_SH1"
"*
default:
abort ();
}
-}")
+}"
+ [(set_attr "type" "arith_media")])
(define_insn "casesi_load_media"
[(set (match_operand:DI 0 "arith_reg_operand" "=r")
default:
abort ();
}
-}")
+}"
+ [(set_attr "type" "load_media")])
(define_expand "return"
[(return)]
"
{
rtx reg = gen_rtx_REG (Pmode, R0_REG);
- rtx sym = gen_rtx_SYMBOL_REF (Pmode,
- \"__GCC_shcompact_return_trampoline\");
+ rtx sym = function_symbol (\"__GCC_shcompact_return_trampoline\");
if (flag_pic)
emit_insn (gen_symGOTPLT2reg (reg, sym));
(define_insn "return_media_i"
[(parallel [(return) (use (match_operand:DI 0 "target_reg_operand" "k"))])]
"TARGET_SHMEDIA && reload_completed"
- "blink %0, r63")
+ "blink %0, r63"
+ [(set_attr "type" "jump_media")])
+
+(define_insn "return_media_rte"
+ [(return)]
+ "TARGET_SHMEDIA && reload_completed && current_function_interrupt"
+ "rte"
+ [(set_attr "type" "jump_media")])
(define_expand "return_media"
[(return)]
int tr_regno = sh_media_register_for_return ();
rtx tr;
+ if (current_function_interrupt)
+ {
+ emit_jump_insn (gen_return_media_rte ());
+ DONE;
+ }
if (tr_regno < 0)
{
rtx r18 = gen_rtx_REG (DImode, PR_MEDIA_REG);
+ if (! call_used_regs[TR0_REG] || fixed_regs[TR0_REG])
+ abort ();
tr_regno = TR0_REG;
tr = gen_rtx_REG (DImode, tr_regno);
emit_move_insn (tr, r18);
}")
(define_insn "shcompact_preserve_incoming_args"
- [(set (match_operand 0 "register_operand" "+r")
- (unspec [(match_dup 0)] UNSPEC_COMPACT_ARGS))]
+ [(set (match_operand:SI 0 "register_operand" "+r")
+ (unspec:SI [(match_dup 0)] UNSPEC_COMPACT_ARGS))]
"TARGET_SHCOMPACT"
""
[(set_attr "length" "0")])
(define_insn "shcompact_incoming_args"
- [(set (reg:SI R2_REG) (unspec [(reg:SI R2_REG)] UNSPEC_COMPACT_ARGS))
- (set (reg:SI R3_REG) (unspec [(reg:SI R3_REG)] UNSPEC_COMPACT_ARGS))
- (set (reg:SI R4_REG) (unspec [(reg:SI R4_REG)] UNSPEC_COMPACT_ARGS))
- (set (reg:SI R5_REG) (unspec [(reg:SI R5_REG)] UNSPEC_COMPACT_ARGS))
- (set (reg:SI R6_REG) (unspec [(reg:SI R6_REG)] UNSPEC_COMPACT_ARGS))
- (set (reg:SI R7_REG) (unspec [(reg:SI R7_REG)] UNSPEC_COMPACT_ARGS))
- (set (reg:SI R8_REG) (unspec [(reg:SI R8_REG)] UNSPEC_COMPACT_ARGS))
- (set (reg:SI R9_REG) (unspec [(reg:SI R9_REG)] UNSPEC_COMPACT_ARGS))
+ [(set (reg:SI R2_REG) (unspec:SI [(reg:SI R2_REG)] UNSPEC_COMPACT_ARGS))
+ (set (reg:SI R3_REG) (unspec:SI [(reg:SI R3_REG)] UNSPEC_COMPACT_ARGS))
+ (set (reg:SI R4_REG) (unspec:SI [(reg:SI R4_REG)] UNSPEC_COMPACT_ARGS))
+ (set (reg:SI R5_REG) (unspec:SI [(reg:SI R5_REG)] UNSPEC_COMPACT_ARGS))
+ (set (reg:SI R6_REG) (unspec:SI [(reg:SI R6_REG)] UNSPEC_COMPACT_ARGS))
+ (set (reg:SI R7_REG) (unspec:SI [(reg:SI R7_REG)] UNSPEC_COMPACT_ARGS))
+ (set (reg:SI R8_REG) (unspec:SI [(reg:SI R8_REG)] UNSPEC_COMPACT_ARGS))
+ (set (reg:SI R9_REG) (unspec:SI [(reg:SI R9_REG)] UNSPEC_COMPACT_ARGS))
(set (mem:BLK (reg:SI MACL_REG))
- (unspec [(reg:SI MACH_REG)] UNSPEC_COMPACT_ARGS))
+ (unspec:BLK [(reg:SI MACH_REG)] UNSPEC_COMPACT_ARGS))
(use (reg:SI R0_REG))
(clobber (reg:SI R0_REG))
(clobber (reg:SI MACL_REG))
DONE;
}")
+(define_expand "eh_return"
+ [(use (match_operand 0 "register_operand" ""))]
+ ""
+{
+ rtx tmp, ra = operands[0];
+
+ if (TARGET_SHMEDIA64)
+ emit_insn (gen_eh_set_ra_di (ra));
+ else
+ emit_insn (gen_eh_set_ra_si (ra));
+
+ DONE;
+})
+
+;; Clobber the return address on the stack. We can't expand this
+;; until we know where it will be put in the stack frame.
+
+(define_insn "eh_set_ra_si"
+ [(unspec [(match_operand:SI 0 "register_operand" "r")] UNSPEC_EH_RETURN)
+ (clobber (match_scratch:SI 1 "=&r"))]
+ "! TARGET_SHMEDIA64"
+ "#")
+
+(define_insn "eh_set_ra_di"
+ [(unspec [(match_operand:DI 0 "register_operand" "r")] UNSPEC_EH_RETURN)
+ (clobber (match_scratch:DI 1 "=&r"))]
+ "TARGET_SHMEDIA64"
+ "#")
+
+(define_split
+ [(unspec [(match_operand 0 "register_operand" "")] UNSPEC_EH_RETURN)
+ (clobber (match_scratch 1 ""))]
+ "reload_completed"
+ [(const_int 0)]
+ "
+{
+ sh_set_return_address (operands[0], operands[1]);
+ DONE;
+}")
+
(define_insn "blockage"
[(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
""
(match_dup 2))))
(set (reg:SI T_REG)
(ne:SI (ior:SI (match_dup 1) (match_dup 2))
- (const_int 0)))])]
+ (const_int 0)))])]
""
"
{
(match_dup 2))))
(set (reg:SI T_REG)
(ne:SI (ior:SI (match_operand 1 "" "") (match_dup 2))
- (const_int 0)))])]
+ (const_int 0)))])]
"TARGET_SH1"
"operands[2] = gen_reg_rtx (SImode);")
;; GO_IF_LEGITIMATE_ADDRESS guards about bogus addresses before reload,
;; SECONDARY_INPUT_RELOAD_CLASS does this during reload, and the insn's
;; predicate after reload.
-;; The gp_fpul type for r/!c might look a bit odd, but it actually schedules
-;; like a gpr <-> fpul move.
+;; The mac_gp type for r/!c might look a bit odd, but it actually schedules
+;; like a mac -> gpr move.
(define_insn "fpu_switch"
- [(set (match_operand:PSI 0 "register_operand" "=c,c,r,c,c,r,m,r")
- (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c"))]
- "TARGET_SH4
+ [(set (match_operand:PSI 0 "general_movdst_operand" "=c,c,r,c,c,r,m,r,<")
+ (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c,c"))]
+ "TARGET_SH2E
&& (! reload_completed
|| true_regnum (operands[0]) != FPSCR_REG
|| GET_CODE (operands[1]) != MEM
lds %1,fpscr
mov %1,%0
mov.l %1,%0
- sts fpscr,%0"
- [(set_attr "length" "0,2,2,4,2,2,2,2")
- (set_attr "type" "dfp_conv,dfp_conv,load,dfp_conv,dfp_conv,move,store,gp_fpul")
- (set_attr "insn_class" "ldsmem_to_fpscr,*,*,lds_to_fpscr,*,*,*,*")])
+ sts fpscr,%0
+ sts.l fpscr,%0"
+ [(set_attr "length" "0,2,2,4,2,2,2,2,2")
+ (set_attr "type" "nil,mem_fpscr,load,mem_fpscr,gp_fpscr,move,store,mac_gp,store")])
(define_split
[(set (reg:PSI FPSCR_REG)
- (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
+ (mem:PSI (match_operand:SI 0 "register_operand" "")))]
"TARGET_SH4 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
[(set (match_dup 0) (match_dup 0))]
"
(define_split
[(set (reg:PSI FPSCR_REG)
- (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
+ (mem:PSI (match_operand:SI 0 "register_operand" "")))]
"TARGET_SH4"
[(set (match_dup 0) (plus:SI (match_dup 0) (const_int -4)))]
"
[(set (reg:PSI FPSCR_REG)
(xor:PSI (reg:PSI FPSCR_REG) (const_int 1048576)))]
"TARGET_SH4"
- "fschg")
+ "fschg"
+ [(set_attr "fp_set" "unknown")])
(define_expand "addsf3"
[(set (match_operand:SF 0 "arith_reg_operand" "")
(plus:SF (match_operand:SF 1 "arith_reg_operand" "")
(match_operand:SF 2 "arith_reg_operand" "")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH3E)
+ if (TARGET_SH2E)
{
expand_sf_binop (&gen_addsf3_i, operands);
DONE;
(plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fadd.s %1, %2, %0")
+ "fadd.s %1, %2, %0"
+ [(set_attr "type" "fparith_media")])
+
+(define_insn_and_split "unary_sf_op"
+ [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
+ (vec_select:V2SF
+ (vec_concat:V2SF
+ (vec_select:SF
+ (match_dup 0)
+ (parallel [(not:BI (match_operand 3 "const_int_operand" "n"))]))
+ (match_operator:SF 2 "unary_float_operator"
+ [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
+ (parallel [(match_operand 4
+ "const_int_operand" "n")]))]))
+ (parallel [(not:BI (match_dup 3)) (match_dup 3)])))]
+ "TARGET_SHMEDIA_FPU"
+ "#"
+ "TARGET_SHMEDIA_FPU && reload_completed"
+ [(set (match_dup 5) (match_dup 6))]
+ "
+{
+ int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
+ rtx op1 = gen_rtx_REG (SFmode,
+ (true_regnum (operands[1])
+ + (INTVAL (operands[4]) ^ endian)));
+
+ operands[7] = gen_rtx_REG (SFmode,
+ (true_regnum (operands[0])
+ + (INTVAL (operands[3]) ^ endian)));
+ operands[6] = gen_rtx (GET_CODE (operands[2]), SFmode, op1);
+}"
+ [(set_attr "type" "fparith_media")])
+
+(define_insn_and_split "binary_sf_op"
+ [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
+ (vec_select:V2SF
+ (vec_concat:V2SF
+ (vec_select:SF
+ (match_dup 0)
+ (parallel [(match_operand 7 "const_int_operand" "n")]))
+ (match_operator:SF 3 "binary_float_operator"
+ [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
+ (parallel [(match_operand 5
+ "const_int_operand" "n")]))
+ (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
+ (parallel [(match_operand 6
+ "const_int_operand" "n")]))]))
+ (parallel [(match_dup 7) (match_operand 4 "const_int_operand" "n")])))]
+ "TARGET_SHMEDIA_FPU && INTVAL (operands[4]) != INTVAL (operands[7])"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 8) (match_dup 9))]
+ "
+{
+ int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
+ rtx op1 = gen_rtx_REG (SFmode,
+ (true_regnum (operands[1])
+ + (INTVAL (operands[5]) ^ endian)));
+ rtx op2 = gen_rtx_REG (SFmode,
+ (true_regnum (operands[2])
+ + (INTVAL (operands[6]) ^ endian)));
+
+ operands[8] = gen_rtx_REG (SFmode,
+ (true_regnum (operands[0])
+ + (INTVAL (operands[4]) ^ endian)));
+ operands[9] = gen_rtx (GET_CODE (operands[3]), SFmode, op1, op2);
+}"
+ [(set_attr "type" "fparith_media")])
(define_insn "addsf3_i"
[(set (match_operand:SF 0 "arith_reg_operand" "=f")
(plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
(match_operand:SF 2 "arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
- "TARGET_SH3E"
+ "TARGET_SH2E"
"fadd %2,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
(match_operand:SF 2 "fp_arith_reg_operand" "")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH3E)
+ if (TARGET_SH2E)
{
expand_sf_binop (&gen_subsf3_i, operands);
DONE;
(minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fsub.s %1, %2, %0")
+ "fsub.s %1, %2, %0"
+ [(set_attr "type" "fparith_media")])
(define_insn "subsf3_i"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
- "TARGET_SH3E"
+ "TARGET_SH2E"
"fsub %2,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
(match_operand:SF 2 "fp_arith_reg_operand" "")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
if (TARGET_SH4)
expand_sf_binop (&gen_mulsf3_i4, operands);
- else if (TARGET_SH3E)
+ else if (TARGET_SH2E)
emit_insn (gen_mulsf3_ie (operands[0], operands[1], operands[2]));
if (! TARGET_SHMEDIA)
DONE;
(mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fmul.s %1, %2, %0")
+ "fmul.s %1, %2, %0"
+ [(set_attr "type" "fparith_media")])
(define_insn "mulsf3_i4"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
- "TARGET_SH3E"
+ "TARGET_SH2E"
"fmul %2,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))]
- "TARGET_SH3E && ! TARGET_SH4"
+ "TARGET_SH2E && ! TARGET_SH4"
"fmul %2,%0"
[(set_attr "type" "fp")])
(match_operand:SF 2 "fp_arith_reg_operand" "f"))
(match_operand:SF 3 "fp_arith_reg_operand" "0")))]
"TARGET_SHMEDIA_FPU"
- "fmac.s %1, %2, %0")
+ "fmac.s %1, %2, %0"
+ [(set_attr "type" "fparith_media")])
(define_insn "*macsf3"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(match_operand:SF 2 "fp_arith_reg_operand" "f"))
(match_operand:SF 3 "arith_reg_operand" "0")))
(use (match_operand:PSI 4 "fpscr_operand" "c"))]
- "TARGET_SH3E && ! TARGET_SH4"
+ "TARGET_SH2E && ! TARGET_SH4"
"fmac fr0,%2,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
[(set (match_operand:SF 0 "arith_reg_operand" "")
(div:SF (match_operand:SF 1 "arith_reg_operand" "")
(match_operand:SF 2 "arith_reg_operand" "")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH3E)
+ if (TARGET_SH2E)
{
expand_sf_binop (&gen_divsf3_i, operands);
DONE;
(div:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fdiv.s %1, %2, %0")
+ "fdiv.s %1, %2, %0"
+ [(set_attr "type" "fdiv_media")])
(define_insn "divsf3_i"
[(set (match_operand:SF 0 "arith_reg_operand" "=f")
(div:SF (match_operand:SF 1 "arith_reg_operand" "0")
(match_operand:SF 2 "arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
- "TARGET_SH3E"
+ "TARGET_SH2E"
"fdiv %2,%0"
[(set_attr "type" "fdiv")
(set_attr "fp_mode" "single")])
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(float:SF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "float.qs %1, %0")
+ "float.qs %1, %0"
+ [(set_attr "type" "fpconv_media")])
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(float:SF (match_operand:SI 1 "fpul_operand" "")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
if (TARGET_SH4)
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(float:SF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "float.ls %1, %0")
+ "float.ls %1, %0"
+ [(set_attr "type" "fpconv_media")])
(define_insn "floatsisf2_i4"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(define_insn "*floatsisf2_ie"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(float:SF (match_operand:SI 1 "fpul_operand" "y")))]
- "TARGET_SH3E && ! TARGET_SH4"
+ "TARGET_SH2E && ! TARGET_SH4"
"float %1,%0"
[(set_attr "type" "fp")])
[(set (match_operand:DI 0 "fp_arith_reg_operand" "=f")
(fix:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "ftrc.sq %1, %0")
+ "ftrc.sq %1, %0"
+ [(set_attr "type" "fpconv_media")])
(define_expand "fix_truncsfsi2"
[(set (match_operand:SI 0 "fpul_operand" "=y")
(fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
if (TARGET_SH4)
[(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
(fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "ftrc.sl %1, %0")
+ "ftrc.sl %1, %0"
+ [(set_attr "type" "fpconv_media")])
(define_insn "fix_truncsfsi2_i4"
[(set (match_operand:SI 0 "fpul_operand" "=y")
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
"TARGET_SH4"
"ftrc %1,%0"
- [(set_attr "type" "fp")
+ [(set_attr "type" "ftrc_s")
(set_attr "fp_mode" "single")])
;; ??? This pattern is used nowhere. fix_truncsfsi2 always expands to
(define_insn "*fixsfsi"
[(set (match_operand:SI 0 "fpul_operand" "=y")
(fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
- "TARGET_SH3E && ! TARGET_SH4"
+ "TARGET_SH2E && ! TARGET_SH4"
"ftrc %1,%0"
[(set_attr "type" "fp")])
[(set (reg:SI T_REG)
(gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f")))]
- "TARGET_SH3E && ! TARGET_SH4"
+ "TARGET_SH2E && ! TARGET_SH4"
"fcmp/gt %1,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
[(set (reg:SI T_REG)
(eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f")))]
- "TARGET_SH3E && ! TARGET_SH4"
+ "TARGET_SH2E && ! TARGET_SH4"
"fcmp/eq %1,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
(ior:SI (reg:SI T_REG)
(eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
- "TARGET_SH3E && TARGET_IEEE && ! TARGET_SH4"
+ "TARGET_SH2E && TARGET_IEEE && ! TARGET_SH4"
"* return output_ieee_ccmpeq (insn, operands);"
[(set_attr "length" "4")])
(eq:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fcmpeq.s %1, %2, %0")
+ "fcmpeq.s %1, %2, %0"
+ [(set_attr "type" "fcmp_media")])
(define_insn "cmpgtsf_media"
[(set (match_operand:DI 0 "register_operand" "=r")
(gt:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fcmpgt.s %1, %2, %0")
+ "fcmpgt.s %1, %2, %0"
+ [(set_attr "type" "fcmp_media")])
(define_insn "cmpgesf_media"
[(set (match_operand:DI 0 "register_operand" "=r")
(ge:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fcmpge.s %1, %2, %0")
+ "fcmpge.s %1, %2, %0"
+ [(set_attr "type" "fcmp_media")])
(define_insn "cmpunsf_media"
[(set (match_operand:DI 0 "register_operand" "=r")
(unordered:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fcmpun.s %1, %2, %0")
+ "fcmpun.s %1, %2, %0"
+ [(set_attr "type" "fcmp_media")])
(define_expand "cmpsf"
[(set (reg:SI T_REG)
(compare (match_operand:SF 0 "arith_operand" "")
(match_operand:SF 1 "arith_operand" "")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
sh_compare_op0 = operands[0];
(define_expand "negsf2"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH3E)
+ if (TARGET_SH2E)
{
expand_sf_unop (&gen_negsf2_i, operands);
DONE;
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fneg.s %1, %0")
+ "fneg.s %1, %0"
+ [(set_attr "type" "fmove_media")])
(define_insn "negsf2_i"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_SH3E"
+ "TARGET_SH2E"
"fneg %0"
[(set_attr "type" "fmove")
(set_attr "fp_mode" "single")])
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fsqrt.s %1, %0")
+ "fsqrt.s %1, %0"
+ [(set_attr "type" "fdiv_media")])
(define_insn "sqrtsf2_i"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(define_expand "abssf2"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH3E)
+ if (TARGET_SH2E)
{
expand_sf_unop (&gen_abssf2_i, operands);
DONE;
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fabs.s %1, %0")
+ "fabs.s %1, %0"
+ [(set_attr "type" "fmove_media")])
(define_insn "abssf2_i"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_SH3E"
+ "TARGET_SH2E"
"fabs %0"
[(set_attr "type" "fmove")
(set_attr "fp_mode" "single")])
(plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
(match_operand:DF 2 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fadd.d %1, %2, %0")
+ "fadd.d %1, %2, %0"
+ [(set_attr "type" "dfparith_media")])
(define_insn "adddf3_i"
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
(minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
(match_operand:DF 2 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fsub.d %1, %2, %0")
+ "fsub.d %1, %2, %0"
+ [(set_attr "type" "dfparith_media")])
(define_insn "subdf3_i"
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
(mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
(match_operand:DF 2 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fmul.d %1, %2, %0")
+ "fmul.d %1, %2, %0"
+ [(set_attr "type" "dfmul_media")])
(define_insn "muldf3_i"
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
(div:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
(match_operand:DF 2 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fdiv.d %1, %2, %0")
+ "fdiv.d %1, %2, %0"
+ [(set_attr "type" "dfdiv_media")])
(define_insn "divdf3_i"
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
(float:DF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "float.qd %1, %0")
+ "float.qd %1, %0"
+ [(set_attr "type" "dfpconv_media")])
(define_expand "floatsidf2"
[(set (match_operand:DF 0 "fp_arith_reg_operand" "")
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
(float:DF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "float.ld %1, %0")
+ "float.ld %1, %0"
+ [(set_attr "type" "dfpconv_media")])
(define_insn "floatsidf2_i"
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
[(set (match_operand:DI 0 "fp_arith_reg_operand" "=f")
(fix:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "ftrc.dq %1, %0")
+ "ftrc.dq %1, %0"
+ [(set_attr "type" "dfpconv_media")])
(define_expand "fix_truncdfsi2"
[(set (match_operand:SI 0 "fpul_operand" "")
[(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
(fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "ftrc.dl %1, %0")
+ "ftrc.dl %1, %0"
+ [(set_attr "type" "dfpconv_media")])
(define_insn "fix_truncdfsi2_i"
[(set (match_operand:SI 0 "fpul_operand" "=y")
"TARGET_SH4"
"ftrc %1,%0"
[(set_attr "type" "dfp_conv")
+ (set_attr "dfp_comp" "no")
(set_attr "fp_mode" "double")])
;; ??? This pattern is used nowhere. fix_truncdfsi2 always expands to
;; "#"
;; [(set_attr "length" "4")
;; (set_attr "fp_mode" "double")])
-;;
+;;
;; (define_split
;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
"* return output_ieee_ccmpeq (insn, operands);"
[(set_attr "length" "4")
(set_attr "fp_mode" "double")])
-
+
(define_insn "cmpeqdf_media"
[(set (match_operand:DI 0 "register_operand" "=r")
(eq:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")
(match_operand:DF 2 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fcmpeq.d %1,%2,%0")
+ "fcmpeq.d %1,%2,%0"
+ [(set_attr "type" "fcmp_media")])
(define_insn "cmpgtdf_media"
[(set (match_operand:DI 0 "register_operand" "=r")
(gt:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")
(match_operand:DF 2 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fcmpgt.d %1,%2,%0")
+ "fcmpgt.d %1,%2,%0"
+ [(set_attr "type" "fcmp_media")])
(define_insn "cmpgedf_media"
[(set (match_operand:DI 0 "register_operand" "=r")
(ge:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")
(match_operand:DF 2 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fcmpge.d %1,%2,%0")
+ "fcmpge.d %1,%2,%0"
+ [(set_attr "type" "fcmp_media")])
(define_insn "cmpundf_media"
[(set (match_operand:DI 0 "register_operand" "=r")
(unordered:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")
(match_operand:DF 2 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fcmpun.d %1,%2,%0")
+ "fcmpun.d %1,%2,%0"
+ [(set_attr "type" "fcmp_media")])
(define_expand "cmpdf"
[(set (reg:SI T_REG)
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
(neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fneg.d %1, %0")
+ "fneg.d %1, %0"
+ [(set_attr "type" "fmove_media")])
(define_insn "negdf2_i"
[(set (match_operand:DF 0 "arith_reg_operand" "=f")
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
(sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fsqrt.d %1, %0")
+ "fsqrt.d %1, %0"
+ [(set_attr "type" "dfdiv_media")])
(define_insn "sqrtdf2_i"
[(set (match_operand:DF 0 "arith_reg_operand" "=f")
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
(abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fabs.d %1, %0")
+ "fabs.d %1, %0"
+ [(set_attr "type" "fmove_media")])
(define_insn "absdf2_i"
[(set (match_operand:DF 0 "arith_reg_operand" "=f")
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
(float_extend:DF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fcnv.sd %1, %0")
+ "fcnv.sd %1, %0"
+ [(set_attr "type" "dfpconv_media")])
(define_insn "extendsfdf2_i4"
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
"TARGET_SHMEDIA_FPU"
- "fcnv.ds %1, %0")
+ "fcnv.ds %1, %0"
+ [(set_attr "type" "dfpconv_media")])
(define_insn "truncdfsf2_i4"
[(set (match_operand:SF 0 "fpul_operand" "=y")
(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
(set (mem:SF (match_dup 0))
(match_operand:SF 2 "general_movsrc_operand" ""))]
- "TARGET_SH3E && REGNO (operands[0]) == 0
+ "TARGET_SH2E && REGNO (operands[0]) == 0
&& ((GET_CODE (operands[2]) == REG
&& FP_OR_XD_REGISTER_P (REGNO (operands[2])))
|| (GET_CODE (operands[2]) == SUBREG
(set (match_operand:SF 2 "general_movdst_operand" "")
(mem:SF (match_dup 0)))]
- "TARGET_SH3E && REGNO (operands[0]) == 0
+ "TARGET_SH2E && REGNO (operands[0]) == 0
&& ((GET_CODE (operands[2]) == REG
&& FP_OR_XD_REGISTER_P (REGNO (operands[2])))
|| (GET_CODE (operands[2]) == SUBREG
"mov.l @r15+,r15\;mov.l @r15+,r0"
[(set_attr "length" "4")])
-;; The following description models the
-;; SH4 pipeline using the DFA based scheduler.
-;; The DFA based description is better way to model
-;; a superscalar pipeline as compared to function unit
-;; reservation model.
-;; 1. The function unit based model is oriented to describe at most one
-;; unit reservation by each insn. It is difficult to model unit reservations in multiple
-;; pipeline units by same insn. This can be done using DFA based description.
-;; 2. The execution performance of DFA based scheduler does not depend on processor complexity.
-;; 3. Writing all unit reservations for an instruction class is more natural description
-;; of the pipeline and makes interface of the hazard recognizer simpler than the
-;; old function unit based model.
-;; 4. The DFA model is richer and is a part of greater overall framework of RCSP.
-
+;; Integer vector moves
-;; Two automata are defined to reduce number of states
-;; which a single large automaton will have.(Factoring)
+(define_expand "movv8qi"
+ [(set (match_operand:V8QI 0 "general_movdst_operand" "")
+ (match_operand:V8QI 1 "general_movsrc_operand" ""))]
+ "TARGET_SHMEDIA"
+ "{ if (prepare_move_operands (operands, V8QImode)) DONE; }")
-(define_automaton "inst_pipeline,fpu_pipe")
+(define_insn "movv8qi_i"
+ [(set (match_operand:V8QI 0 "general_movdst_operand" "=r,r,r,rl,m")
+ (match_operand:V8QI 1 "general_movsrc_operand" "r,I16C16Z,nW,m,rlZ"))]
+ "TARGET_SHMEDIA
+ && (register_operand (operands[0], V8QImode)
+ || sh_register_operand (operands[1], V8QImode))"
+ "@
+ add %1, r63, %0
+ movi %1, %0
+ #
+ ld%M1.q %m1, %0
+ st%M0.q %m0, %N1"
+ [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
+ (set_attr "length" "4,4,16,4,4")])
-;; This unit is basically the decode unit of the processor.
-;; Since SH4 is a dual issue machine,it is as if there are two
-;; units so that any insn can be processed by either one
-;; of the decoding unit.
+(define_split
+ [(set (match_operand:V8QI 0 "arith_reg_dest" "")
+ (subreg:V8QI (const_int 0) 0))]
+ "TARGET_SHMEDIA"
+ [(set (match_dup 0)
+ (const_vector:V8QI [(const_int 0) (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)]))])
-(define_cpu_unit "pipe_01,pipe_02" "inst_pipeline")
+(define_split
+ [(set (match_operand 0 "arith_reg_dest" "")
+ (match_operand 1 "sh_rep_vec" ""))]
+ "TARGET_SHMEDIA && reload_completed
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])
+ && VECTOR_MODE_SUPPORTED_P (GET_MODE (operands[0]))
+ && GET_MODE_SIZE (GET_MODE (operands[0])) == 8
+ && (XVECEXP (operands[1], 0, 0) != const0_rtx
+ || XVECEXP (operands[1], 0, 1) != const0_rtx)
+ && (XVECEXP (operands[1], 0, 0) != constm1_rtx
+ || XVECEXP (operands[1], 0, 1) != constm1_rtx)"
+ [(set (match_dup 0) (match_dup 1))
+ (match_dup 2)]
+ "
+{
+ int unit_size = GET_MODE_UNIT_SIZE (GET_MODE (operands[1]));
+ rtx elt1 = XVECEXP (operands[1], 0, 1);
+
+ if (unit_size > 2)
+ operands[2] = gen_mshflo_l (operands[0], operands[0], operands[0]);
+ else
+ {
+ if (unit_size < 2)
+ operands[0] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
+ operands[2] = gen_mperm_w0 (operands[0], operands[0]);
+ }
+ operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));
+ operands[1] = XVECEXP (operands[1], 0, 0);
+ if (unit_size < 2)
+ {
+ if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (elt1) == CONST_INT)
+ operands[1] = GEN_INT (TARGET_LITTLE_ENDIAN
+ ? INTVAL (operands[1]) + (INTVAL (elt1) << 8)
+ : (INTVAL (operands[1]) << 8) + INTVAL (elt1));
+ else
+ {
+ operands[0] = gen_rtx_REG (V2QImode, true_regnum (operands[0]));
+ operands[1]
+ = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, operands[1], elt1));
+ }
+ }
+}")
+(define_split
+ [(set (match_operand 0 "arith_reg_dest" "")
+ (match_operand 1 "sh_const_vec" ""))]
+ "TARGET_SHMEDIA && reload_completed
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])
+ && VECTOR_MODE_SUPPORTED_P (GET_MODE (operands[0]))
+ && operands[1] != CONST0_RTX (GET_MODE (operands[1]))"
+ [(set (match_dup 0) (match_dup 1))]
+ "
+{
+ rtx v = operands[1];
+ enum machine_mode new_mode
+ = mode_for_size (GET_MODE_BITSIZE (GET_MODE (v)), MODE_INT, 0);
-;; The fixed point arithmetic calculator(?? EX Unit).
+ operands[0] = gen_rtx_REG (new_mode, true_regnum (operands[0]));
+ operands[1]
+ = simplify_subreg (new_mode, operands[1], GET_MODE (operands[1]), 0);
+}")
-(define_cpu_unit "int" "inst_pipeline")
+(define_expand "movv2hi"
+ [(set (match_operand:V2HI 0 "general_movdst_operand" "")
+ (match_operand:V2HI 1 "general_movsrc_operand" ""))]
+ "TARGET_SHMEDIA"
+ "{ if (prepare_move_operands (operands, V2HImode)) DONE; }")
-;; f1_1 and f1_2 are floating point units.Actually there is
-;; a f1 unit which can overlap with other f1 unit but
-;; not another F1 unit.It is as though there were two
-;; f1 units.
+(define_insn "movv2hi_i"
+ [(set (match_operand:V2HI 0 "general_movdst_operand" "=r,r,r,rl,m")
+ (match_operand:V2HI 1 "general_movsrc_operand" "r,I16C16Z,nW,m,rlZ"))]
+ "TARGET_SHMEDIA
+ && (register_operand (operands[0], V2HImode)
+ || sh_register_operand (operands[1], V2HImode))"
+ "@
+ addz.l %1, r63, %0
+ movi %1, %0
+ #
+ ld%M1.l %m1, %0
+ st%M0.l %m0, %N1"
+ [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
+ (set_attr "length" "4,4,16,4,4")])
-(define_cpu_unit "f1_1,f1_2" "fpu_pipe")
+(define_expand "movv4hi"
+ [(set (match_operand:V4HI 0 "general_movdst_operand" "")
+ (match_operand:V4HI 1 "general_movsrc_operand" ""))]
+ "TARGET_SHMEDIA"
+ "{ if (prepare_move_operands (operands, V4HImode)) DONE; }")
-;; The floating point units.
+(define_insn "movv4hi_i"
+ [(set (match_operand:V4HI 0 "general_movdst_operand" "=r,r,r,rl,m")
+ (match_operand:V4HI 1 "general_movsrc_operand" "r,I16C16Z,nW,m,rlZ"))]
+ "TARGET_SHMEDIA
+ && (register_operand (operands[0], V4HImode)
+ || sh_register_operand (operands[1], V4HImode))"
+ "@
+ add %1, r63, %0
+ movi %1, %0
+ #
+ ld%M1.q %m1, %0
+ st%M0.q %m0, %N1"
+ [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
+ (set_attr "length" "4,4,16,4,4")])
-(define_cpu_unit "F1,F2,F3,FS" "fpu_pipe")
+(define_expand "movv2si"
+ [(set (match_operand:V2SI 0 "general_movdst_operand" "")
+ (match_operand:V2SI 1 "general_movsrc_operand" ""))]
+ "TARGET_SHMEDIA"
+ "{ if (prepare_move_operands (operands, V2SImode)) DONE; }")
-;; This is basically the MA unit of SH4
-;; used in LOAD/STORE pipeline.
+(define_insn "movv2si_i"
+ [(set (match_operand:V2SI 0 "general_movdst_operand" "=r,r,r,rl,m")
+ (match_operand:V2SI 1 "general_movsrc_operand" "r,I16C16Z,nW,m,rlZ"))]
+ "TARGET_SHMEDIA
+ && (register_operand (operands[0], V2SImode)
+ || sh_register_operand (operands[1], V2SImode))"
+ "@
+ add %1, r63, %0
+ #
+ #
+ ld%M1.q %m1, %0
+ st%M0.q %m0, %N1"
+ [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
+ (set_attr "length" "4,4,16,4,4")])
-(define_cpu_unit "memory" "inst_pipeline")
+;; Multimedia Intrinsics
-;; The address calculator used for branch instructions.
-;; This will be reserved with "issue" of branch instructions
-;; and this is to make sure that no two branch instructions
-;; can be issued in parallel.
+(define_insn "absv2si2"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (abs:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "mabs.l %1, %0"
+ [(set_attr "type" "mcmp_media")])
-(define_cpu_unit "pcr_addrcalc" "inst_pipeline")
+(define_insn "absv4hi2"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (abs:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "mabs.w %1, %0"
+ [(set_attr "type" "mcmp_media")])
-;; ----------------------------------------------------
-;; This reservation is to simplify the dual issue description.
+(define_insn "addv2si3"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
+ (match_operand:V2SI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "madd.l %1, %2, %0"
+ [(set_attr "type" "arith_media")])
-(define_reservation "issue" "pipe_01|pipe_02")
+(define_insn "addv4hi3"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
+ (match_operand:V4HI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "madd.w %1, %2, %0"
+ [(set_attr "type" "arith_media")])
-;; This is to express the locking of D stage.
+(define_insn "ssaddv2si3"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (ss_plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
+ (match_operand:V2SI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "madds.l %1, %2, %0"
+ [(set_attr "type" "mcmp_media")])
-(define_reservation "d_lock" "pipe_01+pipe_02")
+(define_insn "usaddv8qi3"
+ [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
+ (us_plus:V8QI (match_operand:V8QI 1 "arith_reg_operand" "%r")
+ (match_operand:V8QI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "madds.ub %1, %2, %0"
+ [(set_attr "type" "mcmp_media")])
-;; This is to simplify description where F1,F2,FS
-;; are used simultaneously.
+(define_insn "ssaddv4hi3"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (ss_plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
+ (match_operand:V4HI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "madds.w %1, %2, %0"
+ [(set_attr "type" "mcmp_media")])
-(define_reservation "fpu" "F1+F2+FS")
+(define_insn "negcmpeqv8qi"
+ [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
+ (neg:V8QI (eq:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
+ (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
+ "TARGET_SHMEDIA"
+ "mcmpeq.b %N1, %N2, %0"
+ [(set_attr "type" "mcmp_media")])
-;; This is to highlight the fact that f1
-;; cannot overlap with F1.
+(define_insn "negcmpeqv2si"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (neg:V2SI (eq:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
+ (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
+ "TARGET_SHMEDIA"
+ "mcmpeq.l %N1, %N2, %0"
+ [(set_attr "type" "mcmp_media")])
-(exclusion_set "f1_1,f1_2" "F1")
+(define_insn "negcmpeqv4hi"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (neg:V4HI (eq:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
+ (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
+ "TARGET_SHMEDIA"
+ "mcmpeq.w %N1, %N2, %0"
+ [(set_attr "type" "mcmp_media")])
-;; Although reg moves have a latency of zero
-;; we need to highlight that they use D stage
-;; for one cycle.
+(define_insn "negcmpgtuv8qi"
+ [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
+ (neg:V8QI (gtu:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
+ (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
+ "TARGET_SHMEDIA"
+ "mcmpgt.ub %N1, %N2, %0"
+ [(set_attr "type" "mcmp_media")])
-(define_insn_reservation "reg_mov" 0
- (eq_attr "type" "move,fmove")
- "issue")
+(define_insn "negcmpgtv2si"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (neg:V2SI (gt:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
+ (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
+ "TARGET_SHMEDIA"
+ "mcmpgt.l %N1, %N2, %0"
+ [(set_attr "type" "mcmp_media")])
-;; Other MT group intructions(1 step operations)
-;; Group: MT
-;; Latency: 1
-;; Issue Rate: 1
+(define_insn "negcmpgtv4hi"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (neg:V4HI (gt:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
+ (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
+ "TARGET_SHMEDIA"
+ "mcmpgt.w %N1, %N2, %0"
+ [(set_attr "type" "mcmp_media")])
+
+(define_insn "mcmv"
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:DI 2 "arith_reg_operand" "r"))
+ (and:DI (match_operand:DI 3 "arith_reg_operand" "0")
+ (not:DI (match_dup 2)))))]
+ "TARGET_SHMEDIA"
+ "mcmv %N1, %2, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "mcnvs_lw"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (vec_concat:V4HI
+ (ss_truncate:V2HI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ"))
+ (ss_truncate:V2HI (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
+ "TARGET_SHMEDIA"
+ "mcnvs.lw %N1, %N2, %0"
+ [(set_attr "type" "mcmp_media")])
+
+(define_insn "mcnvs_wb"
+ [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
+ (vec_concat:V8QI
+ (ss_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
+ (ss_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
+ "TARGET_SHMEDIA"
+ "mcnvs.wb %N1, %N2, %0"
+ [(set_attr "type" "mcmp_media")])
+
+(define_insn "mcnvs_wub"
+ [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
+ (vec_concat:V8QI
+ (us_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
+ (us_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
+ "TARGET_SHMEDIA"
+ "mcnvs.wub %N1, %N2, %0"
+ [(set_attr "type" "mcmp_media")])
+
+(define_insn "mextr_rl"
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:HI 3 "mextr_bit_offset" "i"))
+ (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
+ (match_operand:HI 4 "mextr_bit_offset" "i"))))]
+ "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
+ "*
+{
+ static char templ[16];
-(define_insn_reservation "mt" 1
- (eq_attr "insn_class" "mt_group")
- "issue,nothing")
+ sprintf (templ, \"mextr%d\\t%%N1, %%N2, %%0\",
+ (int) INTVAL (operands[3]) >> 3);
+ return templ;
+}"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "*mextr_lr"
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:HI 3 "mextr_bit_offset" "i"))
+ (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
+ (match_operand:HI 4 "mextr_bit_offset" "i"))))]
+ "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
+ "*
+{
+ static char templ[16];
-;; Fixed Point Arithmetic Instructions(1 step operations)
-;; Group: EX
-;; Latency: 1
-;; Issue Rate: 1
+ sprintf (templ, \"mextr%d\\t%%N2, %%N1, %%0\",
+ (int) INTVAL (operands[4]) >> 3);
+ return templ;
+}"
+ [(set_attr "type" "arith_media")])
+
+; mextrN can be modelled with vec_select / vec_concat, but the selection
+; vector then varies depending on endianness.
+(define_expand "mextr1"
+ [(match_operand:DI 0 "arith_reg_dest" "")
+ (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
+ GEN_INT (1 * 8), GEN_INT (7 * 8)));
+ DONE;
+}")
+
+(define_expand "mextr2"
+ [(match_operand:DI 0 "arith_reg_dest" "")
+ (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
+ GEN_INT (2 * 8), GEN_INT (6 * 8)));
+ DONE;
+}")
+
+(define_expand "mextr3"
+ [(match_operand:DI 0 "arith_reg_dest" "")
+ (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
+ GEN_INT (3 * 8), GEN_INT (5 * 8)));
+ DONE;
+}")
+
+(define_expand "mextr4"
+ [(match_operand:DI 0 "arith_reg_dest" "")
+ (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
+ GEN_INT (4 * 8), GEN_INT (4 * 8)));
+ DONE;
+}")
+
+(define_expand "mextr5"
+ [(match_operand:DI 0 "arith_reg_dest" "")
+ (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
+ GEN_INT (5 * 8), GEN_INT (3 * 8)));
+ DONE;
+}")
-(define_insn_reservation "simple_arith" 1
- (eq_attr "insn_class" "ex_group")
- "issue,int")
+(define_expand "mextr6"
+ [(match_operand:DI 0 "arith_reg_dest" "")
+ (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
+ GEN_INT (6 * 8), GEN_INT (2 * 8)));
+ DONE;
+}")
+
+(define_expand "mextr7"
+ [(match_operand:DI 0 "arith_reg_dest" "")
+ (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
+ GEN_INT (7 * 8), GEN_INT (1 * 8)));
+ DONE;
+}")
+
+(define_expand "mmacfx_wl"
+ [(match_operand:V2SI 0 "arith_reg_dest" "")
+ (match_operand:V2HI 1 "extend_reg_operand" "")
+ (match_operand:V2HI 2 "extend_reg_operand" "")
+ (match_operand:V2SI 3 "arith_reg_operand" "")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn (gen_mmacfx_wl_i (operands[0], operands[3],
+ operands[1], operands[2]));
+ DONE;
+}")
+
+(define_insn "mmacfx_wl_i"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (ss_plus:V2SI
+ (match_operand:V2SI 1 "arith_reg_operand" "0")
+ (ss_truncate:V2SI
+ (ashift:V2DI
+ (sign_extend:V2DI
+ (mult:V2SI
+ (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
+ (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
+ (const_int 1)))))]
+ "TARGET_SHMEDIA"
+ "mmacfx.wl %2, %3, %0"
+ [(set_attr "type" "mac_media")])
+
+(define_expand "mmacnfx_wl"
+ [(match_operand:V2SI 0 "arith_reg_dest" "")
+ (match_operand:V2HI 1 "extend_reg_operand" "")
+ (match_operand:V2HI 2 "extend_reg_operand" "")
+ (match_operand:V2SI 3 "arith_reg_operand" "")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn (gen_mmacnfx_wl_i (operands[0], operands[3],
+ operands[1], operands[2]));
+ DONE;
+}")
+
+(define_insn "mmacnfx_wl_i"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (ss_minus:V2SI
+ (match_operand:V2SI 1 "arith_reg_operand" "0")
+ (ss_truncate:V2SI
+ (ashift:V2DI
+ (sign_extend:V2DI
+ (mult:V2SI
+ (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
+ (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
+ (const_int 1)))))]
+ "TARGET_SHMEDIA"
+ "mmacnfx.wl %2, %3, %0"
+ [(set_attr "type" "mac_media")])
+
+(define_insn "mulv2si3"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (mult:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
+ (match_operand:V2SI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "mmul.l %1, %2, %0"
+ [(set_attr "type" "d2mpy_media")])
+
+(define_insn "mulv4hi3"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (mult:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
+ (match_operand:V4HI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "mmul.w %1, %2, %0"
+ [(set_attr "type" "dmpy_media")])
+
+(define_insn "mmulfx_l"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (ss_truncate:V2SI
+ (ashiftrt:V2DI
+ (mult:V2DI
+ (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
+ (sign_extend:V2DI (match_operand:V2SI 2 "arith_reg_operand" "r")))
+ (const_int 31))))]
+ "TARGET_SHMEDIA"
+ "mmulfx.l %1, %2, %0"
+ [(set_attr "type" "d2mpy_media")])
+
+(define_insn "mmulfx_w"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (ss_truncate:V4HI
+ (ashiftrt:V4SI
+ (mult:V4SI
+ (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
+ (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
+ (const_int 15))))]
+ "TARGET_SHMEDIA"
+ "mmulfx.w %1, %2, %0"
+ [(set_attr "type" "dmpy_media")])
+
+(define_insn "mmulfxrp_w"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (ss_truncate:V4HI
+ (ashiftrt:V4SI
+ (plus:V4SI
+ (mult:V4SI
+ (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
+ (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
+ (const_int 16384))
+ (const_int 15))))]
+ "TARGET_SHMEDIA"
+ "mmulfxrp.w %1, %2, %0"
+ [(set_attr "type" "dmpy_media")])
+
+(define_expand "mmulhi_wl"
+ [(match_operand:V2SI 0 "arith_reg_dest" "")
+ (match_operand:V4HI 1 "arith_reg_operand" "")
+ (match_operand:V4HI 2 "arith_reg_operand" "")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul23_wl : gen_mmul01_wl)
+ (operands[0], operands[1], operands[2]));
+ DONE;
+}")
+
+(define_expand "mmullo_wl"
+ [(match_operand:V2SI 0 "arith_reg_dest" "")
+ (match_operand:V4HI 1 "arith_reg_operand" "")
+ (match_operand:V4HI 2 "arith_reg_operand" "")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul01_wl : gen_mmul23_wl)
+ (operands[0], operands[1], operands[2]));
+ DONE;
+}")
+
+(define_insn "mmul23_wl"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (vec_select:V2SI
+ (mult:V4SI
+ (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
+ (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
+ (parallel [(const_int 2) (const_int 3)])))]
+ "TARGET_SHMEDIA"
+ "* return (TARGET_LITTLE_ENDIAN
+ ? \"mmulhi.wl %1, %2, %0\"
+ : \"mmullo.wl %1, %2, %0\");"
+ [(set_attr "type" "dmpy_media")])
+
+(define_insn "mmul01_wl"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (vec_select:V2SI
+ (mult:V4SI
+ (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
+ (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
+ (parallel [(const_int 0) (const_int 1)])))]
+ "TARGET_SHMEDIA"
+ "* return (TARGET_LITTLE_ENDIAN
+ ? \"mmullo.wl %1, %2, %0\"
+ : \"mmulhi.wl %1, %2, %0\");"
+ [(set_attr "type" "dmpy_media")])
+
+(define_expand "mmulsum_wq"
+ [(match_operand:DI 0 "arith_reg_dest" "")
+ (match_operand:V4HI 1 "arith_reg_operand" "")
+ (match_operand:V4HI 2 "arith_reg_operand" "")
+ (match_operand:DI 3 "arith_reg_operand" "")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn (gen_mmulsum_wq_i (operands[0], operands[3],
+ operands[1], operands[2]));
+ DONE;
+}")
+
+(define_insn "mmulsum_wq_i"
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (plus:DI (match_operand:DI 1 "arith_reg_operand" "0")
+ (plus:DI
+ (plus:DI
+ (vec_select:DI
+ (mult:V4DI
+ (sign_extend:V4DI (match_operand:V4HI 2 "arith_reg_operand" "r"))
+ (sign_extend:V4DI (match_operand:V4HI 3 "arith_reg_operand" "r")))
+ (parallel [(const_int 0)]))
+ (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
+ (sign_extend:V4DI (match_dup 3)))
+ (parallel [(const_int 1)])))
+ (plus:DI
+ (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
+ (sign_extend:V4DI (match_dup 3)))
+ (parallel [(const_int 2)]))
+ (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
+ (sign_extend:V4DI (match_dup 3)))
+ (parallel [(const_int 3)]))))))]
+ "TARGET_SHMEDIA"
+ "mmulsum.wq %2, %3, %0"
+ [(set_attr "type" "mac_media")])
+
+(define_expand "mperm_w"
+ [(match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (match_operand:V4HI 1 "arith_reg_operand" "r")
+ (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mperm_w_little : gen_mperm_w_big)
+ (operands[0], operands[1], operands[2]));
+ DONE;
+}")
+
+; This use of vec_select isn't exactly correct according to rtl.texi
+; (because not constant), but it seems a straightforward extension.
+(define_insn "mperm_w_little"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (vec_select:V4HI
+ (match_operand:V4HI 1 "arith_reg_operand" "r")
+ (parallel
+ [(zero_extract:QI (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")
+ (const_int 2) (const_int 0))
+ (zero_extract:QI (match_dup 2) (const_int 2) (const_int 2))
+ (zero_extract:QI (match_dup 2) (const_int 2) (const_int 4))
+ (zero_extract:QI (match_dup 2) (const_int 2) (const_int 6))])))]
+ "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
+ "mperm.w %1, %N2, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "mperm_w_big"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (vec_select:V4HI
+ (match_operand:V4HI 1 "arith_reg_operand" "r")
+ (parallel
+ [(zero_extract:QI (not:QI (match_operand:QI 2
+ "extend_reg_or_0_operand" "rZ"))
+ (const_int 2) (const_int 0))
+ (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 2))
+ (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 4))
+ (zero_extract:QI (not:QI (match_dup 2))
+ (const_int 2) (const_int 6))])))]
+ "TARGET_SHMEDIA && ! TARGET_LITTLE_ENDIAN"
+ "mperm.w %1, %N2, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "mperm_w0"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (vec_duplicate:V4HI (truncate:HI (match_operand 1
+ "trunc_hi_operand" "r"))))]
+ "TARGET_SHMEDIA"
+ "mperm.w %1, r63, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_expand "msad_ubq"
+ [(match_operand:DI 0 "arith_reg_dest" "")
+ (match_operand:V8QI 1 "arith_reg_or_0_operand" "")
+ (match_operand:V8QI 2 "arith_reg_or_0_operand" "")
+ (match_operand:DI 3 "arith_reg_operand" "")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn (gen_msad_ubq_i (operands[0], operands[3],
+ operands[1], operands[2]));
+ DONE;
+}")
+
+(define_insn "msad_ubq_i"
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (plus:DI
+ (plus:DI
+ (plus:DI
+ (plus:DI
+ (match_operand:DI 1 "arith_reg_operand" "0")
+ (abs:DI (vec_select:DI
+ (minus:V8DI
+ (zero_extend:V8DI
+ (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
+ (zero_extend:V8DI
+ (match_operand:V8QI 3 "arith_reg_or_0_operand" "rZ")))
+ (parallel [(const_int 0)]))))
+ (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
+ (zero_extend:V8DI (match_dup 3)))
+ (parallel [(const_int 1)]))))
+ (plus:DI
+ (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
+ (zero_extend:V8DI (match_dup 3)))
+ (parallel [(const_int 2)])))
+ (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
+ (zero_extend:V8DI (match_dup 3)))
+ (parallel [(const_int 3)])))))
+ (plus:DI
+ (plus:DI
+ (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
+ (zero_extend:V8DI (match_dup 3)))
+ (parallel [(const_int 4)])))
+ (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
+ (zero_extend:V8DI (match_dup 3)))
+ (parallel [(const_int 5)]))))
+ (plus:DI
+ (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
+ (zero_extend:V8DI (match_dup 3)))
+ (parallel [(const_int 6)])))
+ (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
+ (zero_extend:V8DI (match_dup 3)))
+ (parallel [(const_int 7)])))))))]
+ "TARGET_SHMEDIA"
+ "msad.ubq %N2, %N3, %0"
+ [(set_attr "type" "mac_media")])
+
+(define_insn "mshalds_l"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (ss_truncate:V2SI
+ (ashift:V2DI
+ (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
+ (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
+ (const_int 31)))))]
+ "TARGET_SHMEDIA"
+ "mshalds.l %1, %2, %0"
+ [(set_attr "type" "mcmp_media")])
+
+(define_insn "mshalds_w"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (ss_truncate:V4HI
+ (ashift:V4SI
+ (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
+ (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
+ (const_int 15)))))]
+ "TARGET_SHMEDIA"
+ "mshalds.w %1, %2, %0"
+ [(set_attr "type" "mcmp_media")])
+
+(define_insn "ashrv2si3"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (ashiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
+ (match_operand:DI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "mshard.l %1, %2, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "ashrv4hi3"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (ashiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
+ (match_operand:DI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "mshard.w %1, %2, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "mshards_q"
+ [(set (match_operand:HI 0 "arith_reg_dest" "=r")
+ (ss_truncate:HI
+ (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rZ"))))]
+ "TARGET_SHMEDIA"
+ "mshards.q %1, %N2, %0"
+ [(set_attr "type" "mcmp_media")])
+
+(define_expand "mshfhi_b"
+ [(match_operand:V8QI 0 "arith_reg_dest" "")
+ (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_b : gen_mshf0_b)
+ (operands[0], operands[1], operands[2]));
+ DONE;
+}")
+
+(define_expand "mshflo_b"
+ [(match_operand:V8QI 0 "arith_reg_dest" "")
+ (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_b : gen_mshf4_b)
+ (operands[0], operands[1], operands[2]));
+ DONE;
+}")
+
+(define_insn "mshf4_b"
+ [(set
+ (match_operand:V8QI 0 "arith_reg_dest" "=r")
+ (vec_select:V8QI
+ (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
+ (parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13)
+ (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))]
+ "TARGET_SHMEDIA"
+ "* return (TARGET_LITTLE_ENDIAN
+ ? \"mshfhi.b %N1, %N2, %0\"
+ : \"mshflo.b %N1, %N2, %0\");"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "mshf0_b"
+ [(set
+ (match_operand:V8QI 0 "arith_reg_dest" "=r")
+ (vec_select:V8QI
+ (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
+ (parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9)
+ (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))]
+ "TARGET_SHMEDIA"
+ "* return (TARGET_LITTLE_ENDIAN
+ ? \"mshflo.b %N1, %N2, %0\"
+ : \"mshfhi.b %N1, %N2, %0\");"
+ [(set_attr "type" "arith_media")])
+
+(define_expand "mshfhi_l"
+ [(match_operand:V2SI 0 "arith_reg_dest" "")
+ (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_l : gen_mshf0_l)
+ (operands[0], operands[1], operands[2]));
+ DONE;
+}")
+
+(define_expand "mshflo_l"
+ [(match_operand:V2SI 0 "arith_reg_dest" "")
+ (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_l : gen_mshf4_l)
+ (operands[0], operands[1], operands[2]));
+ DONE;
+}")
+
+(define_insn "mshf4_l"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (vec_select:V2SI
+ (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
+ (parallel [(const_int 1) (const_int 3)])))]
+ "TARGET_SHMEDIA"
+ "* return (TARGET_LITTLE_ENDIAN
+ ? \"mshfhi.l %N1, %N2, %0\"
+ : \"mshflo.l %N1, %N2, %0\");"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "mshf0_l"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (vec_select:V2SI
+ (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
+ (parallel [(const_int 0) (const_int 2)])))]
+ "TARGET_SHMEDIA"
+ "* return (TARGET_LITTLE_ENDIAN
+ ? \"mshflo.l %N1, %N2, %0\"
+ : \"mshfhi.l %N1, %N2, %0\");"
+ [(set_attr "type" "arith_media")])
+
+(define_expand "mshfhi_w"
+ [(match_operand:V4HI 0 "arith_reg_dest" "")
+ (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_w : gen_mshf0_w)
+ (operands[0], operands[1], operands[2]));
+ DONE;
+}")
+
+(define_expand "mshflo_w"
+ [(match_operand:V4HI 0 "arith_reg_dest" "")
+ (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
+ "TARGET_SHMEDIA"
+ "
+{
+ emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_w : gen_mshf4_w)
+ (operands[0], operands[1], operands[2]));
+ DONE;
+}")
+
+(define_insn "mshf4_w"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (vec_select:V4HI
+ (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
+ (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))]
+ "TARGET_SHMEDIA"
+ "* return (TARGET_LITTLE_ENDIAN
+ ? \"mshfhi.w %N1, %N2, %0\"
+ : \"mshflo.w %N1, %N2, %0\");"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "mshf0_w"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (vec_select:V4HI
+ (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
+ (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))]
+ "TARGET_SHMEDIA"
+ "* return (TARGET_LITTLE_ENDIAN
+ ? \"mshflo.w %N1, %N2, %0\"
+ : \"mshfhi.w %N1, %N2, %0\");"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "mshflo_w_x"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (vec_select:V4HI
+ (vec_concat:V4HI (match_operand:V2HI 1 "extend_reg_or_0_operand" "rZ")
+ (match_operand:V2HI 2 "extend_reg_or_0_operand" "rZ"))
+ (parallel [(const_int 2) (const_int 0) (const_int 3) (const_int 1)])))]
+ "TARGET_SHMEDIA"
+ "mshflo.w %N1, %N2, %0"
+ [(set_attr "type" "arith_media")])
+
+/* These are useful to expand ANDs and as combiner patterns. */
+(define_insn_and_split "mshfhi_l_di"
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r,f")
+ (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ,f")
+ (const_int 32))
+ (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ,?f")
+ (const_int -4294967296))))]
+ "TARGET_SHMEDIA"
+ "@
+ mshfhi.l %N1, %N2, %0
+ #"
+ "TARGET_SHMEDIA && reload_completed
+ && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
+ [(set (match_dup 3) (match_dup 4))
+ (set (match_dup 5) (match_dup 6))]
+ "
+{
+ operands[3] = gen_lowpart (SImode, operands[0]);
+ operands[4] = gen_highpart (SImode, operands[1]);
+ operands[5] = gen_highpart (SImode, operands[0]);
+ operands[6] = gen_highpart (SImode, operands[2]);
+}"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "*mshfhi_l_di_rev"
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (const_int -4294967296))
+ (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
+ (const_int 32))))]
+ "TARGET_SHMEDIA"
+ "mshfhi.l %N2, %N1, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_split
+ [(set (match_operand:DI 0 "arith_reg_dest" "")
+ (ior:DI (zero_extend:DI (match_operand:SI 1
+ "extend_reg_or_0_operand" ""))
+ (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "")
+ (const_int -4294967296))))
+ (clobber (match_operand:DI 3 "arith_reg_dest" ""))]
+ "TARGET_SHMEDIA"
+ [(const_int 0)]
+ "
+{
+ emit_insn (gen_ashldi3_media (operands[3],
+ simplify_gen_subreg (DImode, operands[1],
+ SImode, 0),
+ GEN_INT (32)));
+ emit_insn (gen_mshfhi_l_di (operands[0], operands[3], operands[2]));
+ DONE;
+}")
+
+(define_insn "mshflo_l_di"
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (const_int 4294967295))
+ (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
+ (const_int 32))))]
+
+ "TARGET_SHMEDIA"
+ "mshflo.l %N1, %N2, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "*mshflo_l_di_rev"
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (const_int 32))
+ (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
+ (const_int 4294967295))))]
+
+ "TARGET_SHMEDIA"
+ "mshflo.l %N2, %N1, %0"
+ [(set_attr "type" "arith_media")])
+
+;; Combiner pattern for trampoline initialization.
+(define_insn_and_split "*double_shori"
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
+ (const_int 32))
+ (match_operand:DI 2 "const_int_operand" "n")))]
+ "TARGET_SHMEDIA
+ && INTVAL (operands[2]) == trunc_int_for_mode (INTVAL (operands[2]), SImode)"
+ "#"
+ "rtx_equal_p (operands[0], operands[1])"
+ [(const_int 0)]
+ "
+{
+ HOST_WIDE_INT v = INTVAL (operands[2]);
+
+ emit_insn (gen_shori_media (operands[0], operands[0],
+ gen_int_mode (INTVAL (operands[2]) >> 16, HImode)));
+ emit_insn (gen_shori_media (operands[0], operands[0],
+ gen_int_mode (v, HImode)));
+ DONE;
+}")
+
+
+(define_insn "*mshflo_l_di_x"
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (ior:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_or_0_operand"
+ "rZ"))
+ (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
+ (const_int 32))))]
+
+ "TARGET_SHMEDIA"
+ "mshflo.l %N1, %N2, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_insn_and_split "concat_v2sf"
+ [(set (match_operand:V2SF 0 "register_operand" "=r,f,f?")
+;; (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,0,f")
+ (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,f,f")
+ (match_operand:SF 2 "register_operand" "rZ,f,f")))]
+
+ "TARGET_SHMEDIA"
+ "@
+ mshflo.l %N1, %N2, %0
+ #
+ #"
+ "TARGET_SHMEDIA && reload_completed
+ && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
+ [(set (match_dup 3) (match_dup 1))
+ (set (match_dup 4) (match_dup 2))]
+ "
+{
+ operands[3] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 0);
+ operands[4] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 4);
+}"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "*mshflo_l_di_x_rev"
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (const_int 32))
+ (zero_extend:DI (match_operand:SI 2 "extend_reg_or_0_operand" "rZ"))))]
+
+ "TARGET_SHMEDIA"
+ "mshflo.l %N2, %N1, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "ashlv2si3"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (ashift:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
+ (match_operand:DI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "mshlld.l %1, %2, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "ashlv4hi3"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (ashift:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
+ (match_operand:DI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "mshlld.w %1, %2, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "lshrv2si3"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (lshiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
+ (match_operand:DI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "mshlrd.l %1, %2, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "lshrv4hi3"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (lshiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
+ (match_operand:DI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "mshlrd.w %1, %2, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "subv2si3"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V2SI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "msub.l %N1, %2, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "subv4hi3"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V4HI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "msub.w %N1, %2, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "sssubv2si3"
+ [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
+ (ss_minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V2SI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "msubs.l %N1, %2, %0"
+ [(set_attr "type" "mcmp_media")])
+
+(define_insn "ussubv8qi3"
+ [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
+ (us_minus:V8QI (match_operand:V8QI 1 "arith_reg_operand" "r")
+ (match_operand:V8QI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "msubs.ub %1, %2, %0"
+ [(set_attr "type" "mcmp_media")])
+
+(define_insn "sssubv4hi3"
+ [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
+ (ss_minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V4HI 2 "arith_reg_operand" "r")))]
+ "TARGET_SHMEDIA"
+ "msubs.w %N1, %2, %0"
+ [(set_attr "type" "mcmp_media")])
+
+;; Floating Point Intrinsics
+
+(define_insn "fcosa_s"
+ [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
+ (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
+ UNSPEC_FCOSA))]
+ "TARGET_SHMEDIA"
+ "fcosa.s %1, %0"
+ [(set_attr "type" "atrans_media")])
+
+(define_insn "fsina_s"
+ [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
+ (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
+ UNSPEC_FSINA))]
+ "TARGET_SHMEDIA"
+ "fsina.s %1, %0"
+ [(set_attr "type" "atrans_media")])
+
+(define_insn "fipr"
+ [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
+ (plus:SF (plus:SF (vec_select:SF (mult:V4SF (match_operand:V4SF 1
+ "fp_arith_reg_operand" "f")
+ (match_operand:V4SF 2
+ "fp_arith_reg_operand" "f"))
+ (parallel [(const_int 0)]))
+ (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
+ (parallel [(const_int 1)])))
+ (plus:SF (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
+ (parallel [(const_int 2)]))
+ (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
+ (parallel [(const_int 3)])))))]
+ "TARGET_SHMEDIA"
+ "fipr %1, %2, %0"
+ [(set_attr "type" "fparith_media")])
+
+(define_insn "fsrra_s"
+ [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
+ (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "f")]
+ UNSPEC_FSRRA))]
+ "TARGET_SHMEDIA"
+ "fsrra.s %1, %0"
+ [(set_attr "type" "atrans_media")])
+
+(define_insn "ftrv"
+ [(set (match_operand:V4SF 0 "fp_arith_reg_operand" "=f")
+ (plus:V4SF
+ (plus:V4SF
+ (mult:V4SF
+ (vec_select:V4SF (match_operand:V16SF 1 "fp_arith_reg_operand" "f")
+ (parallel [(const_int 0) (const_int 5)
+ (const_int 10) (const_int 15)]))
+ (match_operand:V4SF 2 "fp_arith_reg_operand" "f"))
+ (mult:V4SF
+ (vec_select:V4SF (match_dup 1)
+ (parallel [(const_int 4) (const_int 9)
+ (const_int 14) (const_int 3)]))
+ (vec_select:V4SF (match_dup 2)
+ (parallel [(const_int 1) (const_int 2)
+ (const_int 3) (const_int 0)]))))
+ (plus:V4SF
+ (mult:V4SF
+ (vec_select:V4SF (match_dup 1)
+ (parallel [(const_int 8) (const_int 13)
+ (const_int 2) (const_int 7)]))
+ (vec_select:V4SF (match_dup 2)
+ (parallel [(const_int 2) (const_int 3)
+ (const_int 0) (const_int 1)])))
+ (mult:V4SF
+ (vec_select:V4SF (match_dup 1)
+ (parallel [(const_int 12) (const_int 1)
+ (const_int 6) (const_int 11)]))
+ (vec_select:V4SF (match_dup 2)
+ (parallel [(const_int 3) (const_int 0)
+ (const_int 1) (const_int 2)]))))))]
+ "TARGET_SHMEDIA"
+ "ftrv %1, %2, %0"
+ [(set_attr "type" "fparith_media")])
+
+(define_insn "nsb"
+ [(set (match_operand:QI 0 "arith_reg_dest" "=r")
+ (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
+ UNSPEC_NSB))]
+ "TARGET_SHMEDIA"
+ "nsb %1, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "nsbsi"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=r")
+ (zero_extend:SI
+ (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
+ UNSPEC_NSB)))]
+ "TARGET_SHMEDIA"
+ "nsb %1, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "nsbdi"
+ [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+ (zero_extend:DI
+ (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
+ UNSPEC_NSB)))]
+ "TARGET_SHMEDIA"
+ "nsb %1, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_expand "ffsdi2"
+ [(set (match_operand:DI 0 "arith_reg_dest" "")
+ (ffs:DI (match_operand:DI 1 "arith_reg_operand" "")))]
+ "TARGET_SHMEDIA"
+ "
+{
+ rtx scratch = gen_reg_rtx (DImode);
+ rtx last;
+
+ emit_insn (gen_adddi3 (scratch, operands[1], GEN_INT (-1)));
+ emit_insn (gen_xordi3 (scratch, operands[1], scratch));
+ emit_insn (gen_lshrdi3_media (scratch, scratch, const1_rtx));
+ emit_insn (gen_nsbdi (scratch, scratch));
+ emit_insn (gen_adddi3 (scratch, scratch, GEN_INT (-64)));
+ emit_insn (gen_movdicc_false (scratch, operands[1], const0_rtx, scratch));
+ last = emit_insn (gen_subdi3 (operands[0], const0_rtx, scratch));
+ REG_NOTES (last)
+ = gen_rtx_EXPR_LIST (REG_EQUAL,
+ gen_rtx_FFS (DImode, operands[0]), REG_NOTES (last));
+ DONE;
+}")
+
+(define_expand "ffssi2"
+ [(set (match_operand:SI 0 "arith_reg_dest" "")
+ (ffs:SI (match_operand:SI 1 "arith_reg_operand" "")))]
+ "TARGET_SHMEDIA"
+ "
+{
+ rtx scratch = gen_reg_rtx (SImode);
+ rtx discratch = gen_reg_rtx (DImode);
+ rtx last;
+
+ emit_insn (gen_adddi3 (discratch,
+ simplify_gen_subreg (DImode, operands[1], SImode, 0),
+ GEN_INT (-1)));
+ emit_insn (gen_andcdi3 (discratch,
+ simplify_gen_subreg (DImode, operands[1], SImode, 0),
+ discratch));
+ emit_insn (gen_nsbsi (scratch, discratch));
+ last = emit_insn (gen_subsi3 (operands[0],
+ force_reg (SImode, GEN_INT (63)), scratch));
+ REG_NOTES (last)
+ = gen_rtx_EXPR_LIST (REG_EQUAL,
+ gen_rtx_FFS (SImode, operands[0]), REG_NOTES (last));
+ DONE;
+}")
+
+(define_insn "byterev"
+ [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
+ (vec_select:V8QI (match_operand:V8QI 1 "arith_reg_operand" "r")
+ (parallel [(const_int 7) (const_int 6) (const_int 5)
+ (const_int 4) (const_int 3) (const_int 2)
+ (const_int 1) (const_int 0)])))]
+ "TARGET_SHMEDIA"
+ "byterev %1, %0"
+ [(set_attr "type" "arith_media")])
+
+(define_insn "prefetch"
+ [(prefetch (match_operand:QI 0 "address_operand" "p")
+ (match_operand:SI 1 "const_int_operand" "n")
+ (match_operand:SI 2 "const_int_operand" "n"))]
+ "TARGET_SHMEDIA"
+ "*
+{
+ operands[0] = gen_rtx_MEM (QImode, operands[0]);
+ output_asm_insn (\"ld%M0.b %m0,r63\", operands);
+ return \"\";
+}"
+ [(set_attr "type" "other")])
+
+;; The following description models the
+;; SH4 pipeline using the DFA based scheduler.
+;; The DFA based description is better way to model
+;; a superscalar pipeline as compared to function unit
+;; reservation model.
+;; 1. The function unit based model is oriented to describe at most one
+;; unit reservation by each insn. It is difficult to model unit reservations in multiple
+;; pipeline units by same insn. This can be done using DFA based description.
+;; 2. The execution performance of DFA based scheduler does not depend on processor complexity.
+;; 3. Writing all unit reservations for an instruction class is more natural description
+;; of the pipeline and makes interface of the hazard recognizer simpler than the
+;; old function unit based model.
+;; 4. The DFA model is richer and is a part of greater overall framework of RCSP.
+
+
+;; Two automata are defined to reduce number of states
+;; which a single large automaton will have.(Factoring)
+
+(define_automaton "inst_pipeline,fpu_pipe")
+
+;; This unit is basically the decode unit of the processor.
+;; Since SH4 is a dual issue machine,it is as if there are two
+;; units so that any insn can be processed by either one
+;; of the decoding unit.
+
+(define_cpu_unit "pipe_01,pipe_02" "inst_pipeline")
+
+
+;; The fixed point arithmetic calculator(?? EX Unit).
+
+(define_cpu_unit "int" "inst_pipeline")
+
+;; f1_1 and f1_2 are floating point units.Actually there is
+;; a f1 unit which can overlap with other f1 unit but
+;; not another F1 unit.It is as though there were two
+;; f1 units.
+
+(define_cpu_unit "f1_1,f1_2" "fpu_pipe")
+
+;; The floating point units (except FS - F2 always precedes it.)
+
+(define_cpu_unit "F0,F1,F2,F3" "fpu_pipe")
+
+;; This is basically the MA unit of SH4
+;; used in LOAD/STORE pipeline.
+
+(define_cpu_unit "memory" "inst_pipeline")
+
+;; However, there are LS group insns that don't use it, even ones that
+;; complete in 0 cycles. So we use an extra unit for the issue of LS insns.
+(define_cpu_unit "load_store" "inst_pipeline")
+
+;; The address calculator used for branch instructions.
+;; This will be reserved after "issue" of branch instructions
+;; and this is to make sure that no two branch instructions
+;; can be issued in parallel.
+
+(define_cpu_unit "pcr_addrcalc" "inst_pipeline")
+
+;; ----------------------------------------------------
+;; This reservation is to simplify the dual issue description.
+
+(define_reservation "issue" "pipe_01|pipe_02")
+
+;; This is to express the locking of D stage.
+;; Note that the issue of a CO group insn also effectively locks the D stage.
+
+(define_reservation "d_lock" "pipe_01+pipe_02")
+
+;; Every FE instruction but fipr / ftrv starts with issue and this.
+(define_reservation "F01" "F0+F1")
+
+;; This is to simplify description where F1,F2,FS
+;; are used simultaneously.
+
+(define_reservation "fpu" "F1+F2")
+
+;; This is to highlight the fact that f1
+;; cannot overlap with F1.
+
+(exclusion_set "f1_1,f1_2" "F1")
+
+(define_insn_reservation "nil" 0 (eq_attr "type" "nil") "nothing")
+
+;; Although reg moves have a latency of zero
+;; we need to highlight that they use D stage
+;; for one cycle.
+
+;; Group: MT
+
+(define_insn_reservation "reg_mov" 0
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "move"))
+ "issue")
+
+;; Group: LS
+
+(define_insn_reservation "freg_mov" 0
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "fmove"))
+ "issue+load_store")
+
+;; We don't model all pipeline stages; we model the issue ('D') stage
+;; inasmuch as we allow only two instructions to issue simultaneously,
+;; and CO instructions prevent any simultaneous issue of another instruction.
+;; (This uses pipe_01 and pipe_02).
+;; Double issue of EX insns is prevented by using the int unit in the EX stage.
+;; Double issue of EX / BR insns is prevented by using the int unit /
+;; pcr_addrcalc unit in the EX stage.
+;; Double issue of BR / LS instructions is prevented by using the
+;; pcr_addrcalc / load_store unit in the issue cycle.
+;; Double issue of FE instructions is prevented by using F0 in the first
+;; pipeline stage after the first D stage.
+;; There is no need to describe the [ES]X / [MN]A / S stages after a D stage
+;; (except in the cases outlined above), nor to describe the FS stage after
+;; the F2 stage.
+
+;; Other MT group instructions(1 step operations)
+;; Group: MT
+;; Latency: 1
+;; Issue Rate: 1
+
+(define_insn_reservation "mt" 1
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "mt_group"))
+ "issue")
+
+;; Fixed Point Arithmetic Instructions(1 step operations)
+;; Group: EX
+;; Latency: 1
+;; Issue Rate: 1
+
+(define_insn_reservation "sh4_simple_arith" 1
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "insn_class" "ex_group"))
+ "issue,int")
+
+;; Load and store instructions have no alignment peculiarities for the SH4,
+;; but they use the load-store unit, which they share with the fmove type
+;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
+;; Loads have a latency of two.
+;; However, call insns can only paired with a preceding insn, and have
+;; a delay slot, so that we want two more insns to be scheduled between the
+;; load of the function address and the call. This is equivalent to a
+;; latency of three.
+;; ADJUST_COST can only properly handle reductions of the cost, so we
+;; use a latency of three here, which gets multiplied by 10 to yield 30.
+;; We only do this for SImode loads of general registers, to make the work
+;; for ADJUST_COST easier.
;; Load Store instructions. (MOV.[BWL]@(d,GBR)
;; Group: LS
;; Latency: 2
;; Issue Rate: 1
-(define_insn_reservation "load_store" 2
- (eq_attr "type" "load,load_si,pcload,pcload_si,store")
- "issue,memory*2")
+(define_insn_reservation "sh4_load" 2
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "load,pcload"))
+ "issue+load_store,nothing,memory")
+
+;; calls / sfuncs need an extra instruction for their delay slot.
+;; Moreover, estimating the latency for SImode loads as 3 will also allow
+;; adjust_cost to meaningfully bump it back up to 3 if they load the shift
+;; count of a dynamic shift.
+(define_insn_reservation "sh4_load_si" 3
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "load_si,pcload_si"))
+ "issue+load_store,nothing,memory")
+
+;; (define_bypass 2 "sh4_load_si" "!sh4_call")
+
+;; The load latency is upped to three higher if the dependent insn does
+;; double precision computation. We want the 'default' latency to reflect
+;; that increased latency because otherwise the insn priorities won't
+;; allow proper scheduling.
+(define_insn_reservation "sh4_fload" 3
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "fload,pcfload"))
+ "issue+load_store,nothing,memory")
+
+;; (define_bypass 2 "sh4_fload" "!")
+
+(define_insn_reservation "sh4_store" 1
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "store"))
+ "issue+load_store,nothing,memory")
+
+;; Load Store instructions.
+;; Group: LS
+;; Latency: 1
+;; Issue Rate: 1
+
+(define_insn_reservation "sh4_gp_fpul" 1
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "gp_fpul"))
+ "issue+load_store")
+
+;; Load Store instructions.
+;; Group: LS
+;; Latency: 3
+;; Issue Rate: 1
+
+(define_insn_reservation "sh4_fpul_gp" 3
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "fpul_gp"))
+ "issue+load_store")
;; Branch (BF,BF/S,BT,BT/S,BRA)
;; Group: BR
-;; Latency: 2 (or 1) Actually Observed to be 5/7
+;; Latency when taken: 2 (or 1)
;; Issue Rate: 1
;; The latency is 1 when displacement is 0.
-;; This reservation can be further broken into 2
-;; 1. branch_zero : One with latency 1 and in the TEST
-;; part it also checks for 0 (ZERO) displacement
-;; 2. branch: Latency 2.
-
-(define_insn_reservation "branch_zero" 5
- (and (eq_attr "type" "cbranch")
- (eq_attr "length" "2"))
- "(issue+pcr_addrcalc),pcr_addrcalc,nothing")
+;; We can't really do much with the latency, even if we could express it,
+;; but the pairing restrictions are useful to take into account.
+;; ??? If the branch is likely, we might want to fill the delay slot;
+;; if the branch is likely, but not very likely, should we pretend to use
+;; a resource that CO instructions use, to get a pairable delay slot insn?
-(define_insn_reservation "branch" 7
- (eq_attr "type" "cbranch")
- "(issue+pcr_addrcalc),pcr_addrcalc,nothing")
+(define_insn_reservation "sh4_branch" 1
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "cbranch,jump"))
+ "issue+pcr_addrcalc")
;; Branch Far (JMP,RTS,BRAF)
;; Group: CO
;; Latency: 3
;; Issue Rate: 2
-;; Since issue stage (D stage) is blocked for 2nd cycle,
-;; cpu_unit int is reserved since it might be required for far
-;; address calculation.
+;; ??? Scheduling happens before branch shortening, and hence jmp and braf
+;; can't be distinguished from bra for the "jump" pattern.
-(define_insn_reservation "branch_far" 12
- (and (eq_attr "type" "jump,return")
- (eq_attr "length" "6"))
- "d_lock*2,int+pcr_addrcalc,pcr_addrcalc")
+(define_insn_reservation "sh4_return" 3
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "return,jump_ind"))
+ "d_lock*2")
;; RTE
;; Group: CO
-;; atency: 5
+;; Latency: 5
;; Issue Rate: 5
-;; this instruction can be executed in any of the pipelines
+;; this instruction can be executed in any of the pipelines
;; and blocks the pipeline for next 4 stages.
-(define_insn_reservation "return_from_exp" 5
- (eq_attr "type" "rte")
- "(issue+pcr_addrcalc),d_lock*4,int+pcr_addrcalc,nothing")
+(define_insn_reservation "sh4_return_from_exp" 5
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "rte"))
+ "d_lock*5")
;; OCBP, OCBWB
;; Group: CO
-;; Latency: 5
+;; Latency: 1-5
;; Issue Rate: 1
-(define_insn_reservation "ocbwb" 5
- (eq_attr "insn_class" "cwb")
- "issue,(int+memory),memory*5")
-
+;; cwb is used for the sequence ocbwb @%0; extu.w %0,%2; or %1,%2; mov.l %0,@%2
+;; ocbwb on its own would be "d_lock,nothing,memory*5"
+(define_insn_reservation "ocbwb" 6
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "cwb"))
+ "d_lock*2,(d_lock+memory)*3,issue+load_store+memory,memory*2")
+
;; LDS to PR,JSR
;; Group: CO
;; Latency: 3
;; Issue Rate: 2
;; The SX stage is blocked for last 2 cycles.
+;; OTOH, the only time that has an effect for insns generated by the compiler
+;; is when lds to PR is followed by sts from PR - and that is highly unlikely -
+;; or when we are doing a function call - and we don't do inter-function
+;; scheduling. For the function call case, it's really best that we end with
+;; something that models an rts.
+
+(define_insn_reservation "sh4_lds_to_pr" 3
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "prset") )
+ "d_lock*2")
+
+;; calls introduce a longisch delay that is likely to flush the pipelines
+;; of the caller's instructions. Ordinary functions tend to end with a
+;; load to restore a register (in the delay slot of rts), while sfuncs
+;; tend to end with an EX or MT insn. But that is not actually relevant,
+;; since there are no instructions that contend for memory access early.
+;; We could, of course, provide exact scheduling information for specific
+;; sfuncs, if that should prove useful.
+
+(define_insn_reservation "sh4_call" 16
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "call,sfunc"))
+ "d_lock*16")
-(define_insn_reservation "lds_to_pr" 3
- (eq_attr "type" "prset,call,sfunc")
- "(issue+pcr_addrcalc),(issue+int+pcr_addrcalc),(int+pcr_addrcalc)*2")
-
-;; LDS.L to PR
+;; LDS.L to PR
;; Group: CO
;; Latency: 3
;; Issue Rate: 2
;; The SX unit is blocked for last 2 cycles.
-
+
(define_insn_reservation "ldsmem_to_pr" 3
- (eq_attr "type" "pload")
- "(issue+pcr_addrcalc),(issue+int+pcr_addrcalc),(int+memory+pcr_addrcalc),(int+pcr_addrcalc)")
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "pload"))
+ "d_lock*2")
;; STS from PR
;; Group: CO
;; The SX unit in second and third cycles.
(define_insn_reservation "sts_from_pr" 2
- (eq_attr "type" "prget")
- "(issue+pcr_addrcalc),(pipe_01+int+pcr_addrcalc),(int+pcr_addrcalc),nothing")
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "prget"))
+ "d_lock*2")
;; STS.L from PR
;; Group: CO
;; Latency: 2
;; Issue Rate: 2
-(define_insn_reservation "prload_mem" 2
- (eq_attr "type" "pstore")
- "(issue+pcr_addrcalc),(pipe_01+int+pcr_addrcalc),(int+memory+pcr_addrcalc),memory")
+(define_insn_reservation "sh4_prstore_mem" 2
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "pstore"))
+ "d_lock*2,nothing,memory")
;; LDS to FPSCR
;; Group: CO
;; Latency: 4
;; Issue Rate: 1
-;; F1 is blocked for last three cycles.
+;; F1 is blocked for last three cycles.
-(define_insn_reservation "fpscr_store" 4
- (eq_attr "insn_class" "lds_to_fpscr")
- "issue,int,F1*3")
+(define_insn_reservation "fpscr_load" 4
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "gp_fpscr"))
+ "d_lock,nothing,F1*3")
;; LDS.L to FPSCR
;; Group: CO
;; Issue Rate: 1
;; F1 is blocked for last three cycles.
-(define_insn_reservation "fpscr_store_mem" 4
- (eq_attr "insn_class" "ldsmem_to_fpscr")
- "issue,(int+memory),(F1+memory),F1*2")
+(define_insn_reservation "fpscr_load_mem" 4
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "mem_fpscr"))
+ "d_lock,nothing,(F1+memory),F1*2")
\f
;; Fixed point multiplication (DMULS.L DMULU.L MUL.L MULS.W,MULU.W)
;; Issue Rate: 1
(define_insn_reservation "multi" 4
- (eq_attr "type" "smpy,dmpy")
- "issue,(issue+int+f1_1),(int+f1_1),(f1_1|f1_2)*2,F2,FS")
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "smpy,dmpy"))
+ "d_lock,(d_lock+f1_1),(f1_1|f1_2)*3,F2")
+
+;; Fixed STS from MACL / MACH
+;; Group: CO
+;; Latency: 3
+;; Issue Rate: 1
+
+(define_insn_reservation "sh4_mac_gp" 3
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "mac_gp"))
+ "d_lock")
;; Single precision floating point computation FCMP/EQ,
-;; FCP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRVHG, FSCHG
+;; FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRVHG, FSCHG
;; Group: FE
-;; Latency: 4
+;; Latency: 3/4
;; Issue Rate: 1
-(define_insn_reservation "fp_arith" 4
- (eq_attr "type" "fp")
- "issue,F1,F2,FS")
+(define_insn_reservation "fp_arith" 3
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "fp"))
+ "issue,F01,F2")
+
+(define_insn_reservation "fp_arith_ftrc" 3
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "ftrc_s"))
+ "issue,F01,F2")
+
+(define_bypass 1 "fp_arith_ftrc" "sh4_fpul_gp")
;; Single Precision FDIV/SQRT
;; Group: FE
-;; Latency: 12/13
+;; Latency: 12/13 (FDIV); 11/12 (FSQRT)
;; Issue Rate: 1
+;; We describe fdiv here; fsqrt is actually one cycle faster.
-(define_insn_reservation "fp_div" 13
- (eq_attr "type" "fdiv")
- "issue,F1+F3,F1+F2+F3,F3*7,F1+F3,F2,FS")
+(define_insn_reservation "fp_div" 12
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "fdiv"))
+ "issue,F01+F3,F2+F3,F3*7,F1+F3,F2")
;; Double Precision floating point computation
;; (FCNVDS, FCNVSD, FLOAT, FTRC)
;; Latency: (3,4)/5
;; Issue Rate: 1
-(define_insn_reservation "dp_float" 5
- (eq_attr "type" "dfp_conv")
- "issue,F1,F1+F2,F2+FS,FS")
+(define_insn_reservation "dp_float" 4
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "dfp_conv"))
+ "issue,F01,F1+F2,F2")
-;; Double-precision floating-point (FADD ,FMUL,FSUB)
+;; Double-precision floating-point (FADD,FMUL,FSUB)
;; Group: FE
;; Latency: (7,8)/9
;; Issue Rate: 1
-(define_insn_reservation "fp_double_arith" 9
- (eq_attr "type" "dfp_arith")
- "issue,F1,F1+F2,fpu*4,F2+FS,FS")
+(define_insn_reservation "fp_double_arith" 8
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "dfp_arith"))
+ "issue,F01,F1+F2,fpu*4,F2")
-;; Double-precision FCMP (FCMP/EQ,FCMP/GT)
-;; Group: FE
+;; Double-precision FCMP (FCMP/EQ,FCMP/GT)
+;; Group: CO
;; Latency: 3/5
;; Issue Rate: 2
-(define_insn_reservation "fp_double_cmp" 5
- (eq_attr "type" "dfp_cmp")
- "issue,(issue+F1),F1+F2,F2+FS,FS")
+(define_insn_reservation "fp_double_cmp" 3
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "dfp_cmp"))
+ "d_lock,(d_lock+F01),F1+F2,F2")
;; Double precision FDIV/SQRT
;; Group: FE
;; Latency: (24,25)/26
;; Issue Rate: 1
-(define_insn_reservation "dp_div" 26
- (eq_attr "type" "dfdiv")
- "issue,F1+F3,F1+F2+F3,F2+F3+FS,F3*16,F1+F3,F1+F2+F3,fpu+F3,F2+FS,FS")
+(define_insn_reservation "dp_div" 25
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "dfdiv"))
+ "issue,F01+F3,F1+F2+F3,F2+F3,F3*16,F1+F3,(fpu+F3)*2,F2")
+
+;; Use the branch-not-taken case to model arith3 insns. For the branch taken
+;; case, we'd get a d_lock instead of issue at the end.
+(define_insn_reservation "arith3" 3
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "arith3"))
+ "issue,d_lock+pcr_addrcalc,issue")
+
+;; arith3b insns schedule the same no matter if the branch is taken or not.
+(define_insn_reservation "arith3b" 2
+ (and (eq_attr "pipe_model" "sh4")
+ (eq_attr "type" "arith3"))
+ "issue,d_lock+pcr_addrcalc")
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