;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
+;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;; GCC is distributed in the hope that it will be useful,
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
-;; Boston, MA 02110-1301, USA.
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
;; ??? Should prepend a * to all pattern names which are not used.
(match_operand:SI 1 "arith_reg_or_0_operand" "rN")))]
"TARGET_SH1"
"cmp/hs %1,%0"
- "&& operands[0] == CONST0_RTX (SImode)"
+ "&& operands[1] == CONST0_RTX (SImode)"
[(pc)]
"
{
{
rtx tmp;
- if (no_new_pseudos)
+ if (!can_create_pseudo_p ())
FAIL;
tmp = gen_reg_rtx (DImode);
(match_operand:SI 3 "register_operand" "0"))
(match_operand:SI 4 "arith_reg_or_0_operand" "r")))
(clobber (match_scratch:SI 5 "=&r"))]
- "TARGET_SHMEDIA && no_new_pseudos"
+ "TARGET_SHMEDIA && !can_create_pseudo_p ()"
"#"
"TARGET_SHMEDIA && reload_completed"
[(pc)]
{
rtx tmp;
- if (no_new_pseudos)
+ if (!can_create_pseudo_p ())
FAIL;
tmp = gen_reg_rtx (SImode);
{
if (TARGET_SH1)
{
- if (no_new_pseudos && ! arith_reg_operand (operands[2], DImode))
+ if (!can_create_pseudo_p () && ! arith_reg_operand (operands[2], DImode))
FAIL;
operands[2] = force_reg (DImode, operands[2]);
emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2]));
}
if (TARGET_SHMEDIA)
{
- if (no_new_pseudos && ! arith_reg_or_0_operand (operands[1], SImode))
+ if (!can_create_pseudo_p ()
+ && ! arith_reg_or_0_operand (operands[1], SImode))
FAIL;
if (operands[1] != const0_rtx && GET_CODE (operands[1]) != SUBREG)
operands[1] = force_reg (SImode, operands[1]);
(clobber (reg:DI TR0_REG))
(clobber (reg:DI TR1_REG))
(clobber (reg:DI TR2_REG))
- (use (match_operand 1 "target_operand" "b"))]
+ (use (match_operand 1 "target_reg_operand" "b"))]
"TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
"blink %1, r18"
[(set_attr "type" "sfunc")
""
"
{
- rtx first, last;
+ rtx last;
operands[3] = gen_reg_rtx (Pmode);
/* Emit the move of the address to a pseudo outside of the libcall. */
function_symbol (operands[3], \"__udivsi3\", SFUNC_STATIC);
last = gen_udivsi3_i1 (operands[0], operands[3]);
}
- first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
+ emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
- last = emit_insn (last);
- /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
- invariant code motion can move it. */
- REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
- REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
+ emit_insn (last);
DONE;
}")
(clobber (reg:SI R20_REG))
(clobber (reg:SI R21_REG))
(clobber (reg:SI TR0_REG))
- (use (match_operand 1 "target_operand" "b"))]
+ (use (match_operand 1 "target_reg_operand" "b"))]
"TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
"blink %1, r18"
[(set_attr "type" "sfunc")])
(clobber (reg:SI R21_REG))
(clobber (reg:SI TR0_REG))
(use (reg:SI R20_REG))
- (use (match_operand 1 "target_operand" "b"))]
+ (use (match_operand 1 "target_reg_operand" "b"))]
"TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
"blink %1, r18"
[(set_attr "type" "sfunc")])
""
"
{
- rtx first, last;
+ rtx last;
operands[3] = gen_reg_rtx (Pmode);
/* Emit the move of the address to a pseudo outside of the libcall. */
function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
last = gen_divsi3_i1 (operands[0], operands[3]);
}
- first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
+ emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
- last = emit_insn (last);
- /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
- invariant code motion can move it. */
- REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
- REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
+ emit_insn (last);
DONE;
}")
(clobber (match_operand:DI 8 "register_operand" "=r"))]
"TARGET_SHMEDIA"
"#"
- "&& no_new_pseudos"
+ "&& !can_create_pseudo_p ()"
[(pc)]
"
{
(clobber (match_operand:DI 4 "register_operand" "=r"))]
"TARGET_SHMEDIA"
"#"
- "&& no_new_pseudos"
+ "&& !can_create_pseudo_p ()"
[(pc)]
"
{
(clobber (match_operand:DI 13 "register_operand" "=r"))]
"TARGET_SHMEDIA"
"#"
- "&& no_new_pseudos"
+ "&& !can_create_pseudo_p ()"
[(pc)]
"
{
rtx scratch1 = operands[8];
rtx scratch2 = operands[9];
+ if (satisfies_constraint_N (dividend))
+ {
+ emit_move_insn (result, dividend);
+ DONE;
+ }
+
emit_insn (gen_mulsidi3_media (scratch0, inv1, dividend));
emit_insn (gen_mulsidi3_media (scratch1, inv2, dividend));
emit_insn (gen_ashrdi3_media (scratch2, scratch0, GEN_INT (63)));
&& (TARGET_DIVIDE_INV_MINLAT
|| TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)"
"#"
- "&& no_new_pseudos"
+ "&& !can_create_pseudo_p ()"
[(pc)]
"
{
(clobber (match_operand:DF 9 "fp_arith_reg_operand" ""))
(clobber (match_operand:DF 10 "fp_arith_reg_operand" ""))
(clobber (match_operand:DF 11 "fp_arith_reg_operand" ""))]
- "TARGET_SHMEDIA_FPU && TARGET_DIVIDE_INV_FP && no_new_pseudos"
+ "TARGET_SHMEDIA_FPU && TARGET_DIVIDE_INV_FP && !can_create_pseudo_p ()"
"#"
"&& 1"
[(set (match_dup 9) (float:DF (match_dup 1)))
"TARGET_SH1"
"
{
- rtx first, last;
+ rtx insn, macl;
- first = emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
- last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
- /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
- invariant code motion can move it. */
- REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
- REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
+ macl = gen_rtx_REG (SImode, MACL_REG);
+ start_sequence ();
+ emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
+ insn = get_insns ();
+ end_sequence ();
/* expand_binop can't find a suitable code in umul_widen_optab to
make a REG_EQUAL note from, so make one here.
See also smulsi3_highpart.
??? Alternatively, we could put this at the calling site of expand_binop,
i.e. expand_expr. */
- set_unique_reg_note (last, REG_EQUAL,
- copy_rtx (SET_SRC (single_set (first))));
+ /* Use emit_libcall_block for loop invariant code motion and to make
+ a REG_EQUAL note. */
+ emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));
DONE;
}")
"TARGET_SH1"
"
{
- rtx first, last;
+ rtx insn, macl;
- first = emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
- last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
- /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
- invariant code motion can move it. */
- REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
- REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
+ macl = gen_rtx_REG (SImode, MACL_REG);
+ start_sequence ();
+ emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
+ insn = get_insns ();
+ end_sequence ();
/* expand_binop can't find a suitable code in umul_widen_optab to
make a REG_EQUAL note from, so make one here.
See also smulsi3_highpart.
??? Alternatively, we could put this at the calling site of expand_binop,
i.e. expand_expr. */
- set_unique_reg_note (last, REG_EQUAL,
- copy_rtx (SET_SRC (single_set (first))));
+ /* Use emit_libcall_block for loop invariant code motion and to make
+ a REG_EQUAL note. */
+ emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));
DONE;
}")
"TARGET_SH1"
"
{
- rtx first, last;
-
if (!TARGET_SH2)
{
/* The address must be set outside the libcall,
rtx addr = force_reg (SImode, sym);
rtx insns = gen_mulsi3_call (operands[0], operands[1],
operands[2], addr);
- first = insns;
- last = emit_insn (insns);
+ emit_insn (insns);
}
else
{
rtx macl = gen_rtx_REG (SImode, MACL_REG);
- first = emit_insn (gen_mul_l (operands[1], operands[2]));
+ emit_insn (gen_mul_l (operands[1], operands[2]));
/* consec_sets_giv can only recognize the first insn that sets a
giv as the giv insn. So we must tag this also with a REG_EQUAL
note. */
- last = emit_insn (gen_movsi_i ((operands[0]), macl));
+ emit_insn (gen_movsi_i ((operands[0]), macl));
}
- /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
- invariant code motion can move it. */
- REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
- REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
DONE;
}")
"TARGET_SH2"
"
{
- rtx first, last;
+ rtx insn, mach;
- first = emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
- last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
- /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
- invariant code motion can move it. */
- REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
- REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
+ mach = gen_rtx_REG (SImode, MACH_REG);
+ start_sequence ();
+ emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
+ insn = get_insns ();
+ end_sequence ();
/* expand_binop can't find a suitable code in mul_highpart_optab to
make a REG_EQUAL note from, so make one here.
See also {,u}mulhisi.
??? Alternatively, we could put this at the calling site of expand_binop,
i.e. expand_mult_highpart. */
- set_unique_reg_note (last, REG_EQUAL,
- copy_rtx (SET_SRC (single_set (first))));
+ /* Use emit_libcall_block for loop invariant code motion and to make
+ a REG_EQUAL note. */
+ emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));
DONE;
}")
"TARGET_SH2"
"
{
- rtx first, last;
+ rtx insn, mach;
+
+ mach = gen_rtx_REG (SImode, MACH_REG);
+ start_sequence ();
+ emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
+ insn = get_insns ();
+ end_sequence ();
+ /* Use emit_libcall_block for loop invariant code motion and to make
+ a REG_EQUAL note. */
+ emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));
- first = emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
- last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
- /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
- invariant code motion can move it. */
- REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
- REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
DONE;
}")
andi %1, %2, %0"
[(set_attr "type" "arith_media")])
+(define_insn "*andsi3_bclr"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=r")
+ (and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
+ (match_operand:SI 2 "const_int_operand" "Psz")))]
+ "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
+ "bclr\\t%W2,%0"
+ [(set_attr "type" "arith")])
+
;; If the constant is 255, then emit an extu.b instruction instead of an
;; and, since that will give better code.
[(set (match_operand:SI 0 "arith_reg_dest" "=r,z")
(ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
(match_operand:SI 2 "logical_operand" "r,K08")))]
- "TARGET_SH1"
+ "TARGET_SH1
+ && !(TARGET_SH2A && satisfies_constraint_Pso (operands[2]))"
"or %2,%0"
[(set_attr "type" "arith")])
ori %1, %2, %0"
[(set_attr "type" "arith_media")])
+(define_insn "*iorsi3_bset"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=r")
+ (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
+ (match_operand:SI 2 "const_int_operand" "Pso")))]
+ "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
+ "bset\\t%V2,%0"
+ [(set_attr "type" "arith")])
+
(define_insn "iordi3"
[(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
(ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
xori %1, %2, %0"
[(set_attr "type" "arith_media")])
+;; Store the complements of the T bit in a register.
+(define_insn "xorsi3_movrt"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=r")
+ (xor:SI (reg:SI T_REG)
+ (const_int 1)))]
+ "TARGET_SH2A"
+ "movrt\\t%0"
+ [(set_attr "type" "arith")])
+
(define_insn "xordi3"
[(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
(xor:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
"@
exts.b %1,%0
mov.b %1,%0"
- [(set_attr "type" "arith,load")])
+ [(set_attr "type" "arith,load")
+ (set_attr_alternative "length"
+ [(const_int 2)
+ (if_then_else
+ (ne (symbol_ref "TARGET_SH2A") (const_int 0))
+ (const_int 4) (const_int 2))])])
(define_insn "*extendqisi2_media"
[(set (match_operand:SI 0 "register_operand" "=r,r")
"@
exts.b %1,%0
mov.b %1,%0"
- [(set_attr "type" "arith,load")])
+ [(set_attr "type" "arith,load")
+ (set_attr_alternative "length"
+ [(const_int 2)
+ (if_then_else
+ (ne (symbol_ref "TARGET_SH2A") (const_int 0))
+ (const_int 4) (const_int 2))])])
/* It would seem useful to combine the truncXi patterns into the movXi
patterns, but unary operators are ignored when matching constraints,
;; TARGET_FMOVD is in effect, and mode switching is done before reload.
(define_insn "movsi_ie"
[(set (match_operand:SI 0 "general_movdst_operand"
- "=r,r,r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
+ "=r,r,r,r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
(match_operand:SI 1 "general_movsrc_operand"
- "Q,r,I08,I20,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
+ "Q,r,I08,I20,I28,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
"(TARGET_SH2E || TARGET_SH2A)
&& (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
mov %1,%0
mov %1,%0
movi20 %1,%0
+ movi20s %1,%0
cmp/pl %1
mov.l %1,%0
sts %1,%0
flds %1,fpul
fmov %1,%0
! move optimized away"
- [(set_attr "type" "pcload_si,move,movi8,move,*,load_si,mac_gp,prget,arith,store,mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
- (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
+ [(set_attr "type" "pcload_si,move,movi8,move,move,*,load_si,mac_gp,prget,arith,store,mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
+ (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
(set_attr_alternative "length"
[(const_int 2)
(const_int 2)
(const_int 2)
(const_int 4)
+ (const_int 4)
(const_int 2)
(if_then_else
(ne (symbol_ref "TARGET_SH2A") (const_int 0))
[(set (match_dup 0) (match_dup 1))]
"
{
- if (TARGET_SHCOMPACT && current_function_has_nonlocal_label)
+ if (TARGET_SHCOMPACT && current_function_saves_all_registers)
operands[1] = gen_frame_mem (SImode, return_address_pointer_rtx);
}")
movt %0
sts %1,%0
lds %1,%0"
- [(set_attr "type" "move,movi8,load,store,arith,prget,prset")])
+ [(set_attr "type" "move,movi8,load,store,arith,prget,prset")
+ (set_attr_alternative "length"
+ [(const_int 2)
+ (const_int 2)
+ (if_then_else
+ (ne (symbol_ref "TARGET_SH2A") (const_int 0))
+ (const_int 4) (const_int 2))
+ (if_then_else
+ (ne (symbol_ref "TARGET_SH2A") (const_int 0))
+ (const_int 4) (const_int 2))
+ (const_int 2)
+ (const_int 2)
+ (const_int 2)])])
(define_insn "*movqi_media"
[(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")
(define_insn "jump_compact"
[(set (pc)
(label_ref (match_operand 0 "" "")))]
- "TARGET_SH1"
+ "TARGET_SH1 && !find_reg_note (insn, REG_CROSSING_JUMP, NULL_RTX)"
"*
{
/* The length is 16 if the delay slot is unfilled. */
(use (reg:PSI FPSCR_REG))
(clobber (reg:SI PR_REG))]
"TARGET_SH1"
- "jsr @%0%#"
+ "*
+ {
+ if (TARGET_SH2A && (dbr_sequence_length () == 0))
+ return \"jsr/n\\t@%0\";
+ else
+ return \"jsr\\t@%0%#\";
+ }"
+
[(set_attr "type" "call")
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
(set_attr "needs_delay_slot" "yes")
(set_attr "fp_set" "unknown")])
+;; This is TBR relative jump instruction for SH2A architecture.
+;; Its use is enabled assigning an attribute "function_vector"
+;; and the vector number to a function during its declaration.
+
+(define_insn "calli_tbr_rel"
+ [(call (mem (match_operand:SI 0 "symbol_ref_operand" ""))
+ (match_operand 1 "" ""))
+ (use (reg:PSI FPSCR_REG))
+ (clobber (reg:SI PR_REG))]
+ "TARGET_SH2A && sh2a_is_function_vector_call (operands[0])"
+ "*
+{
+ unsigned HOST_WIDE_INT vect_num;
+ vect_num = sh2a_get_function_vector_number (operands[0]);
+ operands[2] = GEN_INT (vect_num * 4);
+
+ return \"jsr/n\\t@@(%O2,tbr)\";
+}"
+ [(set_attr "type" "call")
+ (set (attr "fp_mode")
+ (if_then_else (eq_attr "fpu_single" "yes")
+ (const_string "single") (const_string "double")))
+ (set_attr "needs_delay_slot" "no")
+ (set_attr "fp_set" "unknown")])
+
;; This is a pc-rel call, using bsrf, for use with PIC.
(define_insn "calli_pcrel"
(use (reg:PSI FPSCR_REG))
(clobber (reg:SI PR_REG))]
"TARGET_SH1"
- "jsr @%1%#"
+ "*
+ {
+ if (TARGET_SH2A && (dbr_sequence_length () == 0))
+ return \"jsr/n\\t@%1\";
+ else
+ return \"jsr\\t@%1%#\";
+ }"
[(set_attr "type" "call")
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
(set_attr "needs_delay_slot" "yes")
(set_attr "fp_set" "unknown")])
+;; This is TBR relative jump instruction for SH2A architecture.
+;; Its use is enabled assigning an attribute "function_vector"
+;; and the vector number to a function during its declaration.
+
+(define_insn "call_valuei_tbr_rel"
+ [(set (match_operand 0 "" "=rf")
+ (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
+ (match_operand 2 "" "")))
+ (use (reg:PSI FPSCR_REG))
+ (clobber (reg:SI PR_REG))]
+ "TARGET_SH2A && sh2a_is_function_vector_call (operands[1])"
+ "*
+{
+ unsigned HOST_WIDE_INT vect_num;
+ vect_num = sh2a_get_function_vector_number (operands[1]);
+ operands[3] = GEN_INT (vect_num * 4);
+
+ return \"jsr/n\\t@@(%O3,tbr)\";
+}"
+ [(set_attr "type" "call")
+ (set (attr "fp_mode")
+ (if_then_else (eq_attr "fpu_single" "yes")
+ (const_string "single") (const_string "double")))
+ (set_attr "needs_delay_slot" "no")
+ (set_attr "fp_set" "unknown")])
+
(define_insn "call_valuei_pcrel"
[(set (match_operand 0 "" "=rf")
(call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[0], 0)));
XEXP (operands[0], 0) = reg;
}
+ if (!flag_pic && TARGET_SH2A
+ && GET_CODE (operands[0]) == MEM
+ && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
+ {
+ if (sh2a_is_function_vector_call (XEXP (operands[0], 0)))
+ {
+ emit_call_insn (gen_calli_tbr_rel (XEXP (operands[0], 0),
+ operands[1]));
+ DONE;
+ }
+ }
if (flag_pic && TARGET_SH2
&& GET_CODE (operands[0]) == MEM
&& GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[1], 0)));
XEXP (operands[1], 0) = reg;
}
+ if (!flag_pic && TARGET_SH2A
+ && GET_CODE (operands[1]) == MEM
+ && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
+ {
+ if (sh2a_is_function_vector_call (XEXP (operands[1], 0)))
+ {
+ emit_call_insn (gen_call_valuei_tbr_rel (operands[0],
+ XEXP (operands[1], 0), operands[2]));
+ DONE;
+ }
+ }
if (flag_pic && TARGET_SH2
&& GET_CODE (operands[1]) == MEM
&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
{
rtx insn, mem;
- operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
- operands[3] = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
+ operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
+ operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
if (TARGET_SHMEDIA)
{
"
{
rtx gotoffsym, insn;
- rtx t = no_new_pseudos ? operands[0] : gen_reg_rtx (GET_MODE (operands[0]));
+ rtx t = (!can_create_pseudo_p ()
+ ? operands[0]
+ : gen_reg_rtx (GET_MODE (operands[0])));
gotoffsym = gen_sym2GOTOFF (operands[1]);
PUT_MODE (gotoffsym, Pmode);
"
{
rtx dtpoffsym, insn;
- rtx t = no_new_pseudos ? operands[0] : gen_reg_rtx (GET_MODE (operands[0]));
+ rtx t = (!can_create_pseudo_p ()
+ ? operands[0]
+ : gen_reg_rtx (GET_MODE (operands[0])));
dtpoffsym = gen_sym2DTPOFF (operands[1]);
PUT_MODE (dtpoffsym, Pmode);
}")
(define_insn "load_gbr"
- [(set (match_operand:SI 0 "register_operand" "") (reg:SI GBR_REG))
+ [(set (match_operand:SI 0 "register_operand" "=r") (reg:SI GBR_REG))
(use (reg:SI GBR_REG))]
""
"stc gbr,%0"
&& reload_completed
&& lookup_attribute (\"trap_exit\",
DECL_ATTRIBUTES (current_function_decl)) == NULL_TREE"
- "%@ %#"
+ "*
+ {
+ if (TARGET_SH2A && (dbr_sequence_length () == 0)
+ && !current_function_interrupt)
+ return \"rts/n\";
+ else
+ return \"%@ %#\";
+ }"
[(set_attr "type" "return")
(set_attr "needs_delay_slot" "yes")])
"movt %0"
[(set_attr "type" "arith")])
+;; complements the T bit and stores the result in a register
+(define_insn "movrt"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=r")
+ (if_then_else (eq:SI (reg:SI T_REG) (const_int 0))
+ (const_int 1)
+ (const_int 0)))]
+ "TARGET_SH2A"
+ "movrt\\t%0"
+ [(set_attr "type" "arith")])
+
(define_expand "seq"
[(set (match_operand:SI 0 "arith_reg_dest" "")
(match_dup 1))]
reg = operands[0];
if (GET_MODE (operands[0]) != SImode)
- reg = no_new_pseudos ? gen_rtx_SUBREG (SImode, operands[0], 0)
- : gen_reg_rtx (SImode);
+ reg = (!can_create_pseudo_p ()
+ ? gen_rtx_SUBREG (SImode, operands[0], 0)
+ : gen_reg_rtx (SImode));
switch (GET_MODE (sh_compare_op0))
{
reg = operands[0];
if (GET_MODE (operands[0]) != SImode)
- reg = no_new_pseudos ? gen_rtx_SUBREG (SImode, operands[0], 0)
- : gen_reg_rtx (SImode);
+ reg = (!can_create_pseudo_p ()
+ ? gen_rtx_SUBREG (SImode, operands[0], 0)
+ : gen_reg_rtx (SImode));
switch (GET_MODE (sh_compare_op0))
{
reg = operands[0];
if (GET_MODE (operands[0]) != SImode)
- reg = no_new_pseudos ? gen_rtx_SUBREG (SImode, operands[0], 0)
- : gen_reg_rtx (SImode);
+ reg = (!can_create_pseudo_p ()
+ ? gen_rtx_SUBREG (SImode, operands[0], 0)
+ : gen_reg_rtx (SImode));
switch (GET_MODE (sh_compare_op0))
{
case SImode:
{
- tmp = no_new_pseudos ? reg : gen_reg_rtx (SImode);
+ tmp = !can_create_pseudo_p () ? reg : gen_reg_rtx (SImode);
emit_insn (gen_cmpgtsi_media (tmp,
sh_compare_op0, sh_compare_op1));
case DImode:
{
- tmp = no_new_pseudos ? reg : gen_reg_rtx (SImode);
+ tmp = !can_create_pseudo_p () ? reg : gen_reg_rtx (SImode);
emit_insn (gen_cmpgtdi_media (tmp,
sh_compare_op0, sh_compare_op1));
reg = operands[0];
if (GET_MODE (operands[0]) != SImode)
- reg = no_new_pseudos ? gen_rtx_SUBREG (SImode, operands[0], 0)
- : gen_reg_rtx (SImode);
+ reg = (!can_create_pseudo_p () ?
+ gen_rtx_SUBREG (SImode, operands[0], 0)
+ : gen_reg_rtx (SImode));
sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
if (sh_compare_op1 != const0_rtx)
sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
mode = GET_MODE (sh_compare_op1);
reg = operands[0];
if (GET_MODE (operands[0]) != SImode)
- reg = no_new_pseudos ? gen_rtx_SUBREG (SImode, operands[0], 0)
- : gen_reg_rtx (SImode);
+ reg = (!can_create_pseudo_p ()
+ ? gen_rtx_SUBREG (SImode, operands[0], 0)
+ : gen_reg_rtx (SImode));
sh_compare_op0 = force_reg (mode, sh_compare_op0);
if (sh_compare_op1 != const0_rtx)
sh_compare_op1 = force_reg (mode, sh_compare_op1);
{
case SImode:
{
- rtx tmp = no_new_pseudos ? reg : gen_reg_rtx (SImode);
+ rtx tmp = !can_create_pseudo_p () ? reg : gen_reg_rtx (SImode);
emit_insn (gen_cmpgtsi_media (tmp,
sh_compare_op1, sh_compare_op0));
case DImode:
{
- rtx tmp = no_new_pseudos ? reg : gen_reg_rtx (SImode);
+ rtx tmp = !can_create_pseudo_p () ? reg : gen_reg_rtx (SImode);
emit_insn (gen_cmpgtdi_media (tmp,
sh_compare_op1, sh_compare_op0));
reg = operands[0];
if (GET_MODE (operands[0]) == DImode)
- reg = no_new_pseudos ? gen_rtx_SUBREG (SImode, operands[0], 0)
- : gen_reg_rtx (SImode);
+ reg = (!can_create_pseudo_p ()
+ ? gen_rtx_SUBREG (SImode, operands[0], 0)
+ : gen_reg_rtx (SImode));
sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
if (sh_compare_op1 != const0_rtx)
sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
reg = operands[0];
if (GET_MODE (operands[0]) == DImode)
- reg = no_new_pseudos ? gen_rtx_SUBREG (SImode, operands[0], 0)
- : gen_reg_rtx (SImode);
+ reg = (!can_create_pseudo_p ()
+ ? gen_rtx_SUBREG (SImode, operands[0], 0)
+ : gen_reg_rtx (SImode));
sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
if (sh_compare_op1 != const0_rtx)
sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
reg = operands[0];
if (GET_MODE (operands[0]) != SImode)
- reg = no_new_pseudos ? gen_rtx_SUBREG (SImode, operands[0], 0)
- : gen_reg_rtx (SImode);
+ reg = (!can_create_pseudo_p ()
+ ? gen_rtx_SUBREG (SImode, operands[0], 0)
+ : gen_reg_rtx (SImode));
sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
if (sh_compare_op1 != const0_rtx)
sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
: GET_MODE (sh_compare_op1),
sh_compare_op1);
- tmp = no_new_pseudos ? reg : gen_reg_rtx (SImode);
+ tmp = !can_create_pseudo_p () ? reg : gen_reg_rtx (SImode);
emit_insn (gen_cmpgtudi_media (tmp, sh_compare_op0, sh_compare_op1));
emit_insn (gen_cmpeqdi_media (reg, tmp, const0_rtx));
reg = operands[0];
if (GET_MODE (operands[0]) != SImode)
- reg = no_new_pseudos ? gen_rtx_SUBREG (SImode, operands[0], 0)
- : gen_reg_rtx (SImode);
+ reg = (!can_create_pseudo_p ()
+ ? gen_rtx_SUBREG (SImode, operands[0], 0)
+ : gen_reg_rtx (SImode));
sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
if (sh_compare_op1 != const0_rtx)
sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
: GET_MODE (sh_compare_op1),
sh_compare_op1);
- tmp = no_new_pseudos ? operands[0] : gen_reg_rtx (SImode);
+ tmp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (SImode);
emit_insn (gen_cmpgtudi_media (tmp, sh_compare_op1, sh_compare_op0));
emit_insn (gen_cmpeqdi_media (reg, tmp, const0_rtx));
reg = operands[0];
if (GET_MODE (operands[0]) != SImode)
- reg = no_new_pseudos ? gen_rtx_SUBREG (SImode, operands[0], 0)
- : gen_reg_rtx (SImode);
+ reg = (!can_create_pseudo_p ()
+ ? gen_rtx_SUBREG (SImode, operands[0], 0)
+ : gen_reg_rtx (SImode));
if (! TARGET_SHMEDIA_FPU
&& GET_MODE (sh_compare_op0) != DImode
&& GET_MODE (sh_compare_op0) != SImode)
: GET_MODE (sh_compare_op1),
sh_compare_op1);
- tmp = no_new_pseudos ? reg : gen_reg_rtx (SImode);
+ tmp = !can_create_pseudo_p () ? reg : gen_reg_rtx (SImode);
emit_insn (gen_seq (tmp));
emit_insn (gen_cmpeqdi_media (reg, tmp, const0_rtx));
}"
[(set_attr "type" "fparith_media")])
-(define_insn_and_split "binary_sf_op"
+(define_insn_and_split "binary_sf_op0"
[(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
- (vec_select:V2SF
- (vec_concat:V2SF
+ (vec_concat:V2SF
+ (match_operator:SF 3 "binary_float_operator"
+ [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
+ (parallel [(const_int 0)]))
+ (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
+ (parallel [(const_int 0)]))])
(vec_select:SF
(match_dup 0)
- (parallel [(match_operand 7 "const_int_operand" "n")]))
+ (parallel [(const_int 1)]))))]
+ "TARGET_SHMEDIA_FPU"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 4) (match_dup 5))]
+ "
+{
+ int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
+ rtx op1 = gen_rtx_REG (SFmode,
+ true_regnum (operands[1]) + endian);
+ rtx op2 = gen_rtx_REG (SFmode,
+ true_regnum (operands[2]) + endian);
+
+ operands[4] = gen_rtx_REG (SFmode,
+ true_regnum (operands[0]) + endian);
+ operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
+}"
+ [(set_attr "type" "fparith_media")])
+
+(define_insn_and_split "binary_sf_op1"
+ [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
+ (vec_concat:V2SF
+ (vec_select:SF
+ (match_dup 0)
+ (parallel [(const_int 0)]))
(match_operator:SF 3 "binary_float_operator"
[(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
- (parallel [(match_operand 5
- "const_int_operand" "n")]))
+ (parallel [(const_int 1)]))
(vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
- (parallel [(match_operand 6
- "const_int_operand" "n")]))]))
- (parallel [(match_dup 7) (match_operand 4 "const_int_operand" "n")])))]
- "TARGET_SHMEDIA_FPU && INTVAL (operands[4]) != INTVAL (operands[7])"
+ (parallel [(const_int 1)]))])))]
+ "TARGET_SHMEDIA_FPU"
"#"
"&& reload_completed"
- [(set (match_dup 8) (match_dup 9))]
+ [(set (match_dup 4) (match_dup 5))]
"
{
int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
rtx op1 = gen_rtx_REG (SFmode,
- (true_regnum (operands[1])
- + (INTVAL (operands[5]) ^ endian)));
+ true_regnum (operands[1]) + (1 ^ endian));
rtx op2 = gen_rtx_REG (SFmode,
- (true_regnum (operands[2])
- + (INTVAL (operands[6]) ^ endian)));
+ true_regnum (operands[2]) + (1 ^ endian));
- operands[8] = gen_rtx_REG (SFmode,
- (true_regnum (operands[0])
- + (INTVAL (operands[4]) ^ endian)));
- operands[9] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
+ operands[4] = gen_rtx_REG (SFmode,
+ true_regnum (operands[0]) + (1 ^ endian));
+ operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
}"
[(set_attr "type" "fparith_media")])
HOST_WIDE_INT bitsize, size, v = 0;
rtx x = operands[3];
+ if (TARGET_SH2A && TARGET_BITOPS
+ && (satisfies_constraint_Sbw (operands[0])
+ || satisfies_constraint_Sbv (operands[0]))
+ && satisfies_constraint_M (operands[1])
+ && satisfies_constraint_K03 (operands[2]))
+ {
+ if (satisfies_constraint_N (operands[3]))
+ {
+ emit_insn (gen_bclr_m2a (operands[0], operands[2]));
+ DONE;
+ }
+ else if (satisfies_constraint_M (operands[3]))
+ {
+ emit_insn (gen_bset_m2a (operands[0], operands[2]));
+ DONE;
+ }
+ else if ((REG_P (operands[3]) && REGNO (operands[3]) == T_REG)
+ && satisfies_constraint_M (operands[1]))
+ {
+ emit_insn (gen_bst_m2a (operands[0], operands[2]));
+ DONE;
+ }
+ else if (REG_P (operands[3])
+ && satisfies_constraint_M (operands[1]))
+ {
+ emit_insn (gen_bld_reg (operands[3], const0_rtx));
+ emit_insn (gen_bst_m2a (operands[0], operands[2]));
+ DONE;
+ }
+ }
/* ??? expmed doesn't care for non-register predicates. */
if (! memory_operand (operands[0], VOIDmode)
|| ! immediate_operand (operands[1], VOIDmode)
(sign_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
(match_operand 2 "const_int_operand" "")
(match_operand 3 "const_int_operand" "")))]
- "TARGET_SH4A_ARCH"
-{
+ "TARGET_SH4A_ARCH || TARGET_SH2A"
+{
+ if (TARGET_SH2A && TARGET_BITOPS
+ && (satisfies_constraint_Sbw (operands[1])
+ || satisfies_constraint_Sbv (operands[1]))
+ && satisfies_constraint_M (operands[2])
+ && satisfies_constraint_K03 (operands[3]))
+ {
+ emit_insn (gen_bldsign_m2a (operands[1], operands[3]));
+ if (REGNO (operands[0]) != T_REG)
+ emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
+ DONE;
+ }
if (TARGET_SH4A_ARCH
&& INTVAL (operands[2]) == 32
&& INTVAL (operands[3]) == -24 * (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
(zero_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
(match_operand 2 "const_int_operand" "")
(match_operand 3 "const_int_operand" "")))]
- "TARGET_SH4A_ARCH"
+ "TARGET_SH4A_ARCH || TARGET_SH2A"
{
+ if (TARGET_SH2A && TARGET_BITOPS
+ && (satisfies_constraint_Sbw (operands[1])
+ || satisfies_constraint_Sbv (operands[1]))
+ && satisfies_constraint_M (operands[2])
+ && satisfies_constraint_K03 (operands[3]))
+ {
+ emit_insn (gen_bld_m2a (operands[1], operands[3]));
+ if (REGNO (operands[0]) != T_REG)
+ emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
+ DONE;
+ }
if (TARGET_SH4A_ARCH
&& INTVAL (operands[2]) == 32
&& INTVAL (operands[3]) == -24 * (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
FAIL;
})
+;; SH2A instructions for bitwise operations.
+
+;; Clear a bit in a memory location.
+(define_insn "bclr_m2a"
+ [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
+ (and:QI
+ (not:QI (ashift:QI (const_int 1)
+ (match_operand:QI 1 "const_int_operand" "K03,K03")))
+ (match_dup 0)))]
+ "TARGET_SH2A && TARGET_BITOPS"
+ "@
+ bclr.b\\t%1,%0
+ bclr.b\\t%1,@(0,%t0)"
+[(set_attr "length" "4,4")])
+
+(define_insn "bclrmem_m2a"
+ [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
+ (and:QI (match_dup 0)
+ (match_operand:QI 1 "const_int_operand" "Psz,Psz")))]
+ "TARGET_SH2A && satisfies_constraint_Psz (operands[1]) && TARGET_BITOPS"
+ "@
+ bclr.b\\t%W1,%0
+ bclr.b\\t%W1,@(0,%t0)"
+ [(set_attr "length" "4,4")])
+
+;; Set a bit in a memory location.
+(define_insn "bset_m2a"
+ [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
+ (ior:QI
+ (ashift:QI (const_int 1)
+ (match_operand:QI 1 "const_int_operand" "K03,K03"))
+ (match_dup 0)))]
+ "TARGET_SH2A && TARGET_BITOPS"
+ "@
+ bset.b\\t%1,%0
+ bset.b\\t%1,@(0,%t0)"
+ [(set_attr "length" "4,4")])
+
+(define_insn "bsetmem_m2a"
+ [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
+ (ior:QI (match_dup 0)
+ (match_operand:QI 1 "const_int_operand" "Pso,Pso")))]
+ "TARGET_SH2A && satisfies_constraint_Pso (operands[1]) && TARGET_BITOPS"
+ "@
+ bset.b\\t%V1,%0
+ bset.b\\t%V1,@(0,%t0)"
+ [(set_attr "length" "4,4")])
+
+;;; Transfer the contents of the T bit to a specified bit of memory.
+(define_insn "bst_m2a"
+ [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,m")
+ (if_then_else (eq (reg:SI T_REG) (const_int 0))
+ (and:QI
+ (not:QI (ashift:QI (const_int 1)
+ (match_operand:QI 1 "const_int_operand" "K03,K03")))
+ (match_dup 0))
+ (ior:QI
+ (ashift:QI (const_int 1) (match_dup 1))
+ (match_dup 0))))]
+ "TARGET_SH2A && TARGET_BITOPS"
+ "@
+ bst.b\\t%1,%0
+ bst.b\\t%1,@(0,%t0)"
+ [(set_attr "length" "4")])
+
+;; Store a specified bit of memory in the T bit.
+(define_insn "bld_m2a"
+ [(set (reg:SI T_REG)
+ (zero_extract:SI
+ (match_operand:QI 0 "bitwise_memory_operand" "Sbw,Sbv")
+ (const_int 1)
+ (match_operand 1 "const_int_operand" "K03,K03")))]
+ "TARGET_SH2A && TARGET_BITOPS"
+ "@
+ bld.b\\t%1,%0
+ bld.b\\t%1,@(0,%t0)"
+ [(set_attr "length" "4,4")])
+
+;; Store a specified bit of memory in the T bit.
+(define_insn "bldsign_m2a"
+ [(set (reg:SI T_REG)
+ (sign_extract:SI
+ (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
+ (const_int 1)
+ (match_operand 1 "const_int_operand" "K03,K03")))]
+ "TARGET_SH2A && TARGET_BITOPS"
+ "@
+ bld.b\\t%1,%0
+ bld.b\\t%1,@(0,%t0)"
+ [(set_attr "length" "4,4")])
+
+;; Store a specified bit of the LSB 8 bits of a register in the T bit.
+(define_insn "bld_reg"
+ [(set (reg:SI T_REG)
+ (zero_extract:SI (match_operand:SI 0 "arith_reg_operand" "r")
+ (const_int 1)
+ (match_operand 1 "const_int_operand" "K03")))]
+ "TARGET_SH2A"
+ "bld\\t%1,%0")
+
+(define_insn "*bld_regqi"
+ [(set (reg:SI T_REG)
+ (zero_extract:SI (match_operand:QI 0 "arith_reg_operand" "r")
+ (const_int 1)
+ (match_operand 1 "const_int_operand" "K03")))]
+ "TARGET_SH2A"
+ "bld\\t%1,%0")
+
+;; Take logical and of a specified bit of memory with the T bit and
+;; store its result in the T bit.
+(define_insn "band_m2a"
+ [(set (reg:SI T_REG)
+ (and:SI (reg:SI T_REG)
+ (zero_extract:SI
+ (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
+ (const_int 1)
+ (match_operand 1 "const_int_operand" "K03,K03"))))]
+ "TARGET_SH2A && TARGET_BITOPS"
+ "@
+ band.b\\t%1,%0
+ band.b\\t%1,@(0,%t0)"
+ [(set_attr "length" "4,4")])
+
+(define_insn "bandreg_m2a"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (and:SI (zero_extract:SI
+ (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
+ (const_int 1)
+ (match_operand 2 "const_int_operand" "K03,K03"))
+ (match_operand:SI 3 "register_operand" "r,r")))]
+ "TARGET_SH2A && TARGET_BITOPS"
+ "@
+ band.b\\t%2,%1\;movt\\t%0
+ band.b\\t%2,@(0,%t1)\;movt\\t%0"
+ [(set_attr "length" "6,6")])
+
+;; Take logical or of a specified bit of memory with the T bit and
+;; store its result in the T bit.
+(define_insn "bor_m2a"
+ [(set (reg:SI T_REG)
+ (ior:SI (reg:SI T_REG)
+ (zero_extract:SI
+ (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
+ (const_int 1)
+ (match_operand 1 "const_int_operand" "K03,K03"))))]
+ "TARGET_SH2A && TARGET_BITOPS"
+ "@
+ bor.b\\t%1,%0
+ bor.b\\t%1,@(0,%t0)"
+ [(set_attr "length" "4,4")])
+
+(define_insn "borreg_m2a"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (ior:SI (zero_extract:SI
+ (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
+ (const_int 1)
+ (match_operand 2 "const_int_operand" "K03,K03"))
+ (match_operand:SI 3 "register_operand" "=r,r")))]
+ "TARGET_SH2A && TARGET_BITOPS"
+ "@
+ bor.b\\t%2,%1\;movt\\t%0
+ bor.b\\t%2,@(0,%t1)\;movt\\t%0"
+ [(set_attr "length" "6,6")])
+
+;; Take exclusive or of a specified bit of memory with the T bit and
+;; store its result in the T bit.
+(define_insn "bxor_m2a"
+ [(set (reg:SI T_REG)
+ (xor:SI (reg:SI T_REG)
+ (zero_extract:SI
+ (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
+ (const_int 1)
+ (match_operand 1 "const_int_operand" "K03,K03"))))]
+ "TARGET_SH2A && TARGET_BITOPS"
+ "@
+ bxor.b\\t%1,%0
+ bxor.b\\t%1,@(0,%t0)"
+ [(set_attr "length" "4,4")])
+
+(define_insn "bxorreg_m2a"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (xor:SI (zero_extract:SI
+ (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
+ (const_int 1)
+ (match_operand 2 "const_int_operand" "K03,K03"))
+ (match_operand:SI 3 "register_operand" "=r,r")))]
+ "TARGET_SH2A && TARGET_BITOPS"
+ "@
+ bxor.b\\t%2,%1\;movt\\t%0
+ bxor.b\\t%2,@(0,%t1)\;movt\\t%0"
+ [(set_attr "length" "6,6")])
+
\f
;; -------------------------------------------------------------------------
;; Peepholes
;; -------------------------------------------------------------------------
+;; This matches cases where the bit in a memory location is set.
+(define_peephole2
+ [(set (match_operand:SI 0 "arith_reg_operand" "r,r")
+ (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")))
+ (set (match_dup 0)
+ (ior:SI (match_dup 0)
+ (match_operand:SI 2 "const_int_operand" "Pso,Pso")))
+ (set (match_dup 1)
+ (match_operand 3 "arith_reg_operand" "r,r"))]
+ "TARGET_SH2A && TARGET_BITOPS
+ && satisfies_constraint_Pso (operands[2])
+ && REGNO (operands[0]) == REGNO (operands[3])"
+ [(set (match_dup 1)
+ (ior:QI (match_dup 1)
+ (match_dup 2)))]
+ "")
+
+;; This matches cases where the bit in a memory location is cleared.
+(define_peephole2
+ [(set (match_operand:SI 0 "arith_reg_operand" "r,r")
+ (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")))
+ (set (match_dup 0)
+ (and:SI (match_dup 0)
+ (match_operand:SI 2 "const_int_operand" "Psz,Psz")))
+ (set (match_dup 1)
+ (match_operand 3 "arith_reg_operand" "r,r"))]
+ "TARGET_SH2A && TARGET_BITOPS
+ && satisfies_constraint_Psz (operands[2])
+ && REGNO (operands[0]) == REGNO (operands[3])"
+ [(set (match_dup 1)
+ (and:QI (match_dup 1)
+ (match_dup 2)))]
+ "")
;; This matches cases where a stack pointer increment at the start of the
;; epilogue combines with a stack slot read loading the return value.
[(prefetch (match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))]
- "TARGET_HARD_SH4 || TARGET_SHCOMPACT"
+ "(TARGET_HARD_SH4 || TARGET_SHCOMPACT) && !TARGET_VXWORKS_RTP"
"*
{
return \"pref @%0\";
}"
[(set_attr "type" "other")])
+;; In user mode, the "pref" instruction will raise a RADDERR exception
+;; for accesses to [0x80000000,0xffffffff]. This makes it an unsuitable
+;; implementation of __builtin_prefetch for VxWorks RTPs.
(define_expand "prefetch"
[(prefetch (match_operand 0 "address_operand" "p")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))]
- "TARGET_HARD_SH4 || TARGET_SH5"
+ "TARGET_SH2A || ((TARGET_HARD_SH4 || TARGET_SH5)
+ && (TARGET_SHMEDIA || !TARGET_VXWORKS_RTP))"
"
{
if (GET_MODE (operands[0]) != Pmode
operands[0] = force_reg (Pmode, operands[0]);
}")
+(define_insn "prefetch_m2a"
+ [(prefetch (match_operand:SI 0 "register_operand" "r")
+ (match_operand:SI 1 "const_int_operand" "n")
+ (match_operand:SI 2 "const_int_operand" "n"))]
+ "TARGET_SH2A"
+ "pref\\t@%0"
+ [(set_attr "type" "other")])
+
(define_insn "alloco_i"
[(set (mem:BLK (match_operand:QI 0 "cache_address_operand" "p"))
(unspec:BLK [(const_int 0)] UNSPEC_ALLOCO))]