;;- Machine description for GNU compiler -- S/390 / zSeries version.
-;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
;; Free Software Foundation, Inc.
;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
;; Ulrich Weigand (uweigand@de.ibm.com).
;; GCC is free software; you can redistribute it and/or modify it under
;; the terms of the GNU General Public License as published by the Free
-;; Software Foundation; either version 2, or (at your option) any later
+;; Software Foundation; either version 3, or (at your option) any later
;; version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
;; for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING. If not, write to the Free
-;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
-;; 02110-1301, USA.
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
;;
;; See constraints.md for a description of constraints specific to s390.
;; Registers
;;
+; Registers with special meaning
+
(define_constants
[
; Sibling call register.
(TP_REGNUM 36)
])
+; Hardware register names
+
+(define_constants
+ [
+ ; General purpose registers
+ (GPR0_REGNUM 0)
+ ; Floating point registers.
+ (FPR0_REGNUM 16)
+ (FPR2_REGNUM 18)
+ ])
+
+;;
+;; PFPO GPR0 argument format
+;;
+
+(define_constants
+ [
+ ; PFPO operation type
+ (PFPO_CONVERT 0x1000000)
+ ; PFPO operand types
+ (PFPO_OP_TYPE_SF 0x5)
+ (PFPO_OP_TYPE_DF 0x6)
+ (PFPO_OP_TYPE_TF 0x7)
+ (PFPO_OP_TYPE_SD 0x8)
+ (PFPO_OP_TYPE_DD 0x9)
+ (PFPO_OP_TYPE_TD 0xa)
+ ; Bitposition of operand types
+ (PFPO_OP0_TYPE_SHIFT 16)
+ (PFPO_OP1_TYPE_SHIFT 8)
+ ])
+
;; Instruction operand type as used in the Principles of Operation.
;; Used to determine defaults for length and other attribute values.
;; Other includes
(include "tpf.md")
-;; Macros
+;; Iterators
-;; This mode macro allows floating point patterns to be generated from the
+;; These mode iterators allow floating point patterns to be generated from the
;; same template.
-(define_mode_macro FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
-(define_mode_macro BFP [TF DF SF])
-(define_mode_macro DFP [TD DD])
-(define_mode_macro DSF [DF SF])
-(define_mode_macro SD_SF [SF SD])
-(define_mode_macro DD_DF [DF DD])
-(define_mode_macro TD_TF [TF TD])
-
-;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
+(define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
+(define_mode_iterator BFP [TF DF SF])
+(define_mode_iterator DFP [TD DD])
+(define_mode_iterator DFP_ALL [TD DD SD])
+(define_mode_iterator DSF [DF SF])
+(define_mode_iterator SD_SF [SF SD])
+(define_mode_iterator DD_DF [DF DD])
+(define_mode_iterator TD_TF [TF TD])
+
+;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated
;; from the same template.
-(define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI])
+(define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI])
-;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
+;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
;; from the same template.
-(define_mode_macro GPR [(DI "TARGET_64BIT") SI])
-(define_mode_macro DSI [DI SI])
+(define_mode_iterator GPR [(DI "TARGET_64BIT") SI])
+(define_mode_iterator DSI [DI SI])
-;; This mode macro allows :P to be used for patterns that operate on
+;; These mode iterators allow :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match.
-(define_mode_macro DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
-(define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
+(define_mode_iterator DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
+(define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
-;; This mode macro allows the QI and HI patterns to be defined from
+;; This mode iterator allows the QI and HI patterns to be defined from
;; the same template.
-(define_mode_macro HQI [HI QI])
+(define_mode_iterator HQI [HI QI])
-;; This mode macro allows the integer patterns to be defined from the
+;; This mode iterator allows the integer patterns to be defined from the
;; same template.
-(define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
+(define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI])
-;; This macro allows to unify all 'bCOND' expander patterns.
-(define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
+;; This iterator allows to unify all 'bCOND' expander patterns.
+(define_code_iterator COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
ordered uneq unlt ungt unle unge ltgt])
-;; This macro allows to unify all 'sCOND' patterns.
-(define_code_macro SCOND [ltu gtu leu geu])
+;; This iterator allows to unify all 'sCOND' patterns.
+(define_code_iterator SCOND [ltu gtu leu geu])
-;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
+;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
;; the same template.
-(define_code_macro SHIFT [ashift lshiftrt])
+(define_code_iterator SHIFT [ashift lshiftrt])
-;; These macros allow to combine most atomic operations.
-(define_code_macro ATOMIC [and ior xor plus minus mult])
+;; This iterator and attribute allow to combine most atomic operations.
+(define_code_iterator ATOMIC [and ior xor plus minus mult])
(define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
(plus "add") (minus "sub") (mult "nand")])
(define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
;; The decimal floating point variants of add, sub, div and mul support 3
-;; fp register operands. The following macros allow to merge the bfp and
+;; fp register operands. The following attributes allow to merge the bfp and
;; dfp variants in a single insn definition.
-;; This macro is used to set op_type accordingly.
+;; This attribute is used to set op_type accordingly.
(define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
(DD "RRR") (SD "RRR")])
-;; This macro is used in the operand constraint list in order to have the
+;; This attribute is used in the operand constraint list in order to have the
;; first and the second operand match for bfp modes.
(define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
-;; This macro is used in the operand list of the instruction to have an
+;; This attribute is used in the operand list of the instruction to have an
;; additional operand for the dfp instructions.
(define_mode_attr op1 [(TF "") (DF "") (SF "")
(TD "%1,") (DD "%1,") (SD "%1,")])
;; This is used to disable the memory alternative in TFmode patterns.
(define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
-;; This macro adds b for bfp instructions and t for dfp instructions and is used
+;; This attribute adds b for bfp instructions and t for dfp instructions and is used
;; within instruction mnemonics.
(define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
[(set (reg CC_REGNUM)
(compare (match_operand:FP 0 "register_operand" "f")
(match_operand:FP 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
"lt<xde><bt>r\t%0,%0"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<bfp>")])
-; ltxr, ltdr, lter
-(define_insn "*cmp<mode>_ccs_0_ibm"
- [(set (reg CC_REGNUM)
- (compare (match_operand:BFP 0 "register_operand" "f")
- (match_operand:BFP 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lt<xde>r\t%0,%0"
- [(set_attr "op_type" "<RRe>")
- (set_attr "type" "fsimp<mode>")])
-
; cxtr, cxbr, cdbr, cebr, cxb, cdb, ceb, cxbtr, cdbtr
(define_insn "*cmp<mode>_ccs"
[(set (reg CC_REGNUM)
(compare (match_operand:FP 0 "register_operand" "f,f")
(match_operand:FP 1 "general_operand" "f,<Rf>")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
"@
c<xde><bt>r\t%0,%1
c<xde>b\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimp<bfp>")])
-; cxr, cdr, cer, cx, cd, ce
-(define_insn "*cmp<mode>_ccs_ibm"
- [(set (reg CC_REGNUM)
- (compare (match_operand:BFP 0 "register_operand" "f,f")
- (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- c<xde>r\t%0,%1
- c<xde>\t%0,%1"
- [(set_attr "op_type" "<RRe>,<RXe>")
- (set_attr "type" "fsimp<mode>")])
-
-
;;
;;- Move instructions.
;;
{
/* Make it explicit that loading a register from memory
always sign-extends (at least) to SImode. */
- if (optimize && !no_new_pseudos
+ if (optimize && can_create_pseudo_p ()
&& register_operand (operands[0], VOIDmode)
&& GET_CODE (operands[1]) == MEM)
{
{
/* On z/Architecture, zero-extending from memory to register
is just as fast as a QImode load. */
- if (TARGET_ZARCH && optimize && !no_new_pseudos
+ if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
&& register_operand (operands[0], VOIDmode)
&& GET_CODE (operands[1]) == MEM)
{
FAIL;
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
- if (no_new_pseudos)
+ if (!can_create_pseudo_p ())
{
if (GET_CODE (XEXP (operands[1], 0)) == REG)
{
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
- if (no_new_pseudos)
+ if (!can_create_pseudo_p ())
{
if (GET_CODE (XEXP (operands[0], 0)) == REG)
{
; Test data class.
;
+(define_expand "signbit<mode>2"
+ [(set (reg:CCZ CC_REGNUM)
+ (unspec:CCZ [(match_operand:BFP 1 "register_operand" "f")
+ (match_dup 2)]
+ UNSPEC_TDC_INSN))
+ (set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
+ "TARGET_HARD_FLOAT"
+{
+ operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
+})
+
(define_expand "isinf<mode>2"
[(set (reg:CCZ CC_REGNUM)
(unspec:CCZ [(match_operand:BFP 1 "register_operand" "f")
UNSPEC_TDC_INSN))
(set (match_operand:SI 0 "register_operand" "=d")
(unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "TARGET_HARD_FLOAT"
{
operands[2] = GEN_INT (S390_TDC_INFINITY);
})
[(set (reg:CCZ CC_REGNUM)
(unspec:CCZ [(match_operand:BFP 0 "register_operand" "f")
(match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "TARGET_HARD_FLOAT"
"tc<xde>b\t%0,%1"
[(set_attr "op_type" "RXE")
(set_attr "type" "fsimp<mode>")])
(define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand" "")
(unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "TARGET_HARD_FLOAT"
{
rtx label1 = gen_label_rtx ();
rtx label2 = gen_label_rtx ();
REAL_VALUE_TYPE cmp, sub;
operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
- real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
- real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
+ real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:mode>mode);
+ real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:mode>mode);
emit_insn (gen_cmp<BFP:mode> (operands[1],
CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode)));
emit_jump_insn (gen_blt (label1));
emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
- emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_ieee (operands[0], temp,
+ emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
GEN_INT (7)));
emit_jump (label2);
emit_label (label1);
- emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_ieee (operands[0],
+ emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
operands[1], GEN_INT (5)));
emit_label (label2);
DONE;
})
-(define_expand "fix_trunc<mode>di2"
- [(set (match_operand:DI 0 "register_operand" "")
- (fix:DI (match_operand:DSF 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+(define_expand "fix_trunc<DSF:mode><GPR:mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "")
+ (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
+ "TARGET_HARD_FLOAT"
{
- operands[1] = force_reg (<MODE>mode, operands[1]);
- emit_insn (gen_fix_trunc<mode>di2_ieee (operands[0], operands[1],
- GEN_INT (5)));
+ emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
+ GEN_INT (5)));
DONE;
})
; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
-(define_insn "fix_trunc<BFP:mode><GPR:mode>2_ieee"
+(define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
[(set (match_operand:GPR 0 "register_operand" "=d")
(fix:GPR (match_operand:BFP 1 "register_operand" "f")))
(unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "TARGET_HARD_FLOAT"
"c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "ftoi")])
(fix:GPR (match_operand:TF 1 "register_operand" "")))
(unspec:GPR [(const_int 5)] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))])]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "")
-
-;
-; fix_truncdfsi2 instruction pattern(s).
-;
-
-(define_expand "fix_truncdfsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
- "TARGET_HARD_FLOAT"
-{
- if (TARGET_IBM_FLOAT)
- {
- /* This is the algorithm from POP chapter A.5.7.2. */
-
- rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
- rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
- rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
-
- operands[1] = force_reg (DFmode, operands[1]);
- emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
- two31r, two32, temp));
- }
- else
- {
- operands[1] = force_reg (DFmode, operands[1]);
- emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
- }
-
- DONE;
-})
-
-(define_insn "fix_truncdfsi2_ibm"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
- (use (match_operand:DI 2 "immediate_operand" "m"))
- (use (match_operand:DI 3 "immediate_operand" "m"))
- (use (match_operand:BLK 4 "memory_operand" "m"))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-{
- output_asm_insn ("sd\t%1,%2", operands);
- output_asm_insn ("aw\t%1,%3", operands);
- output_asm_insn ("std\t%1,%4", operands);
- output_asm_insn ("xi\t%N4,128", operands);
- return "l\t%0,%N4";
-}
- [(set_attr "length" "20")])
-
-;
-; fix_truncsfsi2 instruction pattern(s).
-;
-
-(define_expand "fix_truncsfsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
"TARGET_HARD_FLOAT"
-{
- if (TARGET_IBM_FLOAT)
- {
- /* Convert to DFmode and then use the POP algorithm. */
- rtx temp = gen_reg_rtx (DFmode);
- emit_insn (gen_extendsfdf2 (temp, operands[1]));
- emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
- }
- else
- {
- operands[1] = force_reg (SFmode, operands[1]);
- emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
- }
+ "")
- DONE;
-})
;
-; float(si|di)(tf|df|sf)2 instruction pattern(s).
+; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
;
; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
(define_insn "floatdi<mode>2"
[(set (match_operand:FP 0 "register_operand" "=f")
(float:FP (match_operand:DI 1 "register_operand" "d")))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "TARGET_64BIT && TARGET_HARD_FLOAT"
"c<xde>g<bt>r\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "itof" )])
; cxfbr, cdfbr, cefbr
-(define_insn "floatsi<mode>2_ieee"
+(define_insn "floatsi<mode>2"
[(set (match_operand:BFP 0 "register_operand" "=f")
(float:BFP (match_operand:SI 1 "register_operand" "d")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "TARGET_HARD_FLOAT"
"c<xde>fbr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "itof" )])
;
-; floatsi(tf|df)2 instruction pattern(s).
-;
-
-(define_expand "floatsitf2"
- [(set (match_operand:TF 0 "register_operand" "")
- (float:TF (match_operand:SI 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "")
-
-(define_expand "floatsidf2"
- [(set (match_operand:DF 0 "register_operand" "")
- (float:DF (match_operand:SI 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT"
-{
- if (TARGET_IBM_FLOAT)
- {
- /* This is the algorithm from POP chapter A.5.7.1. */
-
- rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
- rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
-
- emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
- DONE;
- }
-})
-
-(define_insn "floatsidf2_ibm"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (float:DF (match_operand:SI 1 "register_operand" "d")))
- (use (match_operand:DI 2 "immediate_operand" "m"))
- (use (match_operand:BLK 3 "memory_operand" "m"))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-{
- output_asm_insn ("st\t%1,%N3", operands);
- output_asm_insn ("xi\t%N3,128", operands);
- output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
- output_asm_insn ("ld\t%0,%3", operands);
- return "sd\t%0,%2";
-}
- [(set_attr "length" "20")])
-
-;
-; floatsisf2 instruction pattern(s).
-;
-
-(define_expand "floatsisf2"
- [(set (match_operand:SF 0 "register_operand" "")
- (float:SF (match_operand:SI 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT"
-{
- if (TARGET_IBM_FLOAT)
- {
- /* Use the POP algorithm to convert to DFmode and then truncate. */
- rtx temp = gen_reg_rtx (DFmode);
- emit_insn (gen_floatsidf2 (temp, operands[1]));
- emit_insn (gen_truncdfsf2 (operands[0], temp));
- DONE;
- }
-})
-
-;
; truncdfsf2 instruction pattern(s).
;
-(define_expand "truncdfsf2"
- [(set (match_operand:SF 0 "register_operand" "")
- (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "truncdfsf2_ieee"
+(define_insn "truncdfsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "TARGET_HARD_FLOAT"
"ledbr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "ftruncdf")])
-(define_insn "truncdfsf2_ibm"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- ler\t%0,%1
- le\t%0,%1"
- [(set_attr "op_type" "RR,RX")
- (set_attr "type" "floadsf")])
-
;
-; trunctfdf2 instruction pattern(s).
+; trunctf(df|sf)2 instruction pattern(s).
;
-(define_expand "trunctfdf2"
- [(parallel
- [(set (match_operand:DF 0 "register_operand" "")
- (float_truncate:DF (match_operand:TF 1 "register_operand" "")))
- (clobber (match_scratch:TF 2 "=f"))])]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*trunctfdf2_ieee"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (float_truncate:DF (match_operand:TF 1 "register_operand" "f")))
+; ldxbr, lexbr
+(define_insn "trunctf<mode>2"
+ [(set (match_operand:DSF 0 "register_operand" "=f")
+ (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
(clobber (match_scratch:TF 2 "=f"))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "ldxbr\t%2,%1\;ldr\t%0,%2"
+ "TARGET_HARD_FLOAT"
+ "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
[(set_attr "length" "6")
(set_attr "type" "ftrunctf")])
-(define_insn "*trunctfdf2_ibm"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (float_truncate:DF (match_operand:TF 1 "register_operand" "f")))
- (clobber (match_scratch:TF 2 "=f"))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "ldxr\t%2,%1\;ldr\t%0,%2"
- [(set_attr "length" "4")
- (set_attr "type" "ftrunctf")])
-
-;
-; trunctfsf2 instruction pattern(s).
-;
-
-(define_expand "trunctfsf2"
- [(parallel
- [(set (match_operand:SF 0 "register_operand" "=f")
- (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
- (clobber (match_scratch:TF 2 "=f"))])]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*trunctfsf2_ieee"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
- (clobber (match_scratch:TF 2 "=f"))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lexbr\t%2,%1\;ler\t%0,%2"
- [(set_attr "length" "6")
- (set_attr "type" "ftrunctf")])
-
-(define_insn "*trunctfsf2_ibm"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
- (clobber (match_scratch:TF 2 "=f"))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lexr\t%2,%1\;ler\t%0,%2"
- [(set_attr "length" "6")
- (set_attr "type" "ftrunctf")])
-
;
; trunctddd2 and truncddsd2 instruction pattern(s).
;
(set_attr "type" "fsimptf")])
;
-; extendsfdf2 instruction pattern(s).
-;
-
-(define_expand "extendsfdf2"
- [(set (match_operand:DF 0 "register_operand" "")
- (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
- "TARGET_HARD_FLOAT"
-{
- if (TARGET_IBM_FLOAT)
- {
- emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
- DONE;
- }
-})
-
-(define_insn "extendsfdf2_ieee"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- ldebr\t%0,%1
- ldeb\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpsf, floadsf")])
-
-(define_insn "extendsfdf2_ibm"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- sdr\t%0,%0\;ler\t%0,%1
- sdr\t%0,%0\;le\t%0,%1"
- [(set_attr "length" "4,6")
- (set_attr "type" "floadsf")])
-
-;
-; extenddftf2 instruction pattern(s).
-;
-
-(define_expand "extenddftf2"
- [(set (match_operand:TF 0 "register_operand" "")
- (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*extenddftf2_ieee"
- [(set (match_operand:TF 0 "register_operand" "=f,f")
- (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- lxdbr\t%0,%1
- lxdb\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimptf, floadtf")])
-
-(define_insn "*extenddftf2_ibm"
- [(set (match_operand:TF 0 "register_operand" "=f,f")
- (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- lxdr\t%0,%1
- lxd\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimptf, floadtf")])
-
-;
-; extendsftf2 instruction pattern(s).
+; extend(sf|df)(df|tf)2 instruction pattern(s).
;
-(define_expand "extendsftf2"
- [(set (match_operand:TF 0 "register_operand" "")
- (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*extendsftf2_ieee"
- [(set (match_operand:TF 0 "register_operand" "=f,f")
- (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- lxebr\t%0,%1
- lxeb\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimptf, floadtf")])
-
-(define_insn "*extendsftf2_ibm"
- [(set (match_operand:TF 0 "register_operand" "=f,f")
- (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
+; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
+(define_insn "extend<DSF:mode><BFP:mode>2"
+ [(set (match_operand:BFP 0 "register_operand" "=f,f")
+ (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
+ "TARGET_HARD_FLOAT
+ && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
"@
- lxer\t%0,%1
- lxe\t%0,%1"
+ l<BFP:xde><DSF:xde>br\t%0,%1
+ l<BFP:xde><DSF:xde>b\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimptf, floadtf")])
+ (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
;
; extendddtd2 and extendsddd2 instruction pattern(s).
[(set_attr "op_type" "RRF")
(set_attr "type" "fsimptf")])
+; Binary <-> Decimal floating point trunc patterns
+;
+
+(define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
+ [(set (reg:DFP_ALL FPR0_REGNUM)
+ (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
+ (use (reg:SI GPR0_REGNUM))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_HARD_FLOAT && TARGET_DFP"
+ "pfpo")
+
+(define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
+ [(set (reg:BFP FPR0_REGNUM)
+ (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
+ (use (reg:SI GPR0_REGNUM))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_HARD_FLOAT && TARGET_DFP"
+ "pfpo")
+
+(define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
+ [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
+ (set (reg:SI GPR0_REGNUM) (match_dup 2))
+ (parallel
+ [(set (reg:DFP_ALL FPR0_REGNUM)
+ (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
+ (use (reg:SI GPR0_REGNUM))
+ (clobber (reg:CC CC_REGNUM))])
+ (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
+ (reg:DFP_ALL FPR0_REGNUM))]
+ "TARGET_HARD_FLOAT && TARGET_DFP
+ && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
+{
+ HOST_WIDE_INT flags;
+
+ flags = (PFPO_CONVERT |
+ PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
+ PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
+
+ operands[2] = GEN_INT (flags);
+})
+
+(define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
+ [(set (reg:DFP_ALL FPR2_REGNUM)
+ (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
+ (set (reg:SI GPR0_REGNUM) (match_dup 2))
+ (parallel
+ [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
+ (use (reg:SI GPR0_REGNUM))
+ (clobber (reg:CC CC_REGNUM))])
+ (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
+ "TARGET_HARD_FLOAT && TARGET_DFP
+ && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
+{
+ HOST_WIDE_INT flags;
+
+ flags = (PFPO_CONVERT |
+ PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
+ PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
+
+ operands[2] = GEN_INT (flags);
+})
+
+;
+; Binary <-> Decimal floating point extend patterns
+;
+
+(define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
+ [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
+ (use (reg:SI GPR0_REGNUM))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_HARD_FLOAT && TARGET_DFP"
+ "pfpo")
+
+(define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
+ [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
+ (use (reg:SI GPR0_REGNUM))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_HARD_FLOAT && TARGET_DFP"
+ "pfpo")
+
+(define_expand "extend<BFP:mode><DFP_ALL:mode>2"
+ [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
+ (set (reg:SI GPR0_REGNUM) (match_dup 2))
+ (parallel
+ [(set (reg:DFP_ALL FPR0_REGNUM)
+ (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
+ (use (reg:SI GPR0_REGNUM))
+ (clobber (reg:CC CC_REGNUM))])
+ (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
+ (reg:DFP_ALL FPR0_REGNUM))]
+ "TARGET_HARD_FLOAT && TARGET_DFP
+ && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
+{
+ HOST_WIDE_INT flags;
+
+ flags = (PFPO_CONVERT |
+ PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
+ PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
+
+ operands[2] = GEN_INT (flags);
+})
+
+(define_expand "extend<DFP_ALL:mode><BFP:mode>2"
+ [(set (reg:DFP_ALL FPR2_REGNUM)
+ (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
+ (set (reg:SI GPR0_REGNUM) (match_dup 2))
+ (parallel
+ [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
+ (use (reg:SI GPR0_REGNUM))
+ (clobber (reg:CC CC_REGNUM))])
+ (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
+ "TARGET_HARD_FLOAT && TARGET_DFP
+ && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
+{
+ HOST_WIDE_INT flags;
+
+ flags = (PFPO_CONVERT |
+ PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
+ PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
+
+ operands[2] = GEN_INT (flags);
+})
+
+
;;
;; ARITHMETIC OPERATIONS
;;
(match_dup 7)))
(set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
(parallel
- [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
- (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
+ [(set (match_dup 3) (plus:DI
+ (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
+ (match_dup 4)) (match_dup 5)))
(clobber (reg:CC CC_REGNUM))])]
"operands[3] = operand_subword (operands[0], 0, 0, TImode);
operands[4] = operand_subword (operands[1], 0, 0, TImode);
(match_dup 7)))
(set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
(parallel
- [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
- (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
+ [(set (match_dup 3) (plus:SI
+ (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
+ (match_dup 4)) (match_dup 5)))
(clobber (reg:CC CC_REGNUM))])]
"operands[3] = operand_subword (operands[0], 0, 0, DImode);
operands[4] = operand_subword (operands[1], 0, 0, DImode);
; add(tf|df|sf|td|dd)3 instruction pattern(s).
;
-(define_expand "add<mode>3"
- [(parallel
- [(set (match_operand:FP 0 "register_operand" "")
- (plus:FP (match_operand:FP 1 "nonimmediate_operand" "")
- (match_operand:FP 2 "general_operand" "")))
- (clobber (reg:CC CC_REGNUM))])]
- "TARGET_HARD_FLOAT"
- "")
-
; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
-(define_insn "*add<mode>3"
+(define_insn "add<mode>3"
[(set (match_operand:FP 0 "register_operand" "=f, f")
(plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
(match_operand:FP 2 "general_operand" " f,<Rf>")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "TARGET_HARD_FLOAT"
"@
a<xde><bt>r\t%0,<op1>%2
a<xde>b\t%0,%2"
(match_operand:FP 3 "const0_operand" "")))
(set (match_operand:FP 0 "register_operand" "=f,f")
(plus:FP (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"@
a<xde><bt>r\t%0,<op1>%2
a<xde>b\t%0,%2"
(match_operand:FP 2 "general_operand" " f,<Rf>"))
(match_operand:FP 3 "const0_operand" "")))
(clobber (match_scratch:FP 0 "=f,f"))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"@
a<xde><bt>r\t%0,<op1>%2
a<xde>b\t%0,%2"
[(set_attr "op_type" "<RRer>,RXE")
(set_attr "type" "fsimp<bfp>")])
-; axr, adr, aer, ax, ad, ae
-(define_insn "*add<mode>3_ibm"
- [(set (match_operand:BFP 0 "register_operand" "=f,f")
- (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
- (match_operand:BFP 2 "general_operand" "f,<Rf>")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- a<xde>r\t%0,%2
- a<xde>\t%0,%2"
- [(set_attr "op_type" "<RRe>,<RXe>")
- (set_attr "type" "fsimp<mode>")])
-
;;
;;- Subtract instructions.
; sub(tf|df|sf|td|dd)3 instruction pattern(s).
;
-(define_expand "sub<mode>3"
- [(parallel
- [(set (match_operand:FP 0 "register_operand" "")
- (minus:FP (match_operand:FP 1 "register_operand" "")
- (match_operand:FP 2 "general_operand" "")))
- (clobber (reg:CC CC_REGNUM))])]
- "TARGET_HARD_FLOAT"
- "")
-
; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
-(define_insn "*sub<mode>3"
+(define_insn "sub<mode>3"
[(set (match_operand:FP 0 "register_operand" "=f, f")
(minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
- (match_operand:FP 2 "general_operand" "f,<Rf>")))
+ (match_operand:FP 2 "general_operand" "f,<Rf>")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "TARGET_HARD_FLOAT"
"@
s<xde><bt>r\t%0,<op1>%2
s<xde>b\t%0,%2"
(define_insn "*sub<mode>3_cc"
[(set (reg CC_REGNUM)
(compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
- (match_operand:FP 2 "general_operand" "f,<Rf>"))
+ (match_operand:FP 2 "general_operand" "f,<Rf>"))
(match_operand:FP 3 "const0_operand" "")))
(set (match_operand:FP 0 "register_operand" "=f,f")
(minus:FP (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"@
s<xde><bt>r\t%0,<op1>%2
s<xde>b\t%0,%2"
(match_operand:FP 2 "general_operand" "f,<Rf>"))
(match_operand:FP 3 "const0_operand" "")))
(clobber (match_scratch:FP 0 "=f,f"))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"@
s<xde><bt>r\t%0,<op1>%2
s<xde>b\t%0,%2"
[(set_attr "op_type" "<RRer>,RXE")
(set_attr "type" "fsimp<bfp>")])
-; sxr, sdr, ser, sx, sd, se
-(define_insn "*sub<mode>3_ibm"
- [(set (match_operand:BFP 0 "register_operand" "=f,f")
- (minus:BFP (match_operand:BFP 1 "register_operand" "0,0")
- (match_operand:BFP 2 "general_operand" "f,<Rf>")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- s<xde>r\t%0,%2
- s<xde>\t%0,%2"
- [(set_attr "op_type" "<RRe>,<RXe>")
- (set_attr "type" "fsimp<mode>")])
-
;;
;;- Conditional add/subtract instructions.
; add(di|si)cc instruction pattern(s).
;
+; the following 4 patterns are used when the result of an add with
+; carry is checked for an overflow condition
+
+; op1 + op2 + c < op1
+
+; alcr, alc, alcgr, alcg
+(define_insn "*add<mode>3_alc_carry1_cc"
+ [(set (reg CC_REGNUM)
+ (compare
+ (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
+ (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
+ (match_operand:GPR 2 "general_operand" "d,m"))
+ (match_dup 1)))
+ (set (match_operand:GPR 0 "register_operand" "=d,d")
+ (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
+ "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
+ "@
+ alc<g>r\t%0,%2
+ alc<g>\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")])
+
+; alcr, alc, alcgr, alcg
+(define_insn "*add<mode>3_alc_carry1_cconly"
+ [(set (reg CC_REGNUM)
+ (compare
+ (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
+ (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
+ (match_operand:GPR 2 "general_operand" "d,m"))
+ (match_dup 1)))
+ (clobber (match_scratch:GPR 0 "=d,d"))]
+ "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
+ "@
+ alc<g>r\t%0,%2
+ alc<g>\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")])
+
+; op1 + op2 + c < op2
+
+; alcr, alc, alcgr, alcg
+(define_insn "*add<mode>3_alc_carry2_cc"
+ [(set (reg CC_REGNUM)
+ (compare
+ (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
+ (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
+ (match_operand:GPR 2 "general_operand" "d,m"))
+ (match_dup 2)))
+ (set (match_operand:GPR 0 "register_operand" "=d,d")
+ (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
+ "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
+ "@
+ alc<g>r\t%0,%2
+ alc<g>\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")])
+
+; alcr, alc, alcgr, alcg
+(define_insn "*add<mode>3_alc_carry2_cconly"
+ [(set (reg CC_REGNUM)
+ (compare
+ (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
+ (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
+ (match_operand:GPR 2 "general_operand" "d,m"))
+ (match_dup 2)))
+ (clobber (match_scratch:GPR 0 "=d,d"))]
+ "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
+ "@
+ alc<g>r\t%0,%2
+ alc<g>\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")])
+
; alcr, alc, alcgr, alcg
(define_insn "*add<mode>3_alc_cc"
[(set (reg CC_REGNUM)
(compare
- (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
- (match_operand:GPR 2 "general_operand" "d,m"))
- (match_operand:GPR 3 "s390_alc_comparison" ""))
+ (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
+ (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
+ (match_operand:GPR 2 "general_operand" "d,m"))
(const_int 0)))
(set (match_operand:GPR 0 "register_operand" "=d,d")
- (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
+ (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
"@
alc<g>r\t%0,%2
; alcr, alc, alcgr, alcg
(define_insn "*add<mode>3_alc"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
- (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
- (match_operand:GPR 2 "general_operand" "d,m"))
- (match_operand:GPR 3 "s390_alc_comparison" "")))
+ (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
+ (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
+ (match_operand:GPR 2 "general_operand" "d,m")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH"
"@
"&& reload_completed"
[(set (match_dup 0) (const_int 0))
(parallel
- [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
- (match_dup 1)))
+ [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
+ (match_dup 0)))
(clobber (reg:CC CC_REGNUM))])]
"")
; mul(tf|df|sf|td|dd)3 instruction pattern(s).
;
-(define_expand "mul<mode>3"
- [(set (match_operand:FP 0 "register_operand" "")
- (mult:FP (match_operand:FP 1 "nonimmediate_operand" "")
- (match_operand:FP 2 "general_operand" "")))]
- "TARGET_HARD_FLOAT"
- "")
-
; mxbr mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
-(define_insn "*mul<mode>3"
+(define_insn "mul<mode>3"
[(set (match_operand:FP 0 "register_operand" "=f,f")
(mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
(match_operand:FP 2 "general_operand" "f,<Rf>")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "TARGET_HARD_FLOAT"
"@
m<xdee><bt>r\t%0,<op1>%2
m<xdee>b\t%0,%2"
[(set_attr "op_type" "<RRer>,RXE")
(set_attr "type" "fmul<bfp>")])
-; mxr, mdr, mer, mx, md, me
-(define_insn "*mul<mode>3_ibm"
- [(set (match_operand:BFP 0 "register_operand" "=f,f")
- (mult:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
- (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- m<xde>r\t%0,%2
- m<xde>\t%0,%2"
- [(set_attr "op_type" "<RRe>,<RXe>")
- (set_attr "type" "fmul<mode>")])
-
; maxbr, madbr, maebr, maxb, madb, maeb
(define_insn "*fmadd<mode>"
[(set (match_operand:DSF 0 "register_operand" "=f,f")
(plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f")
(match_operand:DSF 2 "nonimmediate_operand" "f,R"))
(match_operand:DSF 3 "register_operand" "0,0")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
+ "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
"@
ma<xde>br\t%0,%1,%2
ma<xde>b\t%0,%1,%2"
(minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f")
(match_operand:DSF 2 "nonimmediate_operand" "f,R"))
(match_operand:DSF 3 "register_operand" "0,0")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
+ "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
"@
ms<xde>br\t%0,%1,%2
ms<xde>b\t%0,%1,%2"
; div(df|sf)3 instruction pattern(s).
;
-(define_expand "div<mode>3"
- [(set (match_operand:FP 0 "register_operand" "")
- (div:FP (match_operand:FP 1 "register_operand" "")
- (match_operand:FP 2 "general_operand" "")))]
- "TARGET_HARD_FLOAT"
- "")
-
; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
-(define_insn "*div<mode>3"
+(define_insn "div<mode>3"
[(set (match_operand:FP 0 "register_operand" "=f,f")
(div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
(match_operand:FP 2 "general_operand" "f,<Rf>")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "TARGET_HARD_FLOAT"
"@
d<xde><bt>r\t%0,<op1>%2
d<xde>b\t%0,%2"
[(set_attr "op_type" "<RRer>,RXE")
(set_attr "type" "fdiv<bfp>")])
-; dxr, ddr, der, dx, dd, de
-(define_insn "*div<mode>3_ibm"
- [(set (match_operand:BFP 0 "register_operand" "=f,f")
- (div:BFP (match_operand:BFP 1 "register_operand" "0,0")
- (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- d<xde>r\t%0,%2
- d<xde>\t%0,%2"
- [(set_attr "op_type" "<RRe>,<RXe>")
- (set_attr "type" "fdiv<mode>")])
-
;;
;;- And instructions.
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
"@
xgr\t%0,%2
- xr\t%0,%2"
+ xg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*xordi3_extimm"
(match_operand:BFP 2 "const0_operand" "")))
(set (match_operand:BFP 0 "register_operand" "=f")
(neg:BFP (match_dup 1)))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"lc<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
(compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
(match_operand:BFP 2 "const0_operand" "")))
(clobber (match_scratch:BFP 0 "=f"))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"lc<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
[(set (match_operand:BFP 0 "register_operand" "=f")
(neg:BFP (match_operand:BFP 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "TARGET_HARD_FLOAT"
"lc<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
-; lcxr, lcdr, lcer
-(define_insn "*neg<mode>2_ibm"
- [(set (match_operand:BFP 0 "register_operand" "=f")
- (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lc<xde>r\t%0,%1"
- [(set_attr "op_type" "<RRe>")
- (set_attr "type" "fsimp<mode>")])
-
;;
;;- Absolute value instructions.
(match_operand:BFP 2 "const0_operand" "")))
(set (match_operand:BFP 0 "register_operand" "=f")
(abs:BFP (match_dup 1)))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"lp<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
(compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
(match_operand:BFP 2 "const0_operand" "")))
(clobber (match_scratch:BFP 0 "=f"))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"lp<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
[(set (match_operand:BFP 0 "register_operand" "=f")
(abs:BFP (match_operand:BFP 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "TARGET_HARD_FLOAT"
"lp<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
-; lpxr, lpdr, lper
-(define_insn "*abs<mode>2_ibm"
- [(set (match_operand:BFP 0 "register_operand" "=f")
- (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lp<xde>r\t%0,%1"
- [(set_attr "op_type" "<RRe>")
- (set_attr "type" "fsimp<mode>")])
;;
;;- Negated absolute value instructions
(match_operand:BFP 2 "const0_operand" "")))
(set (match_operand:BFP 0 "register_operand" "=f")
(neg:BFP (abs:BFP (match_dup 1))))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"ln<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
(compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
(match_operand:BFP 2 "const0_operand" "")))
(clobber (match_scratch:BFP 0 "=f"))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"ln<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
[(set (match_operand:BFP 0 "register_operand" "=f")
(neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "TARGET_HARD_FLOAT"
"ln<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
(define_insn "sqrt<mode>2"
[(set (match_operand:BFP 0 "register_operand" "=f,f")
(sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "TARGET_HARD_FLOAT"
"@
sq<xde>br\t%0,%1
sq<xde>b\t%0,%1"
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