;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-;; 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
+;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
;; This file is part of GCC.
(UNSPEC_TLSGOTTPREL 28)
(UNSPEC_TLSTLS 29)
(UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
- (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
+ (UNSPEC_MV_CR_EQ 31) ; move_from_CR_eq_bit
])
;;
\f
;; Define an insn type attribute. This is used in function unit delay
;; computations.
-(define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
+(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
(const_string "integer"))
;; Length (in bytes).
(include "8540.md")
(include "power4.md")
(include "power5.md")
+(include "darwin.md")
\f
+;; This mode macro allows :P to be used for patterns that operate on
+;; pointer-sized quantities. Exactly one of the two alternatives will match.
+(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
+
;; Start with fixed-point load and store insns. Here we put only the more
;; complex forms. Basic data transfer is done later.
(match_operand:SI 2 "exact_log2_cint_operand" "N")))]
""
"{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
- [(set_attr "length" "8")])
+ [(set_attr "type" "two")
+ (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
and %0,%1,%2
{rlinm|rlwinm} %0,%1,0,%m2,%M2
{andil.|andi.} %0,%1,%b2
- {andiu.|andis.} %0,%1,%u2")
+ {andiu.|andis.} %0,%1,%u2"
+ [(set_attr "type" "*,*,compare,compare")])
;; Note to set cr's other than cr0 we do the and immediate and then
;; the test again -- this avoids a mfcr which on the higher end
}"
[(set_attr "length" "8")])
-(define_insn_and_split "*andsi3_internal7"
- [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
- (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r")
- (match_operand:SI 1 "mask_operand_wrap" "i,i"))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "TARGET_POWERPC64"
- "#"
- "TARGET_POWERPC64"
- [(parallel [(set (match_dup 2)
- (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4))
- (match_dup 5))
- (const_int 0)))
- (clobber (match_dup 3))])]
- "
-{
- int mb = extract_MB (operands[1]);
- int me = extract_ME (operands[1]);
- operands[4] = GEN_INT (me + 1);
- operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
-}"
- [(set_attr "type" "delayed_compare,compare")
- (set_attr "length" "4,8")])
-
-(define_insn_and_split "*andsi3_internal8"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
- (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "mask_operand_wrap" "i,i"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (and:SI (match_dup 1)
- (match_dup 2)))]
- "TARGET_POWERPC64"
- "#"
- "TARGET_POWERPC64"
- [(parallel [(set (match_dup 3)
- (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4))
- (match_dup 5))
- (const_int 0)))
- (set (match_dup 0)
- (and:SI (rotate:SI (match_dup 1) (match_dup 4))
- (match_dup 5)))])
- (set (match_dup 0)
- (rotate:SI (match_dup 0) (match_dup 6)))]
- "
-{
- int mb = extract_MB (operands[2]);
- int me = extract_ME (operands[2]);
- operands[4] = GEN_INT (me + 1);
- operands[6] = GEN_INT (32 - (me + 1));
- operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
-}"
- [(set_attr "type" "delayed_compare,compare")
- (set_attr "length" "8,12")])
-
(define_expand "iorsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
operands[3] = GEN_INT (start + size);
operands[2] = GEN_INT (64 - size);
return \"rldicl. %4,%1,%3,%2\";
-}")
+}"
+ [(set_attr "type" "compare")])
(define_insn "*extzvdi_internal2"
[(set (match_operand:CC 4 "gpc_reg_operand" "=x")
operands[3] = GEN_INT (start + size);
operands[2] = GEN_INT (64 - size);
return \"rldicl. %0,%1,%3,%2\";
-}")
+}"
+ [(set_attr "type" "compare")])
(define_insn "rotlsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
;; this case, we just lose precision that we would have otherwise gotten but
;; is not guaranteed. Perhaps this should be tightened up at some point.
-(define_insn_and_split "extendsfdf2"
+(define_expand "extendsfdf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "")))]
+ "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
+ "")
+
+(define_insn_and_split "*extendsfdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "0,f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
}
[(set_attr "type" "fp")])
-(define_insn "truncdfsf2"
+(define_expand "truncdfsf2"
+ [(set (match_operand:SF 0 "gpc_reg_operand" "")
+ (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
+ "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
+ "")
+
+(define_insn "*truncdfsf2_fpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
(match_operand:SF 2 "gpc_reg_operand" ""))
(match_dup 1)
(match_dup 2)))]
- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
"{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
(define_expand "minsf3"
(match_operand:SF 2 "gpc_reg_operand" ""))
(match_dup 2)
(match_dup 1)))]
- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
"{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
(define_split
(match_operator:SF 3 "min_max_operator"
[(match_operand:SF 1 "gpc_reg_operand" "")
(match_operand:SF 2 "gpc_reg_operand" "")]))]
- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
[(const_int 0)]
"
{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
"fsel %0,%1,%2,%3"
[(set_attr "type" "fp")])
-(define_insn "negdf2"
+(define_expand "negdf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
+ "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
+ "")
+
+(define_insn "*negdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fneg %0,%1"
[(set_attr "type" "fp")])
-(define_insn "absdf2"
+(define_expand "absdf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
+ "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
+ "")
+
+(define_insn "*absdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fabs %0,%1"
[(set_attr "type" "fp")])
-(define_insn ""
+(define_insn "*nabsdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fnabs %0,%1"
[(set_attr "type" "fp")])
-(define_insn "adddf3"
+(define_expand "adddf3"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
+ (match_operand:DF 2 "gpc_reg_operand" "")))]
+ "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
+ "")
+
+(define_insn "*adddf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
"{fa|fadd} %0,%1,%2"
[(set_attr "type" "fp")])
-(define_insn "subdf3"
+(define_expand "subdf3"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
+ (match_operand:DF 2 "gpc_reg_operand" "")))]
+ "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
+ "")
+
+(define_insn "*subdf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
"{fs|fsub} %0,%1,%2"
[(set_attr "type" "fp")])
-(define_insn "muldf3"
+(define_expand "muldf3"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
+ (match_operand:DF 2 "gpc_reg_operand" "")))]
+ "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
+ "")
+
+(define_insn "*muldf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
"{fm|fmul} %0,%1,%2"
[(set_attr "type" "dmul")])
-(define_insn "divdf3"
+(define_expand "divdf3"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
+ (match_operand:DF 2 "gpc_reg_operand" "")))]
+ "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
+ "")
+
+(define_insn "*divdf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
(match_operand:DF 2 "gpc_reg_operand" ""))
(match_dup 1)
(match_dup 2)))]
- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
"{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
(define_expand "mindf3"
(match_operand:DF 2 "gpc_reg_operand" ""))
(match_dup 2)
(match_dup 1)))]
- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
"{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
(define_split
(match_operator:DF 3 "min_max_operator"
[(match_operand:DF 1 "gpc_reg_operand" "")
(match_operand:DF 2 "gpc_reg_operand" "")]))]
- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
[(const_int 0)]
"
{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
"TARGET_HARD_FLOAT && TARGET_FPRS"
"
{
+ if (TARGET_E500_DOUBLE)
+ {
+ emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
+ DONE;
+ }
if (TARGET_POWERPC64)
{
rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
(use (match_dup 3))
(clobber (match_dup 4))
(clobber (match_dup 5))])]
- "TARGET_HARD_FLOAT && TARGET_FPRS"
+ "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"
{
+ if (TARGET_E500_DOUBLE)
+ {
+ emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
+ DONE;
+ }
if (TARGET_POWERPC64)
{
rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
(clobber (match_dup 2))
(clobber (match_dup 3))])]
- "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "(TARGET_POWER2 || TARGET_POWERPC)
+ && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"
{
+ if (TARGET_E500_DOUBLE)
+ {
+ emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
+ DONE;
+ }
operands[2] = gen_reg_rtx (DImode);
operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
}")
(define_expand "floatdisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
"
{
+ rtx val = operands[1];
if (!flag_unsafe_math_optimizations)
{
rtx label = gen_label_rtx ();
- emit_insn (gen_floatdisf2_internal2 (operands[1], label));
+ val = gen_reg_rtx (DImode);
+ emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
emit_label (label);
}
- emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1]));
+ emit_insn (gen_floatdisf2_internal1 (operands[0], val));
DONE;
}")
;; by a bit that won't be lost at that stage, but is below the SFmode
;; rounding position.
(define_expand "floatdisf2_internal2"
- [(parallel [(set (match_dup 4)
- (compare:CC (and:DI (match_operand:DI 0 "" "")
- (const_int 2047))
- (const_int 0)))
- (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047)))
- (clobber (match_scratch:CC 7 ""))])
- (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53)))
- (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1)))
- (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
- (label_ref (match_operand:DI 1 "" ""))
- (pc)))
- (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2)))
- (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
- (label_ref (match_dup 1))
+ [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
+ (const_int 53)))
+ (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
+ (const_int 2047)))
+ (clobber (scratch:CC))])
+ (set (match_dup 3) (plus:DI (match_dup 3)
+ (const_int 1)))
+ (set (match_dup 0) (plus:DI (match_dup 0)
+ (const_int 2047)))
+ (set (match_dup 4) (compare:CCUNS (match_dup 3)
+ (const_int 3)))
+ (set (match_dup 0) (ior:DI (match_dup 0)
+ (match_dup 1)))
+ (parallel [(set (match_dup 0) (and:DI (match_dup 0)
+ (const_int -2048)))
+ (clobber (scratch:CC))])
+ (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
+ (label_ref (match_operand:DI 2 "" ""))
(pc)))
- (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2)))
- (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
+ (set (match_dup 0) (match_dup 1))]
+ "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
"
{
- operands[2] = gen_reg_rtx (DImode);
operands[3] = gen_reg_rtx (DImode);
- operands[4] = gen_reg_rtx (CCmode);
- operands[5] = gen_reg_rtx (CCUNSmode);
+ operands[4] = gen_reg_rtx (CCUNSmode);
}")
\f
;; Define the DImode operations that can be done in a small number
? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
: \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
}"
- [(set_attr "length" "8")])
+ [(set_attr "type" "two")
+ (set_attr "length" "8")])
(define_insn "*subdi3_noppc64"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
: \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
}"
- [(set_attr "length" "8")])
+ [(set_attr "type" "two")
+ (set_attr "length" "8")])
(define_insn "*negdi2_noppc64"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
: \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
}"
- [(set_attr "length" "8")])
+ [(set_attr "type" "two")
+ (set_attr "length" "8")])
(define_expand "mulsidi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
"@
{srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
{sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
- [(set_attr "length" "8,12")])
+ [(set_attr "type" "two,three")
+ (set_attr "length" "8,12")])
(define_insn "*ashrdisi3_noppc64"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(match_operand:DI 2 "exact_log2_cint_operand" "N")))]
"TARGET_POWERPC64"
"sradi %0,%1,%p2\;addze %0,%0"
- [(set_attr "length" "8")])
+ [(set_attr "type" "two")
+ (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")))]
"TARGET_POWERPC64"
- "sld%I2 %0,%1,%H2"
- [(set_attr "length" "8")])
+ "sld%I2 %0,%1,%H2")
(define_insn "*ashldi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
"")
(define_insn "anddi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
- (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
- (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t")))
- (clobber (match_scratch:CC 3 "=X,X,x,x,X"))]
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
+ (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
+ (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
+ (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
"TARGET_POWERPC64"
"@
and %0,%1,%2
rldic%B2 %0,%1,0,%S2
+ rlwinm %0,%1,0,%m2,%M2
andi. %0,%1,%b2
andis. %0,%1,%u2
#"
- [(set_attr "length" "4,4,4,4,8")])
+ [(set_attr "type" "*,*,*,compare,compare,*")
+ (set_attr "length" "4,4,4,4,4,8")])
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(and:DI (rotate:DI (match_dup 0)
(match_dup 6))
(match_dup 7)))]
- "
{
build_mask64_2_operands (operands[2], &operands[4]);
-}")
+})
(define_insn "*anddi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
{cal|la} %0,%2@l(%1)
{ai|addic} %0,%1,%K2")
-;; Mach-O PIC trickery.
-(define_insn "macho_high"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
- (high:SI (match_operand 1 "" "")))]
- "TARGET_MACHO && ! TARGET_64BIT"
- "{liu|lis} %0,ha16(%1)")
-
-(define_insn "macho_low"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
- (match_operand 2 "" "")))]
- "TARGET_MACHO && ! TARGET_64BIT"
- "@
- {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
- {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
;; Set up a register with a value from the GOT table
[(set_attr "type" "load")
(set_attr "length" "4")])
-(define_insn "movsi_low_st"
- [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand 2 "" "")))
- (match_operand:SI 0 "gpc_reg_operand" "r"))]
- "TARGET_MACHO && ! TARGET_64BIT"
- "{st|stw} %0,lo16(%2)(%1)"
- [(set_attr "type" "store")
- (set_attr "length" "4")])
-
-(define_insn "movdf_low"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
- (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
- (match_operand 2 "" ""))))]
- "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
- "*
-{
- switch (which_alternative)
- {
- case 0:
- return \"lfd %0,lo16(%2)(%1)\";
- case 1:
- {
- rtx operands2[4];
- operands2[0] = operands[0];
- operands2[1] = operands[1];
- operands2[2] = operands[2];
- if (TARGET_POWERPC64 && TARGET_32BIT)
- /* Note, old assemblers didn't support relocation here. */
- return \"ld %0,lo16(%2)(%1)\";
- else
- {
- operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
- output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
-#if TARGET_MACHO
- if (MACHO_DYNAMIC_NO_PIC_P)
- output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands);
- else
- /* We cannot rely on ha16(low half)==ha16(high half), alas,
- although in practice it almost always is. */
- output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
-#endif
- return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
- }
- }
- default:
- abort();
- }
-}"
- [(set_attr "type" "load")
- (set_attr "length" "4,12")])
-
-(define_insn "movdf_low_st"
- [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
- (match_operand 2 "" "")))
- (match_operand:DF 0 "gpc_reg_operand" "f"))]
- "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
- "stfd %0,lo16(%2)(%1)"
- [(set_attr "type" "store")
- (set_attr "length" "4")])
-
-(define_insn "movsf_low"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
- (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
- (match_operand 2 "" ""))))]
- "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
- "@
- lfs %0,lo16(%2)(%1)
- {l|lwz} %0,lo16(%2)(%1)"
- [(set_attr "type" "load")
- (set_attr "length" "4")])
-
-(define_insn "movsf_low_st"
- [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
- (match_operand 2 "" "")))
- (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
- "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
- "@
- stfs %0,lo16(%2)(%1)
- {st|stw} %0,lo16(%2)(%1)"
- [(set_attr "type" "store")
- (set_attr "length" "4")])
-
(define_insn "*movsi_internal1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
(match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
return \"#\";
}
}"
- [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*")
+ [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
(set_attr "length" "8,16,16,4,4,4,8,12,16")])
(define_insn "*movdf_softfloat32"
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
(match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
- "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
+ "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
&& (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))"
"*
return \"#\";
}
}"
- [(set_attr "type" "*,load,store,*,*,*")
+ [(set_attr "type" "two,load,store,*,*,*")
(set_attr "length" "8,8,8,8,12,16")])
; ld/std require word-aligned displacements -> 'Y' constraint.
; It's important to list the o->f and f->o moves before f->f because
; otherwise reload, given m->f, will try to pick f->f and reload it,
-; which doesn't make progress.
+; which doesn't make progress. Likewise r->Y must be before r->r.
(define_insn_and_split "*movtf_internal"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,rm,r")
- (match_operand:TF 1 "input_operand" "f,o,f,r,mGHF"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
+ (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
"(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
&& (gpc_reg_operand (operands[0], TFmode)
"&& reload_completed"
[(pc)]
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
- [(set_attr "length" "8,8,8,20,20")])
+ [(set_attr "length" "8,8,8,20,20,16")])
(define_expand "extenddftf2"
[(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
""
"{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
+; List r->r after r->"o<>", otherwise reload will try to reload a
+; non-offsettable address by using r->r which won't make progress.
(define_insn "*movdi_internal32"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
- (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
+ (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
"! TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"
- "*
-{
- switch (which_alternative)
- {
- default:
- abort ();
- case 0:
- case 1:
- case 2:
- return \"#\";
- case 3:
- return \"fmr %0,%1\";
- case 4:
- return \"lfd%U1%X1 %0,%1\";
- case 5:
- return \"stfd%U0%X0 %1,%0\";
- case 6:
- case 7:
- case 8:
- case 9:
- case 10:
- return \"#\";
- }
-}"
- [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")])
+ "@
+ #
+ #
+ #
+ fmr %0,%1
+ lfd%U1%X1 %0,%1
+ stfd%U0%X0 %1,%0
+ #"
+ [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
[(pc)]
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
-(define_split
- [(set (match_operand:TI 0 "gpc_reg_operand" "")
- (match_operand:TI 1 "const_double_operand" ""))]
- "TARGET_POWERPC64"
- [(set (match_dup 2) (match_dup 4))
- (set (match_dup 3) (match_dup 5))]
- "
-{
- operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
- TImode);
- operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
- TImode);
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
- {
- operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
- operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
- }
- else if (GET_CODE (operands[1]) == CONST_INT)
- {
- operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
- operands[5] = operands[1];
- }
- else
- FAIL;
-}")
-
(define_insn "*movdi_internal64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,?f,f,m,r,*h,*h")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
(match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
"TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode)
;; giving the SCRATCH mq.
(define_insn "*movti_power"
- [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
- (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
- (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
+ [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
+ (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
+ (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
"TARGET_POWER && ! TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
"*
return \"{lsi|lswi} %0,%P1,16\";
/* ... fall through ... */
case 4:
+ case 5:
return \"#\";
}
}"
- [(set_attr "type" "store,store,*,load,load")])
+ [(set_attr "type" "store,store,*,load,load,*")])
(define_insn "*movti_string"
- [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
- (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))]
+ [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
+ (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
"! TARGET_POWER && ! TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
"*
return \"{lsi|lswi} %0,%P1,16\";
/* ... fall through ... */
case 4:
+ case 5:
return \"#\";
}
}"
- [(set_attr "type" "store,store,*,load,load")])
+ [(set_attr "type" "store,store,*,load,load,*")])
(define_insn "*movti_ppc64"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=r,m,r")
- (match_operand:TI 1 "input_operand" "r,r,o"))]
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
+ (match_operand:TI 1 "input_operand" "r,r,m"))]
"TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
|| gpc_reg_operand (operands[1], TImode))"
- "@
- #
- #
- #"
+ "#"
[(set_attr "type" "*,load,store")])
(define_split
+ [(set (match_operand:TI 0 "gpc_reg_operand" "")
+ (match_operand:TI 1 "const_double_operand" ""))]
+ "TARGET_POWERPC64"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))]
+ "
+{
+ operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
+ TImode);
+ operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
+ TImode);
+ if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ {
+ operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
+ operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
+ }
+ else if (GET_CODE (operands[1]) == CONST_INT)
+ {
+ operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
+ operands[5] = operands[1];
+ }
+ else
+ FAIL;
+}")
+
+(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "input_operand" ""))]
"reload_completed
"{stsi|stswi} %2,%1,%O0"
[(set_attr "type" "store")])
\f
+(define_expand "clrmemsi"
+ [(parallel [(set (match_operand:BLK 0 "" "")
+ (const_int 0))
+ (use (match_operand:SI 1 "" ""))
+ (use (match_operand:SI 2 "" ""))])]
+ ""
+ "
+{
+ if (expand_block_clear (operands))
+ DONE;
+ else
+ FAIL;
+}")
+
;; String/block move insn.
;; Argument 0 is the destination
;; Argument 1 is the source
ldu %3,%2(%0)"
[(set_attr "type" "load_ux,load_u")])
-(define_insn "movdi_update"
- [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
- (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))
+(define_insn "movdi_<mode>_update"
+ [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
+ (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
(match_operand:DI 3 "gpc_reg_operand" "r,r"))
- (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
- (plus:DI (match_dup 1) (match_dup 2)))]
+ (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
+ (plus:P (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64 && TARGET_UPDATE"
"@
stdux %3,%0,%2
(match_dup 1))]
"operands[0] = widen_memory_access (operands[0], TFmode, 0);
operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));")
+
+;; after inserting conditional returns we can sometimes have
+;; unnecessary register moves. Unfortunately we cannot have a
+;; modeless peephole here, because some single SImode sets have early
+;; clobber outputs. Although those sets expand to multi-ppc-insn
+;; sequences, using get_attr_length here will smash the operands
+;; array. Neither is there an early_cobbler_p predicate.
+(define_peephole2
+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (match_operand:DF 1 "any_operand" ""))
+ (set (match_operand:DF 2 "gpc_reg_operand" "")
+ (match_dup 0))]
+ "peep2_reg_dead_p (2, operands[0])"
+ [(set (match_dup 2) (match_dup 1))])
+
+(define_peephole2
+ [(set (match_operand:SF 0 "gpc_reg_operand" "")
+ (match_operand:SF 1 "any_operand" ""))
+ (set (match_operand:SF 2 "gpc_reg_operand" "")
+ (match_dup 0))]
+ "peep2_reg_dead_p (2, operands[0])"
+ [(set (match_dup 2) (match_dup 1))])
+
\f
;; TLS support.
neg_op0 = GEN_INT (- INTVAL (operands[1]));
if (TARGET_UPDATE)
- emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
+ emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
(stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
else
"{l|lwz} %0,%2-%3(%1)"
[(set_attr "type" "load")])
-(define_insn "load_macho_picbase"
- [(set (match_operand:SI 0 "register_operand" "=l")
- (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
- UNSPEC_LD_MPIC))]
- "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
- "bcl 20,31,%1\\n%1:"
- [(set_attr "type" "branch")
- (set_attr "length" "4")])
-
-(define_insn "macho_correct_pic"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
- (match_operand:SI 3 "immediate_operand" "s")]
- UNSPEC_MPIC_CORRECT)))]
- "DEFAULT_ABI == ABI_DARWIN"
- "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
- [(set_attr "length" "8")])
;; If the TOC is shared over a translation unit, as happens with all
;; the kinds of PIC that we support, we need to restore the TOC
(define_expand "cmpdf"
[(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
(match_operand:DF 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_FPRS"
+ "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"
{
rs6000_compare_op0 = operands[0];
(define_expand "bunordered"
[(use (match_operand 0 "" ""))]
- ""
+ "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
"{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
(define_expand "bordered"
[(use (match_operand 0 "" ""))]
- ""
+ "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
"{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
(define_expand "buneq"
""
"
{
- if (! rs6000_compare_fp_p
- && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
+ if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
FAIL;
rs6000_emit_sCOND (GE, operands[0]);
""
"
{
- if (! rs6000_compare_fp_p
- && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
+ if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
FAIL;
rs6000_emit_sCOND (GT, operands[0]);
""
"
{
- if (! rs6000_compare_fp_p
- && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
+ if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
FAIL;
rs6000_emit_sCOND (LE, operands[0]);
""
"
{
- if (! rs6000_compare_fp_p
- && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
+ if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
FAIL;
rs6000_emit_sCOND (LT, operands[0]);
(const_string "mfcrf")
]
(const_string "mfcr")))
- (set_attr "length" "12")])
+ (set_attr "length" "8")])
;; Same as above, but get the GT bit.
-(define_insn "move_from_CR_gt_bit"
+(define_insn "move_from_CR_eq_bit"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
+ (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_EQ))]
"TARGET_E500"
"mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1"
[(set_attr "type" "mfcr")
- (set_attr "length" "12")])
+ (set_attr "length" "8")])
;; Same as above, but get the OV/ORDERED bit.
(define_insn "move_from_CR_ov_bit"
"TARGET_ISEL"
"mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
[(set_attr "type" "mfcr")
- (set_attr "length" "12")])
+ (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(const_string "mfcrf")
]
(const_string "mfcr")))
- (set_attr "length" "12")])
+ (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
#"
[(set_attr "type" "delayed_compare")
- (set_attr "length" "12,16")])
+ (set_attr "length" "8,16")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
(const_string "mfcrf")
]
(const_string "mfcr")))
- (set_attr "length" "12")])
+ (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
}"
[(set_attr "type" "delayed_compare")
- (set_attr "length" "12,16")])
+ (set_attr "length" "8,16")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
"REGNO (operands[2]) != REGNO (operands[5])"
"mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
[(set_attr "type" "mfcr")
- (set_attr "length" "20")])
+ (set_attr "length" "12")])
(define_peephole
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
"TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
"mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
[(set_attr "type" "mfcr")
- (set_attr "length" "20")])
+ (set_attr "length" "12")])
;; There are some scc insns that can be done directly, without a compare.
;; These are faster because they don't involve the communications between
{xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
{xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
{sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
- [(set_attr "length" "12,8,12,12,12")])
+ [(set_attr "type" "three,two,three,three,three")
+ (set_attr "length" "12,8,12,12,12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
- [(set_attr "length" "12,8,12,12,12")])
+ [(set_attr "type" "three,two,three,three,three")
+ (set_attr "length" "12,8,12,12,12")])
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
{xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
{xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
{sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
- [(set_attr "length" "12,8,12,12,12")])
+ [(set_attr "type" "three,two,three,three,three")
+ (set_attr "length" "12,8,12,12,12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
{xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
{xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
{sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
- [(set_attr "length" "12,8,12,12,12")])
+ [(set_attr "type" "three,two,three,three,three")
+ (set_attr "length" "12,8,12,12,12")])
;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
;; since it nabs/sr is just as fast.
(clobber (match_scratch:SI 2 "=&r"))]
"! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
"{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
- [(set_attr "length" "8")])
+ [(set_attr "type" "two")
+ (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(clobber (match_scratch:DI 2 "=&r"))]
"TARGET_64BIT"
"addic %2,%1,-1\;subfe %0,%2,%1"
- [(set_attr "length" "8")])
+ [(set_attr "type" "two")
+ (set_attr "length" "8")])
;; This is what (plus (ne X (const_int 0)) Y) looks like.
(define_insn ""
(clobber (match_scratch:SI 3 "=&r"))]
"TARGET_32BIT"
"{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
- [(set_attr "length" "8")])
+ [(set_attr "type" "two")
+ (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(clobber (match_scratch:DI 3 "=&r"))]
"TARGET_64BIT"
"addic %3,%1,-1\;addze %0,%2"
- [(set_attr "length" "8")])
+ [(set_attr "type" "two")
+ (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(match_operand:SI 2 "reg_or_short_operand" "rI")))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
- [(set_attr "length" "12")])
+ [(set_attr "type" "three")
+ (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(match_operand:DI 2 "reg_or_short_operand" "rI")))]
"TARGET_64BIT"
"subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
- [(set_attr "length" "12")])
+ [(set_attr "type" "three")
+ (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(match_operand:SI 3 "gpc_reg_operand" "r")))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
- [(set_attr "length" "8")])
+ [(set_attr "type" "two")
+ (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
- [(set_attr "length" "12")])
+ [(set_attr "type" "three")
+ (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
(match_operand:SI 3 "gpc_reg_operand" "r")))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
- [(set_attr "length" "12")])
+ [(set_attr "type" "three")
+ (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
"doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")])
-(define_insn ""
+(define_insn_and_split ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
"TARGET_32BIT"
- "@
- {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
- {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
- [(set_attr "length" "12")])
+ "#"
+ "TARGET_32BIT"
+ [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
+ (set (match_dup 0) (neg:SI (match_dup 0)))]
+ "")
+
+(define_insn_and_split ""
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+ (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
+ "TARGET_64BIT"
+ "#"
+ "TARGET_64BIT"
+ [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
+ (set (match_dup 0) (neg:DI (match_dup 0)))]
+ "")
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
(const_int 0)))]
"")
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
+(define_insn_and_split ""
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
(match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
"TARGET_32BIT"
- "@
- {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
- {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
- [(set_attr "length" "12")])
+ "#"
+ "TARGET_32BIT"
+ [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
+ (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
+ "")
+
+(define_insn_and_split ""
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+ (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
+ (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))]
+ "TARGET_64BIT"
+ "#"
+ "TARGET_64BIT"
+ [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
+ (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
+ "")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
"TARGET_32BIT"
"@
- {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
- {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
+ {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
+ {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
#
#"
[(set_attr "type" "compare")
(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"TARGET_32BIT"
"@
- {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
- {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
+ {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
+ {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
#
#"
[(set_attr "type" "compare")
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
- [(set_attr "length" "8")])
+ [(set_attr "type" "two")
+ (set_attr "length" "8")])
+
+(define_insn ""
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+ (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))]
+ "TARGET_64BIT"
+ "@
+ {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
+ {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
+ [(set_attr "type" "two")
+ (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
"@
{sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
{ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
- [(set_attr "length" "12")])
+ [(set_attr "type" "three")
+ (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
"@
subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
- [(set_attr "length" "12")])
+ [(set_attr "type" "three")
+ (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
"@
{sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
{ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
- [(set_attr "length" "8")])
+ [(set_attr "type" "two")
+ (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
{sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
- [(set_attr "length" "12")])
+ [(set_attr "type" "three")
+ (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
- [(set_attr "length" "12")])
+ [(set_attr "type" "three")
+ (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
(const_int 0)))]
"TARGET_32BIT"
"{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
- [(set_attr "length" "12")])
+ [(set_attr "type" "three")
+ (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(const_int 0)))]
"TARGET_64BIT"
"subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
- [(set_attr "length" "12")])
+ [(set_attr "type" "three")
+ (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
(match_operand:SI 2 "gpc_reg_operand" "r")))]
"TARGET_32BIT"
"{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
- [(set_attr "length" "12")])
+ [(set_attr "type" "three")
+ (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
(match_operand:DI 2 "gpc_reg_operand" "r")))]
"TARGET_64BIT"
"addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
- [(set_attr "length" "12")])
+ [(set_attr "type" "three")
+ (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(const_int 0))))]
"TARGET_32BIT"
"{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
- [(set_attr "length" "12")])
+ [(set_attr "type" "three")
+ (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(const_int 0))))]
"TARGET_64BIT"
"subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
- [(set_attr "length" "12")])
+ [(set_attr "type" "three")
+ (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
"doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")])
-(define_insn ""
+(define_insn_and_split ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_short_operand" "rI")))]
+ (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "reg_or_short_operand" "rI")))]
"TARGET_32BIT"
- "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
- [(set_attr "length" "12")])
+ "#"
+ "TARGET_32BIT"
+ [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
+ (set (match_dup 0) (neg:SI (match_dup 0)))]
+ "")
-(define_insn ""
+(define_insn_and_split ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "reg_or_short_operand" "rI")))]
+ (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "reg_or_short_operand" "rI")))]
"TARGET_64BIT"
- "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
- [(set_attr "length" "12")])
+ "#"
+ "TARGET_64BIT"
+ [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
+ (set (match_dup 0) (neg:DI (match_dup 0)))]
+ "")
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(const_int 0)))]
"")
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
- (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
- (match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
+(define_insn_and_split ""
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "reg_or_short_operand" "rI"))
+ (match_operand:SI 3 "reg_or_short_operand" "rI")))]
"TARGET_32BIT"
- "@
- {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
- {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
- [(set_attr "length" "8,12")])
+ "#"
+ "TARGET_32BIT"
+ [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
+ (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
+ "")
-(define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
- (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
- (match_operand:DI 3 "reg_or_short_operand" "r,rI")))]
+(define_insn_and_split ""
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "reg_or_short_operand" "rI"))
+ (match_operand:DI 3 "reg_or_short_operand" "rI")))]
"TARGET_64BIT"
- "@
- addic %0,%1,%k2\;addze %0,%3
- subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3"
- [(set_attr "length" "8,12")])
+ "#"
+ "TARGET_64BIT"
+ [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
+ (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
+ "")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
"TARGET_32BIT"
"@
{ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
- {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
+ {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
#
#"
[(set_attr "type" "compare")
"TARGET_64BIT"
"@
addic %4,%1,%k2\;addze. %4,%3
- subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
+ subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3
#
#"
[(set_attr "type" "compare")
"TARGET_32BIT"
"@
{ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
- {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
+ {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
#
#"
[(set_attr "type" "compare")
"TARGET_64BIT"
"@
addic %0,%1,%k2\;addze. %0,%3
- subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3
+ subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3
#
#"
[(set_attr "type" "compare")
(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
- [(set_attr "length" "8")])
+ [(set_attr "type" "two")
+ (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(match_operand:DI 2 "reg_or_short_operand" "rI"))))]
"TARGET_64BIT"
"subf%I2c %0,%1,%2\;subfe %0,%0,%0"
- [(set_attr "length" "8")])
+ [(set_attr "type" "two")
+ (set_attr "length" "8")])
\f
;; Define both directions of branch and return. If we need a reload
;; register, we'd rather use CR0 since it is much easier to copy a
"cc_reg_operand" "0,y")
(const_int 0)])])
(const_int 1)))]
- "!(TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS)"
+ ""
"cr%q1 %E0,%j2,%j4"
[(set_attr "type" "cr_logical,delayed_cr")])
"{stm|stmw} %2,%1")
(define_insn "*save_fpregs_si"
- [(match_parallel 0 "any_operand"
+ [(match_parallel 0 "any_parallel_operand"
[(clobber (match_operand:SI 1 "register_operand" "=l"))
(use (match_operand:SI 2 "call_operand" "s"))
(set (match_operand:DF 3 "memory_operand" "=m")
(set_attr "length" "4")])
(define_insn "*save_fpregs_di"
- [(match_parallel 0 "any_operand"
+ [(match_parallel 0 "any_parallel_operand"
[(clobber (match_operand:DI 1 "register_operand" "=l"))
(use (match_operand:DI 2 "call_operand" "s"))
(set (match_operand:DF 3 "memory_operand" "=m")
[(set_attr "type" "jmpreg")])
; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
-; stuff was in GCC. Oh, and "any_operand" is a bit flexible...
+; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
(define_insn "*return_and_restore_fpregs_si"
- [(match_parallel 0 "any_operand"
+ [(match_parallel 0 "any_parallel_operand"
[(return)
(use (match_operand:SI 1 "register_operand" "l"))
(use (match_operand:SI 2 "call_operand" "s"))
"b %z2")
(define_insn "*return_and_restore_fpregs_di"
- [(match_parallel 0 "any_operand"
+ [(match_parallel 0 "any_parallel_operand"
[(return)
(use (match_operand:DI 1 "register_operand" "l"))
(use (match_operand:DI 2 "call_operand" "s"))
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