;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
-;; Copyright (C) 1990, 91, 92, 93, 94, 1995 Free Software Foundation, Inc.
+;; Copyright (C) 1990, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
;; This file is part of GNU CC.
;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
\f
;; Define an insn type attribute. This is used in function unit delay
;; computations.
-(define_attr "type" "integer,load,fpload,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
+(define_attr "type" "integer,load,store,fpload,fpstore,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
(const_string "integer"))
;; Length (in bytes).
;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in rs6000.h.
-(define_attr "cpu" "rios1,rios2,ppc601,ppc603,ppc604,ppc620"
+(define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"
(const (symbol_ref "rs6000_cpu_attr")))
; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
-; Load/Store Unit -- POWER/2 and pure PowerPC only
+; Load/Store Unit -- pure PowerPC only
; (POWER and 601 use Integer Unit)
(define_function_unit "lsu" 1 0
(and (eq_attr "type" "load")
- (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620"))
- 2 0)
+ (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc620"))
+ 2 1)
+
+(define_function_unit "lsu" 1 0
+ (and (eq_attr "type" "store,fpstore")
+ (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc620"))
+ 1 1)
+
+(define_function_unit "lsu" 1 0
+ (and (eq_attr "type" "fpload")
+ (eq_attr "cpu" "mpccore,ppc603"))
+ 2 1)
(define_function_unit "lsu" 1 0
(and (eq_attr "type" "fpload")
- (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620"))
- 2 0)
+ (eq_attr "cpu" "ppc604,ppc620"))
+ 3 1)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "load")
+ (eq_attr "cpu" "rios1,ppc403,ppc601"))
+ 2 1)
+
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "store,fpstore")
+ (eq_attr "cpu" "rios1,ppc403,ppc601"))
+ 1 1)
+
+(define_function_unit "fpu" 1 0
+ (and (eq_attr "type" "fpstore")
(eq_attr "cpu" "rios1,ppc601"))
- 2 0)
+ 0 1)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "fpload")
- (eq_attr "cpu" "rios1,ppc601"))
- 3 0)
+ (eq_attr "cpu" "rios1"))
+ 2 1)
+
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "fpload")
+ (eq_attr "cpu" "ppc601"))
+ 3 1)
+
+(define_function_unit "iu2" 2 0
+ (and (eq_attr "type" "load,fpload")
+ (eq_attr "cpu" "rios2"))
+ 2 1)
+
+(define_function_unit "iu2" 2 0
+ (and (eq_attr "type" "store,fpstore")
+ (eq_attr "cpu" "rios2"))
+ 1 1)
; Integer Unit (RIOS1, PPC601, PPC603)
-; Trivial operations take one cycle which need not be listed here.
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "integer")
+ (eq_attr "cpu" "rios1,mpccore,ppc403,ppc601,ppc603"))
+ 1 1)
+
(define_function_unit "iu" 1 0
(and (eq_attr "type" "imul")
- (eq_attr "cpu" "rios1"))
- 3 3)
+ (eq_attr "cpu" "ppc403"))
+ 4 4)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "imul")
- (eq_attr "cpu" "ppc601,ppc603"))
+ (eq_attr "cpu" "rios1,ppc601,ppc603"))
5 5)
(define_function_unit "iu" 1 0
(define_function_unit "iu" 1 0
(and (eq_attr "type" "idiv")
+ (eq_attr "cpu" "ppc403"))
+ 33 33)
+
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "idiv")
(eq_attr "cpu" "ppc601"))
36 36)
; RIOS2 has two integer units: a primary one which can perform all
; operations and a secondary one which is fed in lock step with the first
-; and can perform "simple" integer operations.
+; and can perform "simple" integer operations.
+; To catch this we define a 'dummy' imuldiv-unit that is also needed
+; for the complex insns.
(define_function_unit "iu2" 2 0
(and (eq_attr "type" "integer")
(eq_attr "cpu" "rios2"))
- 1 0
- [(eq_attr "type" "imul,idiv")])
+ 1 1)
+
+(define_function_unit "iu2" 2 0
+ (and (eq_attr "type" "imul")
+ (eq_attr "cpu" "rios2"))
+ 2 2)
+
+(define_function_unit "iu2" 2 0
+ (and (eq_attr "type" "idiv")
+ (eq_attr "cpu" "rios2"))
+ 13 13)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul")
(eq_attr "cpu" "rios2"))
- 2 2
- [(eq_attr "type" "integer")])
+ 2 2)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "rios2"))
- 13 13
- [(eq_attr "type" "integer")])
+ 13 13)
+
+; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
+; Divide latency varies greatly from 2-11, use 6 as average
+(define_function_unit "imuldiv" 1 0
+ (and (eq_attr "type" "imul")
+ (eq_attr "cpu" "mpccore"))
+ 2 1)
+
+(define_function_unit "imuldiv" 1 0
+ (and (eq_attr "type" "idiv")
+ (eq_attr "cpu" "mpccore"))
+ 6 6)
-; PPC604 has three integer units: one primary and two secondary.
-(define_function_unit "iu3" 3 0
+; PPC604 has two units that perform integer operations
+; and one unit for divide/multiply operations (and move
+; from/to spr).
+(define_function_unit "iu2" 2 0
(and (eq_attr "type" "integer")
(eq_attr "cpu" "ppc604,ppc620"))
- 1 0
- [(eq_attr "type" "imul,idiv")])
+ 1 1)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul")
(eq_attr "cpu" "ppc604,ppc620"))
- 4 2
- [(eq_attr "type" "integer")])
+ 4 2)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "ppc604,ppc620"))
- 20 19
- [(eq_attr "type" "integer")])
+ 20 19)
-; Branch Processing Unit
-(define_function_unit "bpu" 1 0
- (eq_attr "type" "compare")
- 4 0)
+; compare is done on integer unit, but feeds insns which
+; execute on the branch unit.
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "compare")
+ (eq_attr "cpu" "rios1"))
+ 4 1)
-(define_function_unit "bpu" 1 0
- (eq_attr "type" "delayed_compare")
- 5 0)
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "delayed_compare")
+ (eq_attr "cpu" "rios1"))
+ 5 1)
-(define_function_unit "bpu" 1 0
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "compare,delayed_compare")
+ (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"))
+ 3 1)
+
+(define_function_unit "iu2" 2 0
+ (and (eq_attr "type" "compare,delayed_compare")
+ (eq_attr "cpu" "rios2"))
+ 3 1)
+
+(define_function_unit "iu2" 2 0
+ (and (eq_attr "type" "compare,delayed_compare")
+ (eq_attr "cpu" "ppc604,ppc620"))
+ 1 1)
+
+; fp compare uses fp unit
+(define_function_unit "fpu" 1 0
(and (eq_attr "type" "fpcompare")
- (eq_attr "cpu" "rios1,rios2"))
- 8 0)
+ (eq_attr "cpu" "rios1"))
+ 9 1)
-(define_function_unit "bpu" 1 0
+; rios1 and rios2 have different fpcompare delays
+(define_function_unit "fpu2" 2 0
+ (and (eq_attr "type" "fpcompare")
+ (eq_attr "cpu" "rios2"))
+ 5 1)
+
+; on ppc601 and ppc603, fpcompare takes also 2 cycles from
+; the integer unit
+; here we do not define delays, just occupy the unit. The dependencies
+; will be assigned by the fpcompare definition in the fpu.
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "fpcompare")
+ (eq_attr "cpu" "ppc601,ppc603"))
+ 0 2)
+
+; fp compare uses fp unit
+(define_function_unit "fpu" 1 0
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
- 4 0)
+ 5 1)
+
+(define_function_unit "fpu" 1 0
+ (and (eq_attr "type" "fpcompare")
+ (eq_attr "cpu" "mpccore"))
+ 1 1)
(define_function_unit "bpu" 1 0
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "rios1,rios2"))
- 5 0)
+ 5 1)
(define_function_unit "bpu" 1 0
(and (eq_attr "type" "mtjmpr")
- (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
- 4 0)
+ (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"))
+ 4 1)
+
+; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
+(define_function_unit "bpu" 1 0
+ (eq_attr "type" "jmpreg")
+ 1 1)
+
+(define_function_unit "bpu" 1 0
+ (eq_attr "type" "branch")
+ 1 1)
-; Floating Point Unit (RIOS1, PPC601, PPC603, PPC604).
+; Floating Point Unit
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "fp,dmul")
(eq_attr "cpu" "rios1"))
- 2 0)
+ 2 1)
+
+(define_function_unit "fpu" 1 0
+ (and (eq_attr "type" "fp")
+ (eq_attr "cpu" "mpccore"))
+ 4 4)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "fp")
(eq_attr "cpu" "ppc601"))
- 4 0)
+ 4 1)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "fp")
(eq_attr "cpu" "ppc603,ppc604,ppc620"))
- 3 0)
+ 3 1)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "dmul")
- (eq_attr "cpu" "ppc601"))
+ (eq_attr "cpu" "mpccore"))
5 5)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "dmul")
+ (eq_attr "cpu" "ppc601"))
+ 5 2)
+
+; is this true?
+(define_function_unit "fpu" 1 0
+ (and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppc603"))
4 2)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppc604,ppc620"))
- 3 0)
+ 3 1)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "sdiv,ddiv")
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "sdiv")
+ (eq_attr "cpu" "mpccore"))
+ 10 10)
+
+(define_function_unit "fpu" 1 0
+ (and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc603,ppc604,ppc620"))
18 18)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "ddiv")
+ (eq_attr "cpu" "mpccore"))
+ 17 17)
+
+(define_function_unit "fpu" 1 0
+ (and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc601,ppc604,ppc620"))
31 31)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "fp")
(eq_attr "cpu" "rios2"))
- 2 0)
+ 2 1)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "rios2"))
- 2 0)
+ 2 1)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "sdiv,ddiv")
(and (eq_attr "type" "ssqrt,dsqrt")
(eq_attr "cpu" "rios2"))
26 26)
+
\f
;; Start with fixed-point load and store insns. Here we put only the more
;; complex forms. Basic data transfer is done later.
{cax|add} %0,%1,%2
{cal %0,%2(%1)|addi %0,%1,%2}
{ai|addic} %0,%1,%2
- {cau|addis} %0,%1,%u2")
+ {cau|addis} %0,%1,%v2")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
{cax.|add.} %3,%1,%2
{ai.|addic.} %3,%1,%2"
[(set_attr "type" "compare")])
-
+
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
{cax.|add.} %0,%1,%2
{ai.|addic.} %0,%1,%2"
[(set_attr "type" "compare")])
-
+
;; Split an add that we can't do in one insn into two insns, each of which
;; does one 16-bit part. This is used by combine. Note that the low-order
;; add should be last in case the result gets used in an address.
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
"
{
- int low = INTVAL (operands[2]) & 0xffff;
- int high = (unsigned) INTVAL (operands[2]) >> 16;
+ HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
+ HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
if (low & 0x8000)
- high++, low |= 0xffff0000;
+ high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
- operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16);
- operands[4] = gen_rtx (CONST_INT, VOIDmode, low);
+ operands[3] = GEN_INT (high);
+ operands[4] = GEN_INT (low);
}")
(define_insn "one_cmplsi2"
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(not:SI (match_dup 1)))]
""
- "nor. %0,%2,%1"
+ "nor. %0,%1,%1"
[(set_attr "type" "compare")])
(define_insn ""
;; We don't need abs with condition code because such comparisons should
;; never be done.
-(define_insn "abssi2"
+(define_expand "abssi2"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
+ ""
+ "
+{
+ if (!TARGET_POWER)
+ {
+ emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
+ DONE;
+ }
+}")
+
+(define_insn "abssi2_power"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
"TARGET_POWER"
"abs %0,%1")
+(define_insn "abssi2_nopower"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
+ (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
+ (clobber (match_scratch:SI 2 "=&r,&r"))]
+ "!TARGET_POWER"
+ "*
+{
+ return (TARGET_POWERPC)
+ ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\"
+ : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\";
+}"
+ [(set_attr "length" "12")])
+
+(define_split
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
+ (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
+ (clobber (match_scratch:SI 2 "=&r,&r"))]
+ "!TARGET_POWER && reload_completed"
+ [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
+ (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
+ (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
+ "")
+
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
"TARGET_POWER"
"nabs %0,%1")
+(define_insn ""
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
+ (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
+ (clobber (match_scratch:SI 2 "=&r,&r"))]
+ "!TARGET_POWER"
+ "*
+{
+ return (TARGET_POWERPC)
+ ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\"
+ : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\";
+}"
+ [(set_attr "length" "12")])
+
+(define_split
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
+ (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
+ (clobber (match_scratch:SI 2 "=&r,&r"))]
+ "!TARGET_POWER && reload_completed"
+ [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
+ (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
+ (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
+ "")
+
(define_insn "negsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
(match_operand:SI 2 "reg_or_short_operand" "r,I")))]
"! TARGET_POWER"
"@
- mullw %0,%1,%2
- mulli %0,%1,%2"
+ {muls|mullw} %0,%1,%2
+ {muli|mulli} %0,%1,%2"
[(set_attr "type" "imul")])
(define_insn ""
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
"! TARGET_POWER"
- "mullw. %3,%1,%2"
+ "{muls.|mullw.} %3,%1,%2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(mult:SI (match_dup 1) (match_dup 2)))]
"! TARGET_POWER"
- "mullw. %0,%1,%2"
+ "{muls.|mullw.} %0,%1,%2"
[(set_attr "type" "delayed_compare")])
;; Operand 1 is divided by operand 2; quotient goes to operand
if (GET_CODE (operands[2]) == CONST_INT
&& exact_log2 (INTVAL (operands[2])) >= 0)
;
- else if (TARGET_POWER && ! TARGET_POWERPC)
+ else if (TARGET_POWERPC)
+ operands[2] = force_reg (SImode, operands[2]);
+ else if (TARGET_POWER)
FAIL;
else
- operands[2] = force_reg (SImode, operands[2]);
-
- if (! TARGET_POWER && ! TARGET_POWERPC)
{
emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
;; AIX architecture-independent common-mode multiply (DImode),
;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
-;; R4; results in R3 and somtimes R4; link register always clobbered by bla
+;; R4; results in R3 and sometimes R4; link register always clobbered by bla
;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
;; assumed unused if generating common-mode, so ignore.
(define_insn "mulh_call"
(const_int 32))))
(clobber (match_scratch:SI 0 "=l"))]
"! TARGET_POWER && ! TARGET_POWERPC"
- "bla __mulh")
+ "bla __mulh"
+ [(set_attr "type" "imul")])
(define_insn "mull_call"
[(set (reg:DI 3)
(clobber (match_scratch:SI 0 "=l"))
(clobber (reg:SI 0))]
"! TARGET_POWER && ! TARGET_POWERPC"
- "bla __mull")
+ "bla __mull"
+ [(set_attr "type" "imul")])
(define_insn "divss_call"
[(set (reg:SI 3)
(clobber (match_scratch:SI 0 "=l"))
(clobber (reg:SI 0))]
"! TARGET_POWER && ! TARGET_POWERPC"
- "bla __divss")
+ "bla __divss"
+ [(set_attr "type" "idiv")])
(define_insn "divus_call"
[(set (reg:SI 3)
(set (reg:SI 4)
(umod:SI (reg:SI 3) (reg:SI 4)))
(clobber (match_scratch:SI 0 "=l"))
- (clobber (reg:SI 0))]
+ (clobber (reg:SI 0))
+ (clobber (match_scratch:CC 1 "=x"))
+ (clobber (reg:CC 69))]
"! TARGET_POWER && ! TARGET_POWERPC"
- "bla __divus")
+ "bla __divus"
+ [(set_attr "type" "idiv")])
(define_insn "quoss_call"
[(set (reg:SI 3)
(div:SI (reg:SI 3) (reg:SI 4)))
(clobber (match_scratch:SI 0 "=l"))]
"! TARGET_POWER && ! TARGET_POWERPC"
- "bla __quoss")
+ "bla __quoss"
+ [(set_attr "type" "idiv")])
(define_insn "quous_call"
[(set (reg:SI 3)
(udiv:SI (reg:SI 3) (reg:SI 4)))
(clobber (match_scratch:SI 0 "=l"))
- (clobber (reg:SI 0))]
+ (clobber (reg:SI 0))
+ (clobber (match_scratch:CC 1 "=x"))
+ (clobber (reg:CC 69))]
"! TARGET_POWER && ! TARGET_POWERPC"
- "bla __quous")
+ "bla __quous"
+ [(set_attr "type" "idiv")])
\f
(define_insn "andsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
\f
;; Rotate and shift insns, in all their variants. These support shifts,
;; field inserts and extracts, and various combinations thereof.
-(define_insn "insv"
+(define_expand "insv"
+ [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
+ (match_operand:SI 1 "const_int_operand" "i")
+ (match_operand:SI 2 "const_int_operand" "i"))
+ (match_operand:SI 3 "gpc_reg_operand" "r"))]
+ ""
+ "
+{
+ /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
+ the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
+ compiler if the address of the structure is taken later. */
+ if (GET_CODE (operands[0]) == SUBREG
+ && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
+ FAIL;
+}")
+
+(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "const_int_operand" "i"))
operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size);
operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
- return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
+ return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
+}")
+
+(define_insn ""
+ [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
+ (match_operand:SI 1 "const_int_operand" "i")
+ (match_operand:SI 2 "const_int_operand" "i"))
+ (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
+ (match_operand:SI 4 "const_int_operand" "i")))]
+ ""
+ "*
+{
+ int shift = INTVAL (operands[4]) & 31;
+ int start = INTVAL (operands[2]) & 31;
+ int size = INTVAL (operands[1]) & 31;
+
+ operands[4] = gen_rtx (CONST_INT, VOIDmode, shift - start - size);
+ operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
+ return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
+}")
+
+(define_insn ""
+ [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
+ (match_operand:SI 1 "const_int_operand" "i")
+ (match_operand:SI 2 "const_int_operand" "i"))
+ (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
+ (match_operand:SI 4 "const_int_operand" "i")))]
+ ""
+ "*
+{
+ int shift = INTVAL (operands[4]) & 31;
+ int start = INTVAL (operands[2]) & 31;
+ int size = INTVAL (operands[1]) & 31;
+
+ operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - shift - start - size);
+ operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
+ return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
+}")
+
+(define_insn ""
+ [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
+ (match_operand:SI 1 "const_int_operand" "i")
+ (match_operand:SI 2 "const_int_operand" "i"))
+ (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
+ (match_operand:SI 4 "const_int_operand" "i")))]
+ ""
+ "*
+{
+ int shift = INTVAL (operands[4]) & 31;
+ int start = INTVAL (operands[2]) & 31;
+ int size = INTVAL (operands[1]) & 31;
+
+ operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - shift - start - size);
+ operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
+ return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
}")
-(define_insn "extzv"
+(define_insn ""
+ [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
+ (match_operand:SI 1 "const_int_operand" "i")
+ (match_operand:SI 2 "const_int_operand" "i"))
+ (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
+ (match_operand:SI 4 "const_int_operand" "i")
+ (match_operand:SI 5 "const_int_operand" "i")))]
+ "INTVAL (operands[4]) >= INTVAL (operands[1])"
+ "*
+{
+ int extract_start = INTVAL (operands[5]) & 31;
+ int extract_size = INTVAL (operands[4]) & 31;
+ int insert_start = INTVAL (operands[2]) & 31;
+ int insert_size = INTVAL (operands[1]) & 31;
+
+/* Align extract field with insert field */
+ operands[5] = gen_rtx (CONST_INT, VOIDmode,
+ extract_start + extract_size - insert_start - insert_size);
+ operands[1] = gen_rtx (CONST_INT, VOIDmode, insert_start + insert_size - 1);
+ return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
+}")
+
+(define_insn ""
+ [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
+ (match_operand:DI 1 "const_int_operand" "i")
+ (match_operand:DI 2 "const_int_operand" "i"))
+ (match_operand:DI 3 "gpc_reg_operand" "r"))]
+ "TARGET_POWERPC64"
+ "*
+{
+ int start = INTVAL (operands[2]) & 63;
+ int size = INTVAL (operands[1]) & 63;
+
+ operands[2] = gen_rtx (CONST_INT, VOIDmode, 64 - start - size);
+ return \"rldimi %0,%3,%H2,%H1\";
+}")
+
+(define_expand "extzv"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "const_int_operand" "i")
+ (match_operand:SI 3 "const_int_operand" "i")))]
+ ""
+ "
+{
+ /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
+ the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
+ compiler if the address of the structure is taken later. */
+ if (GET_CODE (operands[0]) == SUBREG
+ && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
+ FAIL;
+}")
+
+(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")
else
return \"{andil.|andi.} %4,%1,%3\";
}
-
+
if (start + size >= 32)
operands[3] = const0_rtx;
else
operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1);
return \"{andil.|andi.} %0,%1,%3\";
}
-
+
if (start + size >= 32)
operands[3] = const0_rtx;
else
}"
[(set_attr "type" "delayed_compare")])
-(define_insn "rotlsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
- ""
- "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
+(define_insn ""
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "const_int_operand" "i")
+ (match_operand:DI 3 "const_int_operand" "i")))]
+ "TARGET_POWERPC64"
+ "*
+{
+ int start = INTVAL (operands[3]) & 63;
+ int size = INTVAL (operands[2]) & 63;
+
+ if (start + size >= 64)
+ operands[3] = const0_rtx;
+ else
+ operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
+ operands[2] = gen_rtx (CONST_INT, VOIDmode, 64 - size);
+ return \"rldicl %0,%1,%3,%2\";
+}")
(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_cint_operand" "ri"))
+ [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
+ (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "const_int_operand" "i")
+ (match_operand:DI 3 "const_int_operand" "i"))
(const_int 0)))
- (clobber (match_scratch:SI 3 "=r"))]
- ""
- "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff"
- [(set_attr "type" "delayed_compare")])
+ (clobber (match_scratch:DI 4 "=r"))]
+ "TARGET_POWERPC64"
+ "*
+{
+ int start = INTVAL (operands[3]) & 63;
+ int size = INTVAL (operands[2]) & 63;
+
+ if (start + size >= 64)
+ operands[3] = const0_rtx;
+ else
+ operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
+ operands[2] = gen_rtx (CONST_INT, VOIDmode, 64 - size);
+ return \"rldicl. %4,%1,%3,%2\";
+}")
(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
+ (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "const_int_operand" "i")
+ (match_operand:DI 3 "const_int_operand" "i"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
+ "TARGET_POWERPC64"
+ "*
+{
+ int start = INTVAL (operands[3]) & 63;
+ int size = INTVAL (operands[2]) & 63;
+
+ if (start + size >= 64)
+ operands[3] = const0_rtx;
+ else
+ operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
+ operands[2] = gen_rtx (CONST_INT, VOIDmode, 64 - size);
+ return \"rldicl. %0,%1,%3,%2\";
+}")
+
+(define_insn "rotlsi3"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
+ ""
+ "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
+
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+ (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "reg_or_cint_operand" "ri"))
+ (const_int 0)))
+ (clobber (match_scratch:SI 3 "=r"))]
+ ""
+ "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff"
+ [(set_attr "type" "delayed_compare")])
+
+(define_insn ""
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")))]
"! TARGET_POWER"
- "slw%I2 %0,%1,%h2"
+ "{sl|slw}%I2 %0,%1,%h2"
[(set_attr "length" "8")])
(define_insn ""
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
"! TARGET_POWER"
- "slw%I2. %3,%1,%h2"
+ "{sl|slw}%I2. %3,%1,%h2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ashift:SI (match_dup 1) (match_dup 2)))]
"! TARGET_POWER"
- "slw%I2. %0,%1,%h2"
+ "{sl|slw}%I2. %0,%1,%h2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "mask_operand" "L")))]
"includes_lshift_p (operands[2], operands[3])"
- "{rlinm|rlwinm} %0,%h1,%h2,%m3,%M3")
+ "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(const_int 0)))
(clobber (match_scratch:SI 4 "=r"))]
"includes_lshift_p (operands[2], operands[3])"
- "{rlinm.|rlwinm.} %4,%h1,%h2,%m3,%M3"
+ "{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3"
[(set_attr "type" "delayed_compare")])
(define_insn ""
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"includes_lshift_p (operands[2], operands[3])"
- "{rlinm.|rlwinm.} %0,%h1,%h2,%m3,%M3"
+ "{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3"
[(set_attr "type" "delayed_compare")])
;; The AIX assembler mis-handles "sri x,x,0", so write that case as
}")
(define_insn "lshrsi3_power"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
- (clobber (match_scratch:SI 3 "=q,X"))]
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
+ (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
+ (clobber (match_scratch:SI 3 "=q,X,X"))]
"TARGET_POWER"
"@
sre %0,%1,%2
+ mr %0,%1
{s%A2i|s%A2wi} %0,%1,%h2")
(define_insn "lshrsi3_no_power"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
"! TARGET_POWER"
- "srw%I2 %0,%1,%h2")
+ "@
+ mr %0,%1
+ {sr|srw}%I2 %0,%1,%h2")
(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x")
+ (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
+ (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))
(const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))
- (clobber (match_scratch:SI 4 "=q,X"))]
+ (clobber (match_scratch:SI 3 "=r,X,r"))
+ (clobber (match_scratch:SI 4 "=q,X,X"))]
"TARGET_POWER"
"@
sre. %3,%1,%2
+ mr. %1,%1
{s%A2i.|s%A2wi.} %3,%1,%h2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_cint_operand" "ri"))
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
+ (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "reg_or_cint_operand" "O,ri"))
(const_int 0)))
- (clobber (match_scratch:SI 3 "=r"))]
+ (clobber (match_scratch:SI 3 "=X,r"))]
"! TARGET_POWER"
- "srw%I2. %3,%1,%h2"
+ "@
+ mr. %1,%1
+ {sr|srw}%I2. %3,%1,%h2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x")
+ (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
+ (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))
(const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
(lshiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:SI 4 "=q,X"))]
+ (clobber (match_scratch:SI 4 "=q,X,X"))]
"TARGET_POWER"
"@
sre. %0,%1,%2
+ mr. %0,%1
{s%A2i.|s%A2wi.} %0,%1,%h2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_cint_operand" "ri"))
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
+ (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "reg_or_cint_operand" "O,ri"))
(const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
"! TARGET_POWER"
- "srw%I2. %0,%1,%h2"
+ "@
+ mr. %0,%1
+ {sr|srw}%I2. %0,%1,%h2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")))]
"! TARGET_POWER"
- "sraw%I2 %0,%1,%h2")
+ "{sra|sraw}%I2 %0,%1,%h2")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
"! TARGET_POWER"
- "sraw%I2. %3,%1,%h2"
+ "{sra|sraw}%I2. %3,%1,%h2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
"! TARGET_POWER"
- "sraw%I2. %0,%1,%h2"
+ "{sra|sraw}%I2. %0,%1,%h2"
[(set_attr "type" "delayed_compare")])
\f
;; Floating-point insns, excluding normal data motion.
"frsp %0,%1"
[(set_attr "type" "fp")])
+(define_insn "aux_truncdfsf2"
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
+ "! TARGET_POWERPC && TARGET_HARD_FLOAT"
+ "frsp %0,%1"
+ [(set_attr "type" "fp")])
+
(define_insn "negsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
(match_operand:SF 2 "gpc_reg_operand" "f")))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT"
"{fm|fmul} %0,%1,%2"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dmul")])
(define_expand "divsf3"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT"
"{fd|fdiv} %0,%1,%2"
- [(set_attr "type" "sdiv")])
+ [(set_attr "type" "ddiv")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(match_operand:SF 3 "gpc_reg_operand" "f")))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT"
"{fma|fmadd} %0,%1,%2,%3"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dmul")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(match_operand:SF 3 "gpc_reg_operand" "f")))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT"
"{fms|fmsub} %0,%1,%2,%3"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dmul")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT"
"{fnma|fnmadd} %0,%1,%2,%3"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dmul")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT"
"{fnms|fnmsub} %0,%1,%2,%3"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dmul")])
(define_expand "sqrtsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
}
DONE;
}")
+
(define_insn "fselsfsf4"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
"fsel %0,%1,%2,%3"
[(set_attr "type" "fp")])
+
(define_insn "negdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
}
DONE;
}")
+
(define_insn "fseldfdf4"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
"fsel %0,%1,%2,%3"
[(set_attr "type" "fp")])
+
(define_insn "fselsfdf4"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
[(set_attr "type" "fp")])
\f
;; Conversions to and from floating-point.
+
(define_expand "floatsidf2"
- [(set (match_dup 2)
- (plus:DI (zero_extend:DI
- (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_dup 3)))
- (match_dup 4)))
- (set (match_operand:DF 0 "gpc_reg_operand" "")
- (minus:DF (subreg:DF (match_dup 2) 0)
- (match_dup 5)))]
+ [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
+ (use (match_dup 2))
+ (use (match_dup 3))
+ (clobber (match_dup 4))
+ (clobber (match_dup 5))
+ (clobber (reg:DF 76))])]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"
{
- operands[2] = gen_reg_rtx (DImode);
- operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000);
- operands[4] = immed_double_const (0, 0x43300000, DImode);
- operands[5] = force_reg (DFmode, immed_double_const (0x43300000,
- 0x80000000, DFmode));
+ operands[2] = force_reg (SImode, GEN_INT (0x43300000));
+ operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
+ operands[4] = gen_reg_rtx (SImode);
+ operands[5] = gen_reg_rtx (Pmode);
}")
-(define_expand "floatunssidf2"
- [(set (match_dup 2)
- (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
- (match_dup 3)))
- (set (match_operand:DF 0 "gpc_reg_operand" "")
- (minus:DF (subreg:DF (match_dup 2) 0)
- (match_dup 4)))]
+(define_insn "*floatsidf2_internal"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
+ (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
+ (use (match_operand:SI 2 "gpc_reg_operand" "r"))
+ (use (match_operand:DF 3 "gpc_reg_operand" "f"))
+ (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
+ (clobber (match_operand:SI 5 "gpc_reg_operand" "=b"))
+ (clobber (reg:DF 76))]
+ "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
+ "#"
+ [(set_attr "length" "24")])
+
+(define_split
+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
+ (use (match_operand:SI 2 "gpc_reg_operand" ""))
+ (use (match_operand:DF 3 "gpc_reg_operand" ""))
+ (clobber (match_operand:SI 4 "gpc_reg_operand" ""))
+ (clobber (match_operand:SI 5 "gpc_reg_operand" ""))
+ (clobber (reg:DF 76))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
+ [(set (match_dup 4)
+ (xor:SI (match_dup 1)
+ (match_dup 6)))
+ (set (match_dup 5)
+ (unspec [(const_int 0)] 11))
+ (set (match_dup 7)
+ (unspec [(match_dup 4)
+ (match_dup 5)] 12)) ;; low word
+ (set (match_dup 7)
+ (unspec [(match_dup 2)
+ (match_dup 5)
+ (match_dup 7)] 13)) ;; high word
+ (set (match_dup 0)
+ (unspec [(match_dup 7)
+ (match_dup 5)] 14))
+ (set (match_dup 0)
+ (minus:DF (match_dup 0)
+ (match_dup 3)))]
"
{
- operands[2] = gen_reg_rtx (DImode);
- operands[3] = immed_double_const (0, 0x43300000, DImode);
- operands[4] = force_reg (DFmode, immed_double_const (0x43300000, 0, DFmode));
+ operands[6] = GEN_INT (0x80000000);
+ operands[7] = gen_rtx (REG, DFmode, FPMEM_REGNUM);
}")
-;; For the above two cases, we always split.
-(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (plus:DI (zero_extend:DI
- (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "logical_operand" "")))
- (match_operand:DI 3 "low_32_bit_operand" "")))]
- "reload_completed"
- [(set (match_dup 6) (xor:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 4) (match_dup 5))]
+(define_expand "floatunssidf2"
+ [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
+ (use (match_dup 2))
+ (use (match_dup 3))
+ (clobber (match_dup 4))
+ (clobber (reg:DF 76))])]
+ "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"
-{ operands[4] = operand_subword (operands[0], 0, 0, DImode);
- operands[5] = operand_subword (operands[3], 0, 0, DImode);
- operands[6] = operand_subword (operands[0], 1, 0, DImode);
+{
+ operands[2] = force_reg (SImode, GEN_INT (0x43300000));
+ operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode));
+ operands[4] = gen_reg_rtx (Pmode);
}")
-(define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (plus:DI (zero_extend:DI
- (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
- (match_operand:SI 2 "logical_operand" "rKJ")))
- (match_operand:DI 3 "low_32_bit_operand" "n")))]
- ""
+(define_insn "*floatunssidf2_internal"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
+ (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
+ (use (match_operand:SI 2 "gpc_reg_operand" "r"))
+ (use (match_operand:DF 3 "gpc_reg_operand" "f"))
+ (clobber (match_operand:SI 4 "gpc_reg_operand" "=b"))
+ (clobber (reg:DF 76))]
+ "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"#"
- [(set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "=")
- (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
- (match_operand:DI 2 "low_32_bit_operand" "")))]
- "reload_completed"
- [(set (match_dup 3) (match_dup 4))
- (set (match_dup 5) (match_dup 1))]
- "
-{ operands[3] = operand_subword (operands[0], 0, 0, DImode);
- operands[4] = operand_subword (operands[2], 0, 0, DImode);
- operands[5] = operand_subword (operands[0], 1, 0, DImode);
+ [(set_attr "length" "20")])
- if (rtx_equal_p (operands[1], operands[5]))
+(define_split
+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
+ (use (match_operand:SI 2 "gpc_reg_operand" ""))
+ (use (match_operand:DF 3 "gpc_reg_operand" ""))
+ (clobber (match_operand:SI 4 "gpc_reg_operand" "=b"))
+ (clobber (reg:DF 76))]
+ "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
+ [(set (match_dup 4)
+ (unspec [(const_int 0)] 11))
+ (set (match_dup 5)
+ (unspec [(match_dup 1)
+ (match_dup 4)] 12)) ;; low word
+ (set (match_dup 5)
+ (unspec [(match_dup 2)
+ (match_dup 4)
+ (match_dup 5)] 13)) ;; high word
+ (set (match_dup 0)
+ (unspec [(match_dup 5)
+ (reg:SI 1)] 14))
+ (set (match_dup 0)
+ (minus:DF (match_dup 0)
+ (match_dup 3)))]
+ "operands[5] = gen_rtx (REG, DFmode, FPMEM_REGNUM);")
+
+;; Load up scratch register with base address + offset if needed
+(define_insn "*floatsidf2_loadaddr"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
+ (unspec [(const_int 0)] 11))]
+ "TARGET_HARD_FLOAT"
+ "*
+{
+ if (rs6000_fpmem_offset > 32760)
{
- emit_move_insn (operands[3], operands[4]);
- DONE;
+ rtx xop[3];
+
+ xop[0] = operands[0];
+ xop[1] = (frame_pointer_needed) ? frame_pointer_rtx : stack_pointer_rtx;
+ xop[2] = GEN_INT ((rs6000_fpmem_offset >> 16) + ((rs6000_fpmem_offset & 0x8000) >> 15));
+ output_asm_insn (\"{cau %0,%2(%1)|addis %0,%1,%2}\", xop);
}
+ else if (rs6000_fpmem_offset < 0)
+ abort ();
- if (rtx_equal_p (operands[1], operands[3]))
- {
- rtx temp;
+ return \"\";
+}"
+ [(set_attr "length" "4")])
+
+(define_insn "*floatsidf2_store1"
+ [(set (reg:DF 76)
+ (unspec [(match_operand:SI 0 "gpc_reg_operand" "r")
+ (match_operand:SI 1 "gpc_reg_operand" "r")] 12))]
+ "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
+ "*
+{
+ rtx indx;
+
+ if (rs6000_fpmem_offset > 32760)
+ indx = operands[1];
+ else if (frame_pointer_needed)
+ indx = frame_pointer_rtx;
+ else
+ indx = stack_pointer_rtx;
+
+ operands[2] = gen_rtx (MEM, SImode,
+ gen_rtx (PLUS, Pmode,
+ indx,
+ GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000)
+ + ((WORDS_BIG_ENDIAN != 0) * 4))));
+
+ return \"{st|stw} %0,%2\";
+}"
+ [(set_attr "type" "store")])
+
+(define_insn "*floatsidf2_store2"
+ [(set (reg:DF 76)
+ (unspec [(match_operand:SI 0 "gpc_reg_operand" "r")
+ (match_operand:SI 1 "gpc_reg_operand" "r")
+ (reg:DF 76)] 13))]
+ "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
+ "*
+{
+ rtx indx;
+
+ if (rs6000_fpmem_offset > 32760)
+ indx = operands[1];
+ else if (frame_pointer_needed)
+ indx = frame_pointer_rtx;
+ else
+ indx = stack_pointer_rtx;
- temp = operands[3]; operands[3] = operands[5]; operands[5] = temp;
- temp = operands[4]; operands[4] = operands[1]; operands[1] = temp;
+ operands[2] = gen_rtx (MEM, SImode,
+ gen_rtx (PLUS, Pmode,
+ indx,
+ GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000)
+ + ((WORDS_BIG_ENDIAN == 0) * 4))));
+
+ return \"{st|stw} %0,%2\";
+}"
+ [(set_attr "type" "store")])
+
+(define_insn "*floatsidf2_load"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (unspec [(reg:DF 76)
+ (match_operand:SI 1 "gpc_reg_operand" "b")] 14))]
+ "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
+ "*
+{
+ rtx indx;
+ HOST_WIDE_INT offset = rs6000_fpmem_offset;
+
+ if (rs6000_fpmem_offset > 32760)
+ {
+ indx = operands[1];
+ offset = (((offset & 0xffff) ^ 0x8000) - 0x8000);
}
-}")
+ else if (frame_pointer_needed)
+ indx = frame_pointer_rtx;
+ else
+ indx = stack_pointer_rtx;
-(define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
- (match_operand:DI 2 "low_32_bit_operand" "n")))]
- ""
- "#"
- [(set_attr "length" "8")])
+ operands[2] = gen_rtx (MEM, SImode,
+ gen_rtx (PLUS, Pmode, indx, GEN_INT (offset)));
+
+ return \"lfd %0,%2\";
+}"
+ [(set_attr "type" "fpload")])
(define_expand "fix_truncdfsi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
+ [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
+ (clobber (match_dup 2))
+ (clobber (match_dup 3))
+ (clobber (match_dup 4))])]
"TARGET_HARD_FLOAT"
"
{
- if (TARGET_POWER2 || TARGET_POWERPC)
- {
- rtx stack_slot = assign_stack_temp (DImode, 8, 0),
- temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_fpcvtsi (temp, operands[1]));
- emit_move_insn (stack_slot, temp);
- emit_move_insn (operands[0],
- operand_subword (stack_slot, 1, 0, DImode));
- DONE;
- }
- else
+ if (!TARGET_POWER2 && !TARGET_POWERPC)
{
emit_insn (gen_trunc_call (operands[0], operands[1],
gen_rtx (SYMBOL_REF, Pmode, RS6000_ITRUNC)));
DONE;
}
+
+ operands[2] = gen_reg_rtx (DImode);
+ operands[3] = gen_reg_rtx (Pmode);
+ operands[4] = gen_rtx (REG, DImode, FPMEM_REGNUM);
}")
-(define_insn "fpcvtsi"
+(define_insn "*fix_truncdfsi2_internal"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
+ (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
+ (clobber (match_operand:SI 3 "gpc_reg_operand" "=b"))
+ (clobber (reg:DI 76))]
+ "TARGET_HARD_FLOAT"
+ "#"
+ [(set_attr "length" "12")])
+
+(define_split
+ [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
+ (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
+ (clobber (match_operand:SI 3 "gpc_reg_operand" ""))
+ (clobber (reg:DI 76))]
+ "TARGET_HARD_FLOAT"
+ [(set (match_dup 2)
+ (sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))))
+ (set (match_dup 3)
+ (unspec [(const_int 0)] 11))
+ (set (match_dup 4)
+ (unspec [(match_dup 2)
+ (match_dup 3)] 15))
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
+ (unspec [(match_dup 4)
+ (match_dup 3)] 16))]
+ "operands[4] = gen_rtx (REG, DImode, FPMEM_REGNUM);")
+
+(define_insn "*fctiwz"
[(set (match_operand:DI 0 "gpc_reg_operand" "=f")
- (sign_extend:DI
- (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))]
+ (sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))]
"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
"{fcirz|fctiwz} %0,%1"
[(set_attr "type" "fp")])
+(define_insn "*fix_truncdfsi2_store"
+ [(set (reg:DI 76)
+ (unspec [(match_operand:DI 0 "gpc_reg_operand" "f")
+ (match_operand:SI 1 "gpc_reg_operand" "b")] 15))]
+ "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
+ "*
+{
+ rtx indx;
+
+ if (rs6000_fpmem_offset > 32760)
+ indx = operands[1];
+ else if (frame_pointer_needed)
+ indx = frame_pointer_rtx;
+ else
+ indx = stack_pointer_rtx;
+
+ operands[2] = gen_rtx (MEM, DFmode,
+ gen_rtx (PLUS, Pmode,
+ indx,
+ GEN_INT ((((rs6000_fpmem_offset & 0xffff)
+ ^ 0x8000) - 0x8000))));
+
+ return \"stfd %0,%w2\";
+}"
+ [(set_attr "type" "fpstore")])
+
+(define_insn "*fix_truncdfsi2_load"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (unspec [(reg:DI 76)
+ (match_operand:SI 1 "gpc_reg_operand" "b")] 16))]
+ "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
+ "*
+{
+ rtx indx;
+
+ if (rs6000_fpmem_offset > 32760)
+ indx = operands[1];
+ else if (frame_pointer_needed)
+ indx = frame_pointer_rtx;
+ else
+ indx = stack_pointer_rtx;
+
+ operands[2] = gen_rtx (MEM, DFmode,
+ gen_rtx (PLUS, Pmode,
+ indx,
+ GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000)
+ + ((WORDS_BIG_ENDIAN) ? 4 : 0))));
+
+ return \"{l|lwz} %0,%2\";
+}"
+ [(set_attr "type" "load")])
+
(define_expand "fixuns_truncdfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
(use (reg:DF 33))
(parallel [(set (reg:SI 3)
(call (mem:SI (match_operand 2 "" "")) (const_int 0)))
+ (use (const_int 0))
(clobber (scratch:SI))])
(set (match_operand:SI 0 "gpc_reg_operand" "")
(reg:SI 3))]
"TARGET_HARD_FLOAT"
"
-{
+{
rs6000_trunc_used = 1;
}")
[(set_attr "type" "fp")])
\f
;; Define the DImode operations that can be done in a small number
-;; of instructions.
-(define_expand "adddi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_short_operand" "")))]
- ""
- "
+;; of instructions. The & constraints are to prevent the register
+;; allocator from allocating registers that overlap with the inputs
+;; (for example, having an input in 7,8 and an output in 6,7). We
+;; also allow for the the output being the same as one of the inputs.
+
+(define_insn "*adddi3_noppc64"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
+ (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
+ (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
+ "! TARGET_POWERPC64"
+ "*
{
- if (! TARGET_POWER && ! TARGET_POWERPC64
- && short_cint_operand (operands[2], DImode))
- FAIL;
-}")
+ if (WORDS_BIG_ENDIAN)
+ return (GET_CODE (operands[2])) != CONST_INT
+ ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
+ : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
+ else
+ return (GET_CODE (operands[2])) != CONST_INT
+ ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
+ : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
+}"
+ [(set_attr "length" "8")])
-(define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
- (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
- "TARGET_POWER && ! TARGET_POWERPC64"
- "@
- {a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2
- {ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1"
+(define_insn "*subdi3_noppc64"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
+ (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
+ "! TARGET_POWERPC64"
+ "*
+{
+ if (WORDS_BIG_ENDIAN)
+ return (GET_CODE (operands[1]) != CONST_INT)
+ ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
+ : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
+ else
+ return (GET_CODE (operands[1]) != CONST_INT)
+ ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
+ : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
+}"
[(set_attr "length" "8")])
-(define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
- (match_operand:DI 2 "gpc_reg_operand" "r")))]
- "! TARGET_POWER && ! TARGET_POWERPC64"
- "addc %L0,%L1,%L2\;adde %0,%1,%2"
+(define_insn "*negdi2_noppc64"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
+ (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
+ "! TARGET_POWERPC64"
+ "*
+{
+ return (WORDS_BIG_ENDIAN)
+ ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
+ : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
+}"
[(set_attr "length" "8")])
-(define_expand "subdi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
+(define_expand "mulsidi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
+ (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
""
"
{
- if (! TARGET_POWER && ! TARGET_POWERPC64
- && short_cint_operand (operands[1], DImode))
- FAIL;
-}")
-
-(define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
- "TARGET_POWER && ! TARGET_POWERPC64"
- "@
- {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1
- {sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2"
- [(set_attr "length" "8")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "gpc_reg_operand" "r")))]
- "! TARGET_POWER && ! TARGET_POWERPC64"
- "subfc %L0,%L2,%L1\;subfe %0,%2,%1"
- [(set_attr "length" "8")])
-
-(define_expand "negdi2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
- ""
- "")
-
-(define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
- "! TARGET_POWERPC64"
- "{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1"
- [(set_attr "length" "8")])
-
-(define_expand "mulsidi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
- (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
- ""
- "
-{
- if (! TARGET_POWER && ! TARGET_POWERPC)
- {
- emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
- emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
- emit_insn (gen_mull_call ());
- emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
- gen_rtx (REG, SImode, 3));
- emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
- gen_rtx (REG, SImode, 4));
- DONE;
- }
- else if (TARGET_POWER)
- {
- emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
- DONE;
- }
+ if (! TARGET_POWER && ! TARGET_POWERPC)
+ {
+ emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
+ emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
+ emit_insn (gen_mull_call ());
+ if (WORDS_BIG_ENDIAN)
+ emit_move_insn (operands[0], gen_rtx (REG, DImode, 3));
+ else
+ {
+ emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
+ gen_rtx (REG, SImode, 3));
+ emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
+ gen_rtx (REG, SImode, 4));
+ }
+ DONE;
+ }
+ else if (TARGET_POWER)
+ {
+ emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
+ DONE;
+ }
}")
(define_insn "mulsidi3_mq"
[(set_attr "type" "imul")
(set_attr "length" "8")])
-(define_insn ""
+(define_insn "*mulsidi3_powerpc"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
(sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
"TARGET_POWERPC && ! TARGET_POWERPC64"
- "mulhw %0,%1,%2\;mullw %L0,%1,%2"
+ "*
+{
+ return (WORDS_BIG_ENDIAN)
+ ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
+ : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
+}"
+ [(set_attr "type" "imul")
+ (set_attr "length" "8")])
+
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
+ (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
+ "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
+ [(set (match_dup 3)
+ (truncate:SI
+ (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
+ (sign_extend:DI (match_dup 2)))
+ (const_int 32))))
+ (set (match_dup 4)
+ (mult:SI (match_dup 1)
+ (match_dup 2)))]
+ "
+{
+ int endian = (WORDS_BIG_ENDIAN == 0);
+ operands[3] = operand_subword (operands[0], endian, 0, DImode);
+ operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
+}")
+
+(define_insn "umulsidi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
+ (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
+ "TARGET_POWERPC && ! TARGET_POWERPC64"
+ "*
+{
+ return (WORDS_BIG_ENDIAN)
+ ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
+ : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
+}"
[(set_attr "type" "imul")
(set_attr "length" "8")])
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
+ (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
+ "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
+ [(set (match_dup 3)
+ (truncate:SI
+ (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
+ (zero_extend:DI (match_dup 2)))
+ (const_int 32))))
+ (set (match_dup 4)
+ (mult:SI (match_dup 1)
+ (match_dup 2)))]
+ "
+{
+ int endian = (WORDS_BIG_ENDIAN == 0);
+ operands[3] = operand_subword (operands[0], endian, 0, DImode);
+ operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
+}")
+
(define_expand "smulsi3_highpart"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(truncate:SI
;; If operands 0 and 2 are in the same register, we have a problem. But
;; operands 0 and 1 (the usual case) can be in the same register. That's
;; why we have the strange constraints below.
-(define_insn "ashldi3"
+(define_insn "ashldi3_power"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
(match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
[(set_attr "length" "8")])
-(define_insn "lshrdi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r")
- (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
- (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
- (clobber (match_scratch:SI 3 "=X,q,q,q"))]
- "TARGET_POWER"
+(define_insn "lshrdi3_power"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r")
+ (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
+ (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
+ (clobber (match_scratch:SI 3 "=X,q,q,q"))]
+ "TARGET_POWER"
+ "@
+ {cal %0,0(0)|li %0,0}\;{s%A2i|s%A2wi} %L0,%1,%h2
+ sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
+ sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
+ sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
+ [(set_attr "length" "8")])
+
+;; Shift by a variable amount is too complex to be worth open-coding. We
+;; just handle shifts by constants.
+(define_insn "ashrdi3_power"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+ (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "const_int_operand" "M,i")))
+ (clobber (match_scratch:SI 3 "=X,q"))]
+ "TARGET_POWER"
+ "@
+ {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
+ sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
+ [(set_attr "length" "8")])
+\f
+;; PowerPC64 DImode operations.
+
+(define_expand "adddi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "add_operand" "")))]
+ ""
+ "
+{
+ if (! TARGET_POWERPC64 && non_add_cint_operand (operands[2], DImode))
+ FAIL;
+}")
+
+;; Discourage ai/addic because of carry but provide it in an alternative
+;; allowing register zero as source.
+
+(define_insn ""
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
+ (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
+ (match_operand:DI 2 "add_operand" "r,I,I,J")))]
+ "TARGET_POWERPC64"
+ "@
+ add %0,%1,%2
+ addi %0,%1,%2
+ addic %0,%1,%2
+ addis %0,%1,%v2")
+
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
+ (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
+ (match_operand:DI 2 "reg_or_short_operand" "r,I"))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r,r"))]
+ "TARGET_POWERPC64"
+ "@
+ add. %3,%1,%2
+ addic. %3,%1,%2"
+ [(set_attr "type" "compare")])
+
+(define_insn ""
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
+ (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
+ (match_operand:DI 2 "reg_or_short_operand" "r,I"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+ (plus:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_POWERPC64"
+ "@
+ add. %0,%1,%2
+ addic. %0,%1,%2"
+ [(set_attr "type" "compare")])
+
+;; Split an add that we can't do in one insn into two insns, each of which
+;; does one 16-bit part. This is used by combine. Note that the low-order
+;; add should be last in case the result gets used in an address.
+
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "non_add_cint_operand" "")))]
+ "TARGET_POWERPC64"
+ [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
+ (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
+"
+{
+ HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
+ HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
+
+ if (low & 0x8000)
+ high+=0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
+
+ operands[3] = GEN_INT (high);
+ operands[4] = GEN_INT (low);
+}")
+
+(define_insn "one_cmpldi2"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
+ "TARGET_POWERPC64"
+ "nor %0,%1,%1")
+
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+ (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
+ (const_int 0)))
+ (clobber (match_scratch:DI 2 "=r"))]
+ "TARGET_POWERPC64"
+ "nor. %2,%1,%1"
+ [(set_attr "type" "compare")])
+
+(define_insn ""
+ [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+ (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (not:DI (match_dup 1)))]
+ "TARGET_POWERPC64"
+ "nor. %0,%1,%1"
+ [(set_attr "type" "compare")])
+
+(define_insn ""
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+ (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
+ "TARGET_POWERPC64"
+ "@
+ subf %0,%2,%1
+ subfic %0,%2,%1")
+
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+ (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "gpc_reg_operand" "r"))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r"))]
+ "TARGET_POWERPC64"
+ "subf. %3,%2,%1"
+ [(set_attr "type" "compare")])
+
+(define_insn ""
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "gpc_reg_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (minus:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_POWERPC64"
+ "subf. %0,%2,%1"
+ [(set_attr "type" "compare")])
+
+(define_expand "subdi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
+ (match_operand:DI 2 "reg_or_cint_operand" "")))]
+ ""
+ "
+{
+ if (GET_CODE (operands[2]) == CONST_INT)
+ {
+ emit_insn (gen_adddi3 (operands[0], operands[1],
+ negate_rtx (DImode, operands[2])));
+ DONE;
+ }
+}")
+
+(define_insn "absdi2"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
+ (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
+ (clobber (match_scratch:DI 2 "=&r,&r"))]
+ "TARGET_POWERPC64"
+ "sradi %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0"
+ [(set_attr "length" "12")])
+
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
+ (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
+ (clobber (match_scratch:DI 2 "=&r,&r"))]
+ "TARGET_POWERPC64 && reload_completed"
+ [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 31)))
+ (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
+ (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
+ "")
+
+(define_insn ""
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
+ (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
+ (clobber (match_scratch:DI 2 "=&r,&r"))]
+ "TARGET_POWERPC64"
+ "sradi %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2"
+ [(set_attr "length" "12")])
+
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
+ (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
+ (clobber (match_scratch:DI 2 "=&r,&r"))]
+ "TARGET_POWERPC64 && reload_completed"
+ [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 31)))
+ (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
+ (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
+ "")
+
+(define_expand "negdi2"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
+ "TARGET_POWERPC64"
+ "neg %0,%1")
+
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+ (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
+ (const_int 0)))
+ (clobber (match_scratch:DI 2 "=r"))]
+ "TARGET_POWERPC64"
+ "neg. %2,%1"
+ [(set_attr "type" "compare")])
+
+(define_insn ""
+ [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+ (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (neg:DI (match_dup 1)))]
+ "TARGET_POWERPC64"
+ "neg. %0,%1"
+ [(set_attr "type" "compare")])
+
+(define_insn "ffsdi2"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
+ (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
+ "TARGET_POWERPC64"
+ "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
+ [(set_attr "length" "16")])
+
+(define_insn "muldi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
+ (match_operand:DI 2 "gpc_reg_operand" "r")))]
+ "TARGET_POWERPC64"
+ "mulld %0,%1,%2"
+ [(set_attr "type" "imul")])
+
+(define_insn "smuldi3_highpart"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (truncate:DI
+ (lshiftrt:TI (mult:TI (sign_extend:TI
+ (match_operand:DI 1 "gpc_reg_operand" "%r"))
+ (sign_extend:TI
+ (match_operand:DI 2 "gpc_reg_operand" "r")))
+ (const_int 64))))]
+ "TARGET_POWERPC64"
+ "mulhd %0,%1,%2"
+ [(set_attr "type" "imul")])
+
+(define_insn "umuldi3_highpart"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (truncate:DI
+ (lshiftrt:TI (mult:TI (zero_extend:TI
+ (match_operand:DI 1 "gpc_reg_operand" "%r"))
+ (zero_extend:TI
+ (match_operand:DI 2 "gpc_reg_operand" "r")))
+ (const_int 64))))]
+ "TARGET_POWERPC64"
+ "mulhdu %0,%1,%2"
+ [(set_attr "type" "imul")])
+
+(define_expand "divdi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "reg_or_cint_operand" "")))]
+ "TARGET_POWERPC64"
+ "
+{
+ if (GET_CODE (operands[2]) == CONST_INT
+ && exact_log2 (INTVAL (operands[2])) >= 0)
+ ;
+ else
+ operands[2] = force_reg (DImode, operands[2]);
+}")
+
+(define_expand "moddi3"
+ [(use (match_operand:DI 0 "gpc_reg_operand" ""))
+ (use (match_operand:DI 1 "gpc_reg_operand" ""))
+ (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
+ "TARGET_POWERPC64"
+ "
+{
+ int i = exact_log2 (INTVAL (operands[2]));
+ rtx temp1;
+ rtx temp2;
+
+ if (GET_CODE (operands[2]) != CONST_INT || i < 0)
+ FAIL;
+
+ temp1 = gen_reg_rtx (DImode);
+ temp2 = gen_reg_rtx (DImode);
+
+ emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
+ emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
+ emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
+ DONE;
+}")
+
+(define_insn ""
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "const_int_operand" "N")))]
+ "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
+ "sradi %0,%1,%p2\;addze %0,%0"
+ [(set_attr "length" "8")])
+
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+ (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "const_int_operand" "N"))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r"))]
+ "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
+ "sradi %3,%1,%p2\;addze. %3,%3"
+ [(set_attr "type" "compare")
+ (set_attr "length" "8")])
+
+(define_insn ""
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "const_int_operand" "N"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (div:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
+ "sradi %0,%1,%p2\;addze. %0,%0"
+ [(set_attr "type" "compare")
+ (set_attr "length" "8")])
+
+(define_insn ""
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "gpc_reg_operand" "r")))]
+ "TARGET_POWERPC64"
+ "divd %0,%1,%2"
+ [(set_attr "type" "idiv")])
+
+(define_insn "udivdi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "gpc_reg_operand" "r")))]
+ "TARGET_POWERPC64"
+ "divdu %0,%1,%2"
+ [(set_attr "type" "idiv")])
+
+(define_insn "rotldi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
+ "TARGET_POWERPC64"
+ "rld%I2cl %0,%1,%H2,0")
+
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+ (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "reg_or_cint_operand" "ri"))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r"))]
+ "TARGET_POWERPC64"
+ "rld%I2cl. %3,%1,%H2,0"
+ [(set_attr "type" "delayed_compare")])
+
+(define_insn ""
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "reg_or_cint_operand" "ri"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (rotate:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_POWERPC64"
+ "rld%I2cl. %0,%1,%H2,0"
+ [(set_attr "type" "delayed_compare")])
+
+(define_expand "ashldi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "reg_or_cint_operand" "")))]
+ "TARGET_POWERPC64 || TARGET_POWER"
+ "
+{
+ if (TARGET_POWERPC64)
+ ;
+ else if (TARGET_POWER)
+ {
+ emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
+ DONE;
+ }
+ else
+ FAIL;
+}")
+
+(define_insn ""
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
+ "TARGET_POWERPC64"
+ "sld%I2 %0,%1,%H2"
+ [(set_attr "length" "8")])
+
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+ (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "reg_or_cint_operand" "ri"))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r"))]
+ "TARGET_POWERPC64"
+ "sld%I2. %3,%1,%H2"
+ [(set_attr "type" "delayed_compare")])
+
+(define_insn ""
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "reg_or_cint_operand" "ri"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (ashift:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_POWERPC64"
+ "sld%I2. %0,%1,%H2"
+ [(set_attr "type" "delayed_compare")])
+
+(define_expand "lshrdi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "reg_or_cint_operand" "")))]
+ "TARGET_POWERPC64 || TARGET_POWER"
+ "
+{
+ if (TARGET_POWERPC64)
+ ;
+ else if (TARGET_POWER)
+ {
+ emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
+ DONE;
+ }
+ else
+ FAIL;
+}")
+
+(define_insn ""
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
+ "TARGET_POWERPC64"
+ "srd%I2 %0,%1,%H2")
+
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+ (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "reg_or_cint_operand" "ri"))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r"))]
+ "TARGET_POWERPC64"
+ "srd%I2. %3,%1,%H2"
+ [(set_attr "type" "delayed_compare")])
+
+(define_insn ""
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "reg_or_cint_operand" "ri"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (lshiftrt:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_POWERPC64"
+ "srd%I2. %0,%1,%H2"
+ [(set_attr "type" "delayed_compare")])
+
+(define_expand "ashrdi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "reg_or_cint_operand" "")))]
+ "TARGET_POWERPC64 || TARGET_POWER"
+ "
+{
+ if (TARGET_POWERPC64)
+ ;
+ else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
+ {
+ emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
+ DONE;
+ }
+ else
+ FAIL;
+}")
+
+(define_insn ""
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
+ "TARGET_POWERPC64"
+ "srad%I2 %0,%1,%H2")
+
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+ (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "reg_or_cint_operand" "ri"))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r"))]
+ "TARGET_POWERPC64"
+ "srad%I2. %3,%1,%H2"
+ [(set_attr "type" "delayed_compare")])
+
+(define_insn ""
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "reg_or_cint_operand" "ri"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (ashiftrt:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_POWERPC64"
+ "srad%I2. %0,%1,%H2"
+ [(set_attr "type" "delayed_compare")])
+
+(define_insn "anddi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
+ (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
+ (match_operand:DI 2 "and_operand" "?r,K,J")))
+ (clobber (match_scratch:CC 3 "=X,x,x"))]
+ "TARGET_POWERPC64"
+ "@
+ and %0,%1,%2
+ andi. %0,%1,%b2
+ andis. %0,%1,%u2")
+
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x")
+ (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
+ (match_operand:DI 2 "and_operand" "r,K,J"))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r,r,r"))]
+ "TARGET_POWERPC64"
+ "@
+ and. %3,%1,%2
+ andi. %3,%1,%b2
+ andis. %3,%1,%u2"
+ [(set_attr "type" "compare,compare,compare")])
+
+(define_insn ""
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x")
+ (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
+ (match_operand:DI 2 "and_operand" "r,K,J"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
+ (and:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_POWERPC64"
+ "@
+ and. %0,%1,%2
+ andi. %0,%1,%b2
+ andis. %0,%1,%u2"
+ [(set_attr "type" "compare,compare,compare")])
+
+;; Take a AND with a constant that cannot be done in a single insn and try to
+;; split it into two insns. This does not verify that the insns are valid
+;; since this need not be done as combine will do it.
+
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "non_and_cint_operand" "")))]
+ "TARGET_POWERPC64"
+ [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
+ (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
+ "
+{
+ int maskval = INTVAL (operands[2]);
+ int i, transitions, last_bit_value;
+ int orig = maskval, first_c = maskval, second_c;
+
+ /* We know that MASKVAL must have more than 2 bit-transitions. Start at
+ the low-order bit and count for the third transition. When we get there,
+ make a first mask that has everything to the left of that position
+ a one. Then make the second mask to turn off whatever else is needed. */
+
+ for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++)
+ {
+ if (((maskval >>= 1) & 1) != last_bit_value)
+ last_bit_value ^= 1, transitions++;
+
+ if (transitions > 2)
+ {
+ first_c |= (~0) << i;
+ break;
+ }
+ }
+
+ second_c = orig | ~ first_c;
+
+ operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c);
+ operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c);
+}")
+
+(define_insn "iordi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
+ (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
+ (match_operand:DI 2 "logical_operand" "r,K,J")))]
+ "TARGET_POWERPC64"
+ "@
+ or %0,%1,%2
+ ori %0,%1,%b2
+ oris %0,%1,%u2")
+
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+ (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
+ (match_operand:DI 2 "gpc_reg_operand" "r"))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r"))]
+ "TARGET_POWERPC64"
+ "or. %3,%1,%2"
+ [(set_attr "type" "compare")])
+
+(define_insn ""
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
+ (match_operand:DI 2 "gpc_reg_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (ior:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_POWERPC64"
+ "or. %0,%1,%2"
+ [(set_attr "type" "compare")])
+
+;; Split an IOR that we can't do in one insn into two insns, each of which
+;; does one 16-bit part. This is used by combine.
+
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "non_logical_cint_operand" "")))]
+ "TARGET_POWERPC64"
+ [(set (match_dup 0) (ior:DI (match_dup 1) (match_dup 3)))
+ (set (match_dup 0) (ior:DI (match_dup 0) (match_dup 4)))]
+"
+{
+ operands[3] = gen_rtx (CONST_INT, VOIDmode,
+ INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
+ operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
+}")
+
+(define_insn "xordi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
+ (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
+ (match_operand:DI 2 "logical_operand" "r,K,J")))]
+ "TARGET_POWERPC64"
"@
- {cal %0,0(0)|li %0,0}\;{s%A2i|s%A2wi} %L0,%1,%h2
- sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
- sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
- sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
- [(set_attr "length" "8")])
+ xor %0,%1,%2
+ xori %0,%1,%b2
+ xoris %0,%1,%u2")
-;; Shift by a variable amount is too complex to be worth open-coding. We
-;; just handle shifts by constants.
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+ (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
+ (match_operand:DI 2 "gpc_reg_operand" "r"))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r"))]
+ "TARGET_POWERPC64"
+ "xor. %3,%1,%2"
+ [(set_attr "type" "compare")])
-(define_expand "ashrdi3"
- [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "general_operand" "")))
- (clobber (match_scratch:SI 3 ""))])]
- "TARGET_POWER"
- "
-{ if (GET_CODE (operands[2]) != CONST_INT)
- FAIL;
+(define_insn ""
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
+ (match_operand:DI 2 "gpc_reg_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (xor:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_POWERPC64"
+ "xor. %0,%1,%2"
+ [(set_attr "type" "compare")])
+
+;; Split an XOR that we can't do in one insn into two insns, each of which
+;; does one 16-bit part. This is used by combine.
+
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "non_logical_cint_operand" "")))]
+ "TARGET_POWERPC64"
+ [(set (match_dup 0) (xor:DI (match_dup 1) (match_dup 3)))
+ (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 4)))]
+"
+{
+ operands[3] = gen_rtx (CONST_INT, VOIDmode,
+ INTVAL (operands[2]) & 0xffff0000);
+ operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
}")
(define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "const_int_operand" "M,i")))
- (clobber (match_scratch:SI 3 "=X,q"))]
- "TARGET_POWER"
- "@
- {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
- sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
- [(set_attr "length" "8")])
-\f
-;; PowerPC64 DImode operations.
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
+ (match_operand:DI 2 "gpc_reg_operand" "r"))))]
+ "TARGET_POWERPC64"
+ "eqv %0,%1,%2")
-(define_insn "ffsdi2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
- (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
- "TARGET_POWERPC64"
- "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
- [(set_attr "length" "16")])
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+ (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
+ (match_operand:DI 2 "gpc_reg_operand" "r")))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r"))]
+ "TARGET_POWERPC64"
+ "eqv. %3,%1,%2"
+ [(set_attr "type" "compare")])
-(define_insn "muldi3"
+(define_insn ""
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
+ (match_operand:DI 2 "gpc_reg_operand" "r")))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (not:DI (xor:DI (match_dup 1) (match_dup 2))))]
+ "TARGET_POWERPC64"
+ "eqv. %0,%1,%2"
+ [(set_attr "type" "compare")])
+
+(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
- (match_operand:DI 2 "gpc_reg_operand" "r")))]
+ (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
+ (match_operand:DI 2 "gpc_reg_operand" "r")))]
"TARGET_POWERPC64"
- "mulld %0,%1,%2"
- [(set_attr "type" "imul")])
+ "andc %0,%2,%1")
-(define_insn "smuldi3_highpart"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (truncate:DI
- (lshiftrt:TI (mult:TI (sign_extend:TI
- (match_operand:DI 1 "gpc_reg_operand" "%r"))
- (sign_extend:TI
- (match_operand:DI 2 "gpc_reg_operand" "r")))
- (const_int 64))))]
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+ (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
+ (match_operand:DI 2 "gpc_reg_operand" "r"))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r"))]
"TARGET_POWERPC64"
- "mulhd %0,%1,%2"
- [(set_attr "type" "imul")])
+ "andc. %3,%2,%1"
+ [(set_attr "type" "compare")])
-(define_insn "umuldi3_highpart"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (truncate:DI
- (lshiftrt:TI (mult:TI (zero_extend:TI
- (match_operand:DI 1 "gpc_reg_operand" "%r"))
- (zero_extend:TI
- (match_operand:DI 2 "gpc_reg_operand" "r")))
- (const_int 64))))]
+(define_insn ""
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
+ (match_operand:DI 2 "gpc_reg_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (and:DI (not:DI (match_dup 1)) (match_dup 2)))]
"TARGET_POWERPC64"
- "mulhdu %0,%1,%2"
- [(set_attr "type" "imul")])
+ "andc. %0,%2,%1"
+ [(set_attr "type" "compare")])
-(define_insn "divdi3"
+(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "gpc_reg_operand" "r")))]
+ (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
+ (match_operand:DI 2 "gpc_reg_operand" "r")))]
"TARGET_POWERPC64"
- "divd %0,%1,%2"
- [(set_attr "type" "idiv")])
+ "orc %0,%2,%1")
-(define_insn "udivdi3"
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+ (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
+ (match_operand:DI 2 "gpc_reg_operand" "r"))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r"))]
+ "TARGET_POWERPC64"
+ "orc. %3,%2,%1"
+ [(set_attr "type" "compare")])
+
+(define_insn ""
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
+ (match_operand:DI 2 "gpc_reg_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (ior:DI (not:DI (match_dup 1)) (match_dup 2)))]
+ "TARGET_POWERPC64"
+ "orc. %0,%2,%1"
+ [(set_attr "type" "compare")])
+
+(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "gpc_reg_operand" "r")))]
+ (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
+ (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
"TARGET_POWERPC64"
- "divdu %0,%1,%2"
- [(set_attr "type" "idiv")])
+ "nand %0,%1,%2")
-(define_insn "rotldi3"
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+ (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
+ (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r"))]
+ "TARGET_POWERPC64"
+ "nand. %3,%1,%2"
+ [(set_attr "type" "compare")])
+
+(define_insn ""
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
+ (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
+ "TARGET_POWERPC64"
+ "nand. %0,%1,%2"
+ [(set_attr "type" "compare")])
+
+(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
+ (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
+ (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
"TARGET_POWERPC64"
- "rld%I2cl %0,%1,%h2,0")
+ "nor %0,%1,%2")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "reg_or_cint_operand" "ri"))
+ (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
+ (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
(const_int 0)))
(clobber (match_scratch:DI 3 "=r"))]
"TARGET_POWERPC64"
- "rld%I2cl. %3,%1,%h2,0"
- [(set_attr "type" "delayed_compare")])
+ "nor. %3,%1,%2"
+ [(set_attr "type" "compare")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "reg_or_cint_operand" "ri"))
+ (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
+ (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (rotate:DI (match_dup 1) (match_dup 2)))]
+ (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
"TARGET_POWERPC64"
- "rld%I2cl. %0,%1,%h2,0"
- [(set_attr "type" "delayed_compare")])
+ "nor. %0,%1,%2"
+ [(set_attr "type" "compare")])
\f
;; Now define ways of moving data around.
-;;
+
+;; Elf specific ways of loading addresses for non-PIC code.
+;; The output of this could be r0, but we limit it to base
+;; registers, since almost all uses of this will need it
+;; in a base register shortly.
+(define_insn "elf_high"
+ [(set (match_operand:SI 0 "register_operand" "=b")
+ (high:SI (match_operand 1 "" "")))]
+ "TARGET_ELF && !TARGET_64BIT"
+ "{cau|addis} %0,0,%1@ha")
+
+(define_insn "elf_low"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (lo_sum:SI (match_operand:SI 1 "register_operand" "b")
+ (match_operand 2 "" "")))]
+ "TARGET_ELF && !TARGET_64BIT"
+ "{cal %0,%a2@l(%1)|addi %0,%1,%2@l}")
+
+;; Set up a register with a value from the GOT table
+
+(define_expand "movsi_got"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (unspec [(match_operand:SI 1 "got_operand" "")
+ (match_dup 2)] 8))]
+ "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
+ "
+{
+ operands[2] = rs6000_got_register (operands[1]);
+}")
+
+(define_insn "*movsi_got_internal"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec [(match_operand:SI 1 "got_operand" "")
+ (match_operand:SI 2 "register_operand" "b")] 8))]
+ "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
+ "{l|lwz} %0,%a1@got(%2)"
+ [(set_attr "type" "load")])
+
;; For SI, we special-case integers that can't be loaded in one insn. We
;; do the load 16-bits at a time. We could do this by loading from memory,
;; and this is even supposed to be faster, but it is simpler not to get
if (GET_CODE (operands[0]) != REG)
operands[1] = force_reg (SImode, operands[1]);
- if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT
+ /* Convert a move of a CONST_DOUBLE into a CONST_INT */
+ if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
+
+ /* Use default pattern for address of ELF small data */
+ if (TARGET_ELF
+ && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
+ && (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
+ && small_data_operand (operands[1], SImode))
+ {
+ emit_insn (gen_rtx (SET, VOIDmode, operands[0], operands[1]));
+ DONE;
+ }
+
+ if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
+ && flag_pic == 1 && got_operand (operands[1], SImode))
+ {
+ emit_insn (gen_movsi_got (operands[0], operands[1]));
+ DONE;
+ }
+
+ if (TARGET_ELF && TARGET_NO_TOC && !TARGET_64BIT
+ && !flag_pic
+ && CONSTANT_P (operands[1])
+ && GET_CODE (operands[1]) != HIGH
+ && GET_CODE (operands[1]) != CONST_INT)
+ {
+ rtx target = (reload_completed || reload_in_progress)
+ ? operands[0] : gen_reg_rtx (SImode);
+
+ /* If this is a function address on -mcall-aixdesc or -mcall-nt,
+ convert it to the address of the descriptor. */
+ if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
+ && GET_CODE (operands[1]) == SYMBOL_REF
+ && XSTR (operands[1], 0)[0] == '.')
+ {
+ char *name = XSTR (operands[1], 0);
+ rtx new_ref;
+ while (*name == '.')
+ name++;
+ new_ref = gen_rtx (SYMBOL_REF, Pmode, name);
+ CONSTANT_POOL_ADDRESS_P (new_ref) = CONSTANT_POOL_ADDRESS_P (operands[1]);
+ SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]);
+ SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
+ operands[1] = new_ref;
+ }
+
+ emit_insn (gen_elf_high (target, operands[1]));
+ emit_insn (gen_elf_low (operands[0], target, operands[1]));
+ DONE;
+ }
+
+ if (GET_CODE (operands[1]) == CONST
+ && DEFAULT_ABI == ABI_NT
+ && !side_effects_p (operands[0]))
+ {
+ rtx const_term = const0_rtx;
+ rtx sym = eliminate_constant_term (XEXP (operands[1], 0), &const_term);
+ if (sym && GET_CODE (const_term) == CONST_INT
+ && (GET_CODE (sym) == SYMBOL_REF || GET_CODE (sym) == LABEL_REF))
+ {
+ unsigned HOST_WIDE_INT value = INTVAL (const_term);
+ int new_reg_p = (flag_expensive_optimizations
+ && !reload_completed
+ && !reload_in_progress);
+ rtx tmp1 = (new_reg_p && value != 0) ? gen_reg_rtx (SImode) : operands[0];
+
+ emit_insn (gen_movsi (tmp1, sym));
+ if (INTVAL (const_term) != 0)
+ {
+ if (value + 0x8000 < 0x10000)
+ emit_insn (gen_addsi3 (operands[0], tmp1, GEN_INT (value)));
+
+ else
+ {
+ HOST_WIDE_INT high_int = value & (~ (HOST_WIDE_INT) 0xffff);
+ HOST_WIDE_INT low_int = value & 0xffff;
+ rtx tmp2 = (!new_reg_p || !low_int) ? operands[0] : gen_reg_rtx (Pmode);
+
+ if (low_int & 0x8000)
+ high_int += 0x10000, low_int |= ((HOST_WIDE_INT) -1) << 16;
+
+ emit_insn (gen_addsi3 (tmp2, tmp1, GEN_INT (high_int)));
+ if (low_int)
+ emit_insn (gen_addsi3 (operands[0], tmp2, GEN_INT (low_int)));
+ }
+ }
+ DONE;
+ }
+ else
+ fatal_insn (\"bad address\", operands[1]);
+ }
+
+ if ((!TARGET_WINDOWS_NT || DEFAULT_ABI != ABI_NT)
+ && CONSTANT_P (operands[1])
+ && GET_CODE (operands[1]) != CONST_INT
+ && GET_CODE (operands[1]) != HIGH
&& ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
{
/* If we are to limit the number of things we put in the TOC and
this is a symbol plus a constant we can add in one insn,
- just put the sumbol in the TOC and add the constant. Don't do
+ just put the symbol in the TOC and add the constant. Don't do
this if reload is in progress. */
if (GET_CODE (operands[1]) == CONST
&& TARGET_NO_SUM_IN_TOC && ! reload_in_progress
operands[1] = change_address (operands[1], SImode,
XEXP (operands[1], 0));
}
-
- if (GET_CODE (operands[1]) == CONST_INT
- && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
- && (INTVAL (operands[1]) & 0xffff) != 0)
- {
- emit_move_insn (operands[0],
- gen_rtx (CONST_INT, VOIDmode,
- INTVAL (operands[1]) & 0xffff0000));
- emit_insn (gen_iorsi3 (operands[0], operands[0],
- gen_rtx (CONST_INT, VOIDmode,
- INTVAL (operands[1]) & 0xffff)));
- DONE;
- }
}")
(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*q,*c*l,*h")
- (match_operand:SI 1 "input_operand" "r,m,r,I,J,R,*h,r,r,0"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
+ (match_operand:SI 1 "input_operand" "r,S,T,U,m,r,I,J,n,R,*h,r,r,0"))]
"gpc_reg_operand (operands[0], SImode)
|| gpc_reg_operand (operands[1], SImode)"
"@
mr %0,%1
+ {l|lwz} %0,[toc]%1(2)
+ {l|lwz} %0,[toc]%l1(2)
+ {cal|la} %0,%a1
{l%U1%X1|lwz%U1%X1} %0,%1
{st%U0%X0|stw%U0%X0} %1,%0
{lil|li} %0,%1
- {liu|lis} %0,%u1
+ {liu|lis} %0,%v1
+ #
{cal|la} %0,%1(%*)
mf%1 %0
mt%0 %1
mt%0 %1
cror 0,0,0"
- [(set_attr "type" "*,load,*,*,*,*,*,*,mtjmpr,*")])
+ [(set_attr "type" "*,load,load,*,load,store,*,*,*,*,*,*,mtjmpr,*")
+ (set_attr "length" "4,4,4,4,4,4,4,4,8,4,4,4,4,4")])
;; Split a load of a large constant into the appropriate two-insn
;; sequence.
mt%0 %1
mt%0 %1
cror 0,0,0"
- [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")])
+ [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
(define_expand "movqi"
[(set (match_operand:QI 0 "general_operand" "")
mt%0 %1
mt%0 %1
cror 0,0,0"
- [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")])
+ [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
\f
;; Here is how to move condition codes around. When we store CC data in
;; an integer register or memory, we store just the high-order 4 bits.
mr %0,%1
{l%U1%X1|lwz%U1%X1} %0,%1
{st%U0%U1|stw%U0%U1} %1,%0"
- [(set_attr "type" "*,*,*,compare,*,*,load,*")
+ [(set_attr "type" "*,*,*,compare,*,*,load,store")
(set_attr "length" "*,*,12,*,8,*,*,*")])
\f
-;; For floating-point, we normally deal with the floating-point registers.
-;; The sole exception is that parameter passing can produce floating-point
-;; values in fixed-point registers. Unless the value is a simple constant
-;; or already in memory, we deal with this by allocating memory and copying
-;; the value explicitly via that memory location.
+;; For floating-point, we normally deal with the floating-point registers
+;; unless -msoft-float is used. The sole exception is that parameter passing
+;; can produce floating-point values in fixed-point registers. Unless the
+;; value is a simple constant or already in memory, we deal with this by
+;; allocating memory and copying the value explicitly via that memory location.
(define_expand "movsf"
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(match_operand:SF 1 "any_operand" ""))]
&& REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
operands[1] = alter_subreg (operands[1]);
- if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
+ if (TARGET_SOFT_FLOAT && GET_CODE (operands[0]) == MEM)
+ operands[1] = force_reg (SFmode, operands[1]);
+
+ else if (TARGET_HARD_FLOAT)
{
- /* If this is a store to memory or another integer register do the
- move directly. Otherwise store to a temporary stack slot and
- load from there into a floating point register. */
-
- if (GET_CODE (operands[0]) == MEM
- || (GET_CODE (operands[0]) == REG
- && (REGNO (operands[0]) < 32
- || (reload_in_progress
- && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))))
- {
- emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
- operand_subword (operands[1], 0, 0, SFmode));
- DONE;
- }
- else
+ if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
{
- rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
-
- emit_move_insn (stack_slot, operands[1]);
- emit_move_insn (operands[0], stack_slot);
- DONE;
+ /* If this is a store to memory or another integer register do the
+ move directly. Otherwise store to a temporary stack slot and
+ load from there into a floating point register. */
+
+ if (GET_CODE (operands[0]) == MEM
+ || (GET_CODE (operands[0]) == REG
+ && (REGNO (operands[0]) < 32
+ || (reload_in_progress
+ && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))))
+ {
+ emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
+ operand_subword (operands[1], 0, 0, SFmode));
+ DONE;
+ }
+ else
+ {
+ rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
+
+ emit_move_insn (stack_slot, operands[1]);
+ emit_move_insn (operands[0], stack_slot);
+ DONE;
+ }
}
- }
- if (GET_CODE (operands[0]) == MEM)
- {
- /* If operands[1] is a register, it may have double-precision data
- in it, so truncate it to single precision. We need not do
- this for POWERPC. */
- if (! TARGET_POWERPC && TARGET_HARD_FLOAT && GET_CODE (operands[1]) == REG)
+ if (GET_CODE (operands[0]) == MEM)
{
- rtx newreg = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
- emit_insn (gen_truncdfsf2 (newreg,
- gen_rtx (SUBREG, DFmode, operands[1], 0)));
- operands[1] = newreg;
+ /* If operands[1] is a register, it may have double-precision data
+ in it, so truncate it to single precision. We need not do
+ this for POWERPC. */
+ if (! TARGET_POWERPC && TARGET_HARD_FLOAT
+ && GET_CODE (operands[1]) == REG)
+ {
+ rtx newreg
+ = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
+ emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
+ operands[1] = newreg;
+ }
+
+ operands[1] = force_reg (SFmode, operands[1]);
}
- operands[1] = force_reg (SFmode, operands[1]);
- }
-
- if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
- {
- if (GET_CODE (operands[1]) == MEM
+ if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
+ {
+ if (GET_CODE (operands[1]) == MEM
#if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
- || GET_CODE (operands[1]) == CONST_DOUBLE
+ || GET_CODE (operands[1]) == CONST_DOUBLE
#endif
- || (GET_CODE (operands[1]) == REG
- && (REGNO (operands[1]) < 32
- || (reload_in_progress
- && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))))
- {
- emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
- operand_subword (operands[1], 0, 0, SFmode));
- DONE;
- }
- else
- {
- rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
-
- emit_move_insn (stack_slot, operands[1]);
- emit_move_insn (operands[0], stack_slot);
- DONE;
+ || (GET_CODE (operands[1]) == REG
+ && (REGNO (operands[1]) < 32
+ || (reload_in_progress
+ && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))))
+ {
+ emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
+ operand_subword (operands[1], 0, 0, SFmode));
+ DONE;
+ }
+ else
+ {
+ rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
+
+ emit_move_insn (stack_slot, operands[1]);
+ emit_move_insn (operands[0], stack_slot);
+ DONE;
+ }
}
}
- if (CONSTANT_P (operands[1]))
+ if (CONSTANT_P (operands[1]) && TARGET_HARD_FLOAT)
{
operands[1] = force_const_mem (SFmode, operands[1]);
if (! memory_address_p (SFmode, XEXP (operands[1], 0))
(define_split
[(set (match_operand:SF 0 "gpc_reg_operand" "")
- (match_operand:SF 1 "easy_fp_constant" ""))]
- "reload_completed && REGNO (operands[0]) <= 31"
+ (match_operand:SF 1 "const_double_operand" ""))]
+ "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], SFmode) <= 1 && REGNO (operands[0]) <= 31"
[(set (match_dup 2) (match_dup 3))]
"
-{ operands[2] = operand_subword (operands[0], 0, 0, SFmode);
- operands[3] = operand_subword (operands[1], 0, 0, SFmode); }")
-
-(define_insn ""
- [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m")
- (match_operand:SF 1 "input_operand" "f,m,f"))]
+{
+ long l;
+ REAL_VALUE_TYPE rv;
+
+ REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
+ REAL_VALUE_TO_TARGET_SINGLE (rv, l);
+
+ operands[2] = gen_rtx (SUBREG, SImode, operands[0], 0);
+ operands[3] = GEN_INT(l);
+}")
+
+(define_split
+ [(set (match_operand:SF 0 "gpc_reg_operand" "")
+ (match_operand:SF 1 "const_double_operand" ""))]
+ "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], SFmode) == 2 && REGNO (operands[0]) <= 31"
+ [(set (match_dup 2) (match_dup 3))
+ (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 4)))]
+ "
+{
+ long l;
+ REAL_VALUE_TYPE rv;
+
+ REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
+ REAL_VALUE_TO_TARGET_SINGLE (rv, l);
+
+ operands[2] = gen_rtx (SUBREG, SImode, operands[0], 0);
+ operands[3] = GEN_INT(l & 0xffff0000);
+ operands[4] = GEN_INT(l & 0x0000ffff);
+}")
+
+(define_insn "*movsf_hardfloat"
+ [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m,!r,!r")
+ (match_operand:SF 1 "input_operand" "f,m,f,G,Fn"))]
"(gpc_reg_operand (operands[0], SFmode)
|| gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT"
"@
fmr %0,%1
lfs%U1%X1 %0,%1
- stfs%U0%X0 %1,%0"
- [(set_attr "type" "fp,fpload,*")])
+ stfs%U0%X0 %1,%0
+ #
+ #"
+ [(set_attr "type" "fp,fpload,fpstore,*,*")
+ (set_attr "length" "4,4,4,4,8")])
-(define_insn ""
- [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
- (match_operand:SF 1 "input_operand" "r,m,r,I,J,R"))]
+(define_insn "*movsf_softfloat"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
+ (match_operand:SF 1 "input_operand" "r,m,r,I,J,R,G,Fn"))]
"(gpc_reg_operand (operands[0], SFmode)
|| gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT"
"@
{l%U1%X1|lwz%U1%X1} %0,%1
{st%U0%X0|stw%U0%X0} %1,%0
{lil|li} %0,%1
- {liu|lis} %0,%u1
- {cal|la} %0,%1(%*)"
- [(set_attr "type" "*,load,*,*,*,*")])
+ {liu|lis} %0,%v1
+ {cal|la} %0,%1(%*)
+ #
+ #"
+ [(set_attr "type" "*,load,store,*,*,*,*,*")
+ (set_attr "length" "4,4,4,4,4,4,4,8")])
\f
(define_expand "movdf"
""
"
{
- if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+ if (GET_CODE (operands[0]) != REG)
+ operands[1] = force_reg (DFmode, operands[1]);
+
+ /* Stores between FPR and any non-FPR registers must go through a
+ temporary stack slot. */
+
+ if (TARGET_POWERPC64
+ && GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
+ && ((FP_REGNO_P (REGNO (operands[0]))
+ && ! FP_REGNO_P (REGNO (operands[1])))
+ || (FP_REGNO_P (REGNO (operands[1]))
+ && ! FP_REGNO_P (REGNO (operands[0])))))
{
- emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
- operand_subword_force (operands[1], 1, DFmode));
- emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
- operand_subword_force (operands[1], 0, DFmode));
+ rtx stack_slot = assign_stack_temp (DFmode, 8, 0);
+
+ emit_move_insn (stack_slot, operands[1]);
+ emit_move_insn (operands[0], stack_slot);
DONE;
}
- if (GET_CODE (operands[0]) != REG)
- operands[1] = force_reg (DFmode, operands[1]);
-
if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode))
{
operands[1] = force_const_mem (DFmode, operands[1]);
(define_split
[(set (match_operand:DF 0 "gpc_reg_operand" "")
- (match_operand:DF 1 "easy_fp_constant" ""))]
- "reload_completed && REGNO (operands[0]) <= 31"
- [(set (match_dup 2) (match_dup 3))
- (set (match_dup 4) (match_dup 5))]
+ (match_operand:DF 1 "const_int_operand" ""))]
+ "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) <= 1 && REGNO (operands[0]) <= 31"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 1))]
+ "
+{
+ operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
+ operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
+ operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
+}")
+
+(define_split
+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (match_operand:DF 1 "const_int_operand" ""))]
+ "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) >= 2 && REGNO (operands[0]) <= 31"
+ [(set (match_dup 3) (match_dup 5))
+ (set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 6)))]
+ "
+{
+ HOST_WIDE_INT value = INTVAL (operands[1]);
+ operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
+ operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
+ operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
+ operands[5] = GEN_INT (value & 0xffff0000);
+ operands[6] = GEN_INT (value & 0x0000ffff);
+}")
+
+(define_split
+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (match_operand:DF 1 "const_double_operand" ""))]
+ "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) <= 2 && REGNO (operands[0]) <= 31"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))]
+ "
+{
+ operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
+ operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
+
+#ifdef HOST_WORDS_BIG_ENDIAN
+ operands[4] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
+ operands[5] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
+#else
+ operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
+ operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
+#endif
+}")
+
+(define_split
+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (match_operand:DF 1 "const_double_operand" ""))]
+ "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) == 3 && REGNO (operands[0]) <= 31"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))
+ (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 6)))]
+ "
+{
+ HOST_WIDE_INT high;
+ HOST_WIDE_INT low;
+ rtx high_reg = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
+ rtx low_reg = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
+
+#ifdef HOST_WORDS_BIG_ENDIAN
+ high = CONST_DOUBLE_LOW (operands[1]);
+ low = CONST_DOUBLE_HIGH (operands[1]);
+#else
+ high = CONST_DOUBLE_HIGH (operands[1]);
+ low = CONST_DOUBLE_LOW (operands[1]);
+#endif
+
+ if (((unsigned HOST_WIDE_INT) (low + 0x8000) < 0x10000)
+ || (low & 0xffff) == 0)
+ {
+ operands[2] = high_reg;
+ operands[3] = low_reg;
+ operands[4] = GEN_INT (high & 0xffff0000);
+ operands[5] = GEN_INT (low);
+ operands[6] = GEN_INT (high & 0x0000ffff);
+ }
+ else
+ {
+ operands[2] = low_reg;
+ operands[3] = high_reg;
+ operands[4] = GEN_INT (low & 0xffff0000);
+ operands[5] = GEN_INT (high);
+ operands[6] = GEN_INT (low & 0x0000ffff);
+ }
+}")
+
+(define_split
+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (match_operand:DF 1 "const_double_operand" ""))]
+ "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) >= 4 && REGNO (operands[0]) <= 31"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))
+ (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 6)))
+ (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 7)))]
"
-{ operands[2] = operand_subword (operands[0], 0, 0, DFmode);
- operands[3] = operand_subword (operands[1], 0, 0, DFmode);
- operands[4] = operand_subword (operands[0], 1, 0, DFmode);
- operands[5] = operand_subword (operands[1], 1, 0, DFmode); }")
+{
+ HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
+ HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]);
+
+ operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
+ operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
+ operands[4] = GEN_INT (high & 0xffff0000);
+ operands[5] = GEN_INT (low & 0xffff0000);
+ operands[6] = GEN_INT (high & 0x0000ffff);
+ operands[7] = GEN_INT (low & 0x0000ffff);
+}")
+
+(define_split
+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ (match_operand:DF 1 "easy_fp_constant" ""))]
+ "TARGET_64BIT && reload_completed && REGNO (operands[0]) <= 31"
+ [(set (subreg:DI (match_dup 0) 0) (subreg:DI (match_dup 1) 0))]
+ "")
;; Don't have reload use general registers to load a constant. First,
;; it might not work if the output operand has is the equivalent of
;; the constant into an FP register, since it will probably be used there.
;; The "??" is a kludge until we can figure out a more reasonable way
;; of handling these non-offsettable values.
-(define_insn ""
- [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m")
- (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))]
+(define_insn "*movdf_hardfloat32"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,!r,!r,f,f,m")
+ (match_operand:DF 1 "input_operand" "r,o,r,G,H,F,f,m,f"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (register_operand (operands[0], DFmode)
|| register_operand (operands[1], DFmode))"
case 2:
return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
case 3:
- return \"#\";
case 4:
- return \"fmr %0,%1\";
case 5:
- return \"lfd%U1%X1 %0,%1\";
+ return \"#\";
case 6:
+ return \"fmr %0,%1\";
+ case 7:
+ return \"lfd%U1%X1 %0,%1\";
+ case 8:
return \"stfd%U0%X0 %1,%0\";
}
}"
- [(set_attr "type" "*,load,*,*,fp,fpload,*")
- (set_attr "length" "8,8,8,8,*,*,*")])
+ [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
+ (set_attr "length" "8,8,8,8,12,16,*,*,*")])
-(define_insn ""
- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r")
- (match_operand:DF 1 "input_operand" "r,o,r,G"))]
+(define_insn "*movdf_softfloat32"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r,r,r")
+ (match_operand:DF 1 "input_operand" "r,o,r,G,H,F"))]
"! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
&& (register_operand (operands[0], DFmode)
|| register_operand (operands[1], DFmode))"
case 2:
return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
case 3:
+ case 4:
+ case 5:
return \"#\";
}
}"
- [(set_attr "type" "*,load,*,*")
- (set_attr "length" "8,8,8,8")])
+ [(set_attr "type" "*,load,store,*,*,*")
+ (set_attr "length" "8,8,8,8,12,16")])
-(define_insn ""
- [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m")
- (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))]
+(define_insn "*movdf_hardfloat64"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,!r,!r,f,f,m")
+ (match_operand:DF 1 "input_operand" "r,o,r,G,H,F,f,m,f"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (register_operand (operands[0], DFmode)
|| register_operand (operands[1], DFmode))"
"@
mr %0,%1
ld%U1%X1 %0,%1
- sd%U0%X0 %1,%0
+ std%U0%X0 %1,%0
+ #
+ #
#
fmr %0,%1
lfd%U1%X1 %0,%1
stfd%U0%X0 %1,%0"
- [(set_attr "type" "*,load,*,*,fp,fpload,*")])
+ [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
+ (set_attr "length" "4,4,4,8,12,16,4,4,4")])
-(define_insn ""
- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r")
- (match_operand:DF 1 "input_operand" "r,o,r,G"))]
+(define_insn "*movdf_softfloat64"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r,r,r")
+ (match_operand:DF 1 "input_operand" "r,o,r,G,H,F"))]
"TARGET_POWERPC64 && TARGET_SOFT_FLOAT
&& (register_operand (operands[0], DFmode)
|| register_operand (operands[1], DFmode))"
"@
mr %0,%1
ld%U1%X1 %0,%1
- sd%U0%X0 %1,%0
+ std%U0%X0 %1,%0
+ #
+ #
#"
- [(set_attr "type" "*,load,*,*")])
+ [(set_attr "type" "*,load,store,*,*,*")
+ (set_attr "length" "*,*,*,8,12,16")])
\f
;; Next come the multi-word integer load and store and the load and store
;; multiple insns.
(define_expand "movdi"
[(set (match_operand:DI 0 "general_operand" "")
- (match_operand:DI 1 "general_operand" ""))]
+ (match_operand:DI 1 "any_operand" ""))]
""
"
{
- if (GET_CODE (operands[1]) == CONST_DOUBLE
- || GET_CODE (operands[1]) == CONST_INT)
+ if (GET_CODE (operands[0]) != REG)
+ operands[1] = force_reg (DImode, operands[1]);
+
+ if (TARGET_64BIT
+ && (GET_CODE (operands[1]) == CONST_DOUBLE
+ || GET_CODE (operands[1]) == CONST_INT))
{
- emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
- operand_subword (operands[1], 0, 0, DImode));
- emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
- operand_subword (operands[1], 1, 0, DImode));
- DONE;
- }
+ HOST_WIDE_INT low;
+ HOST_WIDE_INT high;
- if (GET_CODE (operands[0]) == MEM)
- operands[1] = force_reg (DImode, operands[1]);
+ if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ {
+ low = CONST_DOUBLE_LOW (operands[1]);
+ high = CONST_DOUBLE_HIGH (operands[1]);
+ }
+ else
+#if HOST_BITS_PER_WIDE_INT == 32
+ {
+ low = INTVAL (operands[1]);
+ high = (low < 0) ? ~0 : 0;
+ }
+#else
+ {
+ low = INTVAL (operands[1]) & 0xffffffff;
+ high = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32;
+ }
+#endif
+
+ if (high)
+ {
+ emit_move_insn (operands[0], GEN_INT (high));
+ emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT(32)));
+ if (low)
+ {
+ HOST_WIDE_INT low_low = low & 0xffff;
+ HOST_WIDE_INT low_high = low & (~ (HOST_WIDE_INT) 0xffff);
+ if (low_high)
+ emit_insn (gen_iordi3 (operands[0], operands[0],
+ GEN_INT (low_high)));
+ if (low_low)
+ emit_insn (gen_iordi3 (operands[0], operands[0],
+ GEN_INT (low_low)));
+ }
+ DONE;
+ }
+ }
/* Stores between FPR and any non-FPR registers must go through a
temporary stack slot. */
}
}")
-(define_insn ""
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m")
- (match_operand:DI 1 "input_operand" "r,m,r,f,m,f"))]
- "! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode)
- || gpc_reg_operand (operands[1], DImode))"
+(define_insn "*movdi_32"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
+ (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
+ "TARGET_32BIT
+ && (gpc_reg_operand (operands[0], DImode)
+ || gpc_reg_operand (operands[1], DImode))"
"*
{
switch (which_alternative)
return \"lfd%U1%X1 %0,%1\";
case 5:
return \"stfd%U0%X0 %1,%0\";
+ case 6:
+ case 7:
+ case 8:
+ case 9:
+ case 10:
+ return \"#\";
}
}"
- [(set_attr "type" "*,load,*,fp,fpload,*")
- (set_attr "length" "8,8,8,*,*,*")])
+ [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
+ (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")])
-(define_insn ""
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,f,f,m,r,*h")
- (match_operand:DI 1 "input_operand" "r,m,r,I,J,R,f,m,f,*h,r"))]
- "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode)
- || gpc_reg_operand (operands[1], DImode))"
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (match_operand:DI 1 "const_int_operand" ""))]
+ "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) <= 1"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 1))]
+ "
+{
+ operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
+ operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
+ operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
+}")
+
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (match_operand:DI 1 "const_int_operand" ""))]
+ "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) >= 2"
+ [(set (match_dup 3) (match_dup 5))
+ (set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 6)))]
+ "
+{
+ HOST_WIDE_INT value = INTVAL (operands[1]);
+ operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
+ operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
+ operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
+ operands[5] = GEN_INT (value & 0xffff0000);
+ operands[6] = GEN_INT (value & 0x0000ffff);
+}")
+
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (match_operand:DI 1 "const_double_operand" ""))]
+ "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) <= 2"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))]
+ "
+{
+ operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
+ operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
+ operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
+ operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
+}")
+
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (match_operand:DI 1 "const_double_operand" ""))]
+ "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) == 3"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))
+ (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 6)))]
+ "
+{
+ HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
+ HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]);
+ rtx high_reg = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
+ rtx low_reg = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
+
+ if (((unsigned HOST_WIDE_INT) (low + 0x8000) < 0x10000)
+ || (low & 0xffff) == 0)
+ {
+ operands[2] = high_reg;
+ operands[3] = low_reg;
+ operands[4] = GEN_INT (high & 0xffff0000);
+ operands[5] = GEN_INT (low);
+ operands[6] = GEN_INT (high & 0x0000ffff);
+ }
+ else
+ {
+ operands[2] = low_reg;
+ operands[3] = high_reg;
+ operands[4] = GEN_INT (low & 0xffff0000);
+ operands[5] = GEN_INT (high);
+ operands[6] = GEN_INT (low & 0x0000ffff);
+ }
+}")
+
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (match_operand:DI 1 "const_double_operand" ""))]
+ "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) >= 4"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))
+ (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 6)))
+ (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 7)))]
+ "
+{
+ HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
+ HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]);
+
+ operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
+ operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
+ operands[4] = GEN_INT (high & 0xffff0000);
+ operands[5] = GEN_INT (low & 0xffff0000);
+ operands[6] = GEN_INT (high & 0x0000ffff);
+ operands[7] = GEN_INT (low & 0x0000ffff);
+}")
+
+(define_insn "*movdi_64"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
+ (match_operand:DI 1 "input_operand" "r,m,r,I,J,nF,R,f,m,f,*h,r,0"))]
+ "TARGET_64BIT
+ && (gpc_reg_operand (operands[0], DImode)
+ || gpc_reg_operand (operands[1], DImode))"
"@
mr %0,%1
ld%U1%X1 %0,%1
- sd%U0%X0 %1,%0
+ std%U0%X0 %1,%0
li %0,%1
- lis %0,%u1
+ lis %0,%v1
+ #
{cal|la} %0,%1(%*)
fmr %0,%1
lfd%U1%X1 %0,%1
stfd%U0%X0 %1,%0
mf%1 %0
- mt%0 %1"
- [(set_attr "type" "*,load,*,*,*,*,fp,fpload,*,*,mtjmpr")])
+ mt%0 %1
+ cror 0,0,0"
+ [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
+ (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
+
+;; Split a load of a large constant into the appropriate five-instruction
+;; sequence. The expansion in movdi tries to perform the minimum number of
+;; steps, but here we have to handle anything in a constant number of insns.
+
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (match_operand:DI 1 "const_double_operand" ""))]
+ "TARGET_64BIT && num_insns_constant (operands[1], DImode) > 1"
+ [(set (match_dup 0)
+ (match_dup 2))
+ (set (match_dup 0)
+ (ior:DI (match_dup 0)
+ (match_dup 3)))
+ (set (match_dup 0)
+ (ashift:DI (match_dup 0)
+ (const_int 32)))
+ (set (match_dup 0)
+ (ior:DI (match_dup 0)
+ (match_dup 4)))
+ (set (match_dup 0)
+ (ior:DI (match_dup 0)
+ (match_dup 5)))]
+ "
+{
+ HOST_WIDE_INT low;
+ HOST_WIDE_INT high;
+
+ if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ {
+ low = CONST_DOUBLE_LOW (operands[1]);
+ high = CONST_DOUBLE_HIGH (operands[1]);
+ }
+ else
+#if HOST_BITS_PER_WIDE_INT == 32
+ {
+ low = INTVAL (operands[1]);
+ high = (low < 0) ? ~0 : 0;
+ }
+#else
+ {
+ low = INTVAL (operands[1]) & 0xffffffff;
+ high = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32;
+ }
+#endif
+
+ if ((high + 0x8000) < 0x10000
+ && ((low & 0xffff) == 0 || (low & (~ (HOST_WIDE_INT) 0xffff)) == 0))
+ FAIL;
+
+ operands[2] = GEN_INT (high & (~ (HOST_WIDE_INT) 0xffff));
+ operands[3] = GEN_INT (high & 0xffff);
+ operands[4] = GEN_INT (low & (~ (HOST_WIDE_INT) 0xffff));
+ operands[5] = GEN_INT (low & 0xffff);
+}")
+
+(define_insn ""
+ [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+ (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
+ "TARGET_POWERPC64"
+ "mr. %0,%1"
+ [(set_attr "type" "compare")])
\f
;; TImode is similar, except that we usually want to compute the address into
;; a register and use lsi/stsi (the exception is during reload). MQ is also
[(parallel [(set (match_operand:TI 0 "general_operand" "")
(match_operand:TI 1 "general_operand" ""))
(clobber (scratch:SI))])]
- "TARGET_MULTIPLE || TARGET_POWERPC64"
+ "TARGET_STRING || TARGET_POWERPC64"
"
{
if (GET_CODE (operands[0]) == MEM)
[(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
(match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
(clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
- "TARGET_MULTIPLE && TARGET_POWER && ! TARGET_POWERPC64
+ "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
"*
{
return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
}
}"
- [(set_attr "type" "*,load,load,*,*")
+ [(set_attr "type" "store,store,*,load,load")
(set_attr "length" "*,16,16,*,16")])
(define_insn ""
[(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
(match_operand:TI 1 "reg_or_mem_operand" "r,r,m"))
(clobber (match_scratch:SI 2 "=X,X,X"))]
- "TARGET_MULTIPLE && !TARGET_POWER && ! TARGET_POWERPC64
+ "TARGET_STRING && !TARGET_POWER && ! TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
"*
{
return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
}
}"
- [(set_attr "type" "load,*,*")
+ [(set_attr "type" "store,*,load")
(set_attr "length" "16,16,16")])
(define_insn ""
return \"std%U0 %1,%0\;std %L1,%L0\";
}
}"
- [(set_attr "type" "*,load,*")
+ [(set_attr "type" "*,load,store")
(set_attr "length" "8,8,8")])
\f
(define_expand "load_multiple"
[(match_par_dup 3 [(set (match_operand:SI 0 "" "")
(match_operand:SI 1 "" ""))
(use (match_operand:SI 2 "" ""))])]
- "TARGET_MULTIPLE"
+ "TARGET_STRING"
"
{
int regno;
(define_insn ""
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "gpc_reg_operand" "=r")
- (match_operand:SI 2 "indirect_operand" "Q"))])]
- "TARGET_MULTIPLE"
+ (mem:SI (match_operand:SI 2 "register_operand" "b")))])]
+ "TARGET_STRING"
"*
{
/* We have to handle the case where the pseudo used to contain the address
- is assigned to one of the output registers. In that case, do the
- lsi, but then load the correct value. This is a bit of a mess, but is
- the best we can do.
- We set the length attribute to the maximum possible size (8 bytes). */
- static char result[100];
- char newload[40];
- int i;
+ is assigned to one of the output registers. */
+ int i, j;
+ int words = XVECLEN (operands[0], 0);
+ rtx xop[10];
- strcpy (result, \"{lsi|lswi} %1,%P2,%N0\");
- for (i = 0; i < XVECLEN (operands[0], 0); i++)
+ if (XVECLEN (operands[0], 0) == 1)
+ return \"{l|lwz} %1,0(%2)\";
+
+ for (i = 0; i < words; i++)
if (refers_to_regno_p (REGNO (operands[1]) + i,
REGNO (operands[1]) + i + 1, operands[2], 0))
{
- sprintf (newload, \"\;{l|lwz} %d,%d(%d)\",
- REGNO (operands[1]) + i,
- i * 4, REGNO (XEXP (operands[2], 0)));
- strcat (result, newload);
+ if (i == words-1)
+ {
+ xop[0] = operands[1];
+ xop[1] = operands[2];
+ xop[2] = GEN_INT (4 * (words-1));
+ output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop);
+ return \"\";
+ }
+ else if (i == 0)
+ {
+ xop[0] = operands[1];
+ xop[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+ xop[2] = GEN_INT (4 * (words-1));
+ output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop);
+ return \"\";
+ }
+ else
+ {
+ for (j = 0; j < words; j++)
+ if (j != i)
+ {
+ xop[0] = gen_rtx (REG, SImode, REGNO (operands[1]) + j);
+ xop[1] = operands[2];
+ xop[2] = GEN_INT (j * 4);
+ output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop);
+ }
+ xop[0] = operands[2];
+ xop[1] = GEN_INT (i * 4);
+ output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop);
+ return \"\";
+ }
}
- return result;
+ return \"{lsi|lswi} %1,%2,%N0\";
}"
[(set_attr "type" "load")
- (set_attr "length" "8")])
-\f
+ (set_attr "length" "32")])
+\f
(define_expand "store_multiple"
[(match_par_dup 3 [(set (match_operand:SI 0 "" "")
(match_operand:SI 1 "" ""))
(clobber (scratch:SI))
(use (match_operand:SI 2 "" ""))])]
- "TARGET_MULTIPLE"
+ "TARGET_STRING"
"
{
int regno;
[(set (match_operand:SI 1 "indirect_operand" "=Q")
(match_operand:SI 2 "gpc_reg_operand" "r"))
(clobber (match_scratch:SI 3 "=q"))])]
- "TARGET_MULTIPLE && TARGET_POWER"
- "{stsi|stswi} %2,%P1,%O0")
+ "TARGET_STRING && TARGET_POWER"
+ "{stsi|stswi} %2,%P1,%O0"
+ [(set_attr "type" "store")])
(define_insn ""
[(match_parallel 0 "store_multiple_operation"
- [(set (match_operand:SI 1 "indirect_operand" "=Q")
+ [(set (mem:SI (match_operand:SI 1 "register_operand" "b"))
(match_operand:SI 2 "gpc_reg_operand" "r"))
(clobber (match_scratch:SI 3 "X"))])]
- "TARGET_MULTIPLE && !TARGET_POWER"
- "{stsi|stswi} %2,%P1,%O0")
+ "TARGET_STRING && !TARGET_POWER"
+ "{stsi|stswi} %2,%1,%O0"
+ [(set_attr "type" "store")])
+
+\f
+;; String/block move insn.
+;; Argument 0 is the destination
+;; Argument 1 is the source
+;; Argument 2 is the length
+;; Argument 3 is the alignment
+
+(define_expand "movstrsi"
+ [(parallel [(set (match_operand:BLK 0 "" "")
+ (match_operand:BLK 1 "" ""))
+ (use (match_operand:SI 2 "" ""))
+ (use (match_operand:SI 3 "" ""))])]
+ ""
+ "
+{
+ if (expand_block_move (operands))
+ DONE;
+ else
+ FAIL;
+}")
+
+;; Move up to 32 bytes at a time. The fixed registers are needed because the
+;; register allocator doesn't have a clue about allocating 8 word registers
+(define_expand "movstrsi_8reg"
+ [(parallel [(set (match_operand 0 "" "")
+ (match_operand 1 "" ""))
+ (use (match_operand 2 "" ""))
+ (use (match_operand 3 "" ""))
+ (clobber (reg:SI 5))
+ (clobber (reg:SI 6))
+ (clobber (reg:SI 7))
+ (clobber (reg:SI 8))
+ (clobber (reg:SI 9))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 4 ""))])]
+ "TARGET_STRING"
+ "")
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "b")))
+ (use (match_operand:SI 2 "immediate_operand" "i"))
+ (use (match_operand:SI 3 "immediate_operand" "i"))
+ (clobber (match_operand:SI 4 "register_operand" "=r"))
+ (clobber (reg:SI 6))
+ (clobber (reg:SI 7))
+ (clobber (reg:SI 8))
+ (clobber (reg:SI 9))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 5 "=q"))]
+ "TARGET_STRING && TARGET_POWER
+ && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0)
+ && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
+ && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
+ && REGNO (operands[4]) == 5"
+ "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "b")))
+ (use (match_operand:SI 2 "immediate_operand" "i"))
+ (use (match_operand:SI 3 "immediate_operand" "i"))
+ (clobber (match_operand:SI 4 "register_operand" "=r"))
+ (clobber (reg:SI 6))
+ (clobber (reg:SI 7))
+ (clobber (reg:SI 8))
+ (clobber (reg:SI 9))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 5 "X"))]
+ "TARGET_STRING && !TARGET_POWER
+ && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0)
+ && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
+ && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
+ && REGNO (operands[4]) == 5"
+ "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
+
+;; Move up to 24 bytes at a time. The fixed registers are needed because the
+;; register allocator doesn't have a clue about allocating 6 word registers
+(define_expand "movstrsi_6reg"
+ [(parallel [(set (match_operand 0 "" "")
+ (match_operand 1 "" ""))
+ (use (match_operand 2 "" ""))
+ (use (match_operand 3 "" ""))
+ (clobber (reg:SI 7))
+ (clobber (reg:SI 8))
+ (clobber (reg:SI 9))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 4 ""))])]
+ "TARGET_STRING"
+ "")
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "b")))
+ (use (match_operand:SI 2 "immediate_operand" "i"))
+ (use (match_operand:SI 3 "immediate_operand" "i"))
+ (clobber (match_operand:SI 4 "register_operand" "=r"))
+ (clobber (reg:SI 8))
+ (clobber (reg:SI 9))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 5 "=q"))]
+ "TARGET_STRING && TARGET_POWER
+ && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
+ && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12)
+ && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
+ && REGNO (operands[4]) == 7"
+ "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "b")))
+ (use (match_operand:SI 2 "immediate_operand" "i"))
+ (use (match_operand:SI 3 "immediate_operand" "i"))
+ (clobber (match_operand:SI 4 "register_operand" "=r"))
+ (clobber (reg:SI 8))
+ (clobber (reg:SI 9))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 5 "X"))]
+ "TARGET_STRING && !TARGET_POWER
+ && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
+ && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12)
+ && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
+ && REGNO (operands[4]) == 7"
+ "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
+
+;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill problems
+;; with TImode
+(define_expand "movstrsi_4reg"
+ [(parallel [(set (match_operand 0 "" "")
+ (match_operand 1 "" ""))
+ (use (match_operand 2 "" ""))
+ (use (match_operand 3 "" ""))
+ (clobber (reg:SI 9))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 4 ""))])]
+ "TARGET_STRING"
+ "")
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "b")))
+ (use (match_operand:SI 2 "immediate_operand" "i"))
+ (use (match_operand:SI 3 "immediate_operand" "i"))
+ (clobber (match_operand:SI 4 "register_operand" "=r"))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 5 "=q"))]
+ "TARGET_STRING && TARGET_POWER
+ && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
+ && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12)
+ && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
+ && REGNO (operands[4]) == 9"
+ "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "b")))
+ (use (match_operand:SI 2 "immediate_operand" "i"))
+ (use (match_operand:SI 3 "immediate_operand" "i"))
+ (clobber (match_operand:SI 4 "register_operand" "=r"))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 5 "X"))]
+ "TARGET_STRING && !TARGET_POWER
+ && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
+ && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12)
+ && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
+ && REGNO (operands[4]) == 9"
+ "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
+
+;; Move up to 8 bytes at a time.
+(define_expand "movstrsi_2reg"
+ [(parallel [(set (match_operand 0 "" "")
+ (match_operand 1 "" ""))
+ (use (match_operand 2 "" ""))
+ (use (match_operand 3 "" ""))
+ (clobber (match_scratch:DI 4 ""))
+ (clobber (match_scratch:SI 5 ""))])]
+ "TARGET_STRING && !TARGET_64BIT"
+ "")
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "b")))
+ (use (match_operand:SI 2 "immediate_operand" "i"))
+ (use (match_operand:SI 3 "immediate_operand" "i"))
+ (clobber (match_scratch:DI 4 "=&r"))
+ (clobber (match_scratch:SI 5 "=q"))]
+ "TARGET_STRING && TARGET_POWER && !TARGET_64BIT
+ && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
+ "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "b")))
+ (use (match_operand:SI 2 "immediate_operand" "i"))
+ (use (match_operand:SI 3 "immediate_operand" "i"))
+ (clobber (match_scratch:DI 4 "=&r"))
+ (clobber (match_scratch:SI 5 "X"))]
+ "TARGET_STRING && !TARGET_POWER && !TARGET_64BIT
+ && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
+ "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
+
+;; Move up to 4 bytes at a time.
+(define_expand "movstrsi_1reg"
+ [(parallel [(set (match_operand 0 "" "")
+ (match_operand 1 "" ""))
+ (use (match_operand 2 "" ""))
+ (use (match_operand 3 "" ""))
+ (clobber (match_scratch:SI 4 ""))
+ (clobber (match_scratch:SI 5 ""))])]
+ "TARGET_STRING"
+ "")
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "b")))
+ (use (match_operand:SI 2 "immediate_operand" "i"))
+ (use (match_operand:SI 3 "immediate_operand" "i"))
+ (clobber (match_scratch:SI 4 "=&r"))
+ (clobber (match_scratch:SI 5 "=q"))]
+ "TARGET_STRING && TARGET_POWER
+ && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
+ "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "b")))
+ (use (match_operand:SI 2 "immediate_operand" "i"))
+ (use (match_operand:SI 3 "immediate_operand" "i"))
+ (clobber (match_scratch:SI 4 "=&r"))
+ (clobber (match_scratch:SI 5 "X"))]
+ "TARGET_STRING && !TARGET_POWER
+ && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
+ "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
+
\f
-;; Define insns that do load or store with update. Some of these we can
+;; Define insns that do load or store with update. Some of these we can
;; get by using pre-decrement or pre-increment, but the hardware can also
;; do cases where the increment is not the size of the object.
;;
"lwaux %3,%0,%2"
[(set_attr "type" "load")])
-(define_insn ""
+(define_insn "movdi_update"
[(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
(match_operand:DI 2 "reg_or_short_operand" "r,I")))
(match_operand:DI 3 "gpc_reg_operand" "r,r"))
"TARGET_POWERPC64"
"@
stdux %3,%0,%2
- stdu %3,%2(%0)")
+ stdu %3,%2(%0)"
+ [(set_attr "type" "store")])
(define_insn ""
[(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
{lu|lwzu} %3,%2(%0)"
[(set_attr "type" "load")])
-(define_insn ""
+(define_insn "movsi_update"
[(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
(match_operand:SI 2 "reg_or_short_operand" "r,I")))
(match_operand:SI 3 "gpc_reg_operand" "r,r"))
""
"@
{stux|stwux} %3,%0,%2
- {stu|stwu} %3,%2(%0)")
+ {stu|stwu} %3,%2(%0)"
+ [(set_attr "type" "store")])
(define_insn ""
[(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
""
"@
sthux %3,%0,%2
- sthu %3,%2(%0)")
+ sthu %3,%2(%0)"
+ [(set_attr "type" "store")])
(define_insn ""
[(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
""
"@
stbux %3,%0,%2
- stbu %3,%2(%0)")
+ stbu %3,%2(%0)"
+ [(set_attr "type" "store")])
(define_insn ""
[(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
"TARGET_HARD_FLOAT"
"@
stfsux %3,%0,%2
- stfsu %3,%2(%0)")
+ stfsu %3,%2(%0)"
+ [(set_attr "type" "fpstore")])
(define_insn ""
[(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
"TARGET_HARD_FLOAT"
"@
stfdux %3,%0,%2
- stfdu %3,%2(%0)")
+ stfdu %3,%2(%0)"
+ [(set_attr "type" "fpstore")])
;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
;; Next come insns related to the calling sequence.
;;
;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
-;; We move the back-chain and decrement the stack pointer.
+;; We move the back-chain and decrement the stack pointer.
(define_expand "allocate_stack"
[(set (reg:SI 1)
(minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_short_operand" "")))]
""
"
-{ rtx chain = gen_reg_rtx (SImode);
+{ rtx chain = gen_reg_rtx (Pmode);
rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
+ rtx neg_op0;
emit_move_insn (chain, stack_bot);
- emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[0]));
- emit_move_insn (stack_bot, chain);
+
+ /* Under Windows NT, we need to add stack probes for large/variable allocations,
+ so do it via a call to the external function alloca, instead of doing it
+ inline. */
+ if (DEFAULT_ABI == ABI_NT
+ && (GET_CODE (operands[0]) != CONST_INT || INTVAL (operands[0]) > 4096))
+ {
+ rtx tmp = gen_reg_rtx (SImode);
+ emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"__allocate_stack\"),
+ tmp, 0, SImode, 1, operands[0], Pmode);
+ emit_insn (gen_set_sp (tmp));
+ DONE;
+ }
+
+ if (GET_CODE (operands[0]) != CONST_INT
+ || INTVAL (operands[0]) < -32767
+ || INTVAL (operands[0]) > 32768)
+ {
+ neg_op0 = gen_reg_rtx (Pmode);
+ if (TARGET_32BIT)
+ emit_insn (gen_negsi2 (neg_op0, operands[0]));
+ else
+ emit_insn (gen_negdi2 (neg_op0, operands[0]));
+ }
+ else
+ neg_op0 = GEN_INT (- INTVAL (operands[0]));
+
+ if (TARGET_32BIT)
+ emit_insn (gen_movsi_update (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
+ else
+ emit_insn (gen_movdi_update (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
+
DONE;
}")
+;; Marker to indicate that the stack pointer was changed under NT in
+;; ways not known to the compiler
+
+(define_insn "set_sp"
+ [(set (reg:SI 1)
+ (unspec [(match_operand:SI 0 "register_operand" "r")] 7))]
+ ""
+ ""
+ [(set_attr "length" "0")])
+
;; These patterns say how to save and restore the stack pointer. We need not
;; save the stack pointer at function level since we are careful to
;; preserve the backchain. At block level, we have to restore the backchain
emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]);
DONE;
}")
-
+
(define_expand "restore_stack_nonlocal"
[(match_operand:SI 0 "register_operand" "")
(match_operand:DI 1 "memory_operand" "")]
emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp);
DONE;
}")
+
\f
-;; A function pointer is a pointer to a data area whose first word contains
-;; the actual address of the function, whose second word contains a pointer
-;; to its TOC, and whose third word contains a value to place in the static
-;; chain register (r11). Note that if we load the static chain, our
+;; A function pointer under AIX is a pointer to a data area whose first word
+;; contains the actual address of the function, whose second word contains a
+;; pointer to its TOC, and whose third word contains a value to place in the
+;; static chain register (r11). Note that if we load the static chain, our
;; "trampoline" need not have any executable code.
;;
-;; operands[0] is an SImode pseudo in which we place the address of the
-;; function.
-;; operands[1] is the address of data area of the function to call
+;; operands[0] is a register pointing to the 3 word descriptor (aka, the function address)
+;; operands[1] is the stack size to clean up
+;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for AIX)
+;; operands[3] is location to store the TOC
+;; operands[4] is the TOC register
+;; operands[5] is the static chain register
+;;
+;; We do not break this into separate insns, so that the scheduler will not try
+;; to move the load of the new TOC before any loads from the TOC.
+
+(define_insn "call_indirect_aix"
+ [(call (mem:SI (match_operand:SI 0 "register_operand" "b"))
+ (match_operand 1 "const_int_operand" "n"))
+ (use (match_operand 2 "const_int_operand" "n"))
+ (use (match_operand 3 "offsettable_addr_operand" "p"))
+ (use (match_operand 4 "register_operand" "r"))
+ (clobber (match_operand 5 "register_operand" "=r"))
+ (clobber (match_scratch:SI 6 "=&r"))
+ (clobber (match_scratch:SI 7 "=l"))]
+ "DEFAULT_ABI == ABI_AIX
+ && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)"
+ "{st|stw} %4,%a3\;{l|lwz} %6,0(%0)\;{l|lwz} %4,4(%0)\;mt%7 %6\;{l|lwz} %5,8(%0)\;{brl|blrl}\;{l|lwz} %4,%a3"
+ [(set_attr "type" "load")
+ (set_attr "length" "28")])
+
+(define_insn "call_value_indirect_aix"
+ [(set (match_operand 0 "register_operand" "fg")
+ (call (mem:SI (match_operand:SI 1 "register_operand" "b"))
+ (match_operand 2 "const_int_operand" "n")))
+ (use (match_operand 3 "const_int_operand" "n"))
+ (use (match_operand 4 "offsettable_addr_operand" "p"))
+ (use (match_operand 5 "register_operand" "r"))
+ (clobber (match_operand 6 "register_operand" "=r"))
+ (clobber (match_scratch:SI 7 "=&r"))
+ (clobber (match_scratch:SI 8 "=l"))]
+ "DEFAULT_ABI == ABI_AIX
+ && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)"
+ "{st|stw} %5,%a4\;{l|lwz} %7,0(%1)\;{l|lwz} %5,4(%1);\;mt%8 %7\;{l|lwz} %6,8(%1)\;{brl|blrl}\;{l|lwz} %5,%a4"
+ [(set_attr "type" "load")
+ (set_attr "length" "28")])
-(define_expand "call_via_ptr"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
- (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
- (reg:SI 2))
- (set (reg:SI 2)
- (mem:SI (plus:SI (match_dup 1)
- (const_int 4))))
- (set (reg:SI 11)
- (mem:SI (plus:SI (match_dup 1)
- (const_int 8))))
- (use (reg:SI 2))
- (use (reg:SI 11))]
- ""
- "")
+;; A function pointer undef NT is a pointer to a data area whose first word
+;; contains the actual address of the function, whose second word contains a
+;; pointer to its TOC. The static chain is not stored under NT, which means
+;; that we need a trampoline.
+;;
+;; operands[0] is an SImode pseudo in which we place the address of the function.
+;; operands[1] is the stack size to clean up
+;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for NT)
+;; operands[3] is location to store the TOC
+;; operands[4] is the TOC register
+;;
+;; We do not break this into separate insns, so that the scheduler will not try
+;; to move the load of the new TOC before any loads from the TOC.
+
+(define_insn "call_indirect_nt"
+ [(call (mem:SI (match_operand:SI 0 "register_operand" "b"))
+ (match_operand 1 "const_int_operand" "n"))
+ (use (match_operand 2 "const_int_operand" "n"))
+ (use (match_operand 3 "offsettable_addr_operand" "p"))
+ (use (match_operand 4 "register_operand" "r"))
+ (clobber (match_scratch:SI 5 "=&r"))
+ (clobber (match_scratch:SI 6 "=l"))]
+ "DEFAULT_ABI == ABI_NT
+ && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)"
+ "{st|stw} %4,%a3\;{l|lwz} %5,0(%0)\;{l|lwz} %4,4(%0)\;mt%6 %5\;{brl|blrl}\;{l|lwz} %4,%a3"
+ [(set_attr "type" "load")
+ (set_attr "length" "24")])
+
+(define_insn "call_value_indirect_nt"
+ [(set (match_operand 0 "register_operand" "fg")
+ (call (mem:SI (match_operand:SI 1 "register_operand" "b"))
+ (match_operand 2 "const_int_operand" "n")))
+ (use (match_operand 3 "const_int_operand" "n"))
+ (use (match_operand 4 "offsettable_addr_operand" "p"))
+ (use (match_operand 5 "register_operand" "r"))
+ (clobber (match_scratch:SI 6 "=&r"))
+ (clobber (match_scratch:SI 7 "=l"))]
+ "DEFAULT_ABI == ABI_NT
+ && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)"
+ "{st|stw} %5,%a4\;{l|lwz} %6,0(%1)\;{l|lwz} %5,4(%1)\;mt%7 %6\;{brl|blrl}\;{l|lwz} %5,%a4"
+ [(set_attr "type" "load")
+ (set_attr "length" "24")])
+;; A function pointer under System V is just a normal pointer
+;; operands[0] is the function pointer
+;; operands[1] is the stack size to clean up
+;; operands[2] is the value FUNCTION_ARG returns for the VOID argument which indicates how to set cr1
+
+(define_insn "call_indirect_sysv"
+ [(call (mem:SI (match_operand:SI 0 "register_operand" "l,l"))
+ (match_operand 1 "const_int_operand" "n,n"))
+ (use (match_operand 2 "const_int_operand" "O,n"))
+ (clobber (match_scratch:SI 3 "=l,l"))]
+ "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC"
+ "*
+{
+ if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
+ output_asm_insn (\"crxor 6,6,6\", operands);
+
+ else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
+ output_asm_insn (\"creqv 6,6,6\", operands);
+
+ return \"{brl|blrl}\";
+}"
+ [(set_attr "type" "jmpreg")
+ (set_attr "length" "4,8")])
+
+(define_insn "call_value_indirect_sysv"
+ [(set (match_operand 0 "register_operand" "=fg,fg")
+ (call (mem:SI (match_operand:SI 1 "register_operand" "l,l"))
+ (match_operand 2 "const_int_operand" "n,n")))
+ (use (match_operand 3 "const_int_operand" "O,n"))
+ (clobber (match_scratch:SI 4 "=l,l"))]
+ "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC"
+ "*
+{
+ if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
+ output_asm_insn (\"crxor 6,6,6\", operands);
+
+ else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
+ output_asm_insn (\"creqv 6,6,6\", operands);
+
+ return \"{brl|blrl}\";
+}"
+ [(set_attr "type" "jmpreg")
+ (set_attr "length" "4,8")])
+
+;; Now the definitions for the call and call_value insns
(define_expand "call"
[(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" ""))
(match_operand 1 "" ""))
+ (use (match_operand 2 "" ""))
(clobber (scratch:SI))])]
""
"
abort ();
operands[0] = XEXP (operands[0], 0);
- if (GET_CODE (operands[0]) != SYMBOL_REF)
+
+ /* Convert NT DLL imports into an indirect call. */
+ if (GET_CODE (operands[0]) == SYMBOL_REF
+ && (INTVAL (operands[2]) & CALL_NT_DLLIMPORT) != 0)
+ {
+ operands[0] = rs6000_dll_import_ref (operands[0]);
+ operands[2] = GEN_INT ((int)CALL_NORMAL);
+ }
+
+ if (GET_CODE (operands[0]) != SYMBOL_REF
+ || (INTVAL (operands[2]) & CALL_LONG) != 0)
{
-#ifndef USING_SVR4_H
- /* AIX function pointers are really pointers to a three word area */
- rtx temp = gen_reg_rtx (SImode);
+ if (INTVAL (operands[2]) & CALL_LONG)
+ operands[0] = rs6000_longcall_ref (operands[0]);
- emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0])));
- operands[0] = temp;
-#endif /* !USING_SVR4_H */
+ if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS)
+ emit_call_insn (gen_call_indirect_sysv (force_reg (Pmode, operands[0]),
+ operands[1], operands[2]));
+ else
+ {
+ rtx toc_reg = gen_rtx (REG, Pmode, 2);
+ rtx toc_addr = RS6000_SAVE_TOC;
+
+ if (DEFAULT_ABI == ABI_AIX)
+ {
+ /* AIX function pointers are really pointers to a three word area */
+ rtx static_chain = gen_rtx (REG, Pmode, STATIC_CHAIN_REGNUM);
+ emit_call_insn (gen_call_indirect_aix (force_reg (Pmode, operands[0]),
+ operands[1], operands[2],
+ toc_addr, toc_reg, static_chain));
+ }
+ else if (DEFAULT_ABI == ABI_NT)
+ {
+ /* NT function pointers are really pointers to a two word area */
+ emit_call_insn (gen_call_indirect_nt (force_reg (Pmode, operands[0]),
+ operands[1], operands[2],
+ toc_addr, toc_reg));
+ }
+ else
+ abort ();
+ }
+ DONE;
}
}")
[(parallel [(set (match_operand 0 "" "")
(call (mem:SI (match_operand:SI 1 "address_operand" ""))
(match_operand 2 "" "")))
+ (use (match_operand 3 "" ""))
(clobber (scratch:SI))])]
""
"
abort ();
operands[1] = XEXP (operands[1], 0);
- if (GET_CODE (operands[1]) != SYMBOL_REF)
+
+ /* Convert NT DLL imports into an indirect call. */
+ if (GET_CODE (operands[1]) == SYMBOL_REF
+ && (INTVAL (operands[3]) & CALL_NT_DLLIMPORT) != 0)
+ {
+ operands[1] = rs6000_dll_import_ref (operands[1]);
+ operands[3] = GEN_INT ((int)CALL_NORMAL);
+ }
+
+ if (GET_CODE (operands[1]) != SYMBOL_REF
+ || (INTVAL (operands[3]) & CALL_LONG) != 0)
{
-#ifndef USING_SVR4_H
- /* AIX function pointers are really pointers to a three word area */
- rtx temp = gen_reg_rtx (SImode);
+ if (INTVAL (operands[2]) & CALL_LONG)
+ operands[1] = rs6000_longcall_ref (operands[1]);
- emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1])));
- operands[1] = temp;
-#endif /* !USING_SVR4_H */
+ if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS)
+ emit_call_insn (gen_call_value_indirect_sysv (operands[0], operands[1],
+ operands[2], operands[3]));
+ else
+ {
+ rtx toc_reg = gen_rtx (REG, Pmode, 2);
+ rtx toc_addr = RS6000_SAVE_TOC;
+
+ if (DEFAULT_ABI == ABI_AIX)
+ {
+ /* AIX function pointers are really pointers to a three word area */
+ rtx static_chain = gen_rtx (REG, Pmode, STATIC_CHAIN_REGNUM);
+ emit_call_insn (gen_call_value_indirect_aix (operands[0],
+ force_reg (Pmode, operands[1]),
+ operands[2], operands[3],
+ toc_addr, toc_reg, static_chain));
+ }
+ else if (DEFAULT_ABI == ABI_NT)
+ {
+ /* NT function pointers are really pointers to a two word area */
+ emit_call_insn (gen_call_value_indirect_nt (operands[0],
+ force_reg (Pmode, operands[1]),
+ operands[2], operands[3],
+ toc_addr, toc_reg));
+ }
+ else
+ abort ();
+ }
+ DONE;
}
}")
;; Call to function in current module. No TOC pointer reload needed.
+;; Operand2 is non-zero if we are using the V.4 calling sequence and
+;; either the function was not prototyped, or it was prototyped as a
+;; variable argument function. It is > 0 if FP registers were passed
+;; and < 0 if they were not.
(define_insn ""
- [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s"))
- (match_operand 1 "" "g"))
- (clobber (match_scratch:SI 2 "=l"))]
- ""
- "bl %z0")
+ [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
+ (match_operand 1 "" "g,g"))
+ (use (match_operand:SI 2 "immediate_operand" "O,n"))
+ (clobber (match_scratch:SI 3 "=l,l"))]
+ "(INTVAL (operands[2]) & CALL_LONG) == 0"
+ "*
+{
+ if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
+ output_asm_insn (\"crxor 6,6,6\", operands);
+
+ else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
+ output_asm_insn (\"creqv 6,6,6\", operands);
+
+ return \"bl %z0\";
+}"
+ [(set_attr "type" "branch")
+ (set_attr "length" "4,8")])
;; Call to function which may be in another module. Restore the TOC
;; pointer (r2) after the call unless this is System V.
+;; Operand2 is non-zero if we are using the V.4 calling sequence and
+;; either the function was not prototyped, or it was prototyped as a
+;; variable argument function. It is > 0 if FP registers were passed
+;; and < 0 if they were not.
(define_insn ""
- [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s"))
+ [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s"))
(match_operand 1 "" "fg,fg"))
- (clobber (match_scratch:SI 2 "=l,l"))]
- ""
+ (use (match_operand:SI 2 "immediate_operand" "O,n"))
+ (clobber (match_scratch:SI 3 "=l,l"))]
+ "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
+ && (INTVAL (operands[2]) & CALL_LONG) == 0"
"*
{
+ /* Indirect calls should go through call_indirect */
if (GET_CODE (operands[0]) == REG)
- {
-#ifndef USING_SVR4_H
- return \"{brl|blrl}\;{l|lwz} 2,20(1)\";
-#else
- return \"{brl|blrl}\";
-#endif
- }
+ abort ();
- return \"bl %z0\;%.\";
+ if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
+ output_asm_insn (\"crxor 6,6,6\", operands);
+
+ else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
+ output_asm_insn (\"creqv 6,6,6\", operands);
+
+ return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\";
}"
- [(set_attr "length" "8")])
+ [(set_attr "type" "branch")
+ (set_attr "length" "8,12")])
(define_insn ""
- [(set (match_operand 0 "" "=fg")
- (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s"))
- (match_operand 2 "" "g")))
- (clobber (match_scratch:SI 3 "=l"))]
- ""
- "bl %z1")
+ [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s"))
+ (match_operand 1 "" "fg,fg"))
+ (use (match_operand:SI 2 "immediate_operand" "O,n"))
+ (clobber (match_scratch:SI 3 "=l,l"))]
+ "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
+ && (INTVAL (operands[2]) & CALL_LONG) == 0"
+ "*
+{
+ /* Indirect calls should go through call_indirect */
+ if (GET_CODE (operands[0]) == REG)
+ abort ();
+
+ if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
+ output_asm_insn (\"crxor 6,6,6\", operands);
+
+ else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
+ output_asm_insn (\"creqv 6,6,6\", operands);
+
+ return (flag_pic == 1) ? \"bl %z0@plt\" : \"bl %z0\";
+}"
+ [(set_attr "type" "branch")
+ (set_attr "length" "4,8")])
+
+(define_insn ""
+ [(set (match_operand 0 "" "=fg,fg")
+ (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
+ (match_operand 2 "" "g,g")))
+ (use (match_operand:SI 3 "immediate_operand" "O,n"))
+ (clobber (match_scratch:SI 4 "=l,l"))]
+ "(INTVAL (operands[3]) & CALL_LONG) == 0"
+ "*
+{
+ if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
+ output_asm_insn (\"crxor 6,6,6\", operands);
+
+ else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
+ output_asm_insn (\"creqv 6,6,6\", operands);
+
+ return \"bl %z1\";
+}"
+ [(set_attr "type" "branch")
+ (set_attr "length" "4,8")])
(define_insn ""
[(set (match_operand 0 "" "=fg,fg")
- (call (mem:SI (match_operand:SI 1 "call_operand" "l,s"))
+ (call (mem:SI (match_operand:SI 1 "call_operand" "s,s"))
(match_operand 2 "" "fg,fg")))
- (clobber (match_scratch:SI 3 "=l,l"))]
- ""
+ (use (match_operand:SI 3 "immediate_operand" "O,n"))
+ (clobber (match_scratch:SI 4 "=l,l"))]
+ "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
+ && (INTVAL (operands[3]) & CALL_LONG) == 0"
"*
{
+ /* This should be handled by call_value_indirect */
if (GET_CODE (operands[1]) == REG)
- {
-#ifndef USING_SVR4_H
- return \"{brl|blrl}\;{l|lwz} 2,20(1)\";
-#else
- return \"{brl|blrl}\";
-#endif
- }
+ abort ();
+
+ if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
+ output_asm_insn (\"crxor 6,6,6\", operands);
- return \"bl %z1\;%.\";
+ else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
+ output_asm_insn (\"creqv 6,6,6\", operands);
+
+ return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\";
}"
- [(set_attr "length" "8")])
+ [(set_attr "type" "branch")
+ (set_attr "length" "8,12")])
-;; Call subroutine returning any type.
+(define_insn ""
+ [(set (match_operand 0 "" "=fg,fg")
+ (call (mem:SI (match_operand:SI 1 "call_operand" "s,s"))
+ (match_operand 2 "" "fg,fg")))
+ (use (match_operand:SI 3 "immediate_operand" "O,n"))
+ (clobber (match_scratch:SI 4 "=l,l"))]
+ "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
+ && (INTVAL (operands[3]) & CALL_LONG) == 0"
+ "*
+{
+ /* This should be handled by call_value_indirect */
+ if (GET_CODE (operands[1]) == REG)
+ abort ();
+
+ if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
+ output_asm_insn (\"crxor 6,6,6\", operands);
+
+ else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
+ output_asm_insn (\"creqv 6,6,6\", operands);
+ return (flag_pic == 1) ? \"bl %z1@plt\" : \"bl %z1\";
+}"
+ [(set_attr "type" "branch")
+ (set_attr "length" "4,8")])
+
+;; Call subroutine returning any type.
(define_expand "untyped_call"
[(parallel [(call (match_operand 0 "" "")
(const_int 0))
{
int i;
- emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
+ emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx));
for (i = 0; i < XVECLEN (operands[2], 0); i++)
{
[(unspec_volatile [(const_int 0)] 0)]
""
"")
+
+;; V.4 specific code to initialize the PIC register
+
+(define_insn "init_v4_pic"
+ [(set (match_operand:SI 0 "register_operand" "=l")
+ (unspec [(const_int 0)] 7))]
+ "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS"
+ "bl _GLOBAL_OFFSET_TABLE_@local-4"
+ [(set_attr "type" "branch")
+ (set_attr "length" "4")])
+
\f
;; Compare insns are next. Note that the RS/6000 has two types of compares,
-;; signed & unsigned, and one type of branch.
+;; signed & unsigned, and one type of branch.
;;
;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
;; insns, and branches. We store the operands of compares until we see
DONE;
}")
+(define_expand "cmpdi"
+ [(set (cc0)
+ (compare (match_operand:DI 0 "gpc_reg_operand" "")
+ (match_operand:DI 1 "reg_or_short_operand" "")))]
+ "TARGET_POWERPC64"
+ "
+{
+ /* Take care of the possibility that operands[1] might be negative but
+ this might be a logical operation. That insn doesn't exist. */
+ if (GET_CODE (operands[1]) == CONST_INT
+ && INTVAL (operands[1]) < 0)
+ operands[1] = force_reg (DImode, operands[1]);
+
+ rs6000_compare_op0 = operands[0];
+ rs6000_compare_op1 = operands[1];
+ rs6000_compare_fp_p = 0;
+ DONE;
+}")
+
(define_expand "cmpsf"
[(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
(match_operand:SF 1 "gpc_reg_operand" "")))]
"{cmp%I2|cmpw%I2} %0,%1,%2"
[(set_attr "type" "compare")])
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=y")
+ (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "reg_or_short_operand" "rI")))]
+ "TARGET_POWERPC64"
+ "cmpd%I2 %0,%1,%2"
+ [(set_attr "type" "compare")])
+
;; If we are comparing a register for equality with a large constant,
;; we can do this with an XOR followed by a compare. But we need a scratch
;; register for the result of the XOR.
"{cmpl%I2|cmplw%I2} %0,%1,%W2"
[(set_attr "type" "compare")])
+(define_insn ""
+ [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
+ (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "reg_or_u_short_operand" "rI")))]
+ ""
+ "cmpld%I2 %0,%1,%W2"
+ [(set_attr "type" "compare")])
+
;; The following two insns don't exist as single insns, but if we provide
;; them, we can swap an add and compare, which will enable us to overlap more
;; of the required delay between a compare and branch. We generate code for
""
"#"
[(set_attr "length" "8")])
-
+
(define_insn ""
[(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
(compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
""
"#"
[(set_attr "length" "8")])
-
+
(define_split
[(set (match_operand:CC 3 "cc_reg_operand" "")
(compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
- (compare:CC
+ (compare:CC
(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
(const_int 0)))
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
- (compare:CC
+ (compare:CC
(plus:SI
(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
(define_insn ""
[(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
- (compare:CC
+ (compare:CC
(plus:SI
(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
{sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
[(set_attr "length" "12,8,12,12,12")])
+;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
+;; since it nabs/sr is just as fast.
+(define_insn ""
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
+ (const_int 31)))
+ (clobber (match_scratch:SI 2 "=&r"))]
+ "!TARGET_POWER"
+ "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
+ [(set_attr "length" "8")])
+
;; This is what (plus (ne X (const_int 0)) Y) looks like.
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
""
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
- {sfi|subfic} %0,%1,-1\;a%I2 %0,%0,%2\;{sfe|subfe} %0,%0,%0"
+ {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
[(set_attr "length" "12")])
(define_insn ""
if (get_attr_length (insn) == 8)
return \"%C1bc %t1,%j1,%l0\";
else
- return \"%C1bc %T1,%j1,$+8\;b %l0\";
+ return \"%C1bc %T1,%j1,%$+8\;b %l0\";
+
}"
[(set_attr "type" "branch")])
(pc)))]
"direct_return ()"
"{%C0bcr|%C0bclr} %t0,%j0"
- [(set_attr "length" "8")])
+ [(set_attr "type" "branch")
+ (set_attr "length" "8")])
(define_insn ""
[(set (pc)
if (get_attr_length (insn) == 8)
return \"%C1bc %T1,%j1,%l0\";
else
- return \"%C1bc %t1,%j1,$+8\;b %l0\";
+ return \"%C1bc %t1,%j1,%$+8\;b %l0\";
}"
[(set_attr "type" "branch")])
(return)))]
"direct_return ()"
"{%C0bcr|%C0bclr} %T0,%j0"
- [(set_attr "length" "8")])
+ [(set_attr "type" "branch")
+ (set_attr "length" "8")])
;; Unconditional branch and return.
[(set (pc)
(label_ref (match_operand 0 "" "")))]
""
- "b %l0")
+ "b %l0"
+ [(set_attr "type" "branch")])
(define_insn "return"
[(return)]
{br|blr}"
[(set_attr "type" "jmpreg")])
+(define_insn ""
+ [(set (pc) (match_operand:DI 0 "register_operand" "c,l"))]
+ "TARGET_POWERPC64"
+ "@
+ bctr
+ {br|blr}"
+ [(set_attr "type" "jmpreg")])
+
;; Table jump for switch statements:
(define_expand "tablejump"
+ [(use (match_operand 0 "" ""))
+ (use (label_ref (match_operand 1 "" "")))]
+ ""
+ "
+{
+ if (TARGET_32BIT)
+ emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
+ else
+ emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
+ DONE;
+}")
+
+(define_expand "tablejumpsi"
[(set (match_dup 3)
(plus:SI (match_operand:SI 0 "" "")
(match_dup 2)))
operands[3] = gen_reg_rtx (SImode);
}")
+(define_expand "tablejumpdi"
+ [(set (match_dup 3)
+ (plus:DI (match_operand:DI 0 "" "")
+ (match_dup 2)))
+ (parallel [(set (pc) (match_dup 3))
+ (use (label_ref (match_operand 1 "" "")))])]
+ ""
+ "
+{ operands[0] = force_reg (DImode, operands[0]);
+ operands[2] = force_reg (DImode, gen_rtx (LABEL_REF, VOIDmode, operands[1]));
+ operands[3] = gen_reg_rtx (DImode);
+}")
+
(define_insn ""
[(set (pc)
(match_operand:SI 0 "register_operand" "c,l"))
""
"@
bctr
- {br|blr}")
+ {br|blr}"
+ [(set_attr "type" "jmpreg")])
+
+(define_insn ""
+ [(set (pc)
+ (match_operand:DI 0 "register_operand" "c,l"))
+ (use (label_ref (match_operand 1 "" "")))]
+ "TARGET_POWERPC64"
+ "@
+ bctr
+ {br|blr}"
+ [(set_attr "type" "jmpreg")])
(define_insn "nop"
[(const_int 0)]
""
"{cror 0,0,0|nop}")
\f
-;; Define the subtract-one-and-jump insns, starting with the template
+;; Define the subtract-one-and-jump insns, starting with the template
;; so loop.c knows what to generate.
-(define_expand "decrement_and_branchsi"
- [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "c")
+(define_expand "decrement_and_branch_on_count"
+ [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "")
(const_int 1))
(label_ref (match_operand 1 "" ""))
(pc)))
- (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))])]
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (const_int -1)))
+ (clobber (match_scratch:CC 2 ""))
+ (clobber (match_scratch:SI 3 ""))])]
""
"")
;; We need to be able to do this for any operand, including MEM, or we
;; will cause reload to blow up since we don't allow output reloads on
-;; JUMP_INSNs.
+;; JUMP_INSNs.
+;; In order that the length attribute is calculated correctly, the
+;; label MUST be operand 0.
+
(define_insn ""
[(set (pc)
- (if_then_else (ne (match_operand:SI 1 "register_operand" "0,*r,*r")
+ (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
(const_int 1))
- (label_ref (match_operand 2 "" ""))
+ (label_ref (match_operand 0 "" ""))
(pc)))
- (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
- (plus:SI (match_dup 1) (const_int -1)))
+ (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
+ (plus:SI (match_dup 1)
+ (const_int -1)))
+ (clobber (match_scratch:CC 3 "=X,&x,&x"))
+ (clobber (match_scratch:SI 4 "=X,X,r"))]
+ ""
+ "*
+{
+ if (which_alternative != 0)
+ return \"#\";
+ else if (get_attr_length (insn) == 8)
+ return \"{bdn|bdnz} %l0\";
+ else
+ return \"bdz %$+8\;b %l0\";
+}"
+ [(set_attr "type" "branch")
+ (set_attr "length" "*,12,16")])
+
+(define_insn ""
+ [(set (pc)
+ (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
+ (const_int 1))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))
+ (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
+ (plus:SI (match_dup 1)
+ (const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x"))
(clobber (match_scratch:SI 4 "=X,X,r"))]
""
if (which_alternative != 0)
return \"#\";
else if (get_attr_length (insn) == 8)
- return \"{bdn|bdnz} %l2\";
+ return \"bdz %l0\";
else
- return \"bdz $+8\;b %l2\";
+ return \"{bdn|bdnz} %$+8\;b %l0\";
}"
[(set_attr "type" "branch")
(set_attr "length" "*,12,16")])
-
+
;; Similar, but we can use GE since we have a REG_NONNEG.
(define_insn ""
[(set (pc)
- (if_then_else (ge (match_operand:SI 1 "register_operand" "0,*r,*r")
+ (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
(const_int 0))
- (label_ref (match_operand 2 "" ""))
+ (label_ref (match_operand 0 "" ""))
(pc)))
- (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
- (plus:SI (match_dup 1) (const_int -1)))
+ (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
+ (plus:SI (match_dup 1)
+ (const_int -1)))
+ (clobber (match_scratch:CC 3 "=X,&x,&X"))
+ (clobber (match_scratch:SI 4 "=X,X,r"))]
+ "find_reg_note (insn, REG_NONNEG, 0)"
+ "*
+{
+ if (which_alternative != 0)
+ return \"#\";
+ else if (get_attr_length (insn) == 8)
+ return \"{bdn|bdnz} %l0\";
+ else
+ return \"bdz %$+8\;b %l0\";
+}"
+ [(set_attr "type" "branch")
+ (set_attr "length" "*,12,16")])
+
+(define_insn ""
+ [(set (pc)
+ (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
+ (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))
+ (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
+ (plus:SI (match_dup 1)
+ (const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&X"))
(clobber (match_scratch:SI 4 "=X,X,r"))]
"find_reg_note (insn, REG_NONNEG, 0)"
if (which_alternative != 0)
return \"#\";
else if (get_attr_length (insn) == 8)
- return \"{bdn|bdnz} %l2\";
+ return \"bdz %l0\";
else
- return \"bdz $+8\;b %l2\";
+ return \"{bdn|bdnz} %$+8\;b %l0\";
}"
[(set_attr "type" "branch")
(set_attr "length" "*,12,16")])
-
+
(define_insn ""
[(set (pc)
- (if_then_else (eq (match_operand:SI 1 "register_operand" "0,*r,*r")
+ (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
(const_int 1))
- (label_ref (match_operand 2 "" ""))
+ (label_ref (match_operand 0 "" ""))
(pc)))
- (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
- (plus:SI (match_dup 1) (const_int -1)))
+ (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
+ (plus:SI (match_dup 1)
+ (const_int -1)))
+ (clobber (match_scratch:CC 3 "=X,&x,&x"))
+ (clobber (match_scratch:SI 4 "=X,X,r"))]
+ ""
+ "*
+{
+ if (which_alternative != 0)
+ return \"#\";
+ else if (get_attr_length (insn) == 8)
+ return \"bdz %l0\";
+ else
+ return \"{bdn|bdnz} %$+8\;b %l0\";
+}"
+ [(set_attr "type" "branch")
+ (set_attr "length" "*,12,16")])
+
+(define_insn ""
+ [(set (pc)
+ (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
+ (const_int 1))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))
+ (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
+ (plus:SI (match_dup 1)
+ (const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x"))
(clobber (match_scratch:SI 4 "=X,X,r"))]
""
if (which_alternative != 0)
return \"#\";
else if (get_attr_length (insn) == 8)
- return \"bdz %l2\";
+ return \"{bdn|bdnz} %l0\";
else
- return \"{bdn|bdnz} $+8\;b %l2\";
+ return \"bdz %$+8\;b %l0\";
}"
[(set_attr "type" "branch")
(set_attr "length" "*,12,16")])
(match_operand 5 "" "")
(match_operand 6 "" "")))
(set (match_operand:SI 0 "gpc_reg_operand" "")
- (plus:SI (match_dup 1) (const_int -1)))
+ (plus:SI (match_dup 1)
+ (const_int -1)))
(clobber (match_scratch:CC 3 ""))
(clobber (match_scratch:SI 4 ""))]
"reload_completed"
[(parallel [(set (match_dup 3)
- (compare:CC (plus:SI (match_dup 1) (const_int -1))
+ (compare:CC (plus:SI (match_dup 1)
+ (const_int -1))
(const_int 0)))
- (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))])
- (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
+ (set (match_dup 0)
+ (plus:SI (match_dup 1)
+ (const_int -1)))])
+ (set (pc) (if_then_else (match_dup 7)
+ (match_dup 5)
+ (match_dup 6)))]
"
{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
const0_rtx); }")
(clobber (match_scratch:SI 4 ""))]
"reload_completed && ! gpc_reg_operand (operands[0], SImode)"
[(parallel [(set (match_dup 3)
- (compare:CC (plus:SI (match_dup 1) (const_int -1))
+ (compare:CC (plus:SI (match_dup 1)
+ (const_int -1))
(const_int 0)))
- (set (match_dup 4) (plus:SI (match_dup 1) (const_int -1)))])
- (set (match_dup 0) (match_dup 4))
- (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
+ (set (match_dup 4)
+ (plus:SI (match_dup 1)
+ (const_int -1)))])
+ (set (match_dup 0)
+ (match_dup 4))
+ (set (pc) (if_then_else (match_dup 7)
+ (match_dup 5)
+ (match_dup 6)))]
"
{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
const0_rtx); }")
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