;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
;;
+;; REGNOS
+;;
+
+(define_constants
+ [(MQ_REGNO 64)
+ (LR_REGNO 65)
+ (CTR_REGNO 66)
+ (CR0_REGNO 68)
+ (CR1_REGNO 69)
+ (CR2_REGNO 70)
+ (CR3_REGNO 71)
+ (CR4_REGNO 72)
+ (CR5_REGNO 73)
+ (CR6_REGNO 74)
+ (CR7_REGNO 75)
+ (MAX_CR_REGNO 75)
+ (XER_REGNO 76)
+ (FIRST_ALTIVEC_REGNO 77)
+ (LAST_ALTIVEC_REGNO 108)
+ (VRSAVE_REGNO 109)
+ (VSCR_REGNO 110)
+ (SPE_ACC_REGNO 111)
+ (SPEFSCR_REGNO 112)
+ (SFP_REGNO 113)
+ ])
+
+;;
;; UNSPEC usage
;;
else if (GET_CODE (operands[2]) == CONST_INT
&& ! add_operand (operands[2], <MODE>mode))
{
- rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
+ rtx tmp = ((!can_create_pseudo_p ()
+ || rtx_equal_p (operands[0], operands[1]))
? operands[0] : gen_reg_rtx (<MODE>mode));
HOST_WIDE_INT val = INTVAL (operands[2]);
operands[4] = GEN_INT (low);
if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
operands[3] = GEN_INT (rest);
- else if (! no_new_pseudos)
+ else if (can_create_pseudo_p ())
{
operands[3] = gen_reg_rtx (DImode);
emit_move_insn (operands[3], operands[2]);
(lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
(sign_extend:DI (reg:SI 4)))
(const_int 32))))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __mulh"
[(set_attr "type" "imul")])
[(set (reg:DI 3)
(mult:DI (sign_extend:DI (reg:SI 3))
(sign_extend:DI (reg:SI 4))))
- (clobber (reg:SI 65))
+ (clobber (reg:SI LR_REGNO))
(clobber (reg:SI 0))]
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __mull"
(div:SI (reg:SI 3) (reg:SI 4)))
(set (reg:SI 4)
(mod:SI (reg:SI 3) (reg:SI 4)))
- (clobber (reg:SI 65))
+ (clobber (reg:SI LR_REGNO))
(clobber (reg:SI 0))]
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __divss"
(udiv:SI (reg:SI 3) (reg:SI 4)))
(set (reg:SI 4)
(umod:SI (reg:SI 3) (reg:SI 4)))
- (clobber (reg:SI 65))
+ (clobber (reg:SI LR_REGNO))
(clobber (reg:SI 0))
(clobber (match_scratch:CC 0 "=x"))
- (clobber (reg:CC 69))]
+ (clobber (reg:CC CR1_REGNO))]
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __divus"
[(set_attr "type" "idiv")])
(define_insn "quoss_call"
[(set (reg:SI 3)
(div:SI (reg:SI 3) (reg:SI 4)))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __quoss"
[(set_attr "type" "idiv")])
(define_insn "quous_call"
[(set (reg:SI 3)
(udiv:SI (reg:SI 3) (reg:SI 4)))
- (clobber (reg:SI 65))
+ (clobber (reg:SI LR_REGNO))
(clobber (reg:SI 0))
(clobber (match_scratch:CC 0 "=x"))
- (clobber (reg:CC 69))]
+ (clobber (reg:CC CR1_REGNO))]
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __quous"
[(set_attr "type" "idiv")])
&& ! logical_operand (operands[2], SImode))
{
HOST_WIDE_INT value = INTVAL (operands[2]);
- rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
+ rtx tmp = ((!can_create_pseudo_p ()
+ || rtx_equal_p (operands[0], operands[1]))
? operands[0] : gen_reg_rtx (SImode));
emit_insn (gen_iorsi3 (tmp, operands[1],
&& ! logical_operand (operands[2], SImode))
{
HOST_WIDE_INT value = INTVAL (operands[2]);
- rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
+ rtx tmp = ((!can_create_pseudo_p ()
+ || rtx_equal_p (operands[0], operands[1]))
? operands[0] : gen_reg_rtx (SImode));
emit_insn (gen_xorsi3 (tmp, operands[1],
(clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
"#"
- "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
+ "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
[(pc)]
"
{
(clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
"#"
- "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
+ "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
[(pc)]
"
{
(clobber (match_operand:DI 3 "memory_operand" "=o"))]
"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
"#"
- "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
+ "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
[(pc)]
"
{
if (non_logical_cint_operand (operands[2], DImode))
{
HOST_WIDE_INT value;
- rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
+ rtx tmp = ((!can_create_pseudo_p ()
+ || rtx_equal_p (operands[0], operands[1]))
? operands[0] : gen_reg_rtx (DImode));
if (GET_CODE (operands[2]) == CONST_INT)
if (non_logical_cint_operand (operands[2], DImode))
{
HOST_WIDE_INT value;
- rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
+ rtx tmp = ((!can_create_pseudo_p ()
+ || rtx_equal_p (operands[0], operands[1]))
? operands[0] : gen_reg_rtx (DImode));
if (GET_CODE (operands[2]) == CONST_INT)
value = INTVAL (offset);
if (value != 0)
{
- rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
+ rtx tmp = (!can_create_pseudo_p ()
+ ? operands[0]
+ : gen_reg_rtx (Pmode));
emit_insn (gen_movsi_got (tmp, operands[1]));
emit_insn (gen_addsi3 (operands[0], tmp, offset));
DONE;
|| (GET_CODE (operands[1]) == MEM
&& (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
|| GET_CODE (XEXP (operands[1], 0)) == PRE_INC
- || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
+ || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
+ || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
{
/* If the low-address word is used in the address, we must load
it last. Otherwise, load it first. Note that we cannot have
operands[1], 0))
return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
else
- return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
+ return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
}
else
{
|| (GET_CODE (operands[0]) == MEM
&& (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
|| GET_CODE (XEXP (operands[0], 0)) == PRE_INC
- || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
- return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
+ || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
+ || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
+ return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
else
{
rtx addreg;
operands[1], 0))
return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
else
- return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
+ return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
case 2:
- return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
+ return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
case 3:
case 4:
case 5:
"!TARGET_IEEEQUAD
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
"#"
- "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
+ "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
[(pc)]
{
rtx lowword;
[(set_attr "type" "load")])
(define_insn "load_toc_v4_pic_si"
- [(set (reg:SI 65)
+ [(set (reg:SI LR_REGNO)
(unspec:SI [(const_int 0)] UNSPEC_TOC))]
"DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
"bl _GLOBAL_OFFSET_TABLE_@local-4"
(set_attr "length" "4")])
(define_insn "load_toc_v4_PIC_1"
- [(set (reg:SI 65)
+ [(set (reg:SI LR_REGNO)
(match_operand:SI 0 "immediate_operand" "s"))
(use (unspec [(match_dup 0)] UNSPEC_TOC))]
"TARGET_ELF && DEFAULT_ABI != ABI_AIX
(set_attr "length" "4")])
(define_insn "load_toc_v4_PIC_1b"
- [(set (reg:SI 65)
+ [(set (reg:SI LR_REGNO)
(unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
UNSPEC_TOCPTR))]
"TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
emit_insn (gen_load_macho_picbase (tmplabrtx));
- emit_move_insn (picreg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
+ emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
}
else
(use (reg:SI 11))
(set (reg:SI 2)
(mem:SI (plus:SI (reg:SI 1) (const_int 20))))
- (clobber (reg:SI 65))])]
+ (clobber (reg:SI LR_REGNO))])]
"TARGET_32BIT"
"
{ operands[2] = gen_reg_rtx (SImode); }")
(use (reg:DI 11))
(set (reg:DI 2)
(mem:DI (plus:DI (reg:DI 1) (const_int 40))))
- (clobber (reg:SI 65))])]
+ (clobber (reg:SI LR_REGNO))])]
"TARGET_64BIT"
"
{ operands[2] = gen_reg_rtx (DImode); }")
(use (reg:SI 11))
(set (reg:SI 2)
(mem:SI (plus:SI (reg:SI 1) (const_int 20))))
- (clobber (reg:SI 65))])]
+ (clobber (reg:SI LR_REGNO))])]
"TARGET_32BIT"
"
{ operands[3] = gen_reg_rtx (SImode); }")
(use (reg:DI 11))
(set (reg:DI 2)
(mem:DI (plus:DI (reg:DI 1) (const_int 40))))
- (clobber (reg:SI 65))])]
+ (clobber (reg:SI LR_REGNO))])]
"TARGET_64BIT"
"
{ operands[3] = gen_reg_rtx (DImode); }")
[(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
- (clobber (reg:SI 65))])]
+ (clobber (reg:SI LR_REGNO))])]
""
"
{
operands[1]),
gen_rtx_USE (VOIDmode, operands[2]),
gen_rtx_CLOBBER (VOIDmode,
- gen_rtx_REG (Pmode,
- LINK_REGISTER_REGNUM)));
+ gen_rtx_REG (Pmode, LR_REGNO)));
call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
DONE;
(call (mem:SI (match_operand 1 "address_operand" ""))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
- (clobber (reg:SI 65))])]
+ (clobber (reg:SI LR_REGNO))])]
""
"
{
operands[2])),
gen_rtx_USE (VOIDmode, operands[3]),
gen_rtx_CLOBBER (VOIDmode,
- gen_rtx_REG (Pmode,
- LINK_REGISTER_REGNUM)));
+ gen_rtx_REG (Pmode, LR_REGNO)));
call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
DONE;
[(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
(match_operand 1 "" "g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"(INTVAL (operands[2]) & CALL_LONG) == 0"
"*
{
[(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
(match_operand 1 "" "g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
"*
{
(call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
(match_operand 2 "" "g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"(INTVAL (operands[3]) & CALL_LONG) == 0"
"*
{
(call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
(match_operand 2 "" "g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
"*
{
(use (reg:SI 11))
(set (reg:SI 2)
(mem:SI (plus:SI (reg:SI 1) (const_int 20))))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
"b%T0l\;{l|lwz} 2,20(1)"
[(set_attr "type" "jmpreg")
[(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
(match_operand 1 "" "g"))
(use (match_operand:SI 2 "immediate_operand" "O"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_32BIT
&& DEFAULT_ABI == ABI_AIX
&& (INTVAL (operands[2]) & CALL_LONG) == 0"
(use (reg:DI 11))
(set (reg:DI 2)
(mem:DI (plus:DI (reg:DI 1) (const_int 40))))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
"b%T0l\;ld 2,40(1)"
[(set_attr "type" "jmpreg")
[(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
(match_operand 1 "" "g"))
(use (match_operand:SI 2 "immediate_operand" "O"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_64BIT
&& DEFAULT_ABI == ABI_AIX
&& (INTVAL (operands[2]) & CALL_LONG) == 0"
(use (reg:SI 11))
(set (reg:SI 2)
(mem:SI (plus:SI (reg:SI 1) (const_int 20))))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
"b%T1l\;{l|lwz} 2,20(1)"
[(set_attr "type" "jmpreg")
(call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
(match_operand 2 "" "g")))
(use (match_operand:SI 3 "immediate_operand" "O"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_32BIT
&& DEFAULT_ABI == ABI_AIX
&& (INTVAL (operands[3]) & CALL_LONG) == 0"
(use (reg:DI 11))
(set (reg:DI 2)
(mem:DI (plus:DI (reg:DI 1) (const_int 40))))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
"b%T1l\;ld 2,40(1)"
[(set_attr "type" "jmpreg")
(call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
(match_operand 2 "" "g")))
(use (match_operand:SI 3 "immediate_operand" "O"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"TARGET_64BIT
&& DEFAULT_ABI == ABI_AIX
&& (INTVAL (operands[3]) & CALL_LONG) == 0"
[(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
(match_operand 1 "" "g,g,g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"DEFAULT_ABI == ABI_V4
|| DEFAULT_ABI == ABI_DARWIN"
{
[(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
(match_operand 1 "" "g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"(DEFAULT_ABI == ABI_DARWIN
|| (DEFAULT_ABI == ABI_V4
&& (INTVAL (operands[2]) & CALL_LONG) == 0))"
(call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
(match_operand 2 "" "g,g,g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"DEFAULT_ABI == ABI_V4
|| DEFAULT_ABI == ABI_DARWIN"
{
(call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
(match_operand 2 "" "g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,n"))
- (clobber (reg:SI 65))]
+ (clobber (reg:SI LR_REGNO))]
"(DEFAULT_ABI == ABI_DARWIN
|| (DEFAULT_ABI == ABI_V4
&& (INTVAL (operands[3]) & CALL_LONG) == 0))"
[(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)])]
""
"
[(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
(match_operand 1 "" "g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,n"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"(INTVAL (operands[2]) & CALL_LONG) == 0"
"*
[(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
(match_operand 1 "" "g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,n"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
"*
(call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
(match_operand 2 "" "g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,n"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"(INTVAL (operands[3]) & CALL_LONG) == 0"
"*
(call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
(match_operand 2 "" "g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,n"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
"*
[(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
(match_operand 1 "" "g"))
(use (match_operand:SI 2 "immediate_operand" "O"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"TARGET_32BIT
&& DEFAULT_ABI == ABI_AIX
[(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
(match_operand 1 "" "g"))
(use (match_operand:SI 2 "immediate_operand" "O"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"TARGET_64BIT
&& DEFAULT_ABI == ABI_AIX
(call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
(match_operand 2 "" "g")))
(use (match_operand:SI 3 "immediate_operand" "O"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"TARGET_32BIT
&& DEFAULT_ABI == ABI_AIX
(call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
(match_operand 2 "" "g")))
(use (match_operand:SI 3 "immediate_operand" "O"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"TARGET_64BIT
&& DEFAULT_ABI == ABI_AIX
[(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
(match_operand 1 "" ""))
(use (match_operand 2 "immediate_operand" "O,n"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"(DEFAULT_ABI == ABI_DARWIN
|| DEFAULT_ABI == ABI_V4)
(call (mem:SI (match_operand 1 "address_operand" ""))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)])]
""
"
(call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
(match_operand 2 "" "")))
(use (match_operand:SI 3 "immediate_operand" "O,n"))
- (use (reg:SI 65))
+ (use (reg:SI LR_REGNO))
(return)]
"(DEFAULT_ABI == ABI_DARWIN
|| DEFAULT_ABI == ABI_V4)
(define_insn "movesi_from_cr"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
- (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
+ (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
+ (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
+ (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
+ (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
UNSPEC_MOVESI_FROM_CR))]
""
"mfcr %0"