#define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec"
#endif
+#ifdef HAVE_AS_DCI
+#define ASM_CPU_476_SPEC "-m476"
+#else
+#define ASM_CPU_476_SPEC "-mpower4"
+#endif
+
/* Common ASM definitions used by ASM_SPEC among the various targets for
handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
provide the default assembler options if the user uses -mcpu=native, so if
%{mcpu=power6: %(asm_cpu_power6) -maltivec} \
%{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
%{mcpu=power7: %(asm_cpu_power7)} \
+%{mcpu=a2: -ma2} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rios: -mpwr} \
%{mcpu=rios1: -mpwr} \
%{mcpu=440fp: -m440} \
%{mcpu=464: -m440} \
%{mcpu=464fp: -m440} \
+%{mcpu=476: %(asm_cpu_476)} \
+%{mcpu=476fp: %(asm_cpu_476)} \
%{mcpu=505: -mppc} \
%{mcpu=601: -m601} \
%{mcpu=602: -mppc} \
%{mcpu=e300c2: -me300} \
%{mcpu=e300c3: -me300} \
%{mcpu=e500mc: -me500mc} \
+%{mcpu=e500mc64: -me500mc64} \
%{maltivec: -maltivec} \
-many"
{ "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
{ "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
{ "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
+ { "asm_cpu_476", ASM_CPU_476_SPEC }, \
SUBTARGET_EXTRA_SPECS
/* -mcpu=native handling only makes sense with compiler running on
#define TARGET_SECURE_PLT 0
#endif
+/* Code model for 64-bit linux.
+ small: 16-bit toc offsets.
+ medium: 32-bit toc offsets, static data and code within 2G of TOC pointer.
+ large: 32-bit toc offsets, no limit on static data and code. */
+enum rs6000_cmodel {
+ CMODEL_SMALL,
+ CMODEL_MEDIUM,
+ CMODEL_LARGE
+};
+
+#ifndef TARGET_CMODEL
+#define TARGET_CMODEL CMODEL_SMALL
+#endif
+
#define TARGET_32BIT (! TARGET_64BIT)
#ifndef HAVE_AS_TLS
PROCESSOR_PPC403,
PROCESSOR_PPC405,
PROCESSOR_PPC440,
+ PROCESSOR_PPC476,
PROCESSOR_PPC601,
PROCESSOR_PPC603,
PROCESSOR_PPC604,
PROCESSOR_PPCE300C2,
PROCESSOR_PPCE300C3,
PROCESSOR_PPCE500MC,
+ PROCESSOR_PPCE500MC64,
PROCESSOR_POWER4,
PROCESSOR_POWER5,
PROCESSOR_POWER6,
PROCESSOR_POWER7,
- PROCESSOR_CELL
+ PROCESSOR_CELL,
+ PROCESSOR_PPCA2
};
/* FPU operations supported.
/* E500 processors only support plain "sync", not lwsync. */
#define TARGET_NO_LWSYNC TARGET_E500
+/* Which machine supports the various reciprocal estimate instructions. */
+#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
+ && TARGET_FPRS && TARGET_SINGLE_FLOAT)
+
+#define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \
+ && TARGET_DOUBLE_FLOAT \
+ && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
+
+#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
+ && TARGET_FPRS && TARGET_SINGLE_FLOAT)
+
+#define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \
+ && TARGET_DOUBLE_FLOAT \
+ && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
+
+/* Whether the various reciprocal divide/square root estimate instructions
+ exist, and whether we should automatically generate code for the instruction
+ by default. */
+#define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */
+#define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */
+#define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */
+#define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */
+
+extern unsigned char rs6000_recip_bits[];
+
+#define RS6000_RECIP_HAVE_RE_P(MODE) \
+ (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
+
+#define RS6000_RECIP_AUTO_RE_P(MODE) \
+ (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
+
+#define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
+ (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
+
+#define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
+ (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
+
+#define RS6000_RECIP_HIGH_PRECISION_P(MODE) \
+ ((MODE) == SFmode || (MODE) == V4SFmode || TARGET_RECIP_PRECISION)
+
/* Sometimes certain combinations of command options do not make sense
on a particular target machine. You can define a macro
`OVERRIDE_OPTIONS' to take account of this. This macro, if
mq (not saved; best to use it if we can)
ctr (not saved; when we have the choice ctr is better)
lr (saved)
- cr5, r1, r2, ap, xer (fixed)
+ cr5, r1, r2, ap, ca (fixed)
v0 - v1 (not saved or used for anything)
v13 - v3 (not saved; incoming vector arg registers)
v2 (not saved; incoming vector arg reg; return value)
/* PAIRED SIMD registers are just the FPRs. */
#define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
-/* True if register is the XER register. */
-#define XER_REGNO_P(N) ((N) == XER_REGNO)
+/* True if register is the CA register. */
+#define CA_REGNO_P(N) ((N) == CA_REGNO)
/* True if register is an AltiVec register. */
#define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
#define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)]
-#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
- ((TARGET_32BIT && TARGET_POWERPC64 \
- && (GET_MODE_SIZE (MODE) > 4) \
- && INT_REGNO_P (REGNO)) ? 1 : 0)
+#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
+ (((TARGET_32BIT && TARGET_POWERPC64 \
+ && (GET_MODE_SIZE (MODE) > 4) \
+ && INT_REGNO_P (REGNO)) ? 1 : 0) \
+ || (TARGET_VSX && FP_REGNO_P (REGNO) \
+ && GET_MODE_SIZE (MODE) > 8))
#define VSX_VECTOR_MODE(MODE) \
((MODE) == V4SFmode \
CR0_REGS,
CR_REGS,
NON_FLOAT_REGS,
- XER_REGS,
+ CA_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
"CR0_REGS", \
"CR_REGS", \
"NON_FLOAT_REGS", \
- "XER_REGS", \
+ "CA_REGS", \
"ALL_REGS" \
}
{ 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
{ 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
{ 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */ \
- { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
+ { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \
{ 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \
}
GENERAL_REGS, SPECIAL_REGS, FLOAT_REGS, ALTIVEC_REGS, /* VSX_REGS, */ \
/* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \
/* MQ_REGS, LINK_REGS, CTR_REGS, */ \
- CR_REGS, XER_REGS, LIM_REG_CLASSES \
+ CR_REGS, CA_REGS, LIM_REG_CLASSES \
}
#define IRA_COVER_CLASSES_VSX \
GENERAL_REGS, SPECIAL_REGS, /* FLOAT_REGS, ALTIVEC_REGS, */ VSX_REGS, \
/* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \
/* MQ_REGS, LINK_REGS, CTR_REGS, */ \
- CR_REGS, XER_REGS, LIM_REG_CLASSES \
+ CR_REGS, CA_REGS, LIM_REG_CLASSES \
}
/* The same information, inverted:
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-/* Define how to find the value returned by a function.
- VALTYPE is the data type of the value (as a tree).
- If the precise function being called is known, FUNC is its FUNCTION_DECL;
- otherwise, FUNC is 0. */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
-
/* Define how to find the value returned by a library function
assuming the value has mode MODE. */
goto WIN; \
} while (0)
-/* Go to LABEL if ADDR (a legitimate address expression)
- has an effect that depends on the machine mode it is used for. */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
-do { \
- if (rs6000_mode_dependent_address_ptr (ADDR)) \
- goto LABEL; \
-} while (0)
-
#define FIND_BASE_TERM rs6000_find_base_term
\f
/* The register number of the register used to address a table of
&rs6000_reg_names[74][0], /* cr6 */ \
&rs6000_reg_names[75][0], /* cr7 */ \
\
- &rs6000_reg_names[76][0], /* xer */ \
+ &rs6000_reg_names[76][0], /* ca */ \
\
&rs6000_reg_names[77][0], /* v0 */ \
&rs6000_reg_names[78][0], /* v1 */ \
{"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
{"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
{"cc", 68}, {"sp", 1}, {"toc", 2}, \
+ /* CA is only part of XER, but we do not model the other parts (yet). */ \
+ {"xer", 76}, \
/* VSX registers overlaid on top of FR, Altivec registers */ \
{"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
{"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
extern int flag_expensive_optimizations;
extern int frame_pointer_needed;
+/* Classification of the builtin functions to properly set the declaration tree
+ flags. */
+enum rs6000_btc
+{
+ RS6000_BTC_MISC, /* assume builtin can do anything */
+ RS6000_BTC_CONST, /* builtin is a 'const' function. */
+ RS6000_BTC_PURE, /* builtin is a 'pure' function. */
+ RS6000_BTC_FP_PURE /* builtin is 'pure' if rounding math. */
+};
+
+/* Convenience macros to document the instruction type. */
+#define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches memory */
+#define RS6000_BTC_SAT RS6000_BTC_MISC /* VMX saturate sets VSCR register */
+
+#undef RS6000_BUILTIN
+#undef RS6000_BUILTIN_EQUATE
+#define RS6000_BUILTIN(NAME, TYPE) NAME,
+#define RS6000_BUILTIN_EQUATE(NAME, VALUE) NAME = VALUE,
+
enum rs6000_builtins
{
- /* AltiVec builtins. */
- ALTIVEC_BUILTIN_ST_INTERNAL_4si,
- ALTIVEC_BUILTIN_LD_INTERNAL_4si,
- ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
- ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
- ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
- ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
- ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
- ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
- ALTIVEC_BUILTIN_VADDUBM,
- ALTIVEC_BUILTIN_VADDUHM,
- ALTIVEC_BUILTIN_VADDUWM,
- ALTIVEC_BUILTIN_VADDFP,
- ALTIVEC_BUILTIN_VADDCUW,
- ALTIVEC_BUILTIN_VADDUBS,
- ALTIVEC_BUILTIN_VADDSBS,
- ALTIVEC_BUILTIN_VADDUHS,
- ALTIVEC_BUILTIN_VADDSHS,
- ALTIVEC_BUILTIN_VADDUWS,
- ALTIVEC_BUILTIN_VADDSWS,
- ALTIVEC_BUILTIN_VAND,
- ALTIVEC_BUILTIN_VANDC,
- ALTIVEC_BUILTIN_VAVGUB,
- ALTIVEC_BUILTIN_VAVGSB,
- ALTIVEC_BUILTIN_VAVGUH,
- ALTIVEC_BUILTIN_VAVGSH,
- ALTIVEC_BUILTIN_VAVGUW,
- ALTIVEC_BUILTIN_VAVGSW,
- ALTIVEC_BUILTIN_VCFUX,
- ALTIVEC_BUILTIN_VCFSX,
- ALTIVEC_BUILTIN_VCTSXS,
- ALTIVEC_BUILTIN_VCTUXS,
- ALTIVEC_BUILTIN_VCMPBFP,
- ALTIVEC_BUILTIN_VCMPEQUB,
- ALTIVEC_BUILTIN_VCMPEQUH,
- ALTIVEC_BUILTIN_VCMPEQUW,
- ALTIVEC_BUILTIN_VCMPEQFP,
- ALTIVEC_BUILTIN_VCMPGEFP,
- ALTIVEC_BUILTIN_VCMPGTUB,
- ALTIVEC_BUILTIN_VCMPGTSB,
- ALTIVEC_BUILTIN_VCMPGTUH,
- ALTIVEC_BUILTIN_VCMPGTSH,
- ALTIVEC_BUILTIN_VCMPGTUW,
- ALTIVEC_BUILTIN_VCMPGTSW,
- ALTIVEC_BUILTIN_VCMPGTFP,
- ALTIVEC_BUILTIN_VEXPTEFP,
- ALTIVEC_BUILTIN_VLOGEFP,
- ALTIVEC_BUILTIN_VMADDFP,
- ALTIVEC_BUILTIN_VMAXUB,
- ALTIVEC_BUILTIN_VMAXSB,
- ALTIVEC_BUILTIN_VMAXUH,
- ALTIVEC_BUILTIN_VMAXSH,
- ALTIVEC_BUILTIN_VMAXUW,
- ALTIVEC_BUILTIN_VMAXSW,
- ALTIVEC_BUILTIN_VMAXFP,
- ALTIVEC_BUILTIN_VMHADDSHS,
- ALTIVEC_BUILTIN_VMHRADDSHS,
- ALTIVEC_BUILTIN_VMLADDUHM,
- ALTIVEC_BUILTIN_VMRGHB,
- ALTIVEC_BUILTIN_VMRGHH,
- ALTIVEC_BUILTIN_VMRGHW,
- ALTIVEC_BUILTIN_VMRGLB,
- ALTIVEC_BUILTIN_VMRGLH,
- ALTIVEC_BUILTIN_VMRGLW,
- ALTIVEC_BUILTIN_VMSUMUBM,
- ALTIVEC_BUILTIN_VMSUMMBM,
- ALTIVEC_BUILTIN_VMSUMUHM,
- ALTIVEC_BUILTIN_VMSUMSHM,
- ALTIVEC_BUILTIN_VMSUMUHS,
- ALTIVEC_BUILTIN_VMSUMSHS,
- ALTIVEC_BUILTIN_VMINUB,
- ALTIVEC_BUILTIN_VMINSB,
- ALTIVEC_BUILTIN_VMINUH,
- ALTIVEC_BUILTIN_VMINSH,
- ALTIVEC_BUILTIN_VMINUW,
- ALTIVEC_BUILTIN_VMINSW,
- ALTIVEC_BUILTIN_VMINFP,
- ALTIVEC_BUILTIN_VMULEUB,
- ALTIVEC_BUILTIN_VMULEUB_UNS,
- ALTIVEC_BUILTIN_VMULESB,
- ALTIVEC_BUILTIN_VMULEUH,
- ALTIVEC_BUILTIN_VMULEUH_UNS,
- ALTIVEC_BUILTIN_VMULESH,
- ALTIVEC_BUILTIN_VMULOUB,
- ALTIVEC_BUILTIN_VMULOUB_UNS,
- ALTIVEC_BUILTIN_VMULOSB,
- ALTIVEC_BUILTIN_VMULOUH,
- ALTIVEC_BUILTIN_VMULOUH_UNS,
- ALTIVEC_BUILTIN_VMULOSH,
- ALTIVEC_BUILTIN_VNMSUBFP,
- ALTIVEC_BUILTIN_VNOR,
- ALTIVEC_BUILTIN_VOR,
- ALTIVEC_BUILTIN_VSEL_2DF, /* needed for VSX */
- ALTIVEC_BUILTIN_VSEL_2DI, /* needed for VSX */
- ALTIVEC_BUILTIN_VSEL_4SI,
- ALTIVEC_BUILTIN_VSEL_4SF,
- ALTIVEC_BUILTIN_VSEL_8HI,
- ALTIVEC_BUILTIN_VSEL_16QI,
- ALTIVEC_BUILTIN_VSEL_2DI_UNS,
- ALTIVEC_BUILTIN_VSEL_4SI_UNS,
- ALTIVEC_BUILTIN_VSEL_8HI_UNS,
- ALTIVEC_BUILTIN_VSEL_16QI_UNS,
- ALTIVEC_BUILTIN_VPERM_2DF, /* needed for VSX */
- ALTIVEC_BUILTIN_VPERM_2DI, /* needed for VSX */
- ALTIVEC_BUILTIN_VPERM_4SI,
- ALTIVEC_BUILTIN_VPERM_4SF,
- ALTIVEC_BUILTIN_VPERM_8HI,
- ALTIVEC_BUILTIN_VPERM_16QI,
- ALTIVEC_BUILTIN_VPERM_2DI_UNS,
- ALTIVEC_BUILTIN_VPERM_4SI_UNS,
- ALTIVEC_BUILTIN_VPERM_8HI_UNS,
- ALTIVEC_BUILTIN_VPERM_16QI_UNS,
- ALTIVEC_BUILTIN_VPKUHUM,
- ALTIVEC_BUILTIN_VPKUWUM,
- ALTIVEC_BUILTIN_VPKPX,
- ALTIVEC_BUILTIN_VPKUHSS,
- ALTIVEC_BUILTIN_VPKSHSS,
- ALTIVEC_BUILTIN_VPKUWSS,
- ALTIVEC_BUILTIN_VPKSWSS,
- ALTIVEC_BUILTIN_VPKUHUS,
- ALTIVEC_BUILTIN_VPKSHUS,
- ALTIVEC_BUILTIN_VPKUWUS,
- ALTIVEC_BUILTIN_VPKSWUS,
- ALTIVEC_BUILTIN_VREFP,
- ALTIVEC_BUILTIN_VRFIM,
- ALTIVEC_BUILTIN_VRFIN,
- ALTIVEC_BUILTIN_VRFIP,
- ALTIVEC_BUILTIN_VRFIZ,
- ALTIVEC_BUILTIN_VRLB,
- ALTIVEC_BUILTIN_VRLH,
- ALTIVEC_BUILTIN_VRLW,
- ALTIVEC_BUILTIN_VRSQRTEFP,
- ALTIVEC_BUILTIN_VSLB,
- ALTIVEC_BUILTIN_VSLH,
- ALTIVEC_BUILTIN_VSLW,
- ALTIVEC_BUILTIN_VSL,
- ALTIVEC_BUILTIN_VSLO,
- ALTIVEC_BUILTIN_VSPLTB,
- ALTIVEC_BUILTIN_VSPLTH,
- ALTIVEC_BUILTIN_VSPLTW,
- ALTIVEC_BUILTIN_VSPLTISB,
- ALTIVEC_BUILTIN_VSPLTISH,
- ALTIVEC_BUILTIN_VSPLTISW,
- ALTIVEC_BUILTIN_VSRB,
- ALTIVEC_BUILTIN_VSRH,
- ALTIVEC_BUILTIN_VSRW,
- ALTIVEC_BUILTIN_VSRAB,
- ALTIVEC_BUILTIN_VSRAH,
- ALTIVEC_BUILTIN_VSRAW,
- ALTIVEC_BUILTIN_VSR,
- ALTIVEC_BUILTIN_VSRO,
- ALTIVEC_BUILTIN_VSUBUBM,
- ALTIVEC_BUILTIN_VSUBUHM,
- ALTIVEC_BUILTIN_VSUBUWM,
- ALTIVEC_BUILTIN_VSUBFP,
- ALTIVEC_BUILTIN_VSUBCUW,
- ALTIVEC_BUILTIN_VSUBUBS,
- ALTIVEC_BUILTIN_VSUBSBS,
- ALTIVEC_BUILTIN_VSUBUHS,
- ALTIVEC_BUILTIN_VSUBSHS,
- ALTIVEC_BUILTIN_VSUBUWS,
- ALTIVEC_BUILTIN_VSUBSWS,
- ALTIVEC_BUILTIN_VSUM4UBS,
- ALTIVEC_BUILTIN_VSUM4SBS,
- ALTIVEC_BUILTIN_VSUM4SHS,
- ALTIVEC_BUILTIN_VSUM2SWS,
- ALTIVEC_BUILTIN_VSUMSWS,
- ALTIVEC_BUILTIN_VXOR,
- ALTIVEC_BUILTIN_VSLDOI_16QI,
- ALTIVEC_BUILTIN_VSLDOI_8HI,
- ALTIVEC_BUILTIN_VSLDOI_4SI,
- ALTIVEC_BUILTIN_VSLDOI_4SF,
- ALTIVEC_BUILTIN_VUPKHSB,
- ALTIVEC_BUILTIN_VUPKHPX,
- ALTIVEC_BUILTIN_VUPKHSH,
- ALTIVEC_BUILTIN_VUPKLSB,
- ALTIVEC_BUILTIN_VUPKLPX,
- ALTIVEC_BUILTIN_VUPKLSH,
- ALTIVEC_BUILTIN_MTVSCR,
- ALTIVEC_BUILTIN_MFVSCR,
- ALTIVEC_BUILTIN_DSSALL,
- ALTIVEC_BUILTIN_DSS,
- ALTIVEC_BUILTIN_LVSL,
- ALTIVEC_BUILTIN_LVSR,
- ALTIVEC_BUILTIN_DSTT,
- ALTIVEC_BUILTIN_DSTST,
- ALTIVEC_BUILTIN_DSTSTT,
- ALTIVEC_BUILTIN_DST,
- ALTIVEC_BUILTIN_LVEBX,
- ALTIVEC_BUILTIN_LVEHX,
- ALTIVEC_BUILTIN_LVEWX,
- ALTIVEC_BUILTIN_LVXL,
- ALTIVEC_BUILTIN_LVX,
- ALTIVEC_BUILTIN_STVX,
- ALTIVEC_BUILTIN_LVLX,
- ALTIVEC_BUILTIN_LVLXL,
- ALTIVEC_BUILTIN_LVRX,
- ALTIVEC_BUILTIN_LVRXL,
- ALTIVEC_BUILTIN_STVEBX,
- ALTIVEC_BUILTIN_STVEHX,
- ALTIVEC_BUILTIN_STVEWX,
- ALTIVEC_BUILTIN_STVXL,
- ALTIVEC_BUILTIN_STVLX,
- ALTIVEC_BUILTIN_STVLXL,
- ALTIVEC_BUILTIN_STVRX,
- ALTIVEC_BUILTIN_STVRXL,
- ALTIVEC_BUILTIN_VCMPBFP_P,
- ALTIVEC_BUILTIN_VCMPEQFP_P,
- ALTIVEC_BUILTIN_VCMPEQUB_P,
- ALTIVEC_BUILTIN_VCMPEQUH_P,
- ALTIVEC_BUILTIN_VCMPEQUW_P,
- ALTIVEC_BUILTIN_VCMPGEFP_P,
- ALTIVEC_BUILTIN_VCMPGTFP_P,
- ALTIVEC_BUILTIN_VCMPGTSB_P,
- ALTIVEC_BUILTIN_VCMPGTSH_P,
- ALTIVEC_BUILTIN_VCMPGTSW_P,
- ALTIVEC_BUILTIN_VCMPGTUB_P,
- ALTIVEC_BUILTIN_VCMPGTUH_P,
- ALTIVEC_BUILTIN_VCMPGTUW_P,
- ALTIVEC_BUILTIN_ABSS_V4SI,
- ALTIVEC_BUILTIN_ABSS_V8HI,
- ALTIVEC_BUILTIN_ABSS_V16QI,
- ALTIVEC_BUILTIN_ABS_V4SI,
- ALTIVEC_BUILTIN_ABS_V4SF,
- ALTIVEC_BUILTIN_ABS_V8HI,
- ALTIVEC_BUILTIN_ABS_V16QI,
- ALTIVEC_BUILTIN_MASK_FOR_LOAD,
- ALTIVEC_BUILTIN_MASK_FOR_STORE,
- ALTIVEC_BUILTIN_VEC_INIT_V4SI,
- ALTIVEC_BUILTIN_VEC_INIT_V8HI,
- ALTIVEC_BUILTIN_VEC_INIT_V16QI,
- ALTIVEC_BUILTIN_VEC_INIT_V4SF,
- ALTIVEC_BUILTIN_VEC_SET_V4SI,
- ALTIVEC_BUILTIN_VEC_SET_V8HI,
- ALTIVEC_BUILTIN_VEC_SET_V16QI,
- ALTIVEC_BUILTIN_VEC_SET_V4SF,
- ALTIVEC_BUILTIN_VEC_EXT_V4SI,
- ALTIVEC_BUILTIN_VEC_EXT_V8HI,
- ALTIVEC_BUILTIN_VEC_EXT_V16QI,
- ALTIVEC_BUILTIN_VEC_EXT_V4SF,
- ALTIVEC_BUILTIN_COPYSIGN_V4SF,
-
- /* Altivec overloaded builtins. */
- ALTIVEC_BUILTIN_VCMPEQ_P,
- ALTIVEC_BUILTIN_OVERLOADED_FIRST = ALTIVEC_BUILTIN_VCMPEQ_P,
- ALTIVEC_BUILTIN_VCMPGT_P,
- ALTIVEC_BUILTIN_VCMPGE_P,
- ALTIVEC_BUILTIN_VEC_ABS,
- ALTIVEC_BUILTIN_VEC_ABSS,
- ALTIVEC_BUILTIN_VEC_ADD,
- ALTIVEC_BUILTIN_VEC_ADDC,
- ALTIVEC_BUILTIN_VEC_ADDS,
- ALTIVEC_BUILTIN_VEC_AND,
- ALTIVEC_BUILTIN_VEC_ANDC,
- ALTIVEC_BUILTIN_VEC_AVG,
- ALTIVEC_BUILTIN_VEC_EXTRACT,
- ALTIVEC_BUILTIN_VEC_CEIL,
- ALTIVEC_BUILTIN_VEC_CMPB,
- ALTIVEC_BUILTIN_VEC_CMPEQ,
- ALTIVEC_BUILTIN_VEC_CMPEQUB,
- ALTIVEC_BUILTIN_VEC_CMPEQUH,
- ALTIVEC_BUILTIN_VEC_CMPEQUW,
- ALTIVEC_BUILTIN_VEC_CMPGE,
- ALTIVEC_BUILTIN_VEC_CMPGT,
- ALTIVEC_BUILTIN_VEC_CMPLE,
- ALTIVEC_BUILTIN_VEC_CMPLT,
- ALTIVEC_BUILTIN_VEC_COPYSIGN,
- ALTIVEC_BUILTIN_VEC_CTF,
- ALTIVEC_BUILTIN_VEC_CTS,
- ALTIVEC_BUILTIN_VEC_CTU,
- ALTIVEC_BUILTIN_VEC_DST,
- ALTIVEC_BUILTIN_VEC_DSTST,
- ALTIVEC_BUILTIN_VEC_DSTSTT,
- ALTIVEC_BUILTIN_VEC_DSTT,
- ALTIVEC_BUILTIN_VEC_EXPTE,
- ALTIVEC_BUILTIN_VEC_FLOOR,
- ALTIVEC_BUILTIN_VEC_LD,
- ALTIVEC_BUILTIN_VEC_LDE,
- ALTIVEC_BUILTIN_VEC_LDL,
- ALTIVEC_BUILTIN_VEC_LOGE,
- ALTIVEC_BUILTIN_VEC_LVEBX,
- ALTIVEC_BUILTIN_VEC_LVEHX,
- ALTIVEC_BUILTIN_VEC_LVEWX,
- ALTIVEC_BUILTIN_VEC_LVLX,
- ALTIVEC_BUILTIN_VEC_LVLXL,
- ALTIVEC_BUILTIN_VEC_LVRX,
- ALTIVEC_BUILTIN_VEC_LVRXL,
- ALTIVEC_BUILTIN_VEC_LVSL,
- ALTIVEC_BUILTIN_VEC_LVSR,
- ALTIVEC_BUILTIN_VEC_MADD,
- ALTIVEC_BUILTIN_VEC_MADDS,
- ALTIVEC_BUILTIN_VEC_MAX,
- ALTIVEC_BUILTIN_VEC_MERGEH,
- ALTIVEC_BUILTIN_VEC_MERGEL,
- ALTIVEC_BUILTIN_VEC_MIN,
- ALTIVEC_BUILTIN_VEC_MLADD,
- ALTIVEC_BUILTIN_VEC_MPERM,
- ALTIVEC_BUILTIN_VEC_MRADDS,
- ALTIVEC_BUILTIN_VEC_MRGHB,
- ALTIVEC_BUILTIN_VEC_MRGHH,
- ALTIVEC_BUILTIN_VEC_MRGHW,
- ALTIVEC_BUILTIN_VEC_MRGLB,
- ALTIVEC_BUILTIN_VEC_MRGLH,
- ALTIVEC_BUILTIN_VEC_MRGLW,
- ALTIVEC_BUILTIN_VEC_MSUM,
- ALTIVEC_BUILTIN_VEC_MSUMS,
- ALTIVEC_BUILTIN_VEC_MTVSCR,
- ALTIVEC_BUILTIN_VEC_MULE,
- ALTIVEC_BUILTIN_VEC_MULO,
- ALTIVEC_BUILTIN_VEC_NEARBYINT,
- ALTIVEC_BUILTIN_VEC_NMSUB,
- ALTIVEC_BUILTIN_VEC_NOR,
- ALTIVEC_BUILTIN_VEC_OR,
- ALTIVEC_BUILTIN_VEC_PACK,
- ALTIVEC_BUILTIN_VEC_PACKPX,
- ALTIVEC_BUILTIN_VEC_PACKS,
- ALTIVEC_BUILTIN_VEC_PACKSU,
- ALTIVEC_BUILTIN_VEC_PERM,
- ALTIVEC_BUILTIN_VEC_RE,
- ALTIVEC_BUILTIN_VEC_RL,
- ALTIVEC_BUILTIN_VEC_RINT,
- ALTIVEC_BUILTIN_VEC_ROUND,
- ALTIVEC_BUILTIN_VEC_RSQRTE,
- ALTIVEC_BUILTIN_VEC_SEL,
- ALTIVEC_BUILTIN_VEC_SL,
- ALTIVEC_BUILTIN_VEC_SLD,
- ALTIVEC_BUILTIN_VEC_SLL,
- ALTIVEC_BUILTIN_VEC_SLO,
- ALTIVEC_BUILTIN_VEC_SPLAT,
- ALTIVEC_BUILTIN_VEC_SPLAT_S16,
- ALTIVEC_BUILTIN_VEC_SPLAT_S32,
- ALTIVEC_BUILTIN_VEC_SPLAT_S8,
- ALTIVEC_BUILTIN_VEC_SPLAT_U16,
- ALTIVEC_BUILTIN_VEC_SPLAT_U32,
- ALTIVEC_BUILTIN_VEC_SPLAT_U8,
- ALTIVEC_BUILTIN_VEC_SPLTB,
- ALTIVEC_BUILTIN_VEC_SPLTH,
- ALTIVEC_BUILTIN_VEC_SPLTW,
- ALTIVEC_BUILTIN_VEC_SQRT,
- ALTIVEC_BUILTIN_VEC_SR,
- ALTIVEC_BUILTIN_VEC_SRA,
- ALTIVEC_BUILTIN_VEC_SRL,
- ALTIVEC_BUILTIN_VEC_SRO,
- ALTIVEC_BUILTIN_VEC_ST,
- ALTIVEC_BUILTIN_VEC_STE,
- ALTIVEC_BUILTIN_VEC_STL,
- ALTIVEC_BUILTIN_VEC_STVEBX,
- ALTIVEC_BUILTIN_VEC_STVEHX,
- ALTIVEC_BUILTIN_VEC_STVEWX,
- ALTIVEC_BUILTIN_VEC_STVLX,
- ALTIVEC_BUILTIN_VEC_STVLXL,
- ALTIVEC_BUILTIN_VEC_STVRX,
- ALTIVEC_BUILTIN_VEC_STVRXL,
- ALTIVEC_BUILTIN_VEC_SUB,
- ALTIVEC_BUILTIN_VEC_SUBC,
- ALTIVEC_BUILTIN_VEC_SUBS,
- ALTIVEC_BUILTIN_VEC_SUM2S,
- ALTIVEC_BUILTIN_VEC_SUM4S,
- ALTIVEC_BUILTIN_VEC_SUMS,
- ALTIVEC_BUILTIN_VEC_TRUNC,
- ALTIVEC_BUILTIN_VEC_UNPACKH,
- ALTIVEC_BUILTIN_VEC_UNPACKL,
- ALTIVEC_BUILTIN_VEC_VADDFP,
- ALTIVEC_BUILTIN_VEC_VADDSBS,
- ALTIVEC_BUILTIN_VEC_VADDSHS,
- ALTIVEC_BUILTIN_VEC_VADDSWS,
- ALTIVEC_BUILTIN_VEC_VADDUBM,
- ALTIVEC_BUILTIN_VEC_VADDUBS,
- ALTIVEC_BUILTIN_VEC_VADDUHM,
- ALTIVEC_BUILTIN_VEC_VADDUHS,
- ALTIVEC_BUILTIN_VEC_VADDUWM,
- ALTIVEC_BUILTIN_VEC_VADDUWS,
- ALTIVEC_BUILTIN_VEC_VAVGSB,
- ALTIVEC_BUILTIN_VEC_VAVGSH,
- ALTIVEC_BUILTIN_VEC_VAVGSW,
- ALTIVEC_BUILTIN_VEC_VAVGUB,
- ALTIVEC_BUILTIN_VEC_VAVGUH,
- ALTIVEC_BUILTIN_VEC_VAVGUW,
- ALTIVEC_BUILTIN_VEC_VCFSX,
- ALTIVEC_BUILTIN_VEC_VCFUX,
- ALTIVEC_BUILTIN_VEC_VCMPEQFP,
- ALTIVEC_BUILTIN_VEC_VCMPEQUB,
- ALTIVEC_BUILTIN_VEC_VCMPEQUH,
- ALTIVEC_BUILTIN_VEC_VCMPEQUW,
- ALTIVEC_BUILTIN_VEC_VCMPGTFP,
- ALTIVEC_BUILTIN_VEC_VCMPGTSB,
- ALTIVEC_BUILTIN_VEC_VCMPGTSH,
- ALTIVEC_BUILTIN_VEC_VCMPGTSW,
- ALTIVEC_BUILTIN_VEC_VCMPGTUB,
- ALTIVEC_BUILTIN_VEC_VCMPGTUH,
- ALTIVEC_BUILTIN_VEC_VCMPGTUW,
- ALTIVEC_BUILTIN_VEC_VMAXFP,
- ALTIVEC_BUILTIN_VEC_VMAXSB,
- ALTIVEC_BUILTIN_VEC_VMAXSH,
- ALTIVEC_BUILTIN_VEC_VMAXSW,
- ALTIVEC_BUILTIN_VEC_VMAXUB,
- ALTIVEC_BUILTIN_VEC_VMAXUH,
- ALTIVEC_BUILTIN_VEC_VMAXUW,
- ALTIVEC_BUILTIN_VEC_VMINFP,
- ALTIVEC_BUILTIN_VEC_VMINSB,
- ALTIVEC_BUILTIN_VEC_VMINSH,
- ALTIVEC_BUILTIN_VEC_VMINSW,
- ALTIVEC_BUILTIN_VEC_VMINUB,
- ALTIVEC_BUILTIN_VEC_VMINUH,
- ALTIVEC_BUILTIN_VEC_VMINUW,
- ALTIVEC_BUILTIN_VEC_VMRGHB,
- ALTIVEC_BUILTIN_VEC_VMRGHH,
- ALTIVEC_BUILTIN_VEC_VMRGHW,
- ALTIVEC_BUILTIN_VEC_VMRGLB,
- ALTIVEC_BUILTIN_VEC_VMRGLH,
- ALTIVEC_BUILTIN_VEC_VMRGLW,
- ALTIVEC_BUILTIN_VEC_VMSUMMBM,
- ALTIVEC_BUILTIN_VEC_VMSUMSHM,
- ALTIVEC_BUILTIN_VEC_VMSUMSHS,
- ALTIVEC_BUILTIN_VEC_VMSUMUBM,
- ALTIVEC_BUILTIN_VEC_VMSUMUHM,
- ALTIVEC_BUILTIN_VEC_VMSUMUHS,
- ALTIVEC_BUILTIN_VEC_VMULESB,
- ALTIVEC_BUILTIN_VEC_VMULESH,
- ALTIVEC_BUILTIN_VEC_VMULEUB,
- ALTIVEC_BUILTIN_VEC_VMULEUH,
- ALTIVEC_BUILTIN_VEC_VMULOSB,
- ALTIVEC_BUILTIN_VEC_VMULOSH,
- ALTIVEC_BUILTIN_VEC_VMULOUB,
- ALTIVEC_BUILTIN_VEC_VMULOUH,
- ALTIVEC_BUILTIN_VEC_VPKSHSS,
- ALTIVEC_BUILTIN_VEC_VPKSHUS,
- ALTIVEC_BUILTIN_VEC_VPKSWSS,
- ALTIVEC_BUILTIN_VEC_VPKSWUS,
- ALTIVEC_BUILTIN_VEC_VPKUHUM,
- ALTIVEC_BUILTIN_VEC_VPKUHUS,
- ALTIVEC_BUILTIN_VEC_VPKUWUM,
- ALTIVEC_BUILTIN_VEC_VPKUWUS,
- ALTIVEC_BUILTIN_VEC_VRLB,
- ALTIVEC_BUILTIN_VEC_VRLH,
- ALTIVEC_BUILTIN_VEC_VRLW,
- ALTIVEC_BUILTIN_VEC_VSLB,
- ALTIVEC_BUILTIN_VEC_VSLH,
- ALTIVEC_BUILTIN_VEC_VSLW,
- ALTIVEC_BUILTIN_VEC_VSPLTB,
- ALTIVEC_BUILTIN_VEC_VSPLTH,
- ALTIVEC_BUILTIN_VEC_VSPLTW,
- ALTIVEC_BUILTIN_VEC_VSRAB,
- ALTIVEC_BUILTIN_VEC_VSRAH,
- ALTIVEC_BUILTIN_VEC_VSRAW,
- ALTIVEC_BUILTIN_VEC_VSRB,
- ALTIVEC_BUILTIN_VEC_VSRH,
- ALTIVEC_BUILTIN_VEC_VSRW,
- ALTIVEC_BUILTIN_VEC_VSUBFP,
- ALTIVEC_BUILTIN_VEC_VSUBSBS,
- ALTIVEC_BUILTIN_VEC_VSUBSHS,
- ALTIVEC_BUILTIN_VEC_VSUBSWS,
- ALTIVEC_BUILTIN_VEC_VSUBUBM,
- ALTIVEC_BUILTIN_VEC_VSUBUBS,
- ALTIVEC_BUILTIN_VEC_VSUBUHM,
- ALTIVEC_BUILTIN_VEC_VSUBUHS,
- ALTIVEC_BUILTIN_VEC_VSUBUWM,
- ALTIVEC_BUILTIN_VEC_VSUBUWS,
- ALTIVEC_BUILTIN_VEC_VSUM4SBS,
- ALTIVEC_BUILTIN_VEC_VSUM4SHS,
- ALTIVEC_BUILTIN_VEC_VSUM4UBS,
- ALTIVEC_BUILTIN_VEC_VUPKHPX,
- ALTIVEC_BUILTIN_VEC_VUPKHSB,
- ALTIVEC_BUILTIN_VEC_VUPKHSH,
- ALTIVEC_BUILTIN_VEC_VUPKLPX,
- ALTIVEC_BUILTIN_VEC_VUPKLSB,
- ALTIVEC_BUILTIN_VEC_VUPKLSH,
- ALTIVEC_BUILTIN_VEC_XOR,
- ALTIVEC_BUILTIN_VEC_STEP,
- ALTIVEC_BUILTIN_VEC_PROMOTE,
- ALTIVEC_BUILTIN_VEC_INSERT,
- ALTIVEC_BUILTIN_VEC_SPLATS,
- ALTIVEC_BUILTIN_OVERLOADED_LAST = ALTIVEC_BUILTIN_VEC_SPLATS,
-
- /* SPE builtins. */
- SPE_BUILTIN_EVADDW,
- SPE_BUILTIN_EVAND,
- SPE_BUILTIN_EVANDC,
- SPE_BUILTIN_EVDIVWS,
- SPE_BUILTIN_EVDIVWU,
- SPE_BUILTIN_EVEQV,
- SPE_BUILTIN_EVFSADD,
- SPE_BUILTIN_EVFSDIV,
- SPE_BUILTIN_EVFSMUL,
- SPE_BUILTIN_EVFSSUB,
- SPE_BUILTIN_EVLDDX,
- SPE_BUILTIN_EVLDHX,
- SPE_BUILTIN_EVLDWX,
- SPE_BUILTIN_EVLHHESPLATX,
- SPE_BUILTIN_EVLHHOSSPLATX,
- SPE_BUILTIN_EVLHHOUSPLATX,
- SPE_BUILTIN_EVLWHEX,
- SPE_BUILTIN_EVLWHOSX,
- SPE_BUILTIN_EVLWHOUX,
- SPE_BUILTIN_EVLWHSPLATX,
- SPE_BUILTIN_EVLWWSPLATX,
- SPE_BUILTIN_EVMERGEHI,
- SPE_BUILTIN_EVMERGEHILO,
- SPE_BUILTIN_EVMERGELO,
- SPE_BUILTIN_EVMERGELOHI,
- SPE_BUILTIN_EVMHEGSMFAA,
- SPE_BUILTIN_EVMHEGSMFAN,
- SPE_BUILTIN_EVMHEGSMIAA,
- SPE_BUILTIN_EVMHEGSMIAN,
- SPE_BUILTIN_EVMHEGUMIAA,
- SPE_BUILTIN_EVMHEGUMIAN,
- SPE_BUILTIN_EVMHESMF,
- SPE_BUILTIN_EVMHESMFA,
- SPE_BUILTIN_EVMHESMFAAW,
- SPE_BUILTIN_EVMHESMFANW,
- SPE_BUILTIN_EVMHESMI,
- SPE_BUILTIN_EVMHESMIA,
- SPE_BUILTIN_EVMHESMIAAW,
- SPE_BUILTIN_EVMHESMIANW,
- SPE_BUILTIN_EVMHESSF,
- SPE_BUILTIN_EVMHESSFA,
- SPE_BUILTIN_EVMHESSFAAW,
- SPE_BUILTIN_EVMHESSFANW,
- SPE_BUILTIN_EVMHESSIAAW,
- SPE_BUILTIN_EVMHESSIANW,
- SPE_BUILTIN_EVMHEUMI,
- SPE_BUILTIN_EVMHEUMIA,
- SPE_BUILTIN_EVMHEUMIAAW,
- SPE_BUILTIN_EVMHEUMIANW,
- SPE_BUILTIN_EVMHEUSIAAW,
- SPE_BUILTIN_EVMHEUSIANW,
- SPE_BUILTIN_EVMHOGSMFAA,
- SPE_BUILTIN_EVMHOGSMFAN,
- SPE_BUILTIN_EVMHOGSMIAA,
- SPE_BUILTIN_EVMHOGSMIAN,
- SPE_BUILTIN_EVMHOGUMIAA,
- SPE_BUILTIN_EVMHOGUMIAN,
- SPE_BUILTIN_EVMHOSMF,
- SPE_BUILTIN_EVMHOSMFA,
- SPE_BUILTIN_EVMHOSMFAAW,
- SPE_BUILTIN_EVMHOSMFANW,
- SPE_BUILTIN_EVMHOSMI,
- SPE_BUILTIN_EVMHOSMIA,
- SPE_BUILTIN_EVMHOSMIAAW,
- SPE_BUILTIN_EVMHOSMIANW,
- SPE_BUILTIN_EVMHOSSF,
- SPE_BUILTIN_EVMHOSSFA,
- SPE_BUILTIN_EVMHOSSFAAW,
- SPE_BUILTIN_EVMHOSSFANW,
- SPE_BUILTIN_EVMHOSSIAAW,
- SPE_BUILTIN_EVMHOSSIANW,
- SPE_BUILTIN_EVMHOUMI,
- SPE_BUILTIN_EVMHOUMIA,
- SPE_BUILTIN_EVMHOUMIAAW,
- SPE_BUILTIN_EVMHOUMIANW,
- SPE_BUILTIN_EVMHOUSIAAW,
- SPE_BUILTIN_EVMHOUSIANW,
- SPE_BUILTIN_EVMWHSMF,
- SPE_BUILTIN_EVMWHSMFA,
- SPE_BUILTIN_EVMWHSMI,
- SPE_BUILTIN_EVMWHSMIA,
- SPE_BUILTIN_EVMWHSSF,
- SPE_BUILTIN_EVMWHSSFA,
- SPE_BUILTIN_EVMWHUMI,
- SPE_BUILTIN_EVMWHUMIA,
- SPE_BUILTIN_EVMWLSMIAAW,
- SPE_BUILTIN_EVMWLSMIANW,
- SPE_BUILTIN_EVMWLSSIAAW,
- SPE_BUILTIN_EVMWLSSIANW,
- SPE_BUILTIN_EVMWLUMI,
- SPE_BUILTIN_EVMWLUMIA,
- SPE_BUILTIN_EVMWLUMIAAW,
- SPE_BUILTIN_EVMWLUMIANW,
- SPE_BUILTIN_EVMWLUSIAAW,
- SPE_BUILTIN_EVMWLUSIANW,
- SPE_BUILTIN_EVMWSMF,
- SPE_BUILTIN_EVMWSMFA,
- SPE_BUILTIN_EVMWSMFAA,
- SPE_BUILTIN_EVMWSMFAN,
- SPE_BUILTIN_EVMWSMI,
- SPE_BUILTIN_EVMWSMIA,
- SPE_BUILTIN_EVMWSMIAA,
- SPE_BUILTIN_EVMWSMIAN,
- SPE_BUILTIN_EVMWHSSFAA,
- SPE_BUILTIN_EVMWSSF,
- SPE_BUILTIN_EVMWSSFA,
- SPE_BUILTIN_EVMWSSFAA,
- SPE_BUILTIN_EVMWSSFAN,
- SPE_BUILTIN_EVMWUMI,
- SPE_BUILTIN_EVMWUMIA,
- SPE_BUILTIN_EVMWUMIAA,
- SPE_BUILTIN_EVMWUMIAN,
- SPE_BUILTIN_EVNAND,
- SPE_BUILTIN_EVNOR,
- SPE_BUILTIN_EVOR,
- SPE_BUILTIN_EVORC,
- SPE_BUILTIN_EVRLW,
- SPE_BUILTIN_EVSLW,
- SPE_BUILTIN_EVSRWS,
- SPE_BUILTIN_EVSRWU,
- SPE_BUILTIN_EVSTDDX,
- SPE_BUILTIN_EVSTDHX,
- SPE_BUILTIN_EVSTDWX,
- SPE_BUILTIN_EVSTWHEX,
- SPE_BUILTIN_EVSTWHOX,
- SPE_BUILTIN_EVSTWWEX,
- SPE_BUILTIN_EVSTWWOX,
- SPE_BUILTIN_EVSUBFW,
- SPE_BUILTIN_EVXOR,
- SPE_BUILTIN_EVABS,
- SPE_BUILTIN_EVADDSMIAAW,
- SPE_BUILTIN_EVADDSSIAAW,
- SPE_BUILTIN_EVADDUMIAAW,
- SPE_BUILTIN_EVADDUSIAAW,
- SPE_BUILTIN_EVCNTLSW,
- SPE_BUILTIN_EVCNTLZW,
- SPE_BUILTIN_EVEXTSB,
- SPE_BUILTIN_EVEXTSH,
- SPE_BUILTIN_EVFSABS,
- SPE_BUILTIN_EVFSCFSF,
- SPE_BUILTIN_EVFSCFSI,
- SPE_BUILTIN_EVFSCFUF,
- SPE_BUILTIN_EVFSCFUI,
- SPE_BUILTIN_EVFSCTSF,
- SPE_BUILTIN_EVFSCTSI,
- SPE_BUILTIN_EVFSCTSIZ,
- SPE_BUILTIN_EVFSCTUF,
- SPE_BUILTIN_EVFSCTUI,
- SPE_BUILTIN_EVFSCTUIZ,
- SPE_BUILTIN_EVFSNABS,
- SPE_BUILTIN_EVFSNEG,
- SPE_BUILTIN_EVMRA,
- SPE_BUILTIN_EVNEG,
- SPE_BUILTIN_EVRNDW,
- SPE_BUILTIN_EVSUBFSMIAAW,
- SPE_BUILTIN_EVSUBFSSIAAW,
- SPE_BUILTIN_EVSUBFUMIAAW,
- SPE_BUILTIN_EVSUBFUSIAAW,
- SPE_BUILTIN_EVADDIW,
- SPE_BUILTIN_EVLDD,
- SPE_BUILTIN_EVLDH,
- SPE_BUILTIN_EVLDW,
- SPE_BUILTIN_EVLHHESPLAT,
- SPE_BUILTIN_EVLHHOSSPLAT,
- SPE_BUILTIN_EVLHHOUSPLAT,
- SPE_BUILTIN_EVLWHE,
- SPE_BUILTIN_EVLWHOS,
- SPE_BUILTIN_EVLWHOU,
- SPE_BUILTIN_EVLWHSPLAT,
- SPE_BUILTIN_EVLWWSPLAT,
- SPE_BUILTIN_EVRLWI,
- SPE_BUILTIN_EVSLWI,
- SPE_BUILTIN_EVSRWIS,
- SPE_BUILTIN_EVSRWIU,
- SPE_BUILTIN_EVSTDD,
- SPE_BUILTIN_EVSTDH,
- SPE_BUILTIN_EVSTDW,
- SPE_BUILTIN_EVSTWHE,
- SPE_BUILTIN_EVSTWHO,
- SPE_BUILTIN_EVSTWWE,
- SPE_BUILTIN_EVSTWWO,
- SPE_BUILTIN_EVSUBIFW,
-
- /* Compares. */
- SPE_BUILTIN_EVCMPEQ,
- SPE_BUILTIN_EVCMPGTS,
- SPE_BUILTIN_EVCMPGTU,
- SPE_BUILTIN_EVCMPLTS,
- SPE_BUILTIN_EVCMPLTU,
- SPE_BUILTIN_EVFSCMPEQ,
- SPE_BUILTIN_EVFSCMPGT,
- SPE_BUILTIN_EVFSCMPLT,
- SPE_BUILTIN_EVFSTSTEQ,
- SPE_BUILTIN_EVFSTSTGT,
- SPE_BUILTIN_EVFSTSTLT,
-
- /* EVSEL compares. */
- SPE_BUILTIN_EVSEL_CMPEQ,
- SPE_BUILTIN_EVSEL_CMPGTS,
- SPE_BUILTIN_EVSEL_CMPGTU,
- SPE_BUILTIN_EVSEL_CMPLTS,
- SPE_BUILTIN_EVSEL_CMPLTU,
- SPE_BUILTIN_EVSEL_FSCMPEQ,
- SPE_BUILTIN_EVSEL_FSCMPGT,
- SPE_BUILTIN_EVSEL_FSCMPLT,
- SPE_BUILTIN_EVSEL_FSTSTEQ,
- SPE_BUILTIN_EVSEL_FSTSTGT,
- SPE_BUILTIN_EVSEL_FSTSTLT,
-
- SPE_BUILTIN_EVSPLATFI,
- SPE_BUILTIN_EVSPLATI,
- SPE_BUILTIN_EVMWHSSMAA,
- SPE_BUILTIN_EVMWHSMFAA,
- SPE_BUILTIN_EVMWHSMIAA,
- SPE_BUILTIN_EVMWHUSIAA,
- SPE_BUILTIN_EVMWHUMIAA,
- SPE_BUILTIN_EVMWHSSFAN,
- SPE_BUILTIN_EVMWHSSIAN,
- SPE_BUILTIN_EVMWHSMFAN,
- SPE_BUILTIN_EVMWHSMIAN,
- SPE_BUILTIN_EVMWHUSIAN,
- SPE_BUILTIN_EVMWHUMIAN,
- SPE_BUILTIN_EVMWHGSSFAA,
- SPE_BUILTIN_EVMWHGSMFAA,
- SPE_BUILTIN_EVMWHGSMIAA,
- SPE_BUILTIN_EVMWHGUMIAA,
- SPE_BUILTIN_EVMWHGSSFAN,
- SPE_BUILTIN_EVMWHGSMFAN,
- SPE_BUILTIN_EVMWHGSMIAN,
- SPE_BUILTIN_EVMWHGUMIAN,
- SPE_BUILTIN_MTSPEFSCR,
- SPE_BUILTIN_MFSPEFSCR,
- SPE_BUILTIN_BRINC,
-
- /* PAIRED builtins. */
- PAIRED_BUILTIN_DIVV2SF3,
- PAIRED_BUILTIN_ABSV2SF2,
- PAIRED_BUILTIN_NEGV2SF2,
- PAIRED_BUILTIN_SQRTV2SF2,
- PAIRED_BUILTIN_ADDV2SF3,
- PAIRED_BUILTIN_SUBV2SF3,
- PAIRED_BUILTIN_RESV2SF2,
- PAIRED_BUILTIN_MULV2SF3,
- PAIRED_BUILTIN_MSUB,
- PAIRED_BUILTIN_MADD,
- PAIRED_BUILTIN_NMSUB,
- PAIRED_BUILTIN_NMADD,
- PAIRED_BUILTIN_NABSV2SF2,
- PAIRED_BUILTIN_SUM0,
- PAIRED_BUILTIN_SUM1,
- PAIRED_BUILTIN_MULS0,
- PAIRED_BUILTIN_MULS1,
- PAIRED_BUILTIN_MERGE00,
- PAIRED_BUILTIN_MERGE01,
- PAIRED_BUILTIN_MERGE10,
- PAIRED_BUILTIN_MERGE11,
- PAIRED_BUILTIN_MADDS0,
- PAIRED_BUILTIN_MADDS1,
- PAIRED_BUILTIN_STX,
- PAIRED_BUILTIN_LX,
- PAIRED_BUILTIN_SELV2SF4,
- PAIRED_BUILTIN_CMPU0,
- PAIRED_BUILTIN_CMPU1,
-
- RS6000_BUILTIN_RECIP,
- RS6000_BUILTIN_RECIPF,
- RS6000_BUILTIN_RSQRTF,
- RS6000_BUILTIN_BSWAP_HI,
-
- /* VSX builtins. */
- VSX_BUILTIN_LXSDUX,
- VSX_BUILTIN_LXSDX,
- VSX_BUILTIN_LXVD2UX,
- VSX_BUILTIN_LXVD2X,
- VSX_BUILTIN_LXVDSX,
- VSX_BUILTIN_LXVW4UX,
- VSX_BUILTIN_LXVW4X,
- VSX_BUILTIN_STXSDUX,
- VSX_BUILTIN_STXSDX,
- VSX_BUILTIN_STXVD2UX,
- VSX_BUILTIN_STXVD2X,
- VSX_BUILTIN_STXVW4UX,
- VSX_BUILTIN_STXVW4X,
- VSX_BUILTIN_XSABSDP,
- VSX_BUILTIN_XSADDDP,
- VSX_BUILTIN_XSCMPODP,
- VSX_BUILTIN_XSCMPUDP,
- VSX_BUILTIN_XSCPSGNDP,
- VSX_BUILTIN_XSCVDPSP,
- VSX_BUILTIN_XSCVDPSXDS,
- VSX_BUILTIN_XSCVDPSXWS,
- VSX_BUILTIN_XSCVDPUXDS,
- VSX_BUILTIN_XSCVDPUXWS,
- VSX_BUILTIN_XSCVSPDP,
- VSX_BUILTIN_XSCVSXDDP,
- VSX_BUILTIN_XSCVUXDDP,
- VSX_BUILTIN_XSDIVDP,
- VSX_BUILTIN_XSMADDADP,
- VSX_BUILTIN_XSMADDMDP,
- VSX_BUILTIN_XSMAXDP,
- VSX_BUILTIN_XSMINDP,
- VSX_BUILTIN_XSMOVDP,
- VSX_BUILTIN_XSMSUBADP,
- VSX_BUILTIN_XSMSUBMDP,
- VSX_BUILTIN_XSMULDP,
- VSX_BUILTIN_XSNABSDP,
- VSX_BUILTIN_XSNEGDP,
- VSX_BUILTIN_XSNMADDADP,
- VSX_BUILTIN_XSNMADDMDP,
- VSX_BUILTIN_XSNMSUBADP,
- VSX_BUILTIN_XSNMSUBMDP,
- VSX_BUILTIN_XSRDPI,
- VSX_BUILTIN_XSRDPIC,
- VSX_BUILTIN_XSRDPIM,
- VSX_BUILTIN_XSRDPIP,
- VSX_BUILTIN_XSRDPIZ,
- VSX_BUILTIN_XSREDP,
- VSX_BUILTIN_XSRSQRTEDP,
- VSX_BUILTIN_XSSQRTDP,
- VSX_BUILTIN_XSSUBDP,
- VSX_BUILTIN_CPSGNDP,
- VSX_BUILTIN_CPSGNSP,
- VSX_BUILTIN_XSTDIVDP_FE,
- VSX_BUILTIN_XSTDIVDP_FG,
- VSX_BUILTIN_XSTSQRTDP_FE,
- VSX_BUILTIN_XSTSQRTDP_FG,
- VSX_BUILTIN_XVABSDP,
- VSX_BUILTIN_XVABSSP,
- VSX_BUILTIN_XVADDDP,
- VSX_BUILTIN_XVADDSP,
- VSX_BUILTIN_XVCMPEQDP,
- VSX_BUILTIN_XVCMPEQSP,
- VSX_BUILTIN_XVCMPGEDP,
- VSX_BUILTIN_XVCMPGESP,
- VSX_BUILTIN_XVCMPGTDP,
- VSX_BUILTIN_XVCMPGTSP,
- VSX_BUILTIN_XVCMPEQDP_P,
- VSX_BUILTIN_XVCMPEQSP_P,
- VSX_BUILTIN_XVCMPGEDP_P,
- VSX_BUILTIN_XVCMPGESP_P,
- VSX_BUILTIN_XVCMPGTDP_P,
- VSX_BUILTIN_XVCMPGTSP_P,
- VSX_BUILTIN_XVCPSGNDP,
- VSX_BUILTIN_XVCPSGNSP,
- VSX_BUILTIN_XVCVDPSP,
- VSX_BUILTIN_XVCVDPSXDS,
- VSX_BUILTIN_XVCVDPSXWS,
- VSX_BUILTIN_XVCVDPUXDS,
- VSX_BUILTIN_XVCVDPUXDS_UNS,
- VSX_BUILTIN_XVCVDPUXWS,
- VSX_BUILTIN_XVCVSPDP,
- VSX_BUILTIN_XVCVSPSXDS,
- VSX_BUILTIN_XVCVSPSXWS,
- VSX_BUILTIN_XVCVSPUXDS,
- VSX_BUILTIN_XVCVSPUXWS,
- VSX_BUILTIN_XVCVSXDDP,
- VSX_BUILTIN_XVCVSXDSP,
- VSX_BUILTIN_XVCVSXWDP,
- VSX_BUILTIN_XVCVSXWSP,
- VSX_BUILTIN_XVCVUXDDP,
- VSX_BUILTIN_XVCVUXDDP_UNS,
- VSX_BUILTIN_XVCVUXDSP,
- VSX_BUILTIN_XVCVUXWDP,
- VSX_BUILTIN_XVCVUXWSP,
- VSX_BUILTIN_XVDIVDP,
- VSX_BUILTIN_XVDIVSP,
- VSX_BUILTIN_XVMADDDP,
- VSX_BUILTIN_XVMADDSP,
- VSX_BUILTIN_XVMAXDP,
- VSX_BUILTIN_XVMAXSP,
- VSX_BUILTIN_XVMINDP,
- VSX_BUILTIN_XVMINSP,
- VSX_BUILTIN_XVMSUBDP,
- VSX_BUILTIN_XVMSUBSP,
- VSX_BUILTIN_XVMULDP,
- VSX_BUILTIN_XVMULSP,
- VSX_BUILTIN_XVNABSDP,
- VSX_BUILTIN_XVNABSSP,
- VSX_BUILTIN_XVNEGDP,
- VSX_BUILTIN_XVNEGSP,
- VSX_BUILTIN_XVNMADDDP,
- VSX_BUILTIN_XVNMADDSP,
- VSX_BUILTIN_XVNMSUBDP,
- VSX_BUILTIN_XVNMSUBSP,
- VSX_BUILTIN_XVRDPI,
- VSX_BUILTIN_XVRDPIC,
- VSX_BUILTIN_XVRDPIM,
- VSX_BUILTIN_XVRDPIP,
- VSX_BUILTIN_XVRDPIZ,
- VSX_BUILTIN_XVREDP,
- VSX_BUILTIN_XVRESP,
- VSX_BUILTIN_XVRSPI,
- VSX_BUILTIN_XVRSPIC,
- VSX_BUILTIN_XVRSPIM,
- VSX_BUILTIN_XVRSPIP,
- VSX_BUILTIN_XVRSPIZ,
- VSX_BUILTIN_XVRSQRTEDP,
- VSX_BUILTIN_XVRSQRTESP,
- VSX_BUILTIN_XVSQRTDP,
- VSX_BUILTIN_XVSQRTSP,
- VSX_BUILTIN_XVSUBDP,
- VSX_BUILTIN_XVSUBSP,
- VSX_BUILTIN_XVTDIVDP_FE,
- VSX_BUILTIN_XVTDIVDP_FG,
- VSX_BUILTIN_XVTDIVSP_FE,
- VSX_BUILTIN_XVTDIVSP_FG,
- VSX_BUILTIN_XVTSQRTDP_FE,
- VSX_BUILTIN_XVTSQRTDP_FG,
- VSX_BUILTIN_XVTSQRTSP_FE,
- VSX_BUILTIN_XVTSQRTSP_FG,
- VSX_BUILTIN_XXSEL_2DI,
- VSX_BUILTIN_XXSEL_2DF,
- VSX_BUILTIN_XXSEL_4SI,
- VSX_BUILTIN_XXSEL_4SF,
- VSX_BUILTIN_XXSEL_8HI,
- VSX_BUILTIN_XXSEL_16QI,
- VSX_BUILTIN_XXSEL_2DI_UNS,
- VSX_BUILTIN_XXSEL_4SI_UNS,
- VSX_BUILTIN_XXSEL_8HI_UNS,
- VSX_BUILTIN_XXSEL_16QI_UNS,
- VSX_BUILTIN_VPERM_2DI,
- VSX_BUILTIN_VPERM_2DF,
- VSX_BUILTIN_VPERM_4SI,
- VSX_BUILTIN_VPERM_4SF,
- VSX_BUILTIN_VPERM_8HI,
- VSX_BUILTIN_VPERM_16QI,
- VSX_BUILTIN_VPERM_2DI_UNS,
- VSX_BUILTIN_VPERM_4SI_UNS,
- VSX_BUILTIN_VPERM_8HI_UNS,
- VSX_BUILTIN_VPERM_16QI_UNS,
- VSX_BUILTIN_XXPERMDI_2DF,
- VSX_BUILTIN_XXPERMDI_2DI,
- VSX_BUILTIN_XXPERMDI_4SF,
- VSX_BUILTIN_XXPERMDI_4SI,
- VSX_BUILTIN_XXPERMDI_8HI,
- VSX_BUILTIN_XXPERMDI_16QI,
- VSX_BUILTIN_CONCAT_2DF,
- VSX_BUILTIN_CONCAT_2DI,
- VSX_BUILTIN_SET_2DF,
- VSX_BUILTIN_SET_2DI,
- VSX_BUILTIN_SPLAT_2DF,
- VSX_BUILTIN_SPLAT_2DI,
- VSX_BUILTIN_XXMRGHW_4SF,
- VSX_BUILTIN_XXMRGHW_4SI,
- VSX_BUILTIN_XXMRGLW_4SF,
- VSX_BUILTIN_XXMRGLW_4SI,
- VSX_BUILTIN_XXSLDWI_16QI,
- VSX_BUILTIN_XXSLDWI_8HI,
- VSX_BUILTIN_XXSLDWI_4SI,
- VSX_BUILTIN_XXSLDWI_4SF,
- VSX_BUILTIN_XXSLDWI_2DI,
- VSX_BUILTIN_XXSLDWI_2DF,
- VSX_BUILTIN_VEC_INIT_V2DF,
- VSX_BUILTIN_VEC_INIT_V2DI,
- VSX_BUILTIN_VEC_SET_V2DF,
- VSX_BUILTIN_VEC_SET_V2DI,
- VSX_BUILTIN_VEC_EXT_V2DF,
- VSX_BUILTIN_VEC_EXT_V2DI,
-
- /* VSX overloaded builtins, add the overloaded functions not present in
- Altivec. */
- VSX_BUILTIN_VEC_MUL,
- VSX_BUILTIN_OVERLOADED_FIRST = VSX_BUILTIN_VEC_MUL,
- VSX_BUILTIN_VEC_MSUB,
- VSX_BUILTIN_VEC_NMADD,
- VSX_BUITLIN_VEC_NMSUB,
- VSX_BUILTIN_VEC_DIV,
- VSX_BUILTIN_VEC_XXMRGHW,
- VSX_BUILTIN_VEC_XXMRGLW,
- VSX_BUILTIN_VEC_XXPERMDI,
- VSX_BUILTIN_VEC_XXSLDWI,
- VSX_BUILTIN_VEC_XXSPLTD,
- VSX_BUILTIN_VEC_XXSPLTW,
- VSX_BUILTIN_OVERLOADED_LAST = VSX_BUILTIN_VEC_XXSPLTW,
-
- /* Combined VSX/Altivec builtins. */
- VECTOR_BUILTIN_FLOAT_V4SI_V4SF,
- VECTOR_BUILTIN_UNSFLOAT_V4SI_V4SF,
- VECTOR_BUILTIN_FIX_V4SF_V4SI,
- VECTOR_BUILTIN_FIXUNS_V4SF_V4SI,
-
- /* Power7 builtins, that aren't VSX instructions. */
- POWER7_BUILTIN_BPERMD,
+#include "rs6000-builtin.def"
RS6000_BUILTIN_COUNT
};
+#undef RS6000_BUILTIN
+#undef RS6000_BUILTIN_EQUATE
+
enum rs6000_builtin_type_index
{
RS6000_BTI_NOT_OPAQUE,
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