* config/rs6000/spe.md (SPE_ACC_REGNO): Delete definition.

[pf3gnuchains/gcc-fork.git] / gcc / config / rs6000 / rs6000.h

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 8aadc43..475e466 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -590,6 +590,7 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN)                             \
   (STRICT_ALIGNMENT                                                    \
    || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode       \
+       || (MODE) == DDmode || (MODE) == TDmode                         \
        || (MODE) == DImode)                                            \
        && (ALIGN) < 32))
 \f
@@ -723,21 +724,7 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
    , 0, 0, 0                                       \
 }
 
-#define MQ_REGNO     64
-#define CR0_REGNO    68
-#define CR1_REGNO    69
-#define CR2_REGNO    70
-#define CR3_REGNO    71
-#define CR4_REGNO    72
-#define MAX_CR_REGNO 75
-#define XER_REGNO    76
-#define FIRST_ALTIVEC_REGNO    77
-#define LAST_ALTIVEC_REGNO     108
 #define TOTAL_ALTIVEC_REGS     (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
-#define VRSAVE_REGNO           109
-#define VSCR_REGNO             110
-#define SPE_ACC_REGNO          111
-#define SPEFSCR_REGNO          112
 
 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
 #define FIRST_SAVED_FP_REGNO    (14+32)
@@ -811,10 +798,10 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
 
 /* True if register is a condition register.  */
-#define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
+#define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
 
 /* True if register is a condition register, but not cr0.  */
-#define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
+#define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
 
 /* True if register is an integer register.  */
 #define INT_REGNO_P(N) \
@@ -887,7 +874,7 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
    emitted the vrsave mask.  */
 
 #define HARD_REGNO_RENAME_OK(SRC, DST) \
-  (! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST])
+  (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
 
 /* A C expression returning the cost of moving data from a register of class
    CLASS1 to one of CLASS2.  */
@@ -912,18 +899,12 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
 
 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
 
-/* A fixed register used at prologue and epilogue generation to fix
-   addressing modes.  The SPE needs heavy addressing fixes at the last
-   minute, and it's best to save a register for it.
+/* A fixed register used at epilogue generation to address SPE registers
+   with negative offsets.  The 64-bit load/store instructions on the SPE
+   only take positive offsets (and small ones at that), so we need to
+   reserve a register for consing up negative offsets.  */
 
-   AltiVec also needs fixes, but we've gotten around using r11, which
-   is actually wrong because when use_backchain_to_restore_sp is true,
-   we end up clobbering r11.
-
-   The AltiVec case needs to be fixed.  Dunno if we should break ABI
-   compatibility and reserve a register for it as well..  */
-
-#define FIXED_SCRATCH (TARGET_SPE ? 14 : 11)
+#define FIXED_SCRATCH 0
 
 /* Define this macro to change register usage conditional on target
    flags.  */
@@ -957,11 +938,6 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
 /* Place to put static chain when calling a function that requires it.  */
 #define STATIC_CHAIN_REGNUM 11
 
-/* Link register number.  */
-#define LINK_REGISTER_REGNUM 65
-
-/* Count register number.  */
-#define COUNT_REGISTER_REGNUM 66
 \f
 /* Define the classes of registers for register constraints in the
    machine description.  Also define ranges of constants.
@@ -1090,8 +1066,8 @@ enum reg_class
   : (REGNO) == CR0_REGNO ? CR0_REGS            \
   : CR_REGNO_P (REGNO) ? CR_REGS               \
   : (REGNO) == MQ_REGNO ? MQ_REGS              \
-  : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS        \
-  : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS        \
+  : (REGNO) == LR_REGNO ? LINK_REGS    \
+  : (REGNO) == CTR_REGNO ? CTR_REGS    \
   : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS  \
   : (REGNO) == XER_REGNO ? XER_REGS            \
   : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS      \
@@ -1147,10 +1123,14 @@ enum reg_class
 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE)                    \
  ((CLASS1) != (CLASS2) && (((CLASS1) == FLOAT_REGS                     \
                             && (!TARGET_MFPGPR || !TARGET_POWERPC64    \
-                               || ((MODE != DFmode) && (MODE != DImode)))) \
+                               || ((MODE != DFmode)                    \
+                                   && (MODE != DDmode)                 \
+                                   && (MODE != DImode))))              \
                           || ((CLASS2) == FLOAT_REGS                   \
                                && (!TARGET_MFPGPR || !TARGET_POWERPC64 \
-                               || ((MODE != DFmode) && (MODE != DImode)))) \
+                                  || ((MODE != DFmode)                 \
+                                      && (MODE != DDmode)              \
+                                      && (MODE != DImode))))           \
                           || (CLASS1) == ALTIVEC_REGS                  \
                           || (CLASS2) == ALTIVEC_REGS))
 
@@ -1504,7 +1484,7 @@ typedef struct rs6000_args
    needed.  */
 
 #define        EPILOGUE_USES(REGNO)                                    \
-  ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM)       \
+  ((reload_completed && (REGNO) == LR_REGNO)                   \
    || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO)              \
    || (current_function_calls_eh_return                                \
        && TARGET_AIX                                           \
@@ -1599,6 +1579,8 @@ typedef struct rs6000_args
 
 #define HAVE_PRE_DECREMENT 1
 #define HAVE_PRE_INCREMENT 1
+#define HAVE_PRE_MODIFY_DISP 1
+#define HAVE_PRE_MODIFY_REG 1
 
 /* Macros to check register numbers against specific register classes.  */
 
@@ -2243,8 +2225,8 @@ extern char rs6000_reg_names[][8];        /* register names (0 vs. %r0).  */
    dwarf2 unwind information.  This also enables the table driven
    mechanism.  */
 
-#define INCOMING_RETURN_ADDR_RTX   gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
-#define DWARF_FRAME_RETURN_COLUMN  DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
+#define INCOMING_RETURN_ADDR_RTX   gen_rtx_REG (Pmode, LR_REGNO)
+#define DWARF_FRAME_RETURN_COLUMN  DWARF_FRAME_REGNUM (LR_REGNO)
 
 /* Describe how we implement __builtin_eh_return.  */
 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)