/* Subroutines for insn-output.c for Matsushita MN10300 series
- Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
- Free Software Foundation, Inc.
+ Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
+ 2005, 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
Contributed by Jeff Law (law@cygnus.com).
-This file is part of GCC.
+ This file is part of GCC.
-GCC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
-GCC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with GCC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "tree.h"
#include "regs.h"
#include "hard-reg-set.h"
-#include "real.h"
#include "insn-config.h"
#include "conditions.h"
#include "output.h"
#include "insn-attr.h"
#include "flags.h"
#include "recog.h"
+#include "reload.h"
#include "expr.h"
#include "optabs.h"
#include "function.h"
#include "obstack.h"
-#include "toplev.h"
+#include "diagnostic-core.h"
#include "tm_p.h"
+#include "tm-constrs.h"
#include "target.h"
#include "target-def.h"
-
-/* This is used by GOTaddr2picreg to uniquely identify
- UNSPEC_INT_LABELs. */
-int mn10300_unspec_int_label_counter;
+#include "df.h"
+#include "opts.h"
+#include "cfgloop.h"
/* This is used in the am33_2.0-linux-gnu port, in which global symbol
names are not prefixed by underscores, to tell whether to prefix a
symbol names from register names. */
int mn10300_protect_label;
+/* Selected processor type for tuning. */
+enum processor_type mn10300_tune_cpu = PROCESSOR_DEFAULT;
+
/* The size of the callee register save area. Right now we save everything
on entry since it costs us nothing in code size. It does cost us from a
speed standpoint, so we want to optimize this sooner or later. */
-#define REG_SAVE_BYTES (4 * regs_ever_live[2] \
- + 4 * regs_ever_live[3] \
- + 4 * regs_ever_live[6] \
- + 4 * regs_ever_live[7] \
- + 16 * (regs_ever_live[14] || regs_ever_live[15] \
- || regs_ever_live[16] || regs_ever_live[17]))
-
-
-static int mn10300_address_cost_1 (rtx, int *);
-static int mn10300_address_cost (rtx);
-static bool mn10300_rtx_costs (rtx, int, int, int *);
-static void mn10300_file_start (void);
-
+#define REG_SAVE_BYTES (4 * df_regs_ever_live_p (2) \
+ + 4 * df_regs_ever_live_p (3) \
+ + 4 * df_regs_ever_live_p (6) \
+ + 4 * df_regs_ever_live_p (7) \
+ + 16 * (df_regs_ever_live_p (14) \
+ || df_regs_ever_live_p (15) \
+ || df_regs_ever_live_p (16) \
+ || df_regs_ever_live_p (17)))
+
+#define CC_FLAG_Z 1
+#define CC_FLAG_N 2
+#define CC_FLAG_C 4
+#define CC_FLAG_V 8
+
+static int cc_flags_for_mode(enum machine_mode);
+static int cc_flags_for_code(enum rtx_code);
\f
-/* Initialize the GCC target structure. */
-#undef TARGET_ASM_ALIGNED_HI_OP
-#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
-
-#undef TARGET_RTX_COSTS
-#define TARGET_RTX_COSTS mn10300_rtx_costs
-#undef TARGET_ADDRESS_COST
-#define TARGET_ADDRESS_COST mn10300_address_cost
+/* Implement TARGET_OPTION_OVERRIDE. */
-#undef TARGET_ASM_FILE_START
-#define TARGET_ASM_FILE_START mn10300_file_start
-#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
-#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
+static void
+mn10300_option_override (void)
+{
+ if (TARGET_AM33)
+ target_flags &= ~MASK_MULT_BUG;
+ else
+ {
+ /* Disable scheduling for the MN10300 as we do
+ not have timing information available for it. */
+ flag_schedule_insns = 0;
+ flag_schedule_insns_after_reload = 0;
+
+ /* Force enable splitting of wide types, as otherwise it is trivial
+ to run out of registers. Indeed, this works so well that register
+ allocation problems are now more common *without* optimization,
+ when this flag is not enabled by default. */
+ flag_split_wide_types = 1;
+ }
-#undef TARGET_ENCODE_SECTION_INFO
-#define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
+ if (mn10300_tune_string)
+ {
+ if (strcasecmp (mn10300_tune_string, "mn10300") == 0)
+ mn10300_tune_cpu = PROCESSOR_MN10300;
+ else if (strcasecmp (mn10300_tune_string, "am33") == 0)
+ mn10300_tune_cpu = PROCESSOR_AM33;
+ else if (strcasecmp (mn10300_tune_string, "am33-2") == 0)
+ mn10300_tune_cpu = PROCESSOR_AM33_2;
+ else if (strcasecmp (mn10300_tune_string, "am34") == 0)
+ mn10300_tune_cpu = PROCESSOR_AM34;
+ else
+ error ("-mtune= expects mn10300, am33, am33-2, or am34");
+ }
+}
-static void mn10300_encode_section_info (tree, rtx, int);
-struct gcc_target targetm = TARGET_INITIALIZER;
-\f
static void
mn10300_file_start (void)
{
fprintf (asm_out_file, "\t.am33\n");
}
\f
+/* Note: This list must match the liw_op attribute in mn10300.md. */
+
+static const char *liw_op_names[] =
+{
+ "add", "cmp", "sub", "mov",
+ "and", "or", "xor",
+ "asr", "lsr", "asl",
+ "none", "max"
+};
/* Print operand X using operand code CODE to assembly language output file
FILE. */
void
-print_operand (FILE *file, rtx x, int code)
+mn10300_print_operand (FILE *file, rtx x, int code)
{
switch (code)
{
- case 'b':
- case 'B':
- if (cc_status.mdep.fpCC)
- {
- switch (code == 'b' ? GET_CODE (x)
- : reverse_condition_maybe_unordered (GET_CODE (x)))
- {
- case NE:
- fprintf (file, "ne");
- break;
- case EQ:
- fprintf (file, "eq");
- break;
- case GE:
- fprintf (file, "ge");
- break;
- case GT:
- fprintf (file, "gt");
- break;
- case LE:
- fprintf (file, "le");
- break;
- case LT:
- fprintf (file, "lt");
- break;
- case ORDERED:
- fprintf (file, "lge");
- break;
- case UNORDERED:
- fprintf (file, "uo");
- break;
- case LTGT:
- fprintf (file, "lg");
- break;
- case UNEQ:
- fprintf (file, "ue");
- break;
- case UNGE:
- fprintf (file, "uge");
- break;
- case UNGT:
- fprintf (file, "ug");
- break;
- case UNLE:
- fprintf (file, "ule");
- break;
- case UNLT:
- fprintf (file, "ul");
- break;
- default:
- abort ();
- }
- break;
- }
- /* These are normal and reversed branches. */
- switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
+ case 'W':
+ {
+ unsigned int liw_op = UINTVAL (x);
+
+ gcc_assert (TARGET_ALLOW_LIW);
+ gcc_assert (liw_op < LIW_OP_MAX);
+ fputs (liw_op_names[liw_op], file);
+ break;
+ }
+
+ case 'b':
+ case 'B':
+ {
+ enum rtx_code cmp = GET_CODE (x);
+ enum machine_mode mode = GET_MODE (XEXP (x, 0));
+ const char *str;
+ int have_flags;
+
+ if (code == 'B')
+ cmp = reverse_condition (cmp);
+ have_flags = cc_flags_for_mode (mode);
+
+ switch (cmp)
{
case NE:
- fprintf (file, "ne");
+ str = "ne";
break;
case EQ:
- fprintf (file, "eq");
+ str = "eq";
break;
case GE:
- fprintf (file, "ge");
+ /* bge is smaller than bnc. */
+ str = (have_flags & CC_FLAG_V ? "ge" : "nc");
+ break;
+ case LT:
+ str = (have_flags & CC_FLAG_V ? "lt" : "ns");
break;
case GT:
- fprintf (file, "gt");
+ str = "gt";
break;
case LE:
- fprintf (file, "le");
- break;
- case LT:
- fprintf (file, "lt");
+ str = "le";
break;
case GEU:
- fprintf (file, "cc");
+ str = "cc";
break;
case GTU:
- fprintf (file, "hi");
+ str = "hi";
break;
case LEU:
- fprintf (file, "ls");
+ str = "ls";
break;
case LTU:
- fprintf (file, "cs");
+ str = "cs";
break;
- default:
- abort ();
- }
- break;
- case 'C':
- /* This is used for the operand to a call instruction;
- if it's a REG, enclose it in parens, else output
- the operand normally. */
- if (GET_CODE (x) == REG)
- {
- fputc ('(', file);
- print_operand (file, x, 0);
- fputc (')', file);
- }
- else
- print_operand (file, x, 0);
- break;
-
- case 'D':
- switch (GET_CODE (x))
- {
- case MEM:
- fputc ('(', file);
- output_address (XEXP (x, 0));
- fputc (')', file);
+ case ORDERED:
+ str = "lge";
break;
-
- case REG:
- fprintf (file, "fd%d", REGNO (x) - 18);
+ case UNORDERED:
+ str = "uo";
+ break;
+ case LTGT:
+ str = "lg";
+ break;
+ case UNEQ:
+ str = "ue";
+ break;
+ case UNGE:
+ str = "uge";
+ break;
+ case UNGT:
+ str = "ug";
+ break;
+ case UNLE:
+ str = "ule";
+ break;
+ case UNLT:
+ str = "ul";
break;
-
default:
- abort ();
+ gcc_unreachable ();
}
- break;
+
+ gcc_checking_assert ((cc_flags_for_code (cmp) & ~have_flags) == 0);
+ fputs (str, file);
+ }
+ break;
+
+ case 'C':
+ /* This is used for the operand to a call instruction;
+ if it's a REG, enclose it in parens, else output
+ the operand normally. */
+ if (REG_P (x))
+ {
+ fputc ('(', file);
+ mn10300_print_operand (file, x, 0);
+ fputc (')', file);
+ }
+ else
+ mn10300_print_operand (file, x, 0);
+ break;
+
+ case 'D':
+ switch (GET_CODE (x))
+ {
+ case MEM:
+ fputc ('(', file);
+ output_address (XEXP (x, 0));
+ fputc (')', file);
+ break;
+
+ case REG:
+ fprintf (file, "fd%d", REGNO (x) - 18);
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+ break;
/* These are the least significant word in a 64bit value. */
- case 'L':
- switch (GET_CODE (x))
- {
- case MEM:
- fputc ('(', file);
- output_address (XEXP (x, 0));
- fputc (')', file);
- break;
+ case 'L':
+ switch (GET_CODE (x))
+ {
+ case MEM:
+ fputc ('(', file);
+ output_address (XEXP (x, 0));
+ fputc (')', file);
+ break;
- case REG:
- fprintf (file, "%s", reg_names[REGNO (x)]);
- break;
+ case REG:
+ fprintf (file, "%s", reg_names[REGNO (x)]);
+ break;
- case SUBREG:
- fprintf (file, "%s", reg_names[subreg_regno (x)]);
- break;
+ case SUBREG:
+ fprintf (file, "%s", reg_names[subreg_regno (x)]);
+ break;
- case CONST_DOUBLE:
- {
- long val[2];
- REAL_VALUE_TYPE rv;
+ case CONST_DOUBLE:
+ {
+ long val[2];
+ REAL_VALUE_TYPE rv;
- switch (GET_MODE (x))
- {
- case DFmode:
- REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
- REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
- fprintf (file, "0x%lx", val[0]);
- break;;
- case SFmode:
- REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
- REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
- fprintf (file, "0x%lx", val[0]);
- break;;
- case VOIDmode:
- case DImode:
- print_operand_address (file,
- GEN_INT (CONST_DOUBLE_LOW (x)));
- break;
- default:
- break;
- }
+ switch (GET_MODE (x))
+ {
+ case DFmode:
+ REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
+ REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
+ fprintf (file, "0x%lx", val[0]);
+ break;;
+ case SFmode:
+ REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
+ REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
+ fprintf (file, "0x%lx", val[0]);
+ break;;
+ case VOIDmode:
+ case DImode:
+ mn10300_print_operand_address (file,
+ GEN_INT (CONST_DOUBLE_LOW (x)));
+ break;
+ default:
break;
}
+ break;
+ }
- case CONST_INT:
- {
- rtx low, high;
- split_double (x, &low, &high);
- fprintf (file, "%ld", (long)INTVAL (low));
- break;
+ case CONST_INT:
+ {
+ rtx low, high;
+ split_double (x, &low, &high);
+ fprintf (file, "%ld", (long)INTVAL (low));
+ break;
}
- default:
- abort ();
- }
- break;
+ default:
+ gcc_unreachable ();
+ }
+ break;
/* Similarly, but for the most significant word. */
- case 'H':
- switch (GET_CODE (x))
- {
- case MEM:
- fputc ('(', file);
- x = adjust_address (x, SImode, 4);
- output_address (XEXP (x, 0));
- fputc (')', file);
- break;
+ case 'H':
+ switch (GET_CODE (x))
+ {
+ case MEM:
+ fputc ('(', file);
+ x = adjust_address (x, SImode, 4);
+ output_address (XEXP (x, 0));
+ fputc (')', file);
+ break;
- case REG:
- fprintf (file, "%s", reg_names[REGNO (x) + 1]);
- break;
+ case REG:
+ fprintf (file, "%s", reg_names[REGNO (x) + 1]);
+ break;
- case SUBREG:
- fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
- break;
+ case SUBREG:
+ fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
+ break;
- case CONST_DOUBLE:
- {
- long val[2];
- REAL_VALUE_TYPE rv;
+ case CONST_DOUBLE:
+ {
+ long val[2];
+ REAL_VALUE_TYPE rv;
- switch (GET_MODE (x))
- {
- case DFmode:
- REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
- REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
- fprintf (file, "0x%lx", val[1]);
- break;;
- case SFmode:
- abort ();
- case VOIDmode:
- case DImode:
- print_operand_address (file,
- GEN_INT (CONST_DOUBLE_HIGH (x)));
- break;
- default:
- break;
- }
+ switch (GET_MODE (x))
+ {
+ case DFmode:
+ REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
+ REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
+ fprintf (file, "0x%lx", val[1]);
+ break;;
+ case SFmode:
+ gcc_unreachable ();
+ case VOIDmode:
+ case DImode:
+ mn10300_print_operand_address (file,
+ GEN_INT (CONST_DOUBLE_HIGH (x)));
+ break;
+ default:
break;
}
+ break;
+ }
- case CONST_INT:
- {
- rtx low, high;
- split_double (x, &low, &high);
- fprintf (file, "%ld", (long)INTVAL (high));
- break;
- }
-
- default:
- abort ();
+ case CONST_INT:
+ {
+ rtx low, high;
+ split_double (x, &low, &high);
+ fprintf (file, "%ld", (long)INTVAL (high));
+ break;
}
- break;
- case 'A':
- fputc ('(', file);
- if (GET_CODE (XEXP (x, 0)) == REG)
- output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), GEN_INT (0)));
- else
- output_address (XEXP (x, 0));
- fputc (')', file);
- break;
+ default:
+ gcc_unreachable ();
+ }
+ break;
- case 'N':
- if (INTVAL (x) < -128 || INTVAL (x) > 255)
- abort ();
- fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff));
- break;
+ case 'A':
+ fputc ('(', file);
+ if (REG_P (XEXP (x, 0)))
+ output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx));
+ else
+ output_address (XEXP (x, 0));
+ fputc (')', file);
+ break;
- case 'U':
- if (INTVAL (x) < -128 || INTVAL (x) > 255)
- abort ();
- fprintf (file, "%d", (int)(INTVAL (x) & 0xff));
- break;
+ case 'N':
+ gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
+ fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff));
+ break;
+
+ case 'U':
+ gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
+ fprintf (file, "%d", (int)(INTVAL (x) & 0xff));
+ break;
/* For shift counts. The hardware ignores the upper bits of
any immediate, but the assembler will flag an out of range
shift count as an error. So we mask off the high bits
of the immediate here. */
- case 'S':
- if (GET_CODE (x) == CONST_INT)
- {
- fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
- break;
- }
- /* FALL THROUGH */
+ case 'S':
+ if (CONST_INT_P (x))
+ {
+ fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
+ break;
+ }
+ /* FALL THROUGH */
- default:
- switch (GET_CODE (x))
- {
- case MEM:
- fputc ('(', file);
- output_address (XEXP (x, 0));
- fputc (')', file);
- break;
+ default:
+ switch (GET_CODE (x))
+ {
+ case MEM:
+ fputc ('(', file);
+ output_address (XEXP (x, 0));
+ fputc (')', file);
+ break;
- case PLUS:
- output_address (x);
- break;
+ case PLUS:
+ output_address (x);
+ break;
- case REG:
- fprintf (file, "%s", reg_names[REGNO (x)]);
- break;
+ case REG:
+ fprintf (file, "%s", reg_names[REGNO (x)]);
+ break;
- case SUBREG:
- fprintf (file, "%s", reg_names[subreg_regno (x)]);
- break;
+ case SUBREG:
+ fprintf (file, "%s", reg_names[subreg_regno (x)]);
+ break;
/* This will only be single precision.... */
- case CONST_DOUBLE:
- {
- unsigned long val;
- REAL_VALUE_TYPE rv;
-
- REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
- REAL_VALUE_TO_TARGET_SINGLE (rv, val);
- fprintf (file, "0x%lx", val);
- break;
- }
+ case CONST_DOUBLE:
+ {
+ unsigned long val;
+ REAL_VALUE_TYPE rv;
- case CONST_INT:
- case SYMBOL_REF:
- case CONST:
- case LABEL_REF:
- case CODE_LABEL:
- case UNSPEC:
- print_operand_address (file, x);
+ REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
+ REAL_VALUE_TO_TARGET_SINGLE (rv, val);
+ fprintf (file, "0x%lx", val);
break;
- default:
- abort ();
}
- break;
- }
+
+ case CONST_INT:
+ case SYMBOL_REF:
+ case CONST:
+ case LABEL_REF:
+ case CODE_LABEL:
+ case UNSPEC:
+ mn10300_print_operand_address (file, x);
+ break;
+ default:
+ gcc_unreachable ();
+ }
+ break;
+ }
}
/* Output assembly language output for the address ADDR to FILE. */
void
-print_operand_address (FILE *file, rtx addr)
+mn10300_print_operand_address (FILE *file, rtx addr)
{
switch (GET_CODE (addr))
{
case POST_INC:
- print_operand_address (file, XEXP (addr, 0));
+ mn10300_print_operand (file, XEXP (addr, 0), 0);
+ fputc ('+', file);
+ break;
+
+ case POST_MODIFY:
+ mn10300_print_operand (file, XEXP (addr, 0), 0);
fputc ('+', file);
+ fputc (',', file);
+ mn10300_print_operand (file, XEXP (addr, 1), 0);
break;
+
case REG:
- print_operand (file, addr, 0);
+ mn10300_print_operand (file, addr, 0);
break;
case PLUS:
{
- rtx base, index;
- if (REG_P (XEXP (addr, 0))
- && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
- base = XEXP (addr, 0), index = XEXP (addr, 1);
- else if (REG_P (XEXP (addr, 1))
- && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
- base = XEXP (addr, 1), index = XEXP (addr, 0);
- else
- abort ();
- print_operand (file, index, 0);
+ rtx base = XEXP (addr, 0);
+ rtx index = XEXP (addr, 1);
+
+ if (REG_P (index) && !REG_OK_FOR_INDEX_P (index))
+ {
+ rtx x = base;
+ base = index;
+ index = x;
+
+ gcc_assert (REG_P (index) && REG_OK_FOR_INDEX_P (index));
+ }
+ gcc_assert (REG_OK_FOR_BASE_P (base));
+
+ mn10300_print_operand (file, index, 0);
fputc (',', file);
- print_operand (file, base, 0);;
+ mn10300_print_operand (file, base, 0);
break;
}
case SYMBOL_REF:
}
}
+/* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA.
+
+ Used for PIC-specific UNSPECs. */
+
+static bool
+mn10300_asm_output_addr_const_extra (FILE *file, rtx x)
+{
+ if (GET_CODE (x) == UNSPEC)
+ {
+ switch (XINT (x, 1))
+ {
+ case UNSPEC_PIC:
+ /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
+ output_addr_const (file, XVECEXP (x, 0, 0));
+ break;
+ case UNSPEC_GOT:
+ output_addr_const (file, XVECEXP (x, 0, 0));
+ fputs ("@GOT", file);
+ break;
+ case UNSPEC_GOTOFF:
+ output_addr_const (file, XVECEXP (x, 0, 0));
+ fputs ("@GOTOFF", file);
+ break;
+ case UNSPEC_PLT:
+ output_addr_const (file, XVECEXP (x, 0, 0));
+ fputs ("@PLT", file);
+ break;
+ case UNSPEC_GOTSYM_OFF:
+ assemble_name (file, GOT_SYMBOL_NAME);
+ fputs ("-(", file);
+ output_addr_const (file, XVECEXP (x, 0, 0));
+ fputs ("-.)", file);
+ break;
+ default:
+ return false;
+ }
+ return true;
+ }
+ else
+ return false;
+}
+
/* Count the number of FP registers that have to be saved. */
static int
fp_regs_to_save (void)
return 0;
for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
- if (regs_ever_live[i] && ! call_used_regs[i])
+ if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
++n;
return n;
/* Print a set of registers in the format required by "movm" and "ret".
Register K is saved if bit K of MASK is set. The data and address
registers can be stored individually, but the extended registers cannot.
- We assume that the mask alread takes that into account. For instance,
- bits 14 to 17 must have the same value. */
+ We assume that the mask already takes that into account. For instance,
+ bits 14 to 17 must have the same value. */
void
mn10300_print_reg_list (FILE *file, int mask)
if ((mask & 0x3c000) != 0)
{
- if ((mask & 0x3c000) != 0x3c000)
- abort();
+ gcc_assert ((mask & 0x3c000) == 0x3c000);
if (need_comma)
fputc (',', file);
fputs ("exreg1", file);
fputc (']', file);
}
-int
-can_use_return_insn (void)
+/* If the MDR register is never clobbered, we can use the RETF instruction
+ which takes the address from the MDR register. This is 3 cycles faster
+ than having to load the address from the stack. */
+
+bool
+mn10300_can_use_retf_insn (void)
{
- /* size includes the fixed stack space needed for function calls. */
- int size = get_frame_size () + current_function_outgoing_args_size;
+ /* Don't bother if we're not optimizing. In this case we won't
+ have proper access to df_regs_ever_live_p. */
+ if (!optimize)
+ return false;
- /* And space for the return pointer. */
- size += current_function_outgoing_args_size ? 4 : 0;
-
- return (reload_completed
- && size == 0
- && !regs_ever_live[2]
- && !regs_ever_live[3]
- && !regs_ever_live[6]
- && !regs_ever_live[7]
- && !regs_ever_live[14]
- && !regs_ever_live[15]
- && !regs_ever_live[16]
- && !regs_ever_live[17]
- && fp_regs_to_save () == 0
- && !frame_pointer_needed);
+ /* EH returns alter the saved return address; MDR is not current. */
+ if (crtl->calls_eh_return)
+ return false;
+
+ /* Obviously not if MDR is ever clobbered. */
+ if (df_regs_ever_live_p (MDR_REG))
+ return false;
+
+ /* ??? Careful not to use this during expand_epilogue etc. */
+ gcc_assert (!in_sequence_p ());
+ return leaf_function_p ();
+}
+
+bool
+mn10300_can_use_rets_insn (void)
+{
+ return !mn10300_initial_offset (ARG_POINTER_REGNUM, STACK_POINTER_REGNUM);
}
/* Returns the set of live, callee-saved registers as a bitmask. The
callee-saved extended registers cannot be stored individually, so
- all of them will be included in the mask if any one of them is used. */
+ all of them will be included in the mask if any one of them is used. */
int
mn10300_get_live_callee_saved_regs (void)
mask = 0;
for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
- if (regs_ever_live[i] && ! call_used_regs[i])
+ if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
mask |= (1 << i);
if ((mask & 0x3c000) != 0)
mask |= 0x3c000;
return mask;
}
+static rtx
+F (rtx r)
+{
+ RTX_FRAME_RELATED_P (r) = 1;
+ return r;
+}
+
/* Generate an instruction that pushes several registers onto the stack.
Register K will be saved if bit K in MASK is set. The function does
nothing if MASK is zero.
(const_int -N*4)))
(reg:SI R1))) */
-void
-mn10300_gen_multiple_store (int mask)
+static void
+mn10300_gen_multiple_store (unsigned int mask)
{
- if (mask != 0)
+ /* The order in which registers are stored, from SP-4 through SP-N*4. */
+ static const unsigned int store_order[8] = {
+ /* e2, e3: never saved */
+ FIRST_EXTENDED_REGNUM + 4,
+ FIRST_EXTENDED_REGNUM + 5,
+ FIRST_EXTENDED_REGNUM + 6,
+ FIRST_EXTENDED_REGNUM + 7,
+ /* e0, e1, mdrq, mcrh, mcrl, mcvf: never saved. */
+ FIRST_DATA_REGNUM + 2,
+ FIRST_DATA_REGNUM + 3,
+ FIRST_ADDRESS_REGNUM + 2,
+ FIRST_ADDRESS_REGNUM + 3,
+ /* d0, d1, a0, a1, mdr, lir, lar: never saved. */
+ };
+
+ rtx x, elts[9];
+ unsigned int i;
+ int count;
+
+ if (mask == 0)
+ return;
+
+ for (i = count = 0; i < ARRAY_SIZE(store_order); ++i)
{
- int i;
- int count;
- rtx par;
- int pari;
-
- /* Count how many registers need to be saved. */
- count = 0;
- for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
- if ((mask & (1 << i)) != 0)
- count += 1;
-
- /* We need one PARALLEL element to update the stack pointer and
- an additional element for each register that is stored. */
- par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
-
- /* Create the instruction that updates the stack pointer. */
- XVECEXP (par, 0, 0)
- = gen_rtx_SET (SImode,
- stack_pointer_rtx,
- gen_rtx_PLUS (SImode,
- stack_pointer_rtx,
- GEN_INT (-count * 4)));
+ unsigned regno = store_order[i];
- /* Create each store. */
- pari = 1;
- for (i = LAST_EXTENDED_REGNUM; i >= 0; i--)
- if ((mask & (1 << i)) != 0)
- {
- rtx address = gen_rtx_PLUS (SImode,
- stack_pointer_rtx,
- GEN_INT (-pari * 4));
- XVECEXP(par, 0, pari)
- = gen_rtx_SET (VOIDmode,
- gen_rtx_MEM (SImode, address),
- gen_rtx_REG (SImode, i));
- pari += 1;
- }
+ if (((mask >> regno) & 1) == 0)
+ continue;
+
+ ++count;
+ x = plus_constant (stack_pointer_rtx, count * -4);
+ x = gen_frame_mem (SImode, x);
+ x = gen_rtx_SET (VOIDmode, x, gen_rtx_REG (SImode, regno));
+ elts[count] = F(x);
- par = emit_insn (par);
- RTX_FRAME_RELATED_P (par) = 1;
+ /* Remove the register from the mask so that... */
+ mask &= ~(1u << regno);
}
+
+ /* ... we can make sure that we didn't try to use a register
+ not listed in the store order. */
+ gcc_assert (mask == 0);
+
+ /* Create the instruction that updates the stack pointer. */
+ x = plus_constant (stack_pointer_rtx, count * -4);
+ x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
+ elts[0] = F(x);
+
+ /* We need one PARALLEL element to update the stack pointer and
+ an additional element for each register that is stored. */
+ x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (count + 1, elts));
+ F (emit_insn (x));
}
void
-expand_prologue (void)
+mn10300_expand_prologue (void)
{
- HOST_WIDE_INT size;
-
- /* SIZE includes the fixed stack space needed for function calls. */
- size = get_frame_size () + current_function_outgoing_args_size;
- size += (current_function_outgoing_args_size ? 4 : 0);
+ HOST_WIDE_INT size = mn10300_frame_size ();
- /* If we use any of the callee-saved registers, save them now. */
+ /* If we use any of the callee-saved registers, save them now. */
mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
if (TARGET_AM33_2 && fp_regs_to_save ())
{
int num_regs_to_save = fp_regs_to_save (), i;
HOST_WIDE_INT xsize;
- enum { save_sp_merge,
- save_sp_no_merge,
- save_sp_partial_merge,
- save_a0_merge,
- save_a0_no_merge } strategy;
+ enum
+ {
+ save_sp_merge,
+ save_sp_no_merge,
+ save_sp_partial_merge,
+ save_a0_merge,
+ save_a0_no_merge
+ } strategy;
unsigned int strategy_size = (unsigned)-1, this_strategy_size;
rtx reg;
- rtx insn;
/* We have several different strategies to save FP registers.
We can store them using SP offsets, which is beneficial if
: (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
#define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
: (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
+
+/* We add 0 * (S) in two places to promote to the type of S,
+ so that all arms of the conditional have the same type. */
#define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
- (((S) >= (L)) ? (SIZE1) * (N) \
+ (((S) >= (L)) ? 0 * (S) + (SIZE1) * (N) \
: ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
+ ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
- : (ELSE))
+ : 0 * (S) + (ELSE))
#define SIZE_FMOV_SP_(S,N) \
(SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
frame pointer, size is nonzero and the user hasn't
changed the calling conventions of a0. */
if (! frame_pointer_needed && size
- && call_used_regs[FIRST_ADDRESS_REGNUM]
+ && call_really_used_regs [FIRST_ADDRESS_REGNUM]
&& ! fixed_regs[FIRST_ADDRESS_REGNUM])
{
/* Insn: add -(size + 4 * num_regs_to_save), sp. */
}
/* Consider alternative save_a0_no_merge if the user hasn't
- changed the calling conventions of a0. */
- if (call_used_regs[FIRST_ADDRESS_REGNUM]
+ changed the calling conventions of a0. */
+ if (call_really_used_regs [FIRST_ADDRESS_REGNUM]
&& ! fixed_regs[FIRST_ADDRESS_REGNUM])
{
/* Insn: add -4 * num_regs_to_save, sp. */
{
case save_sp_no_merge:
case save_a0_no_merge:
- emit_insn (gen_addsi3 (stack_pointer_rtx,
- stack_pointer_rtx,
- GEN_INT (-4 * num_regs_to_save)));
+ F (emit_insn (gen_addsi3 (stack_pointer_rtx,
+ stack_pointer_rtx,
+ GEN_INT (-4 * num_regs_to_save))));
xsize = 0;
break;
case save_sp_partial_merge:
- emit_insn (gen_addsi3 (stack_pointer_rtx,
- stack_pointer_rtx,
- GEN_INT (-128)));
+ F (emit_insn (gen_addsi3 (stack_pointer_rtx,
+ stack_pointer_rtx,
+ GEN_INT (-128))));
xsize = 128 - 4 * num_regs_to_save;
size -= xsize;
break;
case save_sp_merge:
case save_a0_merge:
- emit_insn (gen_addsi3 (stack_pointer_rtx,
- stack_pointer_rtx,
- GEN_INT (-(size + 4 * num_regs_to_save))));
+ F (emit_insn (gen_addsi3 (stack_pointer_rtx,
+ stack_pointer_rtx,
+ GEN_INT (-(size + 4 * num_regs_to_save)))));
/* We'll have to adjust FP register saves according to the
- frame size. */
+ frame size. */
xsize = size;
/* Since we've already created the stack frame, don't do it
- again at the end of the function. */
+ again at the end of the function. */
size = 0;
break;
default:
- abort ();
+ gcc_unreachable ();
}
-
+
/* Now prepare register a0, if we have decided to use it. */
switch (strategy)
{
case save_a0_merge:
case save_a0_no_merge:
reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM);
- emit_insn (gen_movsi (reg, stack_pointer_rtx));
+ F (emit_insn (gen_movsi (reg, stack_pointer_rtx)));
if (xsize)
- emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)));
+ F (emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize))));
reg = gen_rtx_POST_INC (SImode, reg);
break;
-
+
default:
- abort ();
+ gcc_unreachable ();
}
-
+
/* Now actually save the FP registers. */
for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
- if (regs_ever_live[i] && ! call_used_regs[i])
+ if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
{
rtx addr;
}
else
addr = stack_pointer_rtx;
-
+
xsize += 4;
}
- insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr),
- gen_rtx_REG (SImode, i)));
-
- RTX_FRAME_RELATED_P (insn) = 1;
+ F (emit_insn (gen_movsf (gen_rtx_MEM (SFmode, addr),
+ gen_rtx_REG (SFmode, i))));
}
}
/* Now put the frame pointer into the frame pointer register. */
if (frame_pointer_needed)
- emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
+ F (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx));
/* Allocate stack for this frame. */
if (size)
- emit_insn (gen_addsi3 (stack_pointer_rtx,
- stack_pointer_rtx,
- GEN_INT (-size)));
- if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
- {
- rtx insn = get_last_insn ();
- rtx last = emit_insn (gen_GOTaddr2picreg ());
-
- /* Mark these insns as possibly dead. Sometimes, flow2 may
- delete all uses of the PIC register. In this case, let it
- delete the initialization too. */
- do
- {
- insn = NEXT_INSN (insn);
+ F (emit_insn (gen_addsi3 (stack_pointer_rtx,
+ stack_pointer_rtx,
+ GEN_INT (-size))));
- REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
- const0_rtx,
- REG_NOTES (insn));
- }
- while (insn != last);
- }
+ if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
+ emit_insn (gen_load_pic ());
}
void
-expand_epilogue (void)
+mn10300_expand_epilogue (void)
{
- HOST_WIDE_INT size;
-
- /* SIZE includes the fixed stack space needed for function calls. */
- size = get_frame_size () + current_function_outgoing_args_size;
- size += (current_function_outgoing_args_size ? 4 : 0);
-
+ HOST_WIDE_INT size = mn10300_frame_size ();
+ int reg_save_bytes = REG_SAVE_BYTES;
+
if (TARGET_AM33_2 && fp_regs_to_save ())
{
int num_regs_to_save = fp_regs_to_save (), i;
this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save);
/* If size is too large, we'll have to adjust SP with an
add. */
- if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
+ if (size + 4 * num_regs_to_save + reg_save_bytes > 255)
{
/* Insn: add size + 4 * num_regs_to_save, sp. */
this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save);
}
/* If we don't have to restore any non-FP registers,
we'll be able to save one byte by using rets. */
- if (! REG_SAVE_BYTES)
+ if (! reg_save_bytes)
this_strategy_size--;
if (this_strategy_size < strategy_size)
/* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
/* We're going to use ret to release the FP registers
- save area, so, no savings. */
+ save area, so, no savings. */
if (this_strategy_size < strategy_size)
{
When size is close to 32Kb, we may be able to adjust SP
with an imm16 add instruction while still using fmov
(d8,sp). */
- if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
+ if (size + 4 * num_regs_to_save + reg_save_bytes > 255)
{
/* Insn: add size + 4 * num_regs_to_save
- + REG_SAVE_BYTES - 252,sp. */
+ + reg_save_bytes - 252,sp. */
this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save
- + REG_SAVE_BYTES - 252);
+ + reg_save_bytes - 252);
/* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */
- this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES
+ this_strategy_size += SIZE_FMOV_SP (252 - reg_save_bytes
- 4 * num_regs_to_save,
num_regs_to_save);
/* We're going to use ret to release the FP registers
- save area, so, no savings. */
+ save area, so, no savings. */
if (this_strategy_size < strategy_size)
{
/* Consider using a1 in post-increment mode, as long as the
user hasn't changed the calling conventions of a1. */
- if (call_used_regs[FIRST_ADDRESS_REGNUM+1]
+ if (call_really_used_regs [FIRST_ADDRESS_REGNUM + 1]
&& ! fixed_regs[FIRST_ADDRESS_REGNUM+1])
{
/* Insn: mov sp,a1. */
this_strategy_size += 3 * num_regs_to_save;
/* If size is large enough, we may be able to save a
couple of bytes. */
- if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
+ if (size + 4 * num_regs_to_save + reg_save_bytes > 255)
{
/* Insn: mov a1,sp. */
this_strategy_size += 2;
}
/* If we don't have to restore any non-FP registers,
we'll be able to save one byte by using rets. */
- if (! REG_SAVE_BYTES)
+ if (! reg_save_bytes)
this_strategy_size--;
if (this_strategy_size < strategy_size)
emit_insn (gen_addsi3 (stack_pointer_rtx,
stack_pointer_rtx,
GEN_INT (size + 4 * num_regs_to_save
- + REG_SAVE_BYTES - 252)));
- size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save;
+ + reg_save_bytes - 252)));
+ size = 252 - reg_save_bytes - 4 * num_regs_to_save;
break;
-
+
case restore_a1:
reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1);
emit_insn (gen_movsi (reg, stack_pointer_rtx));
break;
default:
- abort ();
+ gcc_unreachable ();
}
}
reg = gen_rtx_POST_INC (SImode, reg);
for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
- if (regs_ever_live[i] && ! call_used_regs[i])
+ if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
{
rtx addr;
-
+
if (reg)
addr = reg;
else if (size)
{
/* If we aren't using a post-increment register, use an
- SP offset. */
+ SP offset. */
addr = gen_rtx_PLUS (SImode,
stack_pointer_rtx,
GEN_INT (size));
size += 4;
- emit_insn (gen_movsi (gen_rtx_REG (SImode, i),
- gen_rtx_MEM (SImode, addr)));
+ emit_insn (gen_movsf (gen_rtx_REG (SFmode, i),
+ gen_rtx_MEM (SFmode, addr)));
}
/* If we were using the restore_a1 strategy and the number of
bytes to be released won't fit in the `ret' byte, copy `a1'
to `sp', to avoid having to use `add' to adjust it. */
- if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255)
+ if (! frame_pointer_needed && reg && size + reg_save_bytes > 255)
{
emit_move_insn (stack_pointer_rtx, XEXP (reg, 0));
size = 0;
If the stack size + register save area is more than 255 bytes,
then the stack must be cut back here since the size + register
- save size is too big for a ret/retf instruction.
+ save size is too big for a ret/retf instruction.
Else leave it alone, it will be cut back as part of the
ret/retf instruction, or there wasn't any stack to begin with.
emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
size = 0;
}
- else if (size + REG_SAVE_BYTES > 255)
+ else if (size + reg_save_bytes > 255)
{
emit_insn (gen_addsi3 (stack_pointer_rtx,
stack_pointer_rtx,
}
/* Adjust the stack and restore callee-saved registers, if any. */
- if (size || regs_ever_live[2] || regs_ever_live[3]
- || regs_ever_live[6] || regs_ever_live[7]
- || regs_ever_live[14] || regs_ever_live[15]
- || regs_ever_live[16] || regs_ever_live[17]
- || frame_pointer_needed)
- emit_jump_insn (gen_return_internal_regs
- (GEN_INT (size + REG_SAVE_BYTES)));
+ if (mn10300_can_use_rets_insn ())
+ emit_jump_insn (ret_rtx);
else
- emit_jump_insn (gen_return_internal ());
-}
-
-/* Update the condition code from the insn. */
-
-void
-notice_update_cc (rtx body, rtx insn)
-{
- switch (get_attr_cc (insn))
- {
- case CC_NONE:
- /* Insn does not affect CC at all. */
- break;
-
- case CC_NONE_0HIT:
- /* Insn does not change CC, but the 0'th operand has been changed. */
- if (cc_status.value1 != 0
- && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
- cc_status.value1 = 0;
- break;
-
- case CC_SET_ZN:
- /* Insn sets the Z,N flags of CC to recog_data.operand[0].
- V,C are unusable. */
- CC_STATUS_INIT;
- cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
- cc_status.value1 = recog_data.operand[0];
- break;
-
- case CC_SET_ZNV:
- /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
- C is unusable. */
- CC_STATUS_INIT;
- cc_status.flags |= CC_NO_CARRY;
- cc_status.value1 = recog_data.operand[0];
- break;
-
- case CC_COMPARE:
- /* The insn is a compare instruction. */
- CC_STATUS_INIT;
- cc_status.value1 = SET_SRC (body);
- if (GET_CODE (cc_status.value1) == COMPARE
- && GET_MODE (XEXP (cc_status.value1, 0)) == SFmode)
- cc_status.mdep.fpCC = 1;
- break;
-
- case CC_INVERT:
- /* The insn is a compare instruction. */
- CC_STATUS_INIT;
- cc_status.value1 = SET_SRC (body);
- cc_status.flags |= CC_INVERTED;
- break;
-
- case CC_CLOBBER:
- /* Insn doesn't leave CC in a usable state. */
- CC_STATUS_INIT;
- break;
-
- default:
- abort ();
- }
+ emit_jump_insn (gen_return_ret (GEN_INT (size + REG_SAVE_BYTES)));
}
/* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
registers it saves. Return 0 otherwise. */
int
-store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+mn10300_store_multiple_operation (rtx op,
+ enum machine_mode mode ATTRIBUTE_UNUSED)
{
int count;
int mask;
/* Check that first instruction has the form (set (sp) (plus A B)) */
elt = XVECEXP (op, 0, 0);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_DEST (elt)) != REG
+ || (! REG_P (SET_DEST (elt)))
|| REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
|| GET_CODE (SET_SRC (elt)) != PLUS)
return 0;
/* Check that A is the stack pointer and B is the expected stack size.
For OP to match, each subsequent instruction should push a word onto
the stack. We therefore expect the first instruction to create
- COUNT-1 stack slots. */
+ COUNT-1 stack slots. */
elt = SET_SRC (elt);
- if (GET_CODE (XEXP (elt, 0)) != REG
+ if ((! REG_P (XEXP (elt, 0)))
|| REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
- || GET_CODE (XEXP (elt, 1)) != CONST_INT
+ || (! CONST_INT_P (XEXP (elt, 1)))
|| INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
return 0;
- /* Now go through the rest of the vector elements. They must be
- ordered so that the first instruction stores the highest-numbered
- register to the highest stack slot and that subsequent instructions
- store a lower-numbered register to the slot below.
-
- LAST keeps track of the smallest-numbered register stored so far.
- MASK is the set of stored registers. */
- last = LAST_EXTENDED_REGNUM + 1;
mask = 0;
for (i = 1; i < count; i++)
{
- /* Check that element i is a (set (mem M) R) and that R is valid. */
+ /* Check that element i is a (set (mem M) R). */
+ /* ??? Validate the register order a-la mn10300_gen_multiple_store.
+ Remember: the ordering is *not* monotonic. */
elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_DEST (elt)) != MEM
- || GET_CODE (SET_SRC (elt)) != REG
- || REGNO (SET_SRC (elt)) >= last)
+ || (! MEM_P (SET_DEST (elt)))
+ || (! REG_P (SET_SRC (elt))))
return 0;
- /* R was OK, so provisionally add it to MASK. We return 0 in any
- case if the rest of the instruction has a flaw. */
+ /* Remember which registers are to be saved. */
last = REGNO (SET_SRC (elt));
mask |= (1 << last);
/* Check that M has the form (plus (sp) (const_int -I*4)) */
elt = XEXP (SET_DEST (elt), 0);
if (GET_CODE (elt) != PLUS
- || GET_CODE (XEXP (elt, 0)) != REG
+ || (! REG_P (XEXP (elt, 0)))
|| REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
- || GET_CODE (XEXP (elt, 1)) != CONST_INT
+ || (! CONST_INT_P (XEXP (elt, 1)))
|| INTVAL (XEXP (elt, 1)) != -i * 4)
return 0;
}
- /* All or none of the callee-saved extended registers must be in the set. */
+ /* All or none of the callee-saved extended registers must be in the set. */
if ((mask & 0x3c000) != 0
&& (mask & 0x3c000) != 0x3c000)
return 0;
return mask;
}
-/* Return true if OP is a valid call operand. */
+/* Implement TARGET_PREFERRED_RELOAD_CLASS. */
-int
-call_address_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+static reg_class_t
+mn10300_preferred_reload_class (rtx x, reg_class_t rclass)
{
- if (flag_pic)
- return (EXTRA_CONSTRAINT (op, 'S') || GET_CODE (op) == REG);
-
- return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
-}
-
-/* What (if any) secondary registers are needed to move IN with mode
- MODE into a register in register class CLASS.
-
- We might be able to simplify this. */
-enum reg_class
-secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
-{
- /* Memory loads less than a full word wide can't have an
- address or stack pointer destination. They must use
- a data register as an intermediate register. */
- if ((GET_CODE (in) == MEM
- || (GET_CODE (in) == REG
- && REGNO (in) >= FIRST_PSEUDO_REGISTER)
- || (GET_CODE (in) == SUBREG
- && GET_CODE (SUBREG_REG (in)) == REG
- && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER))
- && (mode == QImode || mode == HImode)
- && (class == ADDRESS_REGS || class == SP_REGS
- || class == SP_OR_ADDRESS_REGS))
+ if (x == stack_pointer_rtx && rclass != SP_REGS)
+ return (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
+ else if (MEM_P (x)
+ || (REG_P (x)
+ && !HARD_REGISTER_P (x))
+ || (GET_CODE (x) == SUBREG
+ && REG_P (SUBREG_REG (x))
+ && !HARD_REGISTER_P (SUBREG_REG (x))))
+ return LIMIT_RELOAD_CLASS (GET_MODE (x), rclass);
+ else
+ return rclass;
+}
+
+/* Implement TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */
+
+static reg_class_t
+mn10300_preferred_output_reload_class (rtx x, reg_class_t rclass)
+{
+ if (x == stack_pointer_rtx && rclass != SP_REGS)
+ return (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
+ return rclass;
+}
+
+/* Implement TARGET_SECONDARY_RELOAD. */
+
+static reg_class_t
+mn10300_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
+ enum machine_mode mode, secondary_reload_info *sri)
+{
+ enum reg_class rclass = (enum reg_class) rclass_i;
+ enum reg_class xclass = NO_REGS;
+ unsigned int xregno = INVALID_REGNUM;
+
+ if (REG_P (x))
{
- if (TARGET_AM33)
- return DATA_OR_EXTENDED_REGS;
- return DATA_REGS;
+ xregno = REGNO (x);
+ if (xregno >= FIRST_PSEUDO_REGISTER)
+ xregno = true_regnum (x);
+ if (xregno != INVALID_REGNUM)
+ xclass = REGNO_REG_CLASS (xregno);
}
- /* We can't directly load sp + const_int into a data register;
- we must use an address register as an intermediate. */
- if (class != SP_REGS
- && class != ADDRESS_REGS
- && class != SP_OR_ADDRESS_REGS
- && class != SP_OR_EXTENDED_REGS
- && class != ADDRESS_OR_EXTENDED_REGS
- && class != SP_OR_ADDRESS_OR_EXTENDED_REGS
- && (in == stack_pointer_rtx
- || (GET_CODE (in) == PLUS
- && (XEXP (in, 0) == stack_pointer_rtx
- || XEXP (in, 1) == stack_pointer_rtx))))
- return ADDRESS_REGS;
-
- if (GET_CODE (in) == PLUS
- && (XEXP (in, 0) == stack_pointer_rtx
- || XEXP (in, 1) == stack_pointer_rtx))
+ if (!TARGET_AM33)
{
- if (TARGET_AM33)
- return DATA_OR_EXTENDED_REGS;
- return DATA_REGS;
+ /* Memory load/stores less than a full word wide can't have an
+ address or stack pointer destination. They must use a data
+ register as an intermediate register. */
+ if (rclass != DATA_REGS
+ && (mode == QImode || mode == HImode)
+ && xclass == NO_REGS)
+ return DATA_REGS;
+
+ /* We can only move SP to/from an address register. */
+ if (in_p
+ && rclass == SP_REGS
+ && xclass != ADDRESS_REGS)
+ return ADDRESS_REGS;
+ if (!in_p
+ && xclass == SP_REGS
+ && rclass != ADDRESS_REGS
+ && rclass != SP_OR_ADDRESS_REGS)
+ return ADDRESS_REGS;
}
-
- if (TARGET_AM33_2 && class == FP_REGS
- && GET_CODE (in) == MEM && ! OK_FOR_Q (in))
+
+ /* We can't directly load sp + const_int into a register;
+ we must use an address register as an scratch. */
+ if (in_p
+ && rclass != SP_REGS
+ && rclass != SP_OR_ADDRESS_REGS
+ && rclass != SP_OR_GENERAL_REGS
+ && GET_CODE (x) == PLUS
+ && (XEXP (x, 0) == stack_pointer_rtx
+ || XEXP (x, 1) == stack_pointer_rtx))
{
- if (TARGET_AM33)
- return DATA_OR_EXTENDED_REGS;
- return DATA_REGS;
+ sri->icode = CODE_FOR_reload_plus_sp_const;
+ return NO_REGS;
+ }
+
+ /* We can only move MDR to/from a data register. */
+ if (rclass == MDR_REGS && xclass != DATA_REGS)
+ return DATA_REGS;
+ if (xclass == MDR_REGS && rclass != DATA_REGS)
+ return DATA_REGS;
+
+ /* We can't load/store an FP register from a constant address. */
+ if (TARGET_AM33_2
+ && (rclass == FP_REGS || xclass == FP_REGS)
+ && (xclass == NO_REGS || rclass == NO_REGS))
+ {
+ rtx addr = NULL;
+
+ if (xregno >= FIRST_PSEUDO_REGISTER && xregno != INVALID_REGNUM)
+ {
+ addr = reg_equiv_mem (xregno);
+ if (addr)
+ addr = XEXP (addr, 0);
+ }
+ else if (MEM_P (x))
+ addr = XEXP (x, 0);
+
+ if (addr && CONSTANT_ADDRESS_P (addr))
+ return GENERAL_REGS;
}
/* Otherwise assume no secondary reloads are needed. */
}
int
-initial_offset (int from, int to)
+mn10300_frame_size (void)
+{
+ /* size includes the fixed stack space needed for function calls. */
+ int size = get_frame_size () + crtl->outgoing_args_size;
+
+ /* And space for the return pointer. */
+ size += crtl->outgoing_args_size ? 4 : 0;
+
+ return size;
+}
+
+int
+mn10300_initial_offset (int from, int to)
{
+ int diff = 0;
+
+ gcc_assert (from == ARG_POINTER_REGNUM || from == FRAME_POINTER_REGNUM);
+ gcc_assert (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
+
+ if (to == STACK_POINTER_REGNUM)
+ diff = mn10300_frame_size ();
+
/* The difference between the argument pointer and the frame pointer
is the size of the callee register save area. */
- if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
+ if (from == ARG_POINTER_REGNUM)
{
- if (regs_ever_live[2] || regs_ever_live[3]
- || regs_ever_live[6] || regs_ever_live[7]
- || regs_ever_live[14] || regs_ever_live[15]
- || regs_ever_live[16] || regs_ever_live[17]
- || fp_regs_to_save ()
- || frame_pointer_needed)
- return REG_SAVE_BYTES
- + 4 * fp_regs_to_save ();
- else
- return 0;
+ diff += REG_SAVE_BYTES;
+ diff += 4 * fp_regs_to_save ();
}
- /* The difference between the argument pointer and the stack pointer is
- the sum of the size of this function's frame, the callee register save
- area, and the fixed stack space needed for function calls (if any). */
- if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
- {
- if (regs_ever_live[2] || regs_ever_live[3]
- || regs_ever_live[6] || regs_ever_live[7]
- || regs_ever_live[14] || regs_ever_live[15]
- || regs_ever_live[16] || regs_ever_live[17]
- || fp_regs_to_save ()
- || frame_pointer_needed)
- return (get_frame_size () + REG_SAVE_BYTES
- + 4 * fp_regs_to_save ()
- + (current_function_outgoing_args_size
- ? current_function_outgoing_args_size + 4 : 0));
- else
- return (get_frame_size ()
- + (current_function_outgoing_args_size
- ? current_function_outgoing_args_size + 4 : 0));
- }
+ return diff;
+}
- /* The difference between the frame pointer and stack pointer is the sum
- of the size of this function's frame and the fixed stack space needed
- for function calls (if any). */
- if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
- return (get_frame_size ()
- + (current_function_outgoing_args_size
- ? current_function_outgoing_args_size + 4 : 0));
+/* Worker function for TARGET_RETURN_IN_MEMORY. */
- abort ();
+static bool
+mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
+{
+ /* Return values > 8 bytes in length in memory. */
+ return (int_size_in_bytes (type) > 8
+ || int_size_in_bytes (type) == 0
+ || TYPE_MODE (type) == BLKmode);
}
/* Flush the argument registers to the stack for a stdarg function;
return the new argument pointer. */
-rtx
+static rtx
mn10300_builtin_saveregs (void)
{
rtx offset, mem;
tree fntype = TREE_TYPE (current_function_decl);
- int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
- && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
- != void_type_node)))
+ int argadj = ((!stdarg_p (fntype))
? UNITS_PER_WORD : 0);
- int set = get_varargs_alias_set ();
+ alias_set_type set = get_varargs_alias_set ();
if (argadj)
- offset = plus_constant (current_function_arg_offset_rtx, argadj);
+ offset = plus_constant (crtl->args.arg_offset_rtx, argadj);
else
- offset = current_function_arg_offset_rtx;
+ offset = crtl->args.arg_offset_rtx;
- mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer);
+ mem = gen_rtx_MEM (SImode, crtl->args.internal_arg_pointer);
set_mem_alias_set (mem, set);
emit_move_insn (mem, gen_rtx_REG (SImode, 0));
mem = gen_rtx_MEM (SImode,
- plus_constant (current_function_internal_arg_pointer, 4));
+ plus_constant (crtl->args.internal_arg_pointer, 4));
set_mem_alias_set (mem, set);
emit_move_insn (mem, gen_rtx_REG (SImode, 1));
return copy_to_reg (expand_binop (Pmode, add_optab,
- current_function_internal_arg_pointer,
+ crtl->args.internal_arg_pointer,
offset, 0, 0, OPTAB_LIB_WIDEN));
}
-void
+static void
mn10300_va_start (tree valist, rtx nextarg)
{
nextarg = expand_builtin_saveregs ();
std_expand_builtin_va_start (valist, nextarg);
}
-rtx
-mn10300_va_arg (tree valist, tree type)
-{
- HOST_WIDE_INT align, rsize;
- tree t, ptr, pptr;
-
- /* Compute the rounded size of the type. */
- align = PARM_BOUNDARY / BITS_PER_UNIT;
- rsize = (((int_size_in_bytes (type) + align - 1) / align) * align);
-
- t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
- build_int_2 ((rsize > 8 ? 4 : rsize), 0));
- TREE_SIDE_EFFECTS (t) = 1;
+/* Return true when a parameter should be passed by reference. */
- ptr = build_pointer_type (type);
-
- /* "Large" types are passed by reference. */
- if (rsize > 8)
- {
- pptr = build_pointer_type (ptr);
- t = build1 (NOP_EXPR, pptr, t);
- TREE_SIDE_EFFECTS (t) = 1;
+static bool
+mn10300_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
+ enum machine_mode mode, const_tree type,
+ bool named ATTRIBUTE_UNUSED)
+{
+ unsigned HOST_WIDE_INT size;
- t = build1 (INDIRECT_REF, ptr, t);
- TREE_SIDE_EFFECTS (t) = 1;
- }
+ if (type)
+ size = int_size_in_bytes (type);
else
- {
- t = build1 (NOP_EXPR, ptr, t);
- TREE_SIDE_EFFECTS (t) = 1;
- }
+ size = GET_MODE_SIZE (mode);
- /* Calculate! */
- return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
+ return (size > 8 || size == 0);
}
/* Return an RTX to represent where a value with mode MODE will be returned
- from a function. If the result is 0, the argument is pushed. */
+ from a function. If the result is NULL_RTX, the argument is pushed. */
-rtx
-function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
- tree type, int named ATTRIBUTE_UNUSED)
+static rtx
+mn10300_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
+ const_tree type, bool named ATTRIBUTE_UNUSED)
{
- rtx result = 0;
- int size, align;
+ CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
+ rtx result = NULL_RTX;
+ int size;
/* We only support using 2 data registers as argument registers. */
int nregs = 2;
else
size = GET_MODE_SIZE (mode);
- /* Figure out the alignment of the object to be passed. */
- align = size;
-
cum->nbytes = (cum->nbytes + 3) & ~3;
/* Don't pass this arg via a register if all the argument registers
are used up. */
if (cum->nbytes > nregs * UNITS_PER_WORD)
- return 0;
+ return result;
/* Don't pass this arg via a register if it would be split between
registers and memory. */
if (type == NULL_TREE
&& cum->nbytes + size > nregs * UNITS_PER_WORD)
- return 0;
+ return result;
switch (cum->nbytes / UNITS_PER_WORD)
{
case 0:
- result = gen_rtx_REG (mode, 0);
+ result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM);
break;
case 1:
- result = gen_rtx_REG (mode, 1);
+ result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM + 1);
break;
default:
- result = 0;
+ break;
}
return result;
}
-/* Return the number of registers to use for an argument passed partially
- in registers and partially in memory. */
+/* Update the data in CUM to advance over an argument
+ of mode MODE and data type TYPE.
+ (TYPE is null for libcalls where that information may not be available.) */
-int
-function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
- tree type, int named ATTRIBUTE_UNUSED)
+static void
+mn10300_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
+ const_tree type, bool named ATTRIBUTE_UNUSED)
+{
+ CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
+
+ cum->nbytes += (mode != BLKmode
+ ? (GET_MODE_SIZE (mode) + 3) & ~3
+ : (int_size_in_bytes (type) + 3) & ~3);
+}
+
+/* Return the number of bytes of registers to use for an argument passed
+ partially in registers and partially in memory. */
+
+static int
+mn10300_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
+ tree type, bool named ATTRIBUTE_UNUSED)
{
- int size, align;
+ CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
+ int size;
/* We only support using 2 data registers as argument registers. */
int nregs = 2;
else
size = GET_MODE_SIZE (mode);
- /* Figure out the alignment of the object to be passed. */
- align = size;
-
cum->nbytes = (cum->nbytes + 3) & ~3;
/* Don't pass this arg via a register if all the argument registers
&& cum->nbytes + size > nregs * UNITS_PER_WORD)
return 0;
- return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD;
+ return nregs * UNITS_PER_WORD - cum->nbytes;
}
-/* Output a tst insn. */
-const char *
-output_tst (rtx operand, rtx insn)
-{
- rtx temp;
- int past_call = 0;
-
- /* We can save a byte if we can find a register which has the value
- zero in it. */
- temp = PREV_INSN (insn);
- while (optimize && temp)
- {
- rtx set;
-
- /* We allow the search to go through call insns. We record
- the fact that we've past a CALL_INSN and reject matches which
- use call clobbered registers. */
- if (GET_CODE (temp) == CODE_LABEL
- || GET_CODE (temp) == JUMP_INSN
- || GET_CODE (temp) == BARRIER)
- break;
-
- if (GET_CODE (temp) == CALL_INSN)
- past_call = 1;
-
- if (GET_CODE (temp) == NOTE)
- {
- temp = PREV_INSN (temp);
- continue;
- }
+/* Return the location of the function's value. This will be either
+ $d0 for integer functions, $a0 for pointers, or a PARALLEL of both
+ $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that
+ we only return the PARALLEL for outgoing values; we do not want
+ callers relying on this extra copy. */
- /* It must be an insn, see if it is a simple set. */
- set = single_set (temp);
- if (!set)
- {
- temp = PREV_INSN (temp);
- continue;
- }
+static rtx
+mn10300_function_value (const_tree valtype,
+ const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
+ bool outgoing)
+{
+ rtx rv;
+ enum machine_mode mode = TYPE_MODE (valtype);
+
+ if (! POINTER_TYPE_P (valtype))
+ return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
+ else if (! TARGET_PTR_A0D0 || ! outgoing
+ || cfun->returns_struct)
+ return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM);
+
+ rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2));
+ XVECEXP (rv, 0, 0)
+ = gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM),
+ GEN_INT (0));
+
+ XVECEXP (rv, 0, 1)
+ = gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_REG (mode, FIRST_DATA_REGNUM),
+ GEN_INT (0));
+ return rv;
+}
- /* Are we setting a data register to zero (this does not win for
- address registers)?
-
- If it's a call clobbered register, have we past a call?
-
- Make sure the register we find isn't the same as ourself;
- the mn10300 can't encode that.
-
- ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
- so the code to detect calls here isn't doing anything useful. */
- if (REG_P (SET_DEST (set))
- && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
- && !reg_set_between_p (SET_DEST (set), temp, insn)
- && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
- == REGNO_REG_CLASS (REGNO (operand)))
- && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
- && REGNO (SET_DEST (set)) != REGNO (operand)
- && (!past_call
- || !call_used_regs[REGNO (SET_DEST (set))]))
- {
- rtx xoperands[2];
- xoperands[0] = operand;
- xoperands[1] = SET_DEST (set);
+/* Implements TARGET_LIBCALL_VALUE. */
- output_asm_insn ("cmp %1,%0", xoperands);
- return "";
- }
+static rtx
+mn10300_libcall_value (enum machine_mode mode,
+ const_rtx fun ATTRIBUTE_UNUSED)
+{
+ return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
+}
- if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS
- && REG_P (SET_DEST (set))
- && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
- && !reg_set_between_p (SET_DEST (set), temp, insn)
- && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
- != REGNO_REG_CLASS (REGNO (operand)))
- && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
- && REGNO (SET_DEST (set)) != REGNO (operand)
- && (!past_call
- || !call_used_regs[REGNO (SET_DEST (set))]))
- {
- rtx xoperands[2];
- xoperands[0] = operand;
- xoperands[1] = SET_DEST (set);
+/* Implements FUNCTION_VALUE_REGNO_P. */
- output_asm_insn ("cmp %1,%0", xoperands);
- return "";
- }
- temp = PREV_INSN (temp);
- }
- return "cmp 0,%0";
+bool
+mn10300_function_value_regno_p (const unsigned int regno)
+{
+ return (regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM);
}
-int
-impossible_plus_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+/* Output an addition operation. */
+
+const char *
+mn10300_output_add (rtx operands[3], bool need_flags)
{
- if (GET_CODE (op) != PLUS)
- return 0;
+ rtx dest, src1, src2;
+ unsigned int dest_regnum, src1_regnum, src2_regnum;
+ enum reg_class src1_class, src2_class, dest_class;
- if (XEXP (op, 0) == stack_pointer_rtx
- || XEXP (op, 1) == stack_pointer_rtx)
- return 1;
+ dest = operands[0];
+ src1 = operands[1];
+ src2 = operands[2];
- return 0;
-}
+ dest_regnum = true_regnum (dest);
+ src1_regnum = true_regnum (src1);
-/* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used
- for the btst insn which may examine memory or a register (the memory
- variant only allows an unsigned 8 bit integer). */
-int
-const_8bit_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return (GET_CODE (op) == CONST_INT
- && INTVAL (op) >= 0
- && INTVAL (op) < 256);
-}
+ dest_class = REGNO_REG_CLASS (dest_regnum);
+ src1_class = REGNO_REG_CLASS (src1_regnum);
-/* Return true if the operand is the 1.0f constant. */
-int
-const_1f_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return (op == CONST1_RTX (SFmode));
-}
+ if (CONST_INT_P (src2))
+ {
+ gcc_assert (dest_regnum == src1_regnum);
-/* Similarly, but when using a zero_extract pattern for a btst where
- the source operand might end up in memory. */
-int
-mask_ok_for_mem_btst (int len, int bit)
-{
- unsigned int mask = 0;
+ if (src2 == const1_rtx && !need_flags)
+ return "inc %0";
+ if (INTVAL (src2) == 4 && !need_flags && dest_class != DATA_REGS)
+ return "inc4 %0";
+
+ gcc_assert (!need_flags || dest_class != SP_REGS);
+ return "add %2,%0";
+ }
+ else if (CONSTANT_P (src2))
+ return "add %2,%0";
- while (len > 0)
+ src2_regnum = true_regnum (src2);
+ src2_class = REGNO_REG_CLASS (src2_regnum);
+
+ if (dest_regnum == src1_regnum)
+ return "add %2,%0";
+ if (dest_regnum == src2_regnum)
+ return "add %1,%0";
+
+ /* The rest of the cases are reg = reg+reg. For AM33, we can implement
+ this directly, as below, but when optimizing for space we can sometimes
+ do better by using a mov+add. For MN103, we claimed that we could
+ implement a three-operand add because the various move and add insns
+ change sizes across register classes, and we can often do better than
+ reload in choosing which operand to move. */
+ if (TARGET_AM33 && optimize_insn_for_speed_p ())
+ return "add %2,%1,%0";
+
+ /* Catch cases where no extended register was used. */
+ if (src1_class != EXTENDED_REGS
+ && src2_class != EXTENDED_REGS
+ && dest_class != EXTENDED_REGS)
{
- mask |= (1 << bit);
- bit++;
- len--;
+ /* We have to copy one of the sources into the destination, then
+ add the other source to the destination.
+
+ Carefully select which source to copy to the destination; a
+ naive implementation will waste a byte when the source classes
+ are different and the destination is an address register.
+ Selecting the lowest cost register copy will optimize this
+ sequence. */
+ if (src1_class == dest_class)
+ return "mov %1,%0\n\tadd %2,%0";
+ else
+ return "mov %2,%0\n\tadd %1,%0";
}
- /* MASK must bit into an 8bit value. */
- return (((mask & 0xff) == mask)
- || ((mask & 0xff00) == mask)
- || ((mask & 0xff0000) == mask)
- || ((mask & 0xff000000) == mask));
+ /* At least one register is an extended register. */
+
+ /* The three operand add instruction on the am33 is a win iff the
+ output register is an extended register, or if both source
+ registers are extended registers. */
+ if (dest_class == EXTENDED_REGS || src1_class == src2_class)
+ return "add %2,%1,%0";
+
+ /* It is better to copy one of the sources to the destination, then
+ perform a 2 address add. The destination in this case must be
+ an address or data register and one of the sources must be an
+ extended register and the remaining source must not be an extended
+ register.
+
+ The best code for this case is to copy the extended reg to the
+ destination, then emit a two address add. */
+ if (src1_class == EXTENDED_REGS)
+ return "mov %1,%0\n\tadd %2,%0";
+ else
+ return "mov %2,%0\n\tadd %1,%0";
}
/* Return 1 if X contains a symbolic expression. We know these
expressions will have one of a few well defined forms, so
we need only check those forms. */
+
int
-symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+mn10300_symbolic_operand (rtx op,
+ enum machine_mode mode ATTRIBUTE_UNUSED)
{
switch (GET_CODE (op))
{
op = XEXP (op, 0);
return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
|| GET_CODE (XEXP (op, 0)) == LABEL_REF)
- && GET_CODE (XEXP (op, 1)) == CONST_INT);
+ && CONST_INT_P (XEXP (op, 1)));
default:
return 0;
}
OLDX is the address as it was before break_out_memory_refs was called.
In some cases it is useful to look at this to decide what needs to be done.
- MODE and WIN are passed so that this macro can use
- GO_IF_LEGITIMATE_ADDRESS.
-
Normally it is always safe for this macro to do nothing. It exists to
recognize opportunities to optimize the output.
But on a few ports with segmented architectures and indexed addressing
(mn10300, hppa) it is used to rewrite certain problematical addresses. */
-rtx
-legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
- enum machine_mode mode ATTRIBUTE_UNUSED)
+
+static rtx
+mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
+ enum machine_mode mode ATTRIBUTE_UNUSED)
{
- if (flag_pic && ! legitimate_pic_operand_p (x))
- x = legitimize_pic_address (oldx, NULL_RTX);
+ if (flag_pic && ! mn10300_legitimate_pic_operand_p (x))
+ x = mn10300_legitimize_pic_address (oldx, NULL_RTX);
/* Uh-oh. We might have an address for x[n-100000]. This needs
special handling to avoid creating an indexed memory address
with x-100000 as the base. */
if (GET_CODE (x) == PLUS
- && symbolic_operand (XEXP (x, 1), VOIDmode))
+ && mn10300_symbolic_operand (XEXP (x, 1), VOIDmode))
{
/* Ugly. We modify things here so that the address offset specified
by the index expression is computed first, then added to x to form
regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
regx1 = force_reg (Pmode,
- gen_rtx (GET_CODE (y), Pmode, regx1, regy2));
+ gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1,
+ regy2));
return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
}
}
}
/* Convert a non-PIC address in `orig' to a PIC address using @GOT or
- @GOTOFF in `reg'. */
+ @GOTOFF in `reg'. */
+
rtx
-legitimize_pic_address (rtx orig, rtx reg)
+mn10300_legitimize_pic_address (rtx orig, rtx reg)
{
+ rtx x;
+
if (GET_CODE (orig) == LABEL_REF
|| (GET_CODE (orig) == SYMBOL_REF
&& (CONSTANT_POOL_ADDRESS_P (orig)
|| ! MN10300_GLOBAL_P (orig))))
{
- if (reg == 0)
+ if (reg == NULL)
reg = gen_reg_rtx (Pmode);
- emit_insn (gen_symGOTOFF2reg (reg, orig));
- return reg;
+ x = gen_rtx_UNSPEC (SImode, gen_rtvec (1, orig), UNSPEC_GOTOFF);
+ x = gen_rtx_CONST (SImode, x);
+ emit_move_insn (reg, x);
+
+ x = emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
}
else if (GET_CODE (orig) == SYMBOL_REF)
{
- if (reg == 0)
+ if (reg == NULL)
reg = gen_reg_rtx (Pmode);
- emit_insn (gen_symGOT2reg (reg, orig));
- return reg;
+ x = gen_rtx_UNSPEC (SImode, gen_rtvec (1, orig), UNSPEC_GOT);
+ x = gen_rtx_CONST (SImode, x);
+ x = gen_rtx_PLUS (SImode, pic_offset_table_rtx, x);
+ x = gen_const_mem (SImode, x);
+
+ x = emit_move_insn (reg, x);
}
- return orig;
+ else
+ return orig;
+
+ set_unique_reg_note (x, REG_EQUAL, orig);
+ return reg;
}
/* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
isn't protected by a PIC unspec; nonzero otherwise. */
+
int
-legitimate_pic_operand_p (rtx x)
+mn10300_legitimate_pic_operand_p (rtx x)
{
- register const char *fmt;
- register int i;
+ const char *fmt;
+ int i;
if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
return 0;
&& (XINT (x, 1) == UNSPEC_PIC
|| XINT (x, 1) == UNSPEC_GOT
|| XINT (x, 1) == UNSPEC_GOTOFF
- || XINT (x, 1) == UNSPEC_PLT))
+ || XINT (x, 1) == UNSPEC_PLT
+ || XINT (x, 1) == UNSPEC_GOTSYM_OFF))
return 1;
- if (GET_CODE (x) == QUEUED)
- return legitimate_pic_operand_p (QUEUED_VAR (x));
-
fmt = GET_RTX_FORMAT (GET_CODE (x));
for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
{
if (fmt[i] == 'E')
{
- register int j;
+ int j;
for (j = XVECLEN (x, i) - 1; j >= 0; j--)
- if (! legitimate_pic_operand_p (XVECEXP (x, i, j)))
+ if (! mn10300_legitimate_pic_operand_p (XVECEXP (x, i, j)))
return 0;
}
- else if (fmt[i] == 'e' && ! legitimate_pic_operand_p (XEXP (x, i)))
+ else if (fmt[i] == 'e'
+ && ! mn10300_legitimate_pic_operand_p (XEXP (x, i)))
return 0;
}
return 1;
}
-static int
-mn10300_address_cost_1 (rtx x, int *unsig)
-{
- switch (GET_CODE (x))
- {
- case REG:
- switch (REGNO_REG_CLASS (REGNO (x)))
- {
- case SP_REGS:
- *unsig = 1;
- return 0;
+/* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is
+ legitimate, and FALSE otherwise.
- case ADDRESS_REGS:
- return 1;
+ On the mn10300, the value in the address register must be
+ in the same memory space/segment as the effective address.
- case DATA_REGS:
- case EXTENDED_REGS:
- case FP_REGS:
- return 3;
+ This is problematical for reload since it does not understand
+ that base+index != index+base in a memory reference.
- case NO_REGS:
- return 5;
+ Note it is still possible to use reg+reg addressing modes,
+ it's just much more difficult. For a discussion of a possible
+ workaround and solution, see the comments in pa.c before the
+ function record_unscaled_index_insn_codes. */
- default:
- abort ();
- }
+static bool
+mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
+{
+ rtx base, index;
- case PLUS:
- case MINUS:
- case ASHIFT:
- case AND:
- case IOR:
- return (mn10300_address_cost_1 (XEXP (x, 0), unsig)
- + mn10300_address_cost_1 (XEXP (x, 1), unsig));
+ if (CONSTANT_ADDRESS_P (x))
+ return !flag_pic || mn10300_legitimate_pic_operand_p (x);
- case EXPR_LIST:
- case SUBREG:
- case MEM:
- return mn10300_address_cost (XEXP (x, 0));
+ if (RTX_OK_FOR_BASE_P (x, strict))
+ return true;
- case ZERO_EXTEND:
- *unsig = 1;
- return mn10300_address_cost_1 (XEXP (x, 0), unsig);
+ if (TARGET_AM33 && (mode == SImode || mode == SFmode || mode == HImode))
+ {
+ if (GET_CODE (x) == POST_INC)
+ return RTX_OK_FOR_BASE_P (XEXP (x, 0), strict);
+ if (GET_CODE (x) == POST_MODIFY)
+ return (RTX_OK_FOR_BASE_P (XEXP (x, 0), strict)
+ && CONSTANT_ADDRESS_P (XEXP (x, 1)));
+ }
- case CONST_INT:
- if (INTVAL (x) == 0)
- return 0;
- if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100)
- return 1;
- if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000)
- return 3;
- if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000)
- return 5;
- return 7;
+ if (GET_CODE (x) != PLUS)
+ return false;
- case CONST:
- case SYMBOL_REF:
- case LABEL_REF:
- return 8;
+ base = XEXP (x, 0);
+ index = XEXP (x, 1);
- case ADDRESSOF:
- switch (GET_CODE (XEXP (x, 0)))
- {
- case MEM:
- return mn10300_address_cost (XEXP (x, 0));
+ if (!REG_P (base))
+ return false;
+ if (REG_P (index))
+ {
+ /* ??? Without AM33 generalized (Ri,Rn) addressing, reg+reg
+ addressing is hard to satisfy. */
+ if (!TARGET_AM33)
+ return false;
- case REG:
- return 1;
+ return (REGNO_GENERAL_P (REGNO (base), strict)
+ && REGNO_GENERAL_P (REGNO (index), strict));
+ }
- default:
- abort ();
- }
+ if (!REGNO_STRICT_OK_FOR_BASE_P (REGNO (base), strict))
+ return false;
- default:
- abort ();
+ if (CONST_INT_P (index))
+ return IN_RANGE (INTVAL (index), -1 - 0x7fffffff, 0x7fffffff);
- }
-}
+ if (CONSTANT_ADDRESS_P (index))
+ return !flag_pic || mn10300_legitimate_pic_operand_p (index);
-static int
-mn10300_address_cost (rtx x)
-{
- int s = 0;
- return mn10300_address_cost_1 (x, &s);
+ return false;
}
-static bool
-mn10300_rtx_costs (rtx x, int code, int outer_code, int *total)
+bool
+mn10300_regno_in_class_p (unsigned regno, int rclass, bool strict)
{
- switch (code)
+ if (regno >= FIRST_PSEUDO_REGISTER)
{
- case CONST_INT:
- /* Zeros are extremely cheap. */
- if (INTVAL (x) == 0 && outer_code == SET)
- *total = 0;
- /* If it fits in 8 bits, then it's still relatively cheap. */
- else if (INT_8_BITS (INTVAL (x)))
- *total = 1;
- /* This is the "base" cost, includes constants where either the
- upper or lower 16bits are all zeros. */
- else if (INT_16_BITS (INTVAL (x))
- || (INTVAL (x) & 0xffff) == 0
- || (INTVAL (x) & 0xffff0000) == 0)
- *total = 2;
- else
- *total = 4;
- return true;
+ if (!strict)
+ return true;
+ if (!reg_renumber)
+ return false;
+ regno = reg_renumber[regno];
+ if (regno == INVALID_REGNUM)
+ return false;
+ }
+ return TEST_HARD_REG_BIT (reg_class_contents[rclass], regno);
+}
- case CONST:
- case LABEL_REF:
- case SYMBOL_REF:
- /* These are more costly than a CONST_INT, but we can relax them,
- so they're less costly than a CONST_DOUBLE. */
- *total = 6;
- return true;
+rtx
+mn10300_legitimize_reload_address (rtx x,
+ enum machine_mode mode ATTRIBUTE_UNUSED,
+ int opnum, int type,
+ int ind_levels ATTRIBUTE_UNUSED)
+{
+ bool any_change = false;
- case CONST_DOUBLE:
- /* We don't optimize CONST_DOUBLEs well nor do we relax them well,
- so their cost is very high. */
- *total = 8;
- return true;
+ /* See above re disabling reg+reg addressing for MN103. */
+ if (!TARGET_AM33)
+ return NULL_RTX;
- /* ??? This probably needs more work. */
- case MOD:
- case DIV:
- case MULT:
- *total = 8;
- return true;
+ if (GET_CODE (x) != PLUS)
+ return NULL_RTX;
- default:
- return false;
+ if (XEXP (x, 0) == stack_pointer_rtx)
+ {
+ push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
+ GENERAL_REGS, GET_MODE (x), VOIDmode, 0, 0,
+ opnum, (enum reload_type) type);
+ any_change = true;
}
+ if (XEXP (x, 1) == stack_pointer_rtx)
+ {
+ push_reload (XEXP (x, 1), NULL_RTX, &XEXP (x, 1), NULL,
+ GENERAL_REGS, GET_MODE (x), VOIDmode, 0, 0,
+ opnum, (enum reload_type) type);
+ any_change = true;
+ }
+
+ return any_change ? x : NULL_RTX;
}
-/* Check whether a constant used to initialize a DImode or DFmode can
- use a clr instruction. The code here must be kept in sync with
- movdf and movdi. */
+/* Implement TARGET_LEGITIMATE_CONSTANT_P. Returns TRUE if X is a valid
+ constant. Note that some "constants" aren't valid, such as TLS
+ symbols and unconverted GOT-based references, so we eliminate
+ those here. */
-bool
-mn10300_wide_const_load_uses_clr (rtx operands[2])
+static bool
+mn10300_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
{
- long val[2];
+ switch (GET_CODE (x))
+ {
+ case CONST:
+ x = XEXP (x, 0);
- if (GET_CODE (operands[0]) != REG
- || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS)
- return false;
+ if (GET_CODE (x) == PLUS)
+ {
+ if (! CONST_INT_P (XEXP (x, 1)))
+ return false;
+ x = XEXP (x, 0);
+ }
- switch (GET_CODE (operands[1]))
- {
- case CONST_INT:
- {
- rtx low, high;
- split_double (operands[1], &low, &high);
- val[0] = INTVAL (low);
- val[1] = INTVAL (high);
- }
- break;
-
+ /* Only some unspecs are valid as "constants". */
+ if (GET_CODE (x) == UNSPEC)
+ {
+ switch (XINT (x, 1))
+ {
+ case UNSPEC_PIC:
+ case UNSPEC_GOT:
+ case UNSPEC_GOTOFF:
+ case UNSPEC_PLT:
+ return true;
+ default:
+ return false;
+ }
+ }
+
+ /* We must have drilled down to a symbol. */
+ if (! mn10300_symbolic_operand (x, Pmode))
+ return false;
+ break;
+
+ default:
+ break;
+ }
+
+ return true;
+}
+
+/* Undo pic address legitimization for the benefit of debug info. */
+
+static rtx
+mn10300_delegitimize_address (rtx orig_x)
+{
+ rtx x = orig_x, ret, addend = NULL;
+ bool need_mem;
+
+ if (MEM_P (x))
+ x = XEXP (x, 0);
+ if (GET_CODE (x) != PLUS || GET_MODE (x) != Pmode)
+ return orig_x;
+
+ if (XEXP (x, 0) == pic_offset_table_rtx)
+ ;
+ /* With the REG+REG addressing of AM33, var-tracking can re-assemble
+ some odd-looking "addresses" that were never valid in the first place.
+ We need to look harder to avoid warnings being emitted. */
+ else if (GET_CODE (XEXP (x, 0)) == PLUS)
+ {
+ rtx x0 = XEXP (x, 0);
+ rtx x00 = XEXP (x0, 0);
+ rtx x01 = XEXP (x0, 1);
+
+ if (x00 == pic_offset_table_rtx)
+ addend = x01;
+ else if (x01 == pic_offset_table_rtx)
+ addend = x00;
+ else
+ return orig_x;
+
+ }
+ else
+ return orig_x;
+ x = XEXP (x, 1);
+
+ if (GET_CODE (x) != CONST)
+ return orig_x;
+ x = XEXP (x, 0);
+ if (GET_CODE (x) != UNSPEC)
+ return orig_x;
+
+ ret = XVECEXP (x, 0, 0);
+ if (XINT (x, 1) == UNSPEC_GOTOFF)
+ need_mem = false;
+ else if (XINT (x, 1) == UNSPEC_GOT)
+ need_mem = true;
+ else
+ return orig_x;
+
+ gcc_assert (GET_CODE (ret) == SYMBOL_REF);
+ if (need_mem != MEM_P (orig_x))
+ return orig_x;
+ if (need_mem && addend)
+ return orig_x;
+ if (addend)
+ ret = gen_rtx_PLUS (Pmode, addend, ret);
+ return ret;
+}
+
+/* For addresses, costs are relative to "MOV (Rm),Rn". For AM33 this is
+ the 3-byte fully general instruction; for MN103 this is the 2-byte form
+ with an address register. */
+
+static int
+mn10300_address_cost (rtx x, bool speed)
+{
+ HOST_WIDE_INT i;
+ rtx base, index;
+
+ switch (GET_CODE (x))
+ {
+ case CONST:
+ case SYMBOL_REF:
+ case LABEL_REF:
+ /* We assume all of these require a 32-bit constant, even though
+ some symbol and label references can be relaxed. */
+ return speed ? 1 : 4;
+
+ case REG:
+ case SUBREG:
+ case POST_INC:
+ return 0;
+
+ case POST_MODIFY:
+ /* Assume any symbolic offset is a 32-bit constant. */
+ i = (CONST_INT_P (XEXP (x, 1)) ? INTVAL (XEXP (x, 1)) : 0x12345678);
+ if (IN_RANGE (i, -128, 127))
+ return speed ? 0 : 1;
+ if (speed)
+ return 1;
+ if (IN_RANGE (i, -0x800000, 0x7fffff))
+ return 3;
+ return 4;
+
+ case PLUS:
+ base = XEXP (x, 0);
+ index = XEXP (x, 1);
+ if (register_operand (index, SImode))
+ {
+ /* Attempt to minimize the number of registers in the address.
+ This is similar to what other ports do. */
+ if (register_operand (base, SImode))
+ return 1;
+
+ base = XEXP (x, 1);
+ index = XEXP (x, 0);
+ }
+
+ /* Assume any symbolic offset is a 32-bit constant. */
+ i = (CONST_INT_P (XEXP (x, 1)) ? INTVAL (XEXP (x, 1)) : 0x12345678);
+ if (IN_RANGE (i, -128, 127))
+ return speed ? 0 : 1;
+ if (IN_RANGE (i, -32768, 32767))
+ return speed ? 0 : 2;
+ return speed ? 2 : 6;
+
+ default:
+ return rtx_cost (x, MEM, 0, speed);
+ }
+}
+
+/* Implement the TARGET_REGISTER_MOVE_COST hook.
+
+ Recall that the base value of 2 is required by assumptions elsewhere
+ in the body of the compiler, and that cost 2 is special-cased as an
+ early exit from reload meaning no work is required. */
+
+static int
+mn10300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
+ reg_class_t ifrom, reg_class_t ito)
+{
+ enum reg_class from = (enum reg_class) ifrom;
+ enum reg_class to = (enum reg_class) ito;
+ enum reg_class scratch, test;
+
+ /* Simplify the following code by unifying the fp register classes. */
+ if (to == FP_ACC_REGS)
+ to = FP_REGS;
+ if (from == FP_ACC_REGS)
+ from = FP_REGS;
+
+ /* Diagnose invalid moves by costing them as two moves. */
+
+ scratch = NO_REGS;
+ test = from;
+ if (to == SP_REGS)
+ scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
+ else if (to == MDR_REGS)
+ scratch = DATA_REGS;
+ else if (to == FP_REGS && to != from)
+ scratch = GENERAL_REGS;
+ else
+ {
+ test = to;
+ if (from == SP_REGS)
+ scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
+ else if (from == MDR_REGS)
+ scratch = DATA_REGS;
+ else if (from == FP_REGS && to != from)
+ scratch = GENERAL_REGS;
+ }
+ if (scratch != NO_REGS && !reg_class_subset_p (test, scratch))
+ return (mn10300_register_move_cost (VOIDmode, from, scratch)
+ + mn10300_register_move_cost (VOIDmode, scratch, to));
+
+ /* From here on, all we need consider are legal combinations. */
+
+ if (optimize_size)
+ {
+ /* The scale here is bytes * 2. */
+
+ if (from == to && (to == ADDRESS_REGS || to == DATA_REGS))
+ return 2;
+
+ if (from == SP_REGS)
+ return (to == ADDRESS_REGS ? 2 : 6);
+
+ /* For MN103, all remaining legal moves are two bytes. */
+ if (TARGET_AM33)
+ return 4;
+
+ if (to == SP_REGS)
+ return (from == ADDRESS_REGS ? 4 : 6);
+
+ if ((from == ADDRESS_REGS || from == DATA_REGS)
+ && (to == ADDRESS_REGS || to == DATA_REGS))
+ return 4;
+
+ if (to == EXTENDED_REGS)
+ return (to == from ? 6 : 4);
+
+ /* What's left are SP_REGS, FP_REGS, or combinations of the above. */
+ return 6;
+ }
+ else
+ {
+ /* The scale here is cycles * 2. */
+
+ if (to == FP_REGS)
+ return 8;
+ if (from == FP_REGS)
+ return 4;
+
+ /* All legal moves between integral registers are single cycle. */
+ return 2;
+ }
+}
+
+/* Implement the TARGET_MEMORY_MOVE_COST hook.
+
+ Given lack of the form of the address, this must be speed-relative,
+ though we should never be less expensive than a size-relative register
+ move cost above. This is not a problem. */
+
+static int
+mn10300_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
+ reg_class_t iclass, bool in ATTRIBUTE_UNUSED)
+{
+ enum reg_class rclass = (enum reg_class) iclass;
+
+ if (rclass == FP_REGS)
+ return 8;
+ return 6;
+}
+
+/* Implement the TARGET_RTX_COSTS hook.
+
+ Speed-relative costs are relative to COSTS_N_INSNS, which is intended
+ to represent cycles. Size-relative costs are in bytes. */
+
+static bool
+mn10300_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
+ int *ptotal, bool speed)
+{
+ /* This value is used for SYMBOL_REF etc where we want to pretend
+ we have a full 32-bit constant. */
+ HOST_WIDE_INT i = 0x12345678;
+ int total;
+
+ switch (code)
+ {
+ case CONST_INT:
+ i = INTVAL (x);
+ do_int_costs:
+ if (speed)
+ {
+ if (outer_code == SET)
+ {
+ /* 16-bit integer loads have latency 1, 32-bit loads 2. */
+ if (IN_RANGE (i, -32768, 32767))
+ total = COSTS_N_INSNS (1);
+ else
+ total = COSTS_N_INSNS (2);
+ }
+ else
+ {
+ /* 16-bit integer operands don't affect latency;
+ 24-bit and 32-bit operands add a cycle. */
+ if (IN_RANGE (i, -32768, 32767))
+ total = 0;
+ else
+ total = COSTS_N_INSNS (1);
+ }
+ }
+ else
+ {
+ if (outer_code == SET)
+ {
+ if (i == 0)
+ total = 1;
+ else if (IN_RANGE (i, -128, 127))
+ total = 2;
+ else if (IN_RANGE (i, -32768, 32767))
+ total = 3;
+ else
+ total = 6;
+ }
+ else
+ {
+ /* Reference here is ADD An,Dn, vs ADD imm,Dn. */
+ if (IN_RANGE (i, -128, 127))
+ total = 0;
+ else if (IN_RANGE (i, -32768, 32767))
+ total = 2;
+ else if (TARGET_AM33 && IN_RANGE (i, -0x01000000, 0x00ffffff))
+ total = 3;
+ else
+ total = 4;
+ }
+ }
+ goto alldone;
+
+ case CONST:
+ case LABEL_REF:
+ case SYMBOL_REF:
case CONST_DOUBLE:
- if (GET_MODE (operands[1]) == DFmode)
+ /* We assume all of these require a 32-bit constant, even though
+ some symbol and label references can be relaxed. */
+ goto do_int_costs;
+
+ case UNSPEC:
+ switch (XINT (x, 1))
{
- REAL_VALUE_TYPE rv;
+ case UNSPEC_PIC:
+ case UNSPEC_GOT:
+ case UNSPEC_GOTOFF:
+ case UNSPEC_PLT:
+ case UNSPEC_GOTSYM_OFF:
+ /* The PIC unspecs also resolve to a 32-bit constant. */
+ goto do_int_costs;
- REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
- REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
+ default:
+ /* Assume any non-listed unspec is some sort of arithmetic. */
+ goto do_arith_costs;
}
- else if (GET_MODE (operands[1]) == VOIDmode
- || GET_MODE (operands[1]) == DImode)
+
+ case PLUS:
+ /* Notice the size difference of INC and INC4. */
+ if (!speed && outer_code == SET && CONST_INT_P (XEXP (x, 1)))
{
- val[0] = CONST_DOUBLE_LOW (operands[1]);
- val[1] = CONST_DOUBLE_HIGH (operands[1]);
+ i = INTVAL (XEXP (x, 1));
+ if (i == 1 || i == 4)
+ {
+ total = 1 + rtx_cost (XEXP (x, 0), PLUS, 0, speed);
+ goto alldone;
+ }
}
+ goto do_arith_costs;
+
+ case MINUS:
+ case AND:
+ case IOR:
+ case XOR:
+ case NOT:
+ case NEG:
+ case ZERO_EXTEND:
+ case SIGN_EXTEND:
+ case COMPARE:
+ case BSWAP:
+ case CLZ:
+ do_arith_costs:
+ total = (speed ? COSTS_N_INSNS (1) : 2);
break;
-
+
+ case ASHIFT:
+ /* Notice the size difference of ASL2 and variants. */
+ if (!speed && CONST_INT_P (XEXP (x, 1)))
+ switch (INTVAL (XEXP (x, 1)))
+ {
+ case 1:
+ case 2:
+ total = 1;
+ goto alldone;
+ case 3:
+ case 4:
+ total = 2;
+ goto alldone;
+ }
+ /* FALLTHRU */
+
+ case ASHIFTRT:
+ case LSHIFTRT:
+ total = (speed ? COSTS_N_INSNS (1) : 3);
+ goto alldone;
+
+ case MULT:
+ total = (speed ? COSTS_N_INSNS (3) : 2);
+ break;
+
+ case DIV:
+ case UDIV:
+ case MOD:
+ case UMOD:
+ total = (speed ? COSTS_N_INSNS (39)
+ /* Include space to load+retrieve MDR. */
+ : code == MOD || code == UMOD ? 6 : 4);
+ break;
+
+ case MEM:
+ total = mn10300_address_cost (XEXP (x, 0), speed);
+ if (speed)
+ total = COSTS_N_INSNS (2 + total);
+ goto alldone;
+
default:
- return false;
+ /* Probably not implemented. Assume external call. */
+ total = (speed ? COSTS_N_INSNS (10) : 7);
+ break;
}
- return val[0] == 0 || val[1] == 0;
+ *ptotal = total;
+ return false;
+
+ alldone:
+ *ptotal = total;
+ return true;
}
+
/* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
may access it using GOTOFF instead of GOT. */
static void
-mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED)
+mn10300_encode_section_info (tree decl, rtx rtl, int first)
{
rtx symbol;
- if (GET_CODE (rtl) != MEM)
+ default_encode_section_info (decl, rtl, first);
+
+ if (! MEM_P (rtl))
return;
symbol = XEXP (rtl, 0);
if (GET_CODE (symbol) != SYMBOL_REF)
if (flag_pic)
SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);
}
+
+/* Dispatch tables on the mn10300 are extremely expensive in terms of code
+ and readonly data size. So we crank up the case threshold value to
+ encourage a series of if/else comparisons to implement many small switch
+ statements. In theory, this value could be increased much more if we
+ were solely optimizing for space, but we keep it "reasonable" to avoid
+ serious code efficiency lossage. */
+
+static unsigned int
+mn10300_case_values_threshold (void)
+{
+ return 6;
+}
+
+/* Worker function for TARGET_TRAMPOLINE_INIT. */
+
+static void
+mn10300_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
+{
+ rtx mem, disp, fnaddr = XEXP (DECL_RTL (fndecl), 0);
+
+ /* This is a strict alignment target, which means that we play
+ some games to make sure that the locations at which we need
+ to store <chain> and <disp> wind up at aligned addresses.
+
+ 0x28 0x00 add 0,d0
+ 0xfc 0xdd mov chain,a1
+ <chain>
+ 0xf8 0xed 0x00 btst 0,d1
+ 0xdc jmp fnaddr
+ <disp>
+
+ Note that the two extra insns are effectively nops; they
+ clobber the flags but do not affect the contents of D0 or D1. */
+
+ disp = expand_binop (SImode, sub_optab, fnaddr,
+ plus_constant (XEXP (m_tramp, 0), 11),
+ NULL_RTX, 1, OPTAB_DIRECT);
+
+ mem = adjust_address (m_tramp, SImode, 0);
+ emit_move_insn (mem, gen_int_mode (0xddfc0028, SImode));
+ mem = adjust_address (m_tramp, SImode, 4);
+ emit_move_insn (mem, chain_value);
+ mem = adjust_address (m_tramp, SImode, 8);
+ emit_move_insn (mem, gen_int_mode (0xdc00edf8, SImode));
+ mem = adjust_address (m_tramp, SImode, 12);
+ emit_move_insn (mem, disp);
+}
+
+/* Output the assembler code for a C++ thunk function.
+ THUNK_DECL is the declaration for the thunk function itself, FUNCTION
+ is the decl for the target function. DELTA is an immediate constant
+ offset to be added to the THIS parameter. If VCALL_OFFSET is nonzero
+ the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be
+ additionally added to THIS. Finally jump to the entry point of
+ FUNCTION. */
+
+static void
+mn10300_asm_output_mi_thunk (FILE * file,
+ tree thunk_fndecl ATTRIBUTE_UNUSED,
+ HOST_WIDE_INT delta,
+ HOST_WIDE_INT vcall_offset,
+ tree function)
+{
+ const char * _this;
+
+ /* Get the register holding the THIS parameter. Handle the case
+ where there is a hidden first argument for a returned structure. */
+ if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
+ _this = reg_names [FIRST_ARGUMENT_REGNUM + 1];
+ else
+ _this = reg_names [FIRST_ARGUMENT_REGNUM];
+
+ fprintf (file, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START);
+
+ if (delta)
+ fprintf (file, "\tadd %d, %s\n", (int) delta, _this);
+
+ if (vcall_offset)
+ {
+ const char * scratch = reg_names [FIRST_ADDRESS_REGNUM + 1];
+
+ fprintf (file, "\tmov %s, %s\n", _this, scratch);
+ fprintf (file, "\tmov (%s), %s\n", scratch, scratch);
+ fprintf (file, "\tadd %d, %s\n", (int) vcall_offset, scratch);
+ fprintf (file, "\tmov (%s), %s\n", scratch, scratch);
+ fprintf (file, "\tadd %s, %s\n", scratch, _this);
+ }
+
+ fputs ("\tjmp ", file);
+ assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
+ putc ('\n', file);
+}
+
+/* Return true if mn10300_output_mi_thunk would be able to output the
+ assembler code for the thunk function specified by the arguments
+ it is passed, and false otherwise. */
+
+static bool
+mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
+ HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
+ HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
+ const_tree function ATTRIBUTE_UNUSED)
+{
+ return true;
+}
+
+bool
+mn10300_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
+{
+ if (REGNO_REG_CLASS (regno) == FP_REGS
+ || REGNO_REG_CLASS (regno) == FP_ACC_REGS)
+ /* Do not store integer values in FP registers. */
+ return GET_MODE_CLASS (mode) == MODE_FLOAT && ((regno & 1) == 0);
+
+ if (((regno) & 1) == 0 || GET_MODE_SIZE (mode) == 4)
+ return true;
+
+ if (REGNO_REG_CLASS (regno) == DATA_REGS
+ || (TARGET_AM33 && REGNO_REG_CLASS (regno) == ADDRESS_REGS)
+ || REGNO_REG_CLASS (regno) == EXTENDED_REGS)
+ return GET_MODE_SIZE (mode) <= 4;
+
+ return false;
+}
+
+bool
+mn10300_modes_tieable (enum machine_mode mode1, enum machine_mode mode2)
+{
+ if (GET_MODE_CLASS (mode1) == MODE_FLOAT
+ && GET_MODE_CLASS (mode2) != MODE_FLOAT)
+ return false;
+
+ if (GET_MODE_CLASS (mode2) == MODE_FLOAT
+ && GET_MODE_CLASS (mode1) != MODE_FLOAT)
+ return false;
+
+ if (TARGET_AM33
+ || mode1 == mode2
+ || (GET_MODE_SIZE (mode1) <= 4 && GET_MODE_SIZE (mode2) <= 4))
+ return true;
+
+ return false;
+}
+
+static int
+cc_flags_for_mode (enum machine_mode mode)
+{
+ switch (mode)
+ {
+ case CCmode:
+ return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_C | CC_FLAG_V;
+ case CCZNCmode:
+ return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_C;
+ case CCZNmode:
+ return CC_FLAG_Z | CC_FLAG_N;
+ case CC_FLOATmode:
+ return -1;
+ default:
+ gcc_unreachable ();
+ }
+}
+
+static int
+cc_flags_for_code (enum rtx_code code)
+{
+ switch (code)
+ {
+ case EQ: /* Z */
+ case NE: /* ~Z */
+ return CC_FLAG_Z;
+
+ case LT: /* N */
+ case GE: /* ~N */
+ return CC_FLAG_N;
+ break;
+
+ case GT: /* ~(Z|(N^V)) */
+ case LE: /* Z|(N^V) */
+ return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_V;
+
+ case GEU: /* ~C */
+ case LTU: /* C */
+ return CC_FLAG_C;
+
+ case GTU: /* ~(C | Z) */
+ case LEU: /* C | Z */
+ return CC_FLAG_Z | CC_FLAG_C;
+
+ case ORDERED:
+ case UNORDERED:
+ case LTGT:
+ case UNEQ:
+ case UNGE:
+ case UNGT:
+ case UNLE:
+ case UNLT:
+ return -1;
+
+ default:
+ gcc_unreachable ();
+ }
+}
+
+enum machine_mode
+mn10300_select_cc_mode (enum rtx_code code, rtx x, rtx y ATTRIBUTE_UNUSED)
+{
+ int req;
+
+ if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
+ return CC_FLOATmode;
+
+ req = cc_flags_for_code (code);
+
+ if (req & CC_FLAG_V)
+ return CCmode;
+ if (req & CC_FLAG_C)
+ return CCZNCmode;
+ return CCZNmode;
+}
+
+static inline bool
+is_load_insn (rtx insn)
+{
+ if (GET_CODE (PATTERN (insn)) != SET)
+ return false;
+
+ return MEM_P (SET_SRC (PATTERN (insn)));
+}
+
+static inline bool
+is_store_insn (rtx insn)
+{
+ if (GET_CODE (PATTERN (insn)) != SET)
+ return false;
+
+ return MEM_P (SET_DEST (PATTERN (insn)));
+}
+
+/* Update scheduling costs for situations that cannot be
+ described using the attributes and DFA machinery.
+ DEP is the insn being scheduled.
+ INSN is the previous insn.
+ COST is the current cycle cost for DEP. */
+
+static int
+mn10300_adjust_sched_cost (rtx insn, rtx link, rtx dep, int cost)
+{
+ int timings = get_attr_timings (insn);
+
+ if (!TARGET_AM33)
+ return 1;
+
+ if (GET_CODE (insn) == PARALLEL)
+ insn = XVECEXP (insn, 0, 0);
+
+ if (GET_CODE (dep) == PARALLEL)
+ dep = XVECEXP (dep, 0, 0);
+
+ /* For the AM34 a load instruction that follows a
+ store instruction incurs an extra cycle of delay. */
+ if (mn10300_tune_cpu == PROCESSOR_AM34
+ && is_load_insn (dep)
+ && is_store_insn (insn))
+ cost += 1;
+
+ /* For the AM34 a non-store, non-branch FPU insn that follows
+ another FPU insn incurs a one cycle throughput increase. */
+ else if (mn10300_tune_cpu == PROCESSOR_AM34
+ && ! is_store_insn (insn)
+ && ! JUMP_P (insn)
+ && GET_CODE (PATTERN (dep)) == SET
+ && GET_CODE (PATTERN (insn)) == SET
+ && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) == MODE_FLOAT
+ && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT)
+ cost += 1;
+
+ /* Resolve the conflict described in section 1-7-4 of
+ Chapter 3 of the MN103E Series Instruction Manual
+ where it says:
+
+ "When the preceeding instruction is a CPU load or
+ store instruction, a following FPU instruction
+ cannot be executed until the CPU completes the
+ latency period even though there are no register
+ or flag dependencies between them." */
+
+ /* Only the AM33-2 (and later) CPUs have FPU instructions. */
+ if (! TARGET_AM33_2)
+ return cost;
+
+ /* If a data dependence already exists then the cost is correct. */
+ if (REG_NOTE_KIND (link) == 0)
+ return cost;
+
+ /* Check that the instruction about to scheduled is an FPU instruction. */
+ if (GET_CODE (PATTERN (dep)) != SET)
+ return cost;
+
+ if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) != MODE_FLOAT)
+ return cost;
+
+ /* Now check to see if the previous instruction is a load or store. */
+ if (! is_load_insn (insn) && ! is_store_insn (insn))
+ return cost;
+
+ /* XXX: Verify: The text of 1-7-4 implies that the restriction
+ only applies when an INTEGER load/store preceeds an FPU
+ instruction, but is this true ? For now we assume that it is. */
+ if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) != MODE_INT)
+ return cost;
+
+ /* Extract the latency value from the timings attribute. */
+ return timings < 100 ? (timings % 10) : (timings % 100);
+}
+
+static void
+mn10300_conditional_register_usage (void)
+{
+ unsigned int i;
+
+ if (!TARGET_AM33)
+ {
+ for (i = FIRST_EXTENDED_REGNUM;
+ i <= LAST_EXTENDED_REGNUM; i++)
+ fixed_regs[i] = call_used_regs[i] = 1;
+ }
+ if (!TARGET_AM33_2)
+ {
+ for (i = FIRST_FP_REGNUM;
+ i <= LAST_FP_REGNUM; i++)
+ fixed_regs[i] = call_used_regs[i] = 1;
+ }
+ if (flag_pic)
+ fixed_regs[PIC_OFFSET_TABLE_REGNUM] =
+ call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
+}
+
+/* Worker function for TARGET_MD_ASM_CLOBBERS.
+ We do this in the mn10300 backend to maintain source compatibility
+ with the old cc0-based compiler. */
+
+static tree
+mn10300_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
+ tree inputs ATTRIBUTE_UNUSED,
+ tree clobbers)
+{
+ clobbers = tree_cons (NULL_TREE, build_string (5, "EPSW"),
+ clobbers);
+ return clobbers;
+}
+\f
+/* A helper function for splitting cbranch patterns after reload. */
+
+void
+mn10300_split_cbranch (enum machine_mode cmp_mode, rtx cmp_op, rtx label_ref)
+{
+ rtx flags, x;
+
+ flags = gen_rtx_REG (cmp_mode, CC_REG);
+ x = gen_rtx_COMPARE (cmp_mode, XEXP (cmp_op, 0), XEXP (cmp_op, 1));
+ x = gen_rtx_SET (VOIDmode, flags, x);
+ emit_insn (x);
+
+ x = gen_rtx_fmt_ee (GET_CODE (cmp_op), VOIDmode, flags, const0_rtx);
+ x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, label_ref, pc_rtx);
+ x = gen_rtx_SET (VOIDmode, pc_rtx, x);
+ emit_jump_insn (x);
+}
+
+/* A helper function for matching parallels that set the flags. */
+
+bool
+mn10300_match_ccmode (rtx insn, enum machine_mode cc_mode)
+{
+ rtx op1, flags;
+ enum machine_mode flags_mode;
+
+ gcc_checking_assert (XVECLEN (PATTERN (insn), 0) == 2);
+
+ op1 = XVECEXP (PATTERN (insn), 0, 1);
+ gcc_checking_assert (GET_CODE (SET_SRC (op1)) == COMPARE);
+
+ flags = SET_DEST (op1);
+ flags_mode = GET_MODE (flags);
+
+ if (GET_MODE (SET_SRC (op1)) != flags_mode)
+ return false;
+ if (GET_MODE_CLASS (flags_mode) != MODE_CC)
+ return false;
+
+ /* Ensure that the mode of FLAGS is compatible with CC_MODE. */
+ if (cc_flags_for_mode (flags_mode) & ~cc_flags_for_mode (cc_mode))
+ return false;
+
+ return true;
+}
+
+/* This function is used to help split:
+
+ (set (reg) (and (reg) (int)))
+
+ into:
+
+ (set (reg) (shift (reg) (int))
+ (set (reg) (shift (reg) (int))
+
+ where the shitfs will be shorter than the "and" insn.
+
+ It returns the number of bits that should be shifted. A positive
+ values means that the low bits are to be cleared (and hence the
+ shifts should be right followed by left) whereas a negative value
+ means that the high bits are to be cleared (left followed by right).
+ Zero is returned when it would not be economical to split the AND. */
+
+int
+mn10300_split_and_operand_count (rtx op)
+{
+ HOST_WIDE_INT val = INTVAL (op);
+ int count;
+
+ if (val < 0)
+ {
+ /* High bit is set, look for bits clear at the bottom. */
+ count = exact_log2 (-val);
+ if (count < 0)
+ return 0;
+ /* This is only size win if we can use the asl2 insn. Otherwise we
+ would be replacing 1 6-byte insn with 2 3-byte insns. */
+ if (count > (optimize_insn_for_speed_p () ? 2 : 4))
+ return 0;
+ return count;
+ }
+ else
+ {
+ /* High bit is clear, look for bits set at the bottom. */
+ count = exact_log2 (val + 1);
+ count = 32 - count;
+ /* Again, this is only a size win with asl2. */
+ if (count > (optimize_insn_for_speed_p () ? 2 : 4))
+ return 0;
+ return -count;
+ }
+}
+\f
+struct liw_data
+{
+ enum attr_liw slot;
+ enum attr_liw_op op;
+ rtx dest;
+ rtx src;
+};
+
+/* Decide if the given insn is a candidate for LIW bundling. If it is then
+ extract the operands and LIW attributes from the insn and use them to fill
+ in the liw_data structure. Return true upon success or false if the insn
+ cannot be bundled. */
+
+static bool
+extract_bundle (rtx insn, struct liw_data * pdata)
+{
+ bool allow_consts = true;
+ rtx p;
+
+ gcc_assert (pdata != NULL);
+
+ if (insn == NULL_RTX)
+ return false;
+ /* Make sure that we are dealing with a simple SET insn. */
+ p = single_set (insn);
+ if (p == NULL_RTX)
+ return false;
+
+ /* Make sure that it could go into one of the LIW pipelines. */
+ pdata->slot = get_attr_liw (insn);
+ if (pdata->slot == LIW_BOTH)
+ return false;
+
+ pdata->op = get_attr_liw_op (insn);
+
+ switch (pdata->op)
+ {
+ case LIW_OP_MOV:
+ pdata->dest = SET_DEST (p);
+ pdata->src = SET_SRC (p);
+ break;
+ case LIW_OP_CMP:
+ pdata->dest = XEXP (SET_SRC (p), 0);
+ pdata->src = XEXP (SET_SRC (p), 1);
+ break;
+ case LIW_OP_NONE:
+ return false;
+ case LIW_OP_AND:
+ case LIW_OP_OR:
+ case LIW_OP_XOR:
+ /* The AND, OR and XOR long instruction words only accept register arguments. */
+ allow_consts = false;
+ /* Fall through. */
+ default:
+ pdata->dest = SET_DEST (p);
+ pdata->src = XEXP (SET_SRC (p), 1);
+ break;
+ }
+
+ if (! REG_P (pdata->dest))
+ return false;
+
+ if (REG_P (pdata->src))
+ return true;
+
+ return allow_consts && satisfies_constraint_O (pdata->src);
+}
+
+/* Make sure that it is OK to execute LIW1 and LIW2 in parallel. GCC generated
+ the instructions with the assumption that LIW1 would be executed before LIW2
+ so we must check for overlaps between their sources and destinations. */
+
+static bool
+check_liw_constraints (struct liw_data * pliw1, struct liw_data * pliw2)
+{
+ /* Check for slot conflicts. */
+ if (pliw2->slot == pliw1->slot && pliw1->slot != LIW_EITHER)
+ return false;
+
+ /* If either operation is a compare, then "dest" is really an input; the real
+ destination is CC_REG. So these instructions need different checks. */
+
+ /* Changing "CMP ; OP" into "CMP | OP" is OK because the comparison will
+ check its values prior to any changes made by OP. */
+ if (pliw1->op == LIW_OP_CMP)
+ {
+ /* Two sequential comparisons means dead code, which ought to
+ have been eliminated given that bundling only happens with
+ optimization. We cannot bundle them in any case. */
+ gcc_assert (pliw1->op != pliw2->op);
+ return true;
+ }
+
+ /* Changing "OP ; CMP" into "OP | CMP" does not work if the value being compared
+ is the destination of OP, as the CMP will look at the old value, not the new
+ one. */
+ if (pliw2->op == LIW_OP_CMP)
+ {
+ if (REGNO (pliw2->dest) == REGNO (pliw1->dest))
+ return false;
+
+ if (REG_P (pliw2->src))
+ return REGNO (pliw2->src) != REGNO (pliw1->dest);
+
+ return true;
+ }
+
+ /* Changing "OP1 ; OP2" into "OP1 | OP2" does not work if they both write to the
+ same destination register. */
+ if (REGNO (pliw2->dest) == REGNO (pliw1->dest))
+ return false;
+
+ /* Changing "OP1 ; OP2" into "OP1 | OP2" generally does not work if the destination
+ of OP1 is the source of OP2. The exception is when OP1 is a MOVE instruction when
+ we can replace the source in OP2 with the source of OP1. */
+ if (REG_P (pliw2->src) && REGNO (pliw2->src) == REGNO (pliw1->dest))
+ {
+ if (pliw1->op == LIW_OP_MOV && REG_P (pliw1->src))
+ {
+ if (! REG_P (pliw1->src)
+ && (pliw2->op == LIW_OP_AND
+ || pliw2->op == LIW_OP_OR
+ || pliw2->op == LIW_OP_XOR))
+ return false;
+
+ pliw2->src = pliw1->src;
+ return true;
+ }
+ return false;
+ }
+
+ /* Everything else is OK. */
+ return true;
+}
+
+/* Combine pairs of insns into LIW bundles. */
+
+static void
+mn10300_bundle_liw (void)
+{
+ rtx r;
+
+ for (r = get_insns (); r != NULL_RTX; r = next_nonnote_nondebug_insn (r))
+ {
+ rtx insn1, insn2;
+ struct liw_data liw1, liw2;
+
+ insn1 = r;
+ if (! extract_bundle (insn1, & liw1))
+ continue;
+
+ insn2 = next_nonnote_nondebug_insn (insn1);
+ if (! extract_bundle (insn2, & liw2))
+ continue;
+
+ /* Check for source/destination overlap. */
+ if (! check_liw_constraints (& liw1, & liw2))
+ continue;
+
+ if (liw1.slot == LIW_OP2 || liw2.slot == LIW_OP1)
+ {
+ struct liw_data temp;
+
+ temp = liw1;
+ liw1 = liw2;
+ liw2 = temp;
+ }
+
+ delete_insn (insn2);
+
+ if (liw1.op == LIW_OP_CMP)
+ insn2 = gen_cmp_liw (liw2.dest, liw2.src, liw1.dest, liw1.src,
+ GEN_INT (liw2.op));
+ else if (liw2.op == LIW_OP_CMP)
+ insn2 = gen_liw_cmp (liw1.dest, liw1.src, liw2.dest, liw2.src,
+ GEN_INT (liw1.op));
+ else
+ insn2 = gen_liw (liw1.dest, liw2.dest, liw1.src, liw2.src,
+ GEN_INT (liw1.op), GEN_INT (liw2.op));
+
+ insn2 = emit_insn_after (insn2, insn1);
+ delete_insn (insn1);
+ r = insn2;
+ }
+}
+
+#define DUMP(reason, insn) \
+ do \
+ { \
+ if (dump_file) \
+ { \
+ fprintf (dump_file, reason "\n"); \
+ if (insn != NULL_RTX) \
+ print_rtl_single (dump_file, insn); \
+ fprintf(dump_file, "\n"); \
+ } \
+ } \
+ while (0)
+
+/* Replace the BRANCH insn with a Lcc insn that goes to LABEL.
+ Insert a SETLB insn just before LABEL. */
+
+static void
+mn10300_insert_setlb_lcc (rtx label, rtx branch)
+{
+ rtx lcc, comparison, cmp_reg;
+
+ if (LABEL_NUSES (label) > 1)
+ {
+ rtx insn;
+
+ /* This label is used both as an entry point to the loop
+ and as a loop-back point for the loop. We need to separate
+ these two functions so that the SETLB happens upon entry,
+ but the loop-back does not go to the SETLB instruction. */
+ DUMP ("Inserting SETLB insn after:", label);
+ insn = emit_insn_after (gen_setlb (), label);
+ label = gen_label_rtx ();
+ emit_label_after (label, insn);
+ DUMP ("Created new loop-back label:", label);
+ }
+ else
+ {
+ DUMP ("Inserting SETLB insn before:", label);
+ emit_insn_before (gen_setlb (), label);
+ }
+
+ comparison = XEXP (SET_SRC (PATTERN (branch)), 0);
+ cmp_reg = XEXP (comparison, 0);
+ gcc_assert (REG_P (cmp_reg));
+
+ /* If the comparison has not already been split out of the branch
+ then do so now. */
+ gcc_assert (REGNO (cmp_reg) == CC_REG);
+
+ if (GET_MODE (cmp_reg) == CC_FLOATmode)
+ lcc = gen_FLcc (comparison, label);
+ else
+ lcc = gen_Lcc (comparison, label);
+
+ lcc = emit_jump_insn_before (lcc, branch);
+ mark_jump_label (XVECEXP (PATTERN (lcc), 0, 0), lcc, 0);
+ JUMP_LABEL (lcc) = label;
+ DUMP ("Replacing branch insn...", branch);
+ DUMP ("... with Lcc insn:", lcc);
+ delete_insn (branch);
+}
+
+static bool
+mn10300_block_contains_call (struct basic_block_def * block)
+{
+ rtx insn;
+
+ FOR_BB_INSNS (block, insn)
+ if (CALL_P (insn))
+ return true;
+
+ return false;
+}
+
+static bool
+mn10300_loop_contains_call_insn (loop_p loop)
+{
+ basic_block * bbs;
+ bool result = false;
+ unsigned int i;
+
+ bbs = get_loop_body (loop);
+
+ for (i = 0; i < loop->num_nodes; i++)
+ if (mn10300_block_contains_call (bbs[i]))
+ {
+ result = true;
+ break;
+ }
+
+ free (bbs);
+ return result;
+}
+
+static void
+mn10300_scan_for_setlb_lcc (void)
+{
+ struct loops loops;
+ loop_iterator liter;
+ loop_p loop;
+
+ DUMP ("Looking for loops that can use the SETLB insn", NULL_RTX);
+
+ df_analyze ();
+ compute_bb_for_insn ();
+
+ /* Find the loops. */
+ if (flow_loops_find (& loops) < 1)
+ DUMP ("No loops found", NULL_RTX);
+ current_loops = & loops;
+
+ /* FIXME: For now we only investigate innermost loops. In practice however
+ if an inner loop is not suitable for use with the SETLB/Lcc insns, it may
+ be the case that its parent loop is suitable. Thus we should check all
+ loops, but work from the innermost outwards. */
+ FOR_EACH_LOOP (liter, loop, LI_ONLY_INNERMOST)
+ {
+ const char * reason = NULL;
+
+ /* Check to see if we can modify this loop. If we cannot
+ then set 'reason' to describe why it could not be done. */
+ if (loop->latch == NULL)
+ reason = "it contains multiple latches";
+ else if (loop->header != loop->latch)
+ /* FIXME: We could handle loops that span multiple blocks,
+ but this requires a lot more work tracking down the branches
+ that need altering, so for now keep things simple. */
+ reason = "the loop spans multiple blocks";
+ else if (mn10300_loop_contains_call_insn (loop))
+ reason = "it contains CALL insns";
+ else
+ {
+ rtx branch = BB_END (loop->latch);
+
+ gcc_assert (JUMP_P (branch));
+ if (single_set (branch) == NULL_RTX || ! any_condjump_p (branch))
+ /* We cannot optimize tablejumps and the like. */
+ /* FIXME: We could handle unconditional jumps. */
+ reason = "it is not a simple loop";
+ else
+ {
+ rtx label;
+
+ if (dump_file)
+ flow_loop_dump (loop, dump_file, NULL, 0);
+
+ label = BB_HEAD (loop->header);
+ gcc_assert (LABEL_P (label));
+
+ mn10300_insert_setlb_lcc (label, branch);
+ }
+ }
+
+ if (dump_file && reason != NULL)
+ fprintf (dump_file, "Loop starting with insn %d is not suitable because %s\n",
+ INSN_UID (BB_HEAD (loop->header)),
+ reason);
+ }
+
+#if 0 /* FIXME: We should free the storage we allocated, but
+ for some unknown reason this leads to seg-faults. */
+ FOR_EACH_LOOP (liter, loop, 0)
+ free_simple_loop_desc (loop);
+
+ flow_loops_free (current_loops);
+#endif
+
+ current_loops = NULL;
+
+ df_finish_pass (false);
+
+ DUMP ("SETLB scan complete", NULL_RTX);
+}
+
+static void
+mn10300_reorg (void)
+{
+ /* These are optimizations, so only run them if optimizing. */
+ if (TARGET_AM33 && (optimize > 0 || optimize_size))
+ {
+ if (TARGET_ALLOW_SETLB)
+ mn10300_scan_for_setlb_lcc ();
+
+ if (TARGET_ALLOW_LIW)
+ mn10300_bundle_liw ();
+ }
+}
+\f
+/* Initialize the GCC target structure. */
+
+#undef TARGET_MACHINE_DEPENDENT_REORG
+#define TARGET_MACHINE_DEPENDENT_REORG mn10300_reorg
+
+#undef TARGET_ASM_ALIGNED_HI_OP
+#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
+
+#undef TARGET_LEGITIMIZE_ADDRESS
+#define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address
+
+#undef TARGET_ADDRESS_COST
+#define TARGET_ADDRESS_COST mn10300_address_cost
+#undef TARGET_REGISTER_MOVE_COST
+#define TARGET_REGISTER_MOVE_COST mn10300_register_move_cost
+#undef TARGET_MEMORY_MOVE_COST
+#define TARGET_MEMORY_MOVE_COST mn10300_memory_move_cost
+#undef TARGET_RTX_COSTS
+#define TARGET_RTX_COSTS mn10300_rtx_costs
+
+#undef TARGET_ASM_FILE_START
+#define TARGET_ASM_FILE_START mn10300_file_start
+#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
+#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
+
+#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
+#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA mn10300_asm_output_addr_const_extra
+
+#undef TARGET_OPTION_OVERRIDE
+#define TARGET_OPTION_OVERRIDE mn10300_option_override
+
+#undef TARGET_ENCODE_SECTION_INFO
+#define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
+
+#undef TARGET_PROMOTE_PROTOTYPES
+#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
+#undef TARGET_RETURN_IN_MEMORY
+#define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory
+#undef TARGET_PASS_BY_REFERENCE
+#define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference
+#undef TARGET_CALLEE_COPIES
+#define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
+#undef TARGET_ARG_PARTIAL_BYTES
+#define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes
+#undef TARGET_FUNCTION_ARG
+#define TARGET_FUNCTION_ARG mn10300_function_arg
+#undef TARGET_FUNCTION_ARG_ADVANCE
+#define TARGET_FUNCTION_ARG_ADVANCE mn10300_function_arg_advance
+
+#undef TARGET_EXPAND_BUILTIN_SAVEREGS
+#define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs
+#undef TARGET_EXPAND_BUILTIN_VA_START
+#define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start
+
+#undef TARGET_CASE_VALUES_THRESHOLD
+#define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold
+
+#undef TARGET_LEGITIMATE_ADDRESS_P
+#define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p
+#undef TARGET_DELEGITIMIZE_ADDRESS
+#define TARGET_DELEGITIMIZE_ADDRESS mn10300_delegitimize_address
+#undef TARGET_LEGITIMATE_CONSTANT_P
+#define TARGET_LEGITIMATE_CONSTANT_P mn10300_legitimate_constant_p
+
+#undef TARGET_PREFERRED_RELOAD_CLASS
+#define TARGET_PREFERRED_RELOAD_CLASS mn10300_preferred_reload_class
+#undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
+#define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS \
+ mn10300_preferred_output_reload_class
+#undef TARGET_SECONDARY_RELOAD
+#define TARGET_SECONDARY_RELOAD mn10300_secondary_reload
+
+#undef TARGET_TRAMPOLINE_INIT
+#define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init
+
+#undef TARGET_FUNCTION_VALUE
+#define TARGET_FUNCTION_VALUE mn10300_function_value
+#undef TARGET_LIBCALL_VALUE
+#define TARGET_LIBCALL_VALUE mn10300_libcall_value
+
+#undef TARGET_ASM_OUTPUT_MI_THUNK
+#define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk
+#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
+#define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk
+
+#undef TARGET_SCHED_ADJUST_COST
+#define TARGET_SCHED_ADJUST_COST mn10300_adjust_sched_cost
+
+#undef TARGET_CONDITIONAL_REGISTER_USAGE
+#define TARGET_CONDITIONAL_REGISTER_USAGE mn10300_conditional_register_usage
+
+#undef TARGET_MD_ASM_CLOBBERS
+#define TARGET_MD_ASM_CLOBBERS mn10300_md_asm_clobbers
+
+#undef TARGET_FLAGS_REGNUM
+#define TARGET_FLAGS_REGNUM CC_REG
+
+struct gcc_target targetm = TARGET_INITIALIZER;
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