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Canonicalize mips nmadd/nmsub patterns.
[pf3gnuchains/gcc-fork.git] / gcc / config / mips / mips.md
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 3ffa7f7..8a6440e 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -53,6 +53,8 @@
    (UNSPEC_ADDRESS_FIRST       100)
 
    (FAKE_CALL_REGNO            79)])
+
+(include "predicates.md")
 \f
 ;; ....................
 ;;
@@ -364,7 +366,7 @@
   [(set_attr "type"    "trap")])
 
 (define_expand "conditional_trap"
-  [(trap_if (match_operator 0 "cmp_op"
+  [(trap_if (match_operator 0 "comparison_operator"
                            [(match_dup 2) (match_dup 3)])
            (match_operand 1 "const_int_operand"))]
   "ISA_HAS_COND_TRAP"
@@ -379,7 +381,7 @@
 })
 
 (define_insn ""
-  [(trap_if (match_operator 0 "trap_cmp_op"
+  [(trap_if (match_operator 0 "trap_comparison_operator"
                             [(match_operand:SI 1 "reg_or_0_operand" "dJ")
                              (match_operand:SI 2 "arith_operand" "dI")])
            (const_int 0))]
@@ -388,7 +390,7 @@
   [(set_attr "type"    "trap")])
 
 (define_insn ""
-  [(trap_if (match_operator 0 "trap_cmp_op"
+  [(trap_if (match_operator 0 "trap_comparison_operator"
                             [(match_operand:DI 1 "reg_or_0_operand" "dJ")
                              (match_operand:DI 2 "arith_operand" "dI")])
            (const_int 0))]
@@ -446,7 +448,7 @@
 (define_insn ""
   [(set (reg:SI 29)
        (plus:SI (reg:SI 29)
-                (match_operand:SI 0 "small_int" "I")))]
+                (match_operand:SI 0 "const_arith_operand" "")))]
   "TARGET_MIPS16"
   "addu\t%$,%$,%0"
   [(set_attr "type"    "arith")
@@ -458,7 +460,7 @@
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d")
        (plus:SI (reg:SI 29)
-                (match_operand:SI 1 "small_int" "I")))]
+                (match_operand:SI 1 "const_arith_operand" "")))]
   "TARGET_MIPS16"
   "addu\t%0,%$,%1"
   [(set_attr "type"    "arith")
@@ -581,7 +583,7 @@
 (define_insn ""
   [(set (reg:DI 29)
        (plus:DI (reg:DI 29)
-                (match_operand:DI 0 "small_int" "I")))]
+                (match_operand:DI 0 "const_arith_operand" "")))]
   "TARGET_MIPS16 && TARGET_64BIT"
   "daddu\t%$,%$,%0"
   [(set_attr "type"    "arith")
@@ -593,7 +595,7 @@
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=d")
        (plus:DI (reg:DI 29)
-                (match_operand:DI 1 "small_int" "I")))]
+                (match_operand:DI 1 "const_arith_operand" "")))]
   "TARGET_MIPS16 && TARGET_64BIT"
   "daddu\t%0,%$,%1"
   [(set_attr "type"    "arith")
@@ -1449,8 +1451,7 @@
        (mult:DI
           (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
           (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
-   (clobber (match_scratch:DI 3 "=l"))
-   (clobber (match_scratch:DI 4 "=h"))]
+   (clobber (match_scratch:DI 3 "=x"))]
   "!TARGET_64BIT && TARGET_FIX_R4000"
   "mult\t%1,%2\;mflo\t%L0;mfhi\t%M0"
   [(set_attr "type"    "imul")
@@ -1567,8 +1568,7 @@
        (mult:DI
           (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
           (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))
-   (clobber (match_scratch:DI 3 "=l"))
-   (clobber (match_scratch:DI 4 "=h"))]
+   (clobber (match_scratch:DI 3 "=x"))]
   "!TARGET_64BIT && TARGET_FIX_R4000"
   "multu\t%1,%2\;mflo\t%L0;mfhi\t%M0"
   [(set_attr "type"    "imul")
@@ -1904,7 +1904,19 @@
        (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
                                  (match_operand:DF 2 "register_operand" "f"))
                         (match_operand:DF 3 "register_operand" "f"))))]
-  "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
+  "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+   && TARGET_FUSED_MADD && HONOR_SIGNED_ZEROS (DFmode)"
+  "nmadd.d\t%0,%3,%1,%2"
+  [(set_attr "type"    "fmadd")
+   (set_attr "mode"    "DF")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=f")
+       (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "f"))
+                                  (match_operand:DF 2 "register_operand" "f"))
+                 (match_operand:DF 3 "register_operand" "f")))]
+  "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+   && TARGET_FUSED_MADD && !HONOR_SIGNED_ZEROS (DFmode)"
   "nmadd.d\t%0,%3,%1,%2"
   [(set_attr "type"    "fmadd")
    (set_attr "mode"    "DF")])
@@ -1914,27 +1926,63 @@
        (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
                                  (match_operand:SF 2 "register_operand" "f"))
                         (match_operand:SF 3 "register_operand" "f"))))]
-  "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+  "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD
+   && HONOR_SIGNED_ZEROS (SFmode)"
+  "nmadd.s\t%0,%3,%1,%2"
+  [(set_attr "type"    "fmadd")
+   (set_attr "mode"    "SF")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=f")
+       (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
+                          (match_operand:SF 2 "register_operand" "f"))
+                 (match_operand:SF 3 "register_operand" "f")))]
+  "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD
+   && !HONOR_SIGNED_ZEROS (SFmode)"
   "nmadd.s\t%0,%3,%1,%2"
   [(set_attr "type"    "fmadd")
    (set_attr "mode"    "SF")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
+       (neg:DF (minus:DF (mult:DF (match_operand:DF 2 "register_operand" "f")
+                                  (match_operand:DF 3 "register_operand" "f"))
+                         (match_operand:DF 1 "register_operand" "f"))))]
+  "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+   && TARGET_FUSED_MADD && HONOR_SIGNED_ZEROS (DFmode)"
+  "nmsub.d\t%0,%1,%2,%3"
+  [(set_attr "type"    "fmadd")
+   (set_attr "mode"    "DF")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=f")
        (minus:DF (match_operand:DF 1 "register_operand" "f")
                  (mult:DF (match_operand:DF 2 "register_operand" "f")
                           (match_operand:DF 3 "register_operand" "f"))))]
-  "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
+  "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+   && TARGET_FUSED_MADD && !HONOR_SIGNED_ZEROS (DFmode)"
   "nmsub.d\t%0,%1,%2,%3"
   [(set_attr "type"    "fmadd")
    (set_attr "mode"    "DF")])
 
 (define_insn ""
   [(set (match_operand:SF 0 "register_operand" "=f")
+       (neg:SF (minus:SF (mult:SF (match_operand:SF 2 "register_operand" "f")
+                                  (match_operand:SF 3 "register_operand" "f"))
+                         (match_operand:SF 1 "register_operand" "f"))))]
+  "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD
+   && HONOR_SIGNED_ZEROS (SFmode)"
+  "nmsub.s\t%0,%1,%2,%3"
+  [(set_attr "type"    "fmadd")
+   (set_attr "mode"    "SF")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=f")
        (minus:SF (match_operand:SF 1 "register_operand" "f")
                  (mult:SF (match_operand:SF 2 "register_operand" "f")
                           (match_operand:SF 3 "register_operand" "f"))))]
-  "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+  "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD
+   && !HONOR_SIGNED_ZEROS (SFmode)"
   "nmsub.s\t%0,%1,%2,%3"
   [(set_attr "type"    "fmadd")
    (set_attr "mode"    "SF")])
@@ -1949,11 +1997,11 @@
 
 (define_expand "divdf3"
   [(set (match_operand:DF 0 "register_operand")
-       (div:DF (match_operand:DF 1 "reg_or_const_float_1_operand")
+       (div:DF (match_operand:DF 1 "reg_or_1_operand")
                (match_operand:DF 2 "register_operand")))]
   "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
 {
-  if (const_float_1_operand (operands[1], DFmode))
+  if (const_1_operand (operands[1], DFmode))
     if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
       operands[1] = force_reg (DFmode, operands[1]);
 })
@@ -1999,11 +2047,11 @@
 ;; precision is OK (i.e., flag_unsafe_math_optimizations is set).
 (define_expand "divsf3"
   [(set (match_operand:SF 0 "register_operand")
-       (div:SF (match_operand:SF 1 "reg_or_const_float_1_operand")
+       (div:SF (match_operand:SF 1 "reg_or_1_operand")
                (match_operand:SF 2 "register_operand")))]
   "TARGET_HARD_FLOAT && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)"
 {
-  if (const_float_1_operand (operands[1], SFmode))
+  if (const_1_operand (operands[1], SFmode))
     if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
       operands[1] = force_reg (SFmode, operands[1]);
 })
@@ -2035,7 +2083,7 @@
 ;; "divdf3" comment for details).
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
-       (div:DF (match_operand:DF 1 "const_float_1_operand" "")
+       (div:DF (match_operand:DF 1 "const_1_operand" "")
                (match_operand:DF 2 "register_operand" "f")))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
 {
@@ -2055,7 +2103,7 @@
 ;; "divdf3" comment for details).
 (define_insn ""
   [(set (match_operand:SF 0 "register_operand" "=f")
-       (div:SF (match_operand:SF 1 "const_float_1_operand" "")
+       (div:SF (match_operand:SF 1 "const_1_operand" "")
                (match_operand:SF 2 "register_operand" "f")))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
 {
@@ -2170,7 +2218,7 @@
 ;; "divdf3" comment for details).
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
-       (div:DF (match_operand:DF 1 "const_float_1_operand" "")
+       (div:DF (match_operand:DF 1 "const_1_operand" "")
                (sqrt:DF (match_operand:DF 2 "register_operand" "f"))))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
 {
@@ -2190,7 +2238,7 @@
 ;; "divdf3" comment for details).
 (define_insn ""
   [(set (match_operand:SF 0 "register_operand" "=f")
-       (div:SF (match_operand:SF 1 "const_float_1_operand" "")
+       (div:SF (match_operand:SF 1 "const_1_operand" "")
                (sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
 {
@@ -2205,6 +2253,46 @@
         (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
                       (const_int 8)
                       (const_int 4)))])
+
+;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
+;; "divdf3" comment for details).
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=f")
+       (sqrt:DF (div:DF (match_operand:DF 1 "const_1_operand" "")
+                        (match_operand:DF 2 "register_operand" "f"))))]
+  "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
+{
+  if (TARGET_FIX_SB1)
+    return "rsqrt.d\t%0,%2\;mov.d\t%0,%0";
+  else
+    return "rsqrt.d\t%0,%2";
+}
+  [(set_attr "type"    "frsqrt")
+   (set_attr "mode"    "DF")
+   (set (attr "length")
+        (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+                      (const_int 8)
+                      (const_int 4)))])
+
+;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
+;; "divdf3" comment for details).
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=f")
+       (sqrt:SF (div:SF (match_operand:SF 1 "const_1_operand" "")
+                        (match_operand:SF 2 "register_operand" "f"))))]
+  "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
+{
+  if (TARGET_FIX_SB1)
+    return "rsqrt.s\t%0,%2\;mov.s\t%0,%0";
+  else
+    return "rsqrt.s\t%0,%2";
+}
+  [(set_attr "type"    "frsqrt")
+   (set_attr "mode"    "SF")
+   (set (attr "length")
+        (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+                      (const_int 8)
+                      (const_int 4)))])
 \f
 ;;
 ;;  ....................
@@ -2745,8 +2833,9 @@ dsrl\t%3,%3,1\n\
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d")
-        (truncate:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
-                                  (match_operand:DI 2 "small_int" "I"))))]
+        (truncate:SI
+         (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
+                       (match_operand:DI 2 "const_arith_operand" ""))))]
   "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
   "dsra\t%0,%1,%2"
   [(set_attr "type" "shift")
@@ -4247,7 +4336,7 @@ dsrl\t%3,%3,1\n\
 ;; into a GPR takes a single movcc, moving elsewhere takes
 ;; two.  We can leave these cases to the generic reload code.
 (define_expand "reload_incc"
-  [(set (match_operand:CC 0 "fcc_register_operand" "=z")
+  [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
        (match_operand:CC 1 "general_operand" ""))
    (clobber (match_operand:TF 2 "register_operand" "=&f"))]
   "ISA_HAS_8CC && TARGET_HARD_FLOAT"
@@ -4257,7 +4346,7 @@ dsrl\t%3,%3,1\n\
 })
 
 (define_expand "reload_outcc"
-  [(set (match_operand:CC 0 "fcc_register_operand" "=z")
+  [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
        (match_operand:CC 1 "register_operand" ""))
    (clobber (match_operand:TF 2 "register_operand" "=&f"))]
   "ISA_HAS_8CC && TARGET_HARD_FLOAT"
@@ -4789,16 +4878,21 @@ dsrl\t%3,%3,1\n\
    (set_attr "mode"    "none")
    (set_attr "length"  "0")])
 
-;; Emit a .cprestore directive, which expands to a single store instruction.
-;; Note that we continue to use .cprestore for explicit reloc code so that
-;; jals inside inlines asms will work correctly.
+;; Emit a .cprestore directive, which normally expands to a single store
+;; instruction.  Note that we continue to use .cprestore for explicit reloc
+;; code so that jals inside inline asms will work correctly.
 (define_insn "cprestore"
-  [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
+  [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")]
                    UNSPEC_CPRESTORE)]
   ""
-  ".cprestore\t%0"
+{
+  if (set_nomacro && which_alternative == 1)
+    return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
+  else
+    return ".cprestore\t%0";
+}
   [(set_attr "type" "store")
-   (set_attr "length" "4")])
+   (set_attr "length" "4,12")])
 \f
 ;; Block moves, see mips.c for more details.
 ;; Argument 0 is the destination
@@ -5454,7 +5548,7 @@ dsrl\t%3,%3,1\n\
 (define_insn "branch_fp"
   [(set (pc)
         (if_then_else
-         (match_operator:CC 0 "cmp_op"
+         (match_operator:CC 0 "comparison_operator"
                             [(match_operand:CC 2 "register_operand" "z")
                             (const_int 0)])
          (label_ref (match_operand 1 "" ""))
@@ -5474,7 +5568,7 @@ dsrl\t%3,%3,1\n\
 (define_insn "branch_fp_inverted"
   [(set (pc)
         (if_then_else
-         (match_operator:CC 0 "cmp_op"
+         (match_operator:CC 0 "comparison_operator"
                             [(match_operand:CC 2 "register_operand" "z")
                             (const_int 0)])
          (pc)
@@ -5496,7 +5590,7 @@ dsrl\t%3,%3,1\n\
 (define_insn "branch_zero"
   [(set (pc)
        (if_then_else
-         (match_operator:SI 0 "cmp_op"
+         (match_operator:SI 0 "comparison_operator"
                            [(match_operand:SI 2 "register_operand" "d")
                             (const_int 0)])
         (label_ref (match_operand 1 "" ""))
@@ -5516,7 +5610,7 @@ dsrl\t%3,%3,1\n\
 (define_insn "branch_zero_inverted"
   [(set (pc)
        (if_then_else
-         (match_operator:SI 0 "cmp_op"
+         (match_operator:SI 0 "comparison_operator"
                            [(match_operand:SI 2 "register_operand" "d")
                             (const_int 0)])
         (pc)
@@ -5536,7 +5630,7 @@ dsrl\t%3,%3,1\n\
 (define_insn "branch_zero_di"
   [(set (pc)
        (if_then_else
-         (match_operator:DI 0 "cmp_op"
+         (match_operator:DI 0 "comparison_operator"
                            [(match_operand:DI 2 "register_operand" "d")
                             (const_int 0)])
         (label_ref (match_operand 1 "" ""))
@@ -5556,7 +5650,7 @@ dsrl\t%3,%3,1\n\
 (define_insn "branch_zero_di_inverted"
   [(set (pc)
        (if_then_else
-         (match_operator:DI 0 "cmp_op"
+         (match_operator:DI 0 "comparison_operator"
                            [(match_operand:DI 2 "register_operand" "d")
                             (const_int 0)])
         (pc)
@@ -5578,7 +5672,7 @@ dsrl\t%3,%3,1\n\
 (define_insn "branch_equality"
   [(set (pc)
        (if_then_else
-         (match_operator:SI 0 "equality_op"
+         (match_operator:SI 0 "equality_operator"
                            [(match_operand:SI 2 "register_operand" "d")
                             (match_operand:SI 3 "register_operand" "d")])
          (label_ref (match_operand 1 "" ""))
@@ -5598,7 +5692,7 @@ dsrl\t%3,%3,1\n\
 (define_insn "branch_equality_di"
   [(set (pc)
        (if_then_else
-         (match_operator:DI 0 "equality_op"
+         (match_operator:DI 0 "equality_operator"
                            [(match_operand:DI 2 "register_operand" "d")
                             (match_operand:DI 3 "register_operand" "d")])
         (label_ref (match_operand 1 "" ""))
@@ -5618,7 +5712,7 @@ dsrl\t%3,%3,1\n\
 (define_insn "branch_equality_inverted"
   [(set (pc)
        (if_then_else
-         (match_operator:SI 0 "equality_op"
+         (match_operator:SI 0 "equality_operator"
                            [(match_operand:SI 2 "register_operand" "d")
                             (match_operand:SI 3 "register_operand" "d")])
          (pc)
@@ -5638,7 +5732,7 @@ dsrl\t%3,%3,1\n\
 (define_insn "branch_equality_di_inverted"
   [(set (pc)
        (if_then_else
-         (match_operator:DI 0 "equality_op"
+         (match_operator:DI 0 "equality_operator"
                            [(match_operand:DI 2 "register_operand" "d")
                             (match_operand:DI 3 "register_operand" "d")])
         (pc)
@@ -5659,9 +5753,10 @@ dsrl\t%3,%3,1\n\
 
 (define_insn ""
   [(set (pc)
-       (if_then_else (match_operator:SI 0 "equality_op"
-                                        [(match_operand:SI 1 "register_operand" "d,t")
-                                         (const_int 0)])
+       (if_then_else
+        (match_operator:SI 0 "equality_operator"
+                           [(match_operand:SI 1 "register_operand" "d,t")
+                            (const_int 0)])
        (match_operand 2 "pc_or_label_operand" "")
        (match_operand 3 "pc_or_label_operand" "")))]
   "TARGET_MIPS16"
@@ -5687,9 +5782,10 @@ dsrl\t%3,%3,1\n\
 
 (define_insn ""
   [(set (pc)
-       (if_then_else (match_operator:DI 0 "equality_op"
-                                        [(match_operand:DI 1 "register_operand" "d,t")
-                                         (const_int 0)])
+       (if_then_else
+        (match_operator:DI 0 "equality_operator"
+                           [(match_operand:DI 1 "register_operand" "d,t")
+                            (const_int 0)])
        (match_operand 2 "pc_or_label_operand" "")
        (match_operand 3 "pc_or_label_operand" "")))]
   "TARGET_MIPS16"
@@ -6862,17 +6958,19 @@ dsrl\t%3,%3,1\n\
   DONE;
 })
 
-(define_insn "exception_receiver"
+(define_insn_and_split "exception_receiver"
   [(set (reg:SI 28)
        (unspec_volatile:SI [(const_int 0)] UNSPEC_EH_RECEIVER))]
   "TARGET_ABICALLS && TARGET_OLDABI"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
 {
-  operands[0] = pic_offset_table_rtx;
-  operands[1] = mips_gp_save_slot ();
-  return mips_output_move (operands[0], operands[1]);
+  mips_restore_gp ();
+  DONE;
 }
   [(set_attr "type"   "load")
-   (set_attr "length" "8")])
+   (set_attr "length" "12")])
 \f
 ;;
 ;;  ....................
@@ -7043,7 +7141,7 @@ dsrl\t%3,%3,1\n\
 {
   emit_call_insn (gen_call_split (operands[0], operands[1]));
   if (!find_reg_note (operands[2], REG_NORETURN, 0))
-    emit_move_insn (pic_offset_table_rtx, mips_gp_save_slot ());
+    mips_restore_gp ();
   DONE;
 }
   [(set_attr "jal" "indirect,direct")
@@ -7084,7 +7182,7 @@ dsrl\t%3,%3,1\n\
   emit_call_insn (gen_call_value_split (operands[0], operands[1],
                                        operands[2]));
   if (!find_reg_note (operands[3], REG_NORETURN, 0))
-    emit_move_insn (pic_offset_table_rtx, mips_gp_save_slot ());
+    mips_restore_gp ();
   DONE;
 }
   [(set_attr "jal" "indirect,direct")
@@ -7117,7 +7215,7 @@ dsrl\t%3,%3,1\n\
   emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
                                                 operands[2], operands[3]));
   if (!find_reg_note (operands[4], REG_NORETURN, 0))
-    emit_move_insn (pic_offset_table_rtx, mips_gp_save_slot ());
+    mips_restore_gp ();
   DONE;
 }
   [(set_attr "jal" "indirect,direct")
@@ -7260,9 +7358,9 @@ dsrl\t%3,%3,1\n\
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d,d")
        (if_then_else:SI
-        (match_operator 4 "equality_op"
-                        [(match_operand:SI 1 "register_operand" "d,d")
-                         (const_int 0)])
+        (match_operator:SI 4 "equality_operator"
+                           [(match_operand:SI 1 "register_operand" "d,d")
+                            (const_int 0)])
         (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
         (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
   "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
@@ -7275,9 +7373,9 @@ dsrl\t%3,%3,1\n\
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d,d")
        (if_then_else:SI
-        (match_operator 4 "equality_op"
-                        [(match_operand:DI 1 "register_operand" "d,d")
-                         (const_int 0)])
+        (match_operator:DI 4 "equality_operator"
+                           [(match_operand:DI 1 "register_operand" "d,d")
+                            (const_int 0)])
         (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
         (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
   "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
@@ -7290,10 +7388,9 @@ dsrl\t%3,%3,1\n\
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d,d")
        (if_then_else:SI
-        (match_operator 3 "equality_op" [(match_operand:CC 4
-                                                           "register_operand"
-                                                           "z,z")
-                                         (const_int 0)])
+        (match_operator:CC 3 "equality_operator"
+                           [(match_operand:CC 4 "register_operand" "z,z")
+                            (const_int 0)])
         (match_operand:SI 1 "reg_or_0_operand" "dJ,0")
         (match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
@@ -7306,9 +7403,9 @@ dsrl\t%3,%3,1\n\
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=d,d")
        (if_then_else:DI
-        (match_operator 4 "equality_op"
-                        [(match_operand:SI 1 "register_operand" "d,d")
-                         (const_int 0)])
+        (match_operator:SI 4 "equality_operator"
+                           [(match_operand:SI 1 "register_operand" "d,d")
+                            (const_int 0)])
         (match_operand:DI 2 "reg_or_0_operand" "dJ,0")
         (match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
   "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
@@ -7321,9 +7418,9 @@ dsrl\t%3,%3,1\n\
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=d,d")
        (if_then_else:DI
-        (match_operator 4 "equality_op"
-                        [(match_operand:DI 1 "register_operand" "d,d")
-                         (const_int 0)])
+        (match_operator:DI 4 "equality_operator"
+                           [(match_operand:DI 1 "register_operand" "d,d")
+                            (const_int 0)])
         (match_operand:DI 2 "reg_or_0_operand" "dJ,0")
         (match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
   "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
@@ -7336,10 +7433,9 @@ dsrl\t%3,%3,1\n\
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=d,d")
        (if_then_else:DI
-        (match_operator 3 "equality_op" [(match_operand:CC 4
-                                                           "register_operand"
-                                                           "z,z")
-                                         (const_int 0)])
+        (match_operator:CC 3 "equality_operator"
+                           [(match_operand:CC 4 "register_operand" "z,z")
+                            (const_int 0)])
         (match_operand:DI 1 "reg_or_0_operand" "dJ,0")
         (match_operand:DI 2 "reg_or_0_operand" "0,dJ")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_64BIT"
@@ -7352,9 +7448,9 @@ dsrl\t%3,%3,1\n\
 (define_insn ""
   [(set (match_operand:SF 0 "register_operand" "=f,f")
        (if_then_else:SF
-        (match_operator 4 "equality_op"
-                        [(match_operand:SI 1 "register_operand" "d,d")
-                         (const_int 0)])
+        (match_operator:SI 4 "equality_operator"
+                           [(match_operand:SI 1 "register_operand" "d,d")
+                            (const_int 0)])
         (match_operand:SF 2 "register_operand" "f,0")
         (match_operand:SF 3 "register_operand" "0,f")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
@@ -7367,9 +7463,9 @@ dsrl\t%3,%3,1\n\
 (define_insn ""
   [(set (match_operand:SF 0 "register_operand" "=f,f")
        (if_then_else:SF
-        (match_operator 4 "equality_op"
-                        [(match_operand:DI 1 "register_operand" "d,d")
-                         (const_int 0)])
+        (match_operator:DI 4 "equality_operator"
+                           [(match_operand:DI 1 "register_operand" "d,d")
+                            (const_int 0)])
         (match_operand:SF 2 "register_operand" "f,0")
         (match_operand:SF 3 "register_operand" "0,f")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
@@ -7382,10 +7478,9 @@ dsrl\t%3,%3,1\n\
 (define_insn ""
   [(set (match_operand:SF 0 "register_operand" "=f,f")
        (if_then_else:SF
-        (match_operator 3 "equality_op" [(match_operand:CC 4
-                                                           "register_operand"
-                                                           "z,z")
-                                         (const_int 0)])
+        (match_operator:CC 3 "equality_operator"
+                           [(match_operand:CC 4 "register_operand" "z,z")
+                            (const_int 0)])
         (match_operand:SF 1 "register_operand" "f,0")
         (match_operand:SF 2 "register_operand" "0,f")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
@@ -7398,9 +7493,9 @@ dsrl\t%3,%3,1\n\
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f,f")
        (if_then_else:DF
-        (match_operator 4 "equality_op"
-                        [(match_operand:SI 1 "register_operand" "d,d")
-                         (const_int 0)])
+        (match_operator:SI 4 "equality_operator"
+                           [(match_operand:SI 1 "register_operand" "d,d")
+                            (const_int 0)])
         (match_operand:DF 2 "register_operand" "f,0")
         (match_operand:DF 3 "register_operand" "0,f")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
@@ -7413,9 +7508,9 @@ dsrl\t%3,%3,1\n\
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f,f")
        (if_then_else:DF
-        (match_operator 4 "equality_op"
-                        [(match_operand:DI 1 "register_operand" "d,d")
-                         (const_int 0)])
+        (match_operator:DI 4 "equality_operator"
+                           [(match_operand:DI 1 "register_operand" "d,d")
+                            (const_int 0)])
         (match_operand:DF 2 "register_operand" "f,0")
         (match_operand:DF 3 "register_operand" "0,f")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
@@ -7428,10 +7523,9 @@ dsrl\t%3,%3,1\n\
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f,f")
        (if_then_else:DF
-        (match_operator 3 "equality_op" [(match_operand:CC 4
-                                                           "register_operand"
-                                                           "z,z")
-                                         (const_int 0)])
+        (match_operator:CC 3 "equality_operator"
+                           [(match_operand:CC 4 "register_operand" "z,z")
+                            (const_int 0)])
         (match_operand:DF 1 "register_operand" "f,0")
         (match_operand:DF 2 "register_operand" "0,f")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
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