;; Mips.md Machine Description for MIPS based processors
;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-;; 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
+;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
+;; Free Software Foundation, Inc.
;; Contributed by A. Lichnewsky, lich@inria.inria.fr
;; Changes by Michael Meissner, meissner@osf.org
-;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
+;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
;; Brendan Eich, brendan@microunity.com.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
+;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;; GCC is distributed in the hope that it will be useful,
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
(define_constants
[(UNSPEC_LOAD_DF_LOW 0)
(UNSPEC_GET_FNADDR 3)
(UNSPEC_BLOCKAGE 4)
(UNSPEC_CPRESTORE 5)
- (UNSPEC_EH_RECEIVER 6)
+ (UNSPEC_NONLOCAL_GOTO_RECEIVER 6)
(UNSPEC_EH_RETURN 7)
(UNSPEC_CONSTTABLE_INT 8)
(UNSPEC_CONSTTABLE_FLOAT 9)
(UNSPEC_LOAD_GOT 24)
(UNSPEC_GP 25)
(UNSPEC_MFHILO 26)
-
+ (UNSPEC_TLS_LDM 27)
+ (UNSPEC_TLS_GET_TP 28)
+ (UNSPEC_MFHC1 31)
+ (UNSPEC_MTHC1 32)
+ (UNSPEC_CLEAR_HAZARD 33)
+ (UNSPEC_RDHWR 34)
+ (UNSPEC_SYNCI 35)
+ (UNSPEC_SYNC 36)
+ (UNSPEC_COMPARE_AND_SWAP 37)
+ (UNSPEC_SYNC_OLD_OP 38)
+ (UNSPEC_SYNC_NEW_OP 39)
+ (UNSPEC_SYNC_EXCHANGE 40)
+
(UNSPEC_ADDRESS_FIRST 100)
(FAKE_CALL_REGNO 79)
(UNSPEC_CVT_PW_PS 205)
(UNSPEC_CVT_PS_PW 206)
(UNSPEC_MULR_PS 207)
-
- (UNSPEC_RSQRT1 208)
- (UNSPEC_RSQRT2 209)
- (UNSPEC_RECIP1 210)
- (UNSPEC_RECIP2 211)
+ (UNSPEC_ABS_PS 208)
+
+ (UNSPEC_RSQRT1 209)
+ (UNSPEC_RSQRT2 210)
+ (UNSPEC_RECIP1 211)
+ (UNSPEC_RECIP2 212)
+ (UNSPEC_SINGLE_CC 213)
+ (UNSPEC_SCC 214)
+
+ ;; MIPS DSP ASE Revision 0.98 3/24/2005
+ (UNSPEC_ADDQ 300)
+ (UNSPEC_ADDQ_S 301)
+ (UNSPEC_SUBQ 302)
+ (UNSPEC_SUBQ_S 303)
+ (UNSPEC_ADDSC 304)
+ (UNSPEC_ADDWC 305)
+ (UNSPEC_MODSUB 306)
+ (UNSPEC_RADDU_W_QB 307)
+ (UNSPEC_ABSQ_S 308)
+ (UNSPEC_PRECRQ_QB_PH 309)
+ (UNSPEC_PRECRQ_PH_W 310)
+ (UNSPEC_PRECRQ_RS_PH_W 311)
+ (UNSPEC_PRECRQU_S_QB_PH 312)
+ (UNSPEC_PRECEQ_W_PHL 313)
+ (UNSPEC_PRECEQ_W_PHR 314)
+ (UNSPEC_PRECEQU_PH_QBL 315)
+ (UNSPEC_PRECEQU_PH_QBR 316)
+ (UNSPEC_PRECEQU_PH_QBLA 317)
+ (UNSPEC_PRECEQU_PH_QBRA 318)
+ (UNSPEC_PRECEU_PH_QBL 319)
+ (UNSPEC_PRECEU_PH_QBR 320)
+ (UNSPEC_PRECEU_PH_QBLA 321)
+ (UNSPEC_PRECEU_PH_QBRA 322)
+ (UNSPEC_SHLL 323)
+ (UNSPEC_SHLL_S 324)
+ (UNSPEC_SHRL_QB 325)
+ (UNSPEC_SHRA_PH 326)
+ (UNSPEC_SHRA_R 327)
+ (UNSPEC_MULEU_S_PH_QBL 328)
+ (UNSPEC_MULEU_S_PH_QBR 329)
+ (UNSPEC_MULQ_RS_PH 330)
+ (UNSPEC_MULEQ_S_W_PHL 331)
+ (UNSPEC_MULEQ_S_W_PHR 332)
+ (UNSPEC_DPAU_H_QBL 333)
+ (UNSPEC_DPAU_H_QBR 334)
+ (UNSPEC_DPSU_H_QBL 335)
+ (UNSPEC_DPSU_H_QBR 336)
+ (UNSPEC_DPAQ_S_W_PH 337)
+ (UNSPEC_DPSQ_S_W_PH 338)
+ (UNSPEC_MULSAQ_S_W_PH 339)
+ (UNSPEC_DPAQ_SA_L_W 340)
+ (UNSPEC_DPSQ_SA_L_W 341)
+ (UNSPEC_MAQ_S_W_PHL 342)
+ (UNSPEC_MAQ_S_W_PHR 343)
+ (UNSPEC_MAQ_SA_W_PHL 344)
+ (UNSPEC_MAQ_SA_W_PHR 345)
+ (UNSPEC_BITREV 346)
+ (UNSPEC_INSV 347)
+ (UNSPEC_REPL_QB 348)
+ (UNSPEC_REPL_PH 349)
+ (UNSPEC_CMP_EQ 350)
+ (UNSPEC_CMP_LT 351)
+ (UNSPEC_CMP_LE 352)
+ (UNSPEC_CMPGU_EQ_QB 353)
+ (UNSPEC_CMPGU_LT_QB 354)
+ (UNSPEC_CMPGU_LE_QB 355)
+ (UNSPEC_PICK 356)
+ (UNSPEC_PACKRL_PH 357)
+ (UNSPEC_EXTR_W 358)
+ (UNSPEC_EXTR_R_W 359)
+ (UNSPEC_EXTR_RS_W 360)
+ (UNSPEC_EXTR_S_H 361)
+ (UNSPEC_EXTP 362)
+ (UNSPEC_EXTPDP 363)
+ (UNSPEC_SHILO 364)
+ (UNSPEC_MTHLIP 365)
+ (UNSPEC_WRDSP 366)
+ (UNSPEC_RDDSP 367)
+
+ ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
+ (UNSPEC_ABSQ_S_QB 400)
+ (UNSPEC_ADDU_PH 401)
+ (UNSPEC_ADDU_S_PH 402)
+ (UNSPEC_ADDUH_QB 403)
+ (UNSPEC_ADDUH_R_QB 404)
+ (UNSPEC_APPEND 405)
+ (UNSPEC_BALIGN 406)
+ (UNSPEC_CMPGDU_EQ_QB 407)
+ (UNSPEC_CMPGDU_LT_QB 408)
+ (UNSPEC_CMPGDU_LE_QB 409)
+ (UNSPEC_DPA_W_PH 410)
+ (UNSPEC_DPS_W_PH 411)
+ (UNSPEC_MADD 412)
+ (UNSPEC_MADDU 413)
+ (UNSPEC_MSUB 414)
+ (UNSPEC_MSUBU 415)
+ (UNSPEC_MUL_PH 416)
+ (UNSPEC_MUL_S_PH 417)
+ (UNSPEC_MULQ_RS_W 418)
+ (UNSPEC_MULQ_S_PH 419)
+ (UNSPEC_MULQ_S_W 420)
+ (UNSPEC_MULSA_W_PH 421)
+ (UNSPEC_MULT 422)
+ (UNSPEC_MULTU 423)
+ (UNSPEC_PRECR_QB_PH 424)
+ (UNSPEC_PRECR_SRA_PH_W 425)
+ (UNSPEC_PRECR_SRA_R_PH_W 426)
+ (UNSPEC_PREPEND 427)
+ (UNSPEC_SHRA_QB 428)
+ (UNSPEC_SHRA_R_QB 429)
+ (UNSPEC_SHRL_PH 430)
+ (UNSPEC_SUBU_PH 431)
+ (UNSPEC_SUBU_S_PH 432)
+ (UNSPEC_SUBUH_QB 433)
+ (UNSPEC_SUBUH_R_QB 434)
+ (UNSPEC_ADDQH_PH 435)
+ (UNSPEC_ADDQH_R_PH 436)
+ (UNSPEC_ADDQH_W 437)
+ (UNSPEC_ADDQH_R_W 438)
+ (UNSPEC_SUBQH_PH 439)
+ (UNSPEC_SUBQH_R_PH 440)
+ (UNSPEC_SUBQH_W 441)
+ (UNSPEC_SUBQH_R_W 442)
+ (UNSPEC_DPAX_W_PH 443)
+ (UNSPEC_DPSX_W_PH 444)
+ (UNSPEC_DPAQX_S_W_PH 445)
+ (UNSPEC_DPAQX_SA_W_PH 446)
+ (UNSPEC_DPSQX_S_W_PH 447)
+ (UNSPEC_DPSQX_SA_W_PH 448)
]
)
(include "predicates.md")
+(include "constraints.md")
\f
;; ....................
;;
;; This attribute is YES if the instruction is a jal macro (not a
;; real jal instruction).
;;
-;; jal is always a macro in SVR4 PIC since it includes an instruction to
-;; restore $gp. Direct jals are also macros in NewABI PIC since they
-;; load the target address into $25.
+;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
+;; an instruction to restore $gp. Direct jals are also macros for
+;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
+;; the target address into a register.
(define_attr "jal_macro" "no,yes"
(cond [(eq_attr "jal" "direct")
- (symbol_ref "TARGET_ABICALLS != 0")
+ (symbol_ref "TARGET_CALL_CLOBBERED_GP
+ || (flag_pic && !TARGET_ABSOLUTE_ABICALLS)")
(eq_attr "jal" "indirect")
- (symbol_ref "(TARGET_ABICALLS && !TARGET_NEWABI) != 0")]
+ (symbol_ref "TARGET_CALL_CLOBBERED_GP")]
(const_string "no")))
;; Classification of each insn.
;; prefetch memory prefetch (register + offset)
;; prefetchx memory indexed prefetch (register + register)
;; condmove conditional moves
-;; xfer transfer to/from coprocessor
+;; mfc transfer from coprocessor
+;; mtc transfer to coprocessor
;; mthilo transfer to hi/lo registers
;; mfhilo transfer from hi/lo registers
;; const load constant
-;; arith integer arithmetic and logical instructions
+;; arith integer arithmetic instructions
+;; logical integer logical instructions
;; shift integer shift instructions
;; slt set less than instructions
+;; signext sign extend instructions
;; clz the clz and clo instructions
;; trap trap if instructions
-;; imul integer multiply
+;; imul integer multiply 2 operands
+;; imul3 integer multiply 3 operands
;; imadd integer multiply-add
;; idiv integer divide
+;; move integer register move ({,D}ADD{,U} with rt = 0)
;; fmove floating point register move
;; fadd floating point add/subtract
;; fmul floating point multiply
;; multi multiword sequence (or user asm statements)
;; nop no operation
(define_attr "type"
- "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
+ "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,mfc,mtc,mthilo,mfhilo,const,arith,logical,shift,slt,signext,clz,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
(cond [(eq_attr "jal" "!unset") (const_string "call")
(eq_attr "got" "load") (const_string "load")]
(const_string "unknown")))
(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
(const_string "unknown"))
+;; Mode for conversion types (fcvt)
+;; I2S integer to float single (SI/DI to SF)
+;; I2D integer to float double (SI/DI to DF)
+;; S2I float to integer (SF to SI/DI)
+;; D2I float to integer (DF to SI/DI)
+;; D2S double to float single
+;; S2D float single to double
+
+(define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
+ (const_string "unknown"))
+
;; Is this an extended instruction in mips16 mode?
(define_attr "extended_mips16" "no,yes"
(const_string "no"))
(eq_attr "type" "const")
(symbol_ref "mips_const_insns (operands[1]) * 4")
(eq_attr "type" "load,fpload")
- (symbol_ref "mips_fetch_insns (operands[1]) * 4")
+ (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
(eq_attr "type" "store,fpstore")
- (symbol_ref "mips_fetch_insns (operands[0]) * 4")
+ (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
;; In the worst case, a call macro will take 8 instructions:
;;
;; VR4120 errata MD(4): if there are consecutive dmult instructions,
;; the result of the second one is missed. The assembler should work
;; around this by inserting a nop after the first dmult.
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,imul3")
(and (eq_attr "mode" "DI")
(ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
(const_int 8)
;; Attribute describing the processor. This attribute must match exactly
;; with the processor_type enumeration in mips.h.
(define_attr "cpu"
- "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
+ "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
(const (symbol_ref "mips_tune")))
;; The type of hardware hazard associated with this instruction.
(ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
(const_string "delay")
- (and (eq_attr "type" "xfer")
+ (and (eq_attr "type" "mfc,mtc")
(ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
(const_string "delay")
;; True if an instruction might assign to hi or lo when reloaded.
;; This is used by the TUNE_MACC_CHAINS code.
(define_attr "may_clobber_hilo" "no,yes"
- (if_then_else (eq_attr "type" "imul,imadd,idiv,mthilo")
+ (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
(const_string "yes")
(const_string "no")))
;; Describe a user's asm statement.
(define_asm_attributes
- [(set_attr "type" "multi")])
+ [(set_attr "type" "multi")
+ (set_attr "can_delay" "no")])
\f
-;; This mode macro allows 32-bit and 64-bit GPR patterns to be generated
+;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
;; from the same template.
-(define_mode_macro GPR [SI (DI "TARGET_64BIT")])
+(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
-;; This mode macro allows :P to be used for patterns that operate on
+;; This mode iterator allows :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match.
-(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
+(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
-;; This mode macro allows :MOVECC to be used anywhere that a
+;; This mode iterator allows :MOVECC to be used anywhere that a
;; conditional-move-type condition is needed.
-(define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
+(define_mode_iterator MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
-;; This mode macro allows the QI and HI extension patterns to be defined from
+;; This mode iterator allows the QI and HI extension patterns to be defined from
;; the same template.
-(define_mode_macro SHORT [QI HI])
+(define_mode_iterator SHORT [QI HI])
-;; This mode macro allows :ANYF to be used wherever a scalar or vector
+;; This mode iterator allows :ANYF to be used wherever a scalar or vector
;; floating-point mode is allowed.
-(define_mode_macro ANYF [(SF "TARGET_HARD_FLOAT")
- (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
- (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
+(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
+ (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
+ (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
;; Like ANYF, but only applies to scalar modes.
-(define_mode_macro SCALARF [(SF "TARGET_HARD_FLOAT")
- (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
+(define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
+ (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
;; 32-bit version and "dsubu" in the 64-bit version.
(define_mode_attr store [(SI "sw") (DI "sd")])
;; Similarly for MIPS IV indexed FPR loads and stores.
-(define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1")])
-(define_mode_attr storex [(SF "swxc1") (DF "sdxc1")])
+(define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
+(define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
;; The unextended ranges of the MIPS16 addiu and daddiu instructions
;; are different. Some forms of unextended addiu have an 8-bit immediate
(define_mode_attr recip_condition
[(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")])
-;; This code macro allows all branch instructions to be generated from
+;; This code iterator allows all branch instructions to be generated from
;; a single define_expand template.
-(define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
- eq ne gt ge lt le gtu geu ltu leu])
+(define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
+ eq ne gt ge lt le gtu geu ltu leu])
-;; This code macro allows signed and unsigned widening multiplications
+;; This code iterator allows signed and unsigned widening multiplications
;; to use the same template.
-(define_code_macro any_extend [sign_extend zero_extend])
+(define_code_iterator any_extend [sign_extend zero_extend])
-;; This code macro allows the three shift instructions to be generated
+;; This code iterator allows the three shift instructions to be generated
;; from the same template.
-(define_code_macro any_shift [ashift ashiftrt lshiftrt])
+(define_code_iterator any_shift [ashift ashiftrt lshiftrt])
-;; This code macro allows all native floating-point comparisons to be
+;; This code iterator allows all native floating-point comparisons to be
;; generated from the same template.
-(define_code_macro fcond [unordered uneq unlt unle eq lt le])
+(define_code_iterator fcond [unordered uneq unlt unle eq lt le])
+
+;; This code iterator is used for comparisons that can be implemented
+;; by swapping the operands.
+(define_code_iterator swapped_fcond [ge gt unge ungt])
;; <u> expands to an empty string when doing a signed operation and
;; "u" when doing an unsigned operation.
;; <optab> expands to the name of the optab for a particular code.
(define_code_attr optab [(ashift "ashl")
(ashiftrt "ashr")
- (lshiftrt "lshr")])
+ (lshiftrt "lshr")
+ (ior "ior")
+ (xor "xor")
+ (and "and")])
;; <insn> expands to the name of the insn that implements a particular code.
(define_code_attr insn [(ashift "sll")
(ashiftrt "sra")
- (lshiftrt "srl")])
+ (lshiftrt "srl")
+ (ior "or")
+ (xor "xor")
+ (and "and")])
;; <fcond> is the c.cond.fmt condition associated with a particular code.
(define_code_attr fcond [(unordered "un")
(eq "eq")
(lt "lt")
(le "le")])
+
+;; Similar, but for swapped conditions.
+(define_code_attr swapped_fcond [(ge "le")
+ (gt "lt")
+ (unge "ule")
+ (ungt "ult")])
+
+;; Atomic fetch bitwise operations.
+(define_code_iterator fetchop_bit [ior xor and])
+
+;; <immediate_insn> expands to the name of the insn that implements
+;; a particular code to operate in immediate values.
+(define_code_attr immediate_insn [(ior "ori") (xor "xori") (and "andi")])
+
\f
;; .........................
;;
(define_cpu_unit "alu" "alu")
(define_cpu_unit "imuldiv" "imuldiv")
+(include "4k.md")
+(include "5k.md")
+(include "20kc.md")
+(include "24k.md")
+(include "74k.md")
(include "3000.md")
(include "4000.md")
(include "4100.md")
[(set_attr "type" "arith")
(set_attr "mode" "<MODE>")])
-;; We need to recognize MIPS16 stack pointer additions explicitly, since
-;; we don't have a constraint for $sp. These insns will be generated by
-;; the save_restore_insns functions.
-
-(define_insn "*add<mode>3_sp1"
- [(set (reg:GPR 29)
- (plus:GPR (reg:GPR 29)
- (match_operand:GPR 0 "const_arith_operand" "")))]
- "TARGET_MIPS16"
- "<d>addiu\t%$,%$,%0"
- [(set_attr "type" "arith")
- (set_attr "mode" "<MODE>")
- (set (attr "length") (if_then_else (match_operand 0 "m16_simm8_8")
- (const_int 4)
- (const_int 8)))])
-
-(define_insn "*add<mode>3_sp2"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (plus:GPR (reg:GPR 29)
- (match_operand:GPR 1 "const_arith_operand" "")))]
- "TARGET_MIPS16"
- "<d>addiu\t%0,%$,%1"
- [(set_attr "type" "arith")
- (set_attr "mode" "<MODE>")
- (set (attr "length") (if_then_else (match_operand 1 "m16_uimm<si8_di5>_4")
- (const_int 4)
- (const_int 8)))])
-
(define_insn "*add<mode>3_mips16"
- [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
- (plus:GPR (match_operand:GPR 1 "register_operand" "0,d,d")
- (match_operand:GPR 2 "arith_operand" "Q,O,d")))]
+ [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
+ (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
+ (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
"TARGET_MIPS16"
"@
<d>addiu\t%0,%2
<d>addiu\t%0,%1,%2
+ <d>addiu\t%0,%2
+ <d>addiu\t%0,%1,%2
<d>addu\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "<MODE>")
(set_attr_alternative "length"
- [(if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
+ [(if_then_else (match_operand 2 "m16_simm8_8")
+ (const_int 4)
+ (const_int 8))
+ (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
+ (const_int 4)
+ (const_int 8))
+ (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
(const_int 4)
(const_int 8))
(if_then_else (match_operand 2 "m16_simm4_1")
(const_int 8))
(const_int 4)])])
-
;; On the mips16, we can sometimes split an add of a constant which is
;; a 4 byte instruction into two adds which are both 2 byte
;; instructions. There are two cases: one where we are adding a
(plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) > 0x7f
(plus:SI (match_operand:SI 1 "register_operand")
(match_operand:SI 2 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG
+ && REG_P (operands[1])
&& M16_REG_P (REGNO (operands[1]))
&& REGNO (operands[0]) != REGNO (operands[1])
&& GET_CODE (operands[2]) == CONST_INT
(plus:DI (match_dup 0)
(match_operand:DI 1 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) > 0xf
(plus:DI (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG
+ && REG_P (operands[1])
&& M16_REG_P (REGNO (operands[1]))
&& REGNO (operands[0]) != REGNO (operands[1])
&& GET_CODE (operands[2]) == CONST_INT
;; These processors have PRId values of 0x00004220 and 0x00004300,
;; respectively.
-(define_expand "mul<mode>3"
- [(set (match_operand:GPR 0 "register_operand")
- (mult:GPR (match_operand:GPR 1 "register_operand")
- (match_operand:GPR 2 "register_operand")))]
+(define_expand "mulsi3"
+ [(set (match_operand:SI 0 "register_operand")
+ (mult:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "register_operand")))]
""
{
- if (GENERATE_MULT3_<MODE>)
- emit_insn (gen_mul<mode>3_mult3 (operands[0], operands[1], operands[2]));
- else if (!TARGET_FIX_R4000)
- emit_insn (gen_mul<mode>3_internal (operands[0], operands[1],
- operands[2]));
+ if (ISA_HAS_MUL3)
+ emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
+ else if (TARGET_FIX_R4000)
+ emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
else
- emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
+ emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "muldi3"
+ [(set (match_operand:DI 0 "register_operand")
+ (mult:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "register_operand")))]
+ "TARGET_64BIT"
+{
+ if (TARGET_FIX_R4000)
+ emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2]));
+ else
+ emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
DONE;
})
(match_operand:SI 2 "register_operand" "d,d")))
(clobber (match_scratch:SI 3 "=h,h"))
(clobber (match_scratch:SI 4 "=l,X"))]
- "GENERATE_MULT3_SI"
+ "ISA_HAS_MUL3"
{
if (which_alternative == 1)
return "mult\t%1,%2";
- if (TARGET_MAD
- || TARGET_MIPS5400
- || TARGET_MIPS5500
- || TARGET_MIPS7000
- || TARGET_MIPS9000
- || ISA_MIPS32
- || ISA_MIPS32R2
- || ISA_MIPS64)
- return "mul\t%0,%1,%2";
- return "mult\t%0,%1,%2";
+ if (TARGET_MIPS3900)
+ return "mult\t%0,%1,%2";
+ return "mul\t%0,%1,%2";
}
- [(set_attr "type" "imul")
+ [(set_attr "type" "imul3,imul")
(set_attr "mode" "SI")])
-(define_insn "muldi3_mult3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (mult:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:DI 2 "register_operand" "d")))
- (clobber (match_scratch:DI 3 "=h"))
- (clobber (match_scratch:DI 4 "=l"))]
- "TARGET_64BIT && GENERATE_MULT3_DI"
- "dmult\t%0,%1,%2"
- [(set_attr "type" "imul")
- (set_attr "mode" "DI")])
-
;; If a register gets allocated to LO, and we spill to memory, the reload
;; will include a move from LO to a GPR. Merge it into the multiplication
;; if it can set the GPR directly.
(clobber (scratch:SI))])
(set (match_operand:SI 4 "register_operand")
(unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
- "GENERATE_MULT3_SI && peep2_reg_dead_p (2, operands[0])"
+ "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
[(parallel
[(set (match_dup 4)
(mult:SI (match_dup 1)
(clobber (match_operand:SI 3 "register_operand"))])
(set (match_operand:SI 4 "register_operand")
(unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
- "ISA_HAS_MACC && !GENERATE_MULT3_SI"
+ "ISA_HAS_MACC && !ISA_HAS_MUL3"
[(set (match_dup 0)
(const_int 0))
(parallel
(clobber (match_scratch:SI 5 "=X,3,l"))
(clobber (match_scratch:SI 6 "=X,X,&d"))]
"(TARGET_MIPS3900
- || ISA_HAS_MADD_MSUB)
+ || GENERATE_MADD_MSUB)
&& !TARGET_MIPS16"
{
static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
if (which_alternative == 2)
return "#";
- if (ISA_HAS_MADD_MSUB && which_alternative != 0)
+ if (GENERATE_MADD_MSUB && which_alternative != 0)
return "#";
return madd[which_alternative];
}
- [(set_attr "type" "imadd,imadd,multi")
+ [(set_attr "type" "imadd")
(set_attr "mode" "SI")
(set_attr "length" "4,4,8")])
(match_operand:SI 4 "macc_msac_operand"))
(clobber (match_operand:SI 5 "register_operand"))
(clobber (match_dup 1))])]
- "GENERATE_MULT3_SI
+ "ISA_HAS_MUL3
&& true_regnum (operands[1]) == LO_REGNUM
&& peep2_reg_dead_p (2, operands[1])
&& GP_REG_P (true_regnum (operands[3]))"
(match_dup 0)
(set (match_operand:SI 5 "register_operand")
(unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
- "GENERATE_MULT3_SI && peep2_reg_dead_p (3, operands[1])"
+ "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
[(parallel [(set (match_dup 0)
(match_dup 6))
(clobber (match_dup 4))
(clobber (match_scratch:SI 4 "=h,h,h"))
(clobber (match_scratch:SI 5 "=X,1,l"))
(clobber (match_scratch:SI 6 "=X,X,&d"))]
- "ISA_HAS_MADD_MSUB"
+ "GENERATE_MADD_MSUB"
"@
msub\t%2,%3
#
#"
- [(set_attr "type" "imadd,multi,multi")
+ [(set_attr "type" "imadd")
(set_attr "mode" "SI")
(set_attr "length" "4,8,8")])
"@
muls\t$0,%1,%2
muls\t%0,%1,%2"
- [(set_attr "type" "imul")
+ [(set_attr "type" "imul,imul3")
(set_attr "mode" "SI")])
;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
[(set (match_operand:DI 0 "register_operand" "=x")
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
- "!TARGET_64BIT && !TARGET_FIX_R4000"
+ "!TARGET_64BIT && !TARGET_FIX_R4000 && !TARGET_DSPR2"
"mult<u>\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
(any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
(clobber (match_scratch:DI 3 "=x"))]
"!TARGET_64BIT && TARGET_FIX_R4000"
- "mult\t%1,%2\;mflo\t%L0;mfhi\t%M0"
+ "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
[(set_attr "type" "imul")
(set_attr "mode" "SI")
(set_attr "length" "12")])
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
-(define_insn "*msac<u>_di"
- [(set (match_operand:DI 0 "register_operand" "=x")
+(define_insn "<u>msubsidi4"
+ [(set (match_operand:DI 0 "register_operand" "=ka")
(minus:DI
(match_operand:DI 3 "register_operand" "0")
(mult:DI
(any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
- "!TARGET_64BIT && ISA_HAS_MSAC"
+ "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || TARGET_DSPR2)"
{
- if (TARGET_MIPS5500)
+ if (TARGET_DSPR2)
+ return "msub<u>\t%q0,%1,%2";
+ else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
return "msub<u>\t%1,%2";
else
return "msac<u>\t$0,%1,%2";
"@
mult<u>\t%1,%2
mulhi<u>\t%0,%1,%2"
- [(set_attr "type" "imul")
+ [(set_attr "type" "imul,imul3")
(set_attr "mode" "SI")])
(define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
"@
mulshi<u>\t%.,%1,%2
mulshi<u>\t%0,%1,%2"
- [(set_attr "type" "imul")
+ [(set_attr "type" "imul,imul3")
(set_attr "mode" "SI")])
;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
-;; The R4650 supports a 32 bit multiply/ 64 bit accumulate
-;; instruction. The HI/LO registers are used as a 64 bit accumulator.
+;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
+;; instruction. The HI/LO registers are used as a 64-bit accumulator.
(define_insn "madsi"
[(set (match_operand:SI 0 "register_operand" "+l")
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
-(define_insn "*<su>mul_acc_di"
- [(set (match_operand:DI 0 "register_operand" "=x")
+(define_insn "<u>maddsidi4"
+ [(set (match_operand:DI 0 "register_operand" "=ka")
(plus:DI
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))
(match_operand:DI 3 "register_operand" "0")))]
- "(TARGET_MAD || ISA_HAS_MACC)
+ "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || TARGET_DSPR2)
&& !TARGET_64BIT"
{
if (TARGET_MAD)
return "mad<u>\t%1,%2";
- else if (TARGET_MIPS5500)
+ else if (TARGET_DSPR2)
+ return "madd<u>\t%q0,%1,%2";
+ else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
return "madd<u>\t%1,%2";
else
/* See comment in *macc. */
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "f"))))]
"ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
- && HONOR_SIGNED_ZEROS (<MODE>mode)"
+ && HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
"nmadd.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "f")))]
"ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
- && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ && !HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
"nmadd.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
(match_operand:ANYF 3 "register_operand" "f"))
(match_operand:ANYF 1 "register_operand" "f"))))]
"ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
- && HONOR_SIGNED_ZEROS (<MODE>mode)"
+ && HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
"nmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
(mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
(match_operand:ANYF 3 "register_operand" "f"))))]
"ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
- && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ && !HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
"nmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
;; Do not use the integer abs macro instruction, since that signals an
;; exception on -2147483648 (sigh).
-(define_insn "abs<mode>2"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (abs:GPR (match_operand:GPR 1 "register_operand" "d")))]
- "!TARGET_MIPS16"
-{
- if (REGNO (operands[0]) == REGNO (operands[1]) && GENERATE_BRANCHLIKELY)
- return "%(bltzl\t%1,1f\;<d>subu\t%0,%.,%0\n%~1:%)";
- else
- return "%(bgez\t%1,1f\;move\t%0,%1\;<d>subu\t%0,%.,%0\n%~1:%)";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "<MODE>")
- (set_attr "length" "12")])
+;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
+;; invalid; it does not clear their sign bits. We therefore can't use
+;; abs.fmt if the signs of NaNs matter.
(define_insn "abs<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
- ""
+ "!HONOR_NANS (<MODE>mode)"
"abs.<fmt>\t%0,%1"
[(set_attr "type" "fabs")
(set_attr "mode" "<UNITMODE>")])
\f
;;
-;; ....................
-;;
-;; FIND FIRST BIT INSTRUCTION
-;;
-;; ....................
-;;
-
-(define_insn "ffs<mode>2"
- [(set (match_operand:GPR 0 "register_operand" "=&d")
- (ffs:GPR (match_operand:GPR 1 "register_operand" "d")))
- (clobber (match_scratch:GPR 2 "=&d"))
- (clobber (match_scratch:GPR 3 "=&d"))]
- "!TARGET_MIPS16"
-{
- if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
- return "%(\
-move\t%0,%.\;\
-beq\t%1,%.,2f\n\
-%~1:\tand\t%2,%1,0x0001\;\
-<d>addu\t%0,%0,1\;\
-beq\t%2,%.,1b\;\
-<d>srl\t%1,%1,1\n\
-%~2:%)";
-
- return "%(\
-move\t%0,%.\;\
-move\t%3,%1\;\
-beq\t%3,%.,2f\n\
-%~1:\tand\t%2,%3,0x0001\;\
-<d>addu\t%0,%0,1\;\
-beq\t%2,%.,1b\;\
-<d>srl\t%3,%3,1\n\
-%~2:%)";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "<MODE>")
- (set_attr "length" "28")])
-\f
-;;
;; ...................
;;
;; Count leading zeroes.
[(set_attr "type" "arith")
(set_attr "mode" "DI")])
+;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
+;; invalid; it does not flip their sign bit. We therefore can't use
+;; neg.fmt if the signs of NaNs matter.
+
(define_insn "neg<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
- ""
+ "!HONOR_NANS (<MODE>mode)"
"neg.<fmt>\t%0,%1"
[(set_attr "type" "fneg")
(set_attr "mode" "<UNITMODE>")])
else
return "nor\t%0,%.,%1";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
\f
;;
"@
and\t%0,%1,%2
andi\t%0,%1,%x2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
(define_insn "*and<mode>3_mips16"
(match_operand:GPR 2 "register_operand" "d")))]
"TARGET_MIPS16"
"and\t%0,%2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
(define_expand "ior<mode>3"
"@
or\t%0,%1,%2
ori\t%0,%1,%x2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
(define_insn "*ior<mode>3_mips16"
(match_operand:GPR 2 "register_operand" "d")))]
"TARGET_MIPS16"
"or\t%0,%2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
(define_expand "xor<mode>3"
"@
xor\t%0,%1,%2
xori\t%0,%1,%x2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
(define_insn ""
xor\t%0,%2
cmpi\t%1,%2
cmp\t%1,%2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical,arith,arith")
(set_attr "mode" "<MODE>")
(set_attr_alternative "length"
[(const_int 4)
(not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
"!TARGET_MIPS16"
"nor\t%0,%1,%2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
\f
;;
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"cvt.s.d\t%0,%1"
[(set_attr "type" "fcvt")
+ (set_attr "cnv_mode" "D2S")
(set_attr "mode" "SF")])
;; Integer truncation patterns. Truncating SImode values to smaller
(match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"andi\t%0,%1,0xffff"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "SI")])
(define_insn ""
(match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"andi\t%0,%1,0xff"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "SI")])
(define_insn ""
(match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"andi\t%0,%1,0xff"
- [(set_attr "type" "arith")
+ [(set_attr "type" "logical")
(set_attr "mode" "HI")])
\f
;;
(set_attr "mode" "DI")
(set_attr "length" "8,*")])
+;; Combine is not allowed to convert this insn into a zero_extendsidi2
+;; because of TRULY_NOOP_TRUNCATION.
+
+(define_insn_and_split "*clear_upper32"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
+ (const_int 4294967295)))]
+ "TARGET_64BIT"
+{
+ if (which_alternative == 0)
+ return "#";
+
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ return "lwu\t%0,%1";
+}
+ "&& reload_completed && REG_P (operands[1])"
+ [(set (match_dup 0)
+ (ashift:DI (match_dup 1) (const_int 32)))
+ (set (match_dup 0)
+ (lshiftrt:DI (match_dup 0) (const_int 32)))]
+ ""
+ [(set_attr "type" "multi,load")
+ (set_attr "mode" "DI")
+ (set_attr "length" "8,*")])
+
(define_expand "zero_extend<SHORT:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand")
(zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
""
{
- if (TARGET_MIPS16 && !memory_operand (operands[1], <SHORT:MODE>mode))
+ if (TARGET_MIPS16 && !GENERATE_MIPS16E
+ && !memory_operand (operands[1], <SHORT:MODE>mode))
{
emit_insn (gen_and<GPR:mode>3 (operands[0],
gen_lowpart (<GPR:MODE>mode, operands[1]),
"@
andi\t%0,%1,<SHORT:mask>
l<SHORT:size>u\t%0,%1"
- [(set_attr "type" "arith,load")
+ [(set_attr "type" "logical,load")
+ (set_attr "mode" "<GPR:MODE>")])
+
+(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
+ "GENERATE_MIPS16E"
+ "ze<SHORT:size>\t%0"
+ [(set_attr "type" "arith")
(set_attr "mode" "<GPR:MODE>")])
(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
"@
andi\t%0,%1,0x00ff
lbu\t%0,%1"
- [(set_attr "type" "arith,load")
+ [(set_attr "type" "logical,load")
(set_attr "mode" "HI")])
(define_insn "*zero_extendqihi2_mips16"
(sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
"")
+(define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
+ "GENERATE_MIPS16E"
+ "@
+ se<SHORT:size>\t%0
+ l<SHORT:size>\t%0,%1"
+ [(set_attr "type" "signext,load")
+ (set_attr "mode" "<GPR:MODE>")])
+
(define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(sign_extend:GPR
(match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
- "!ISA_HAS_SEB_SEH"
+ "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
"@
#
l<SHORT:size>\t%0,%1"
"@
se<SHORT:size>\t%0,%1
l<SHORT:size>\t%0,%1"
- [(set_attr "type" "arith,load")
+ [(set_attr "type" "signext,load")
(set_attr "mode" "<GPR:MODE>")])
-;; This pattern generates the same code as extendqisi2; split it into
-;; that form after reload.
-(define_insn_and_split "extendqihi2"
+(define_expand "extendqihi2"
+ [(set (match_operand:HI 0 "register_operand")
+ (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
+ "")
+
+(define_insn "*extendqihi2_mips16e"
[(set (match_operand:HI 0 "register_operand" "=d,d")
- (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
- ""
- "#"
- "reload_completed"
- [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
- { operands[0] = gen_lowpart (SImode, operands[0]); }
- [(set_attr "type" "arith,load")
+ (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
+ "GENERATE_MIPS16E"
+ "@
+ seb\t%0
+ lb\t%0,%1"
+ [(set_attr "type" "signext,load")
+ (set_attr "mode" "SI")])
+
+(define_insn_and_split "*extendqihi2"
+ [(set (match_operand:HI 0 "register_operand" "=d,d")
+ (sign_extend:HI
+ (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
+ "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
+ "@
+ #
+ lb\t%0,%1"
+ "&& reload_completed && REG_P (operands[1])"
+ [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
+{
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
+ - GET_MODE_BITSIZE (QImode));
+}
+ [(set_attr "type" "multi,load")
(set_attr "mode" "SI")
(set_attr "length" "8,*")])
+(define_insn "*extendqihi2_seb"
+ [(set (match_operand:HI 0 "register_operand" "=d,d")
+ (sign_extend:HI
+ (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
+ "ISA_HAS_SEB_SEH"
+ "@
+ seb\t%0,%1
+ lb\t%0,%1"
+ [(set_attr "type" "signext,load")
+ (set_attr "mode" "SI")])
+
(define_insn "extendsfdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"cvt.d.s\t%0,%1"
[(set_attr "type" "fcvt")
+ (set_attr "cnv_mode" "S2D")
(set_attr "mode" "DF")])
\f
;;
"trunc.w.d %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "D2I")
(set_attr "length" "4")])
(define_insn "fix_truncdfsi2_macro"
}
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "D2I")
(set_attr "length" "36")])
(define_expand "fix_truncsfsi2"
"TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
"trunc.w.s %0,%1"
[(set_attr "type" "fcvt")
- (set_attr "mode" "DF")
+ (set_attr "mode" "SF")
+ (set_attr "cnv_mode" "S2I")
(set_attr "length" "4")])
(define_insn "fix_truncsfsi2_macro"
return "trunc.w.s %0,%1,%2";
}
[(set_attr "type" "fcvt")
- (set_attr "mode" "DF")
+ (set_attr "mode" "SF")
+ (set_attr "cnv_mode" "S2I")
(set_attr "length" "36")])
"trunc.l.d %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "D2I")
(set_attr "length" "4")])
"trunc.l.s %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
+ (set_attr "cnv_mode" "S2I")
(set_attr "length" "4")])
"cvt.d.w\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "I2D")
(set_attr "length" "4")])
"cvt.d.l\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "I2D")
(set_attr "length" "4")])
"cvt.s.w\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
+ (set_attr "cnv_mode" "I2S")
(set_attr "length" "4")])
"cvt.s.l\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
+ (set_attr "cnv_mode" "I2S")
(set_attr "length" "4")])
rtx label2 = gen_label_rtx ();
REAL_VALUE_TYPE offset;
- real_2expN (&offset, 31);
+ real_2expN (&offset, 31, DFmode);
if (reg1) /* Turn off complaints about unreached code. */
{
- emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
+ mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
do_pending_stack_adjust ();
emit_insn (gen_cmpdf (operands[1], reg1));
emit_barrier ();
emit_label (label1);
- emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
- emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
+ mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
+ mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
(BITMASK_HIGH, SImode)));
emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
rtx label2 = gen_label_rtx ();
REAL_VALUE_TYPE offset;
- real_2expN (&offset, 63);
+ real_2expN (&offset, 63, DFmode);
- emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
+ mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
do_pending_stack_adjust ();
emit_insn (gen_cmpdf (operands[1], reg1));
emit_barrier ();
emit_label (label1);
- emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
- emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
+ mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
+ mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
rtx label2 = gen_label_rtx ();
REAL_VALUE_TYPE offset;
- real_2expN (&offset, 31);
+ real_2expN (&offset, 31, SFmode);
- emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
+ mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
do_pending_stack_adjust ();
emit_insn (gen_cmpsf (operands[1], reg1));
emit_barrier ();
emit_label (label1);
- emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
- emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
+ mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
+ mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
(BITMASK_HIGH, SImode)));
emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
rtx label2 = gen_label_rtx ();
REAL_VALUE_TYPE offset;
- real_2expN (&offset, 63);
+ real_2expN (&offset, 63, SFmode);
- emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
+ mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
do_pending_stack_adjust ();
emit_insn (gen_cmpsf (operands[1], reg1));
emit_barrier ();
emit_label (label1);
- emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
- emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
+ mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
+ mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
(define_expand "extzv"
[(set (match_operand 0 "register_operand")
- (zero_extract (match_operand:QI 1 "memory_operand")
+ (zero_extract (match_operand 1 "nonimmediate_operand")
(match_operand 2 "immediate_operand")
(match_operand 3 "immediate_operand")))]
"!TARGET_MIPS16"
INTVAL (operands[2]),
INTVAL (operands[3])))
DONE;
+ else if (mips_use_ins_ext_p (operands[1], operands[2], operands[3]))
+ {
+ if (GET_MODE (operands[0]) == DImode)
+ emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
+ operands[3]));
+ else
+ emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
+ operands[3]));
+ DONE;
+ }
else
FAIL;
})
+(define_insn "extzv<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:SI 2 "immediate_operand" "I")
+ (match_operand:SI 3 "immediate_operand" "I")))]
+ "mips_use_ins_ext_p (operands[1], operands[2], operands[3])"
+ "<d>ext\t%0,%1,%3,%2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<MODE>")])
+
+
(define_expand "insv"
- [(set (zero_extract (match_operand:QI 0 "memory_operand")
+ [(set (zero_extract (match_operand 0 "nonimmediate_operand")
(match_operand 1 "immediate_operand")
(match_operand 2 "immediate_operand"))
(match_operand 3 "reg_or_0_operand"))]
INTVAL (operands[1]),
INTVAL (operands[2])))
DONE;
- else
- FAIL;
+ else if (mips_use_ins_ext_p (operands[0], operands[1], operands[2]))
+ {
+ if (GET_MODE (operands[0]) == DImode)
+ emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
+ operands[3]));
+ else
+ emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
+ operands[3]));
+ DONE;
+ }
+ else
+ FAIL;
})
+(define_insn "insv<mode>"
+ [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
+ (match_operand:SI 1 "immediate_operand" "I")
+ (match_operand:SI 2 "immediate_operand" "I"))
+ (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
+ "mips_use_ins_ext_p (operands[0], operands[1], operands[2])"
+ "<d>ins\t%0,%z3,%2,%1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<MODE>")])
+
;; Unaligned word moves generated by the bit field patterns.
;;
;; As far as the rtl is concerned, both the left-part and right-part
(unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
(match_operand:QI 2 "memory_operand" "m")]
UNSPEC_LOAD_LEFT))]
- "!TARGET_MIPS16"
+ "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
"<load>l\t%0,%2"
[(set_attr "type" "load")
- (set_attr "mode" "<MODE>")
- (set_attr "hazard" "none")])
+ (set_attr "mode" "<MODE>")])
(define_insn "mov_<load>r"
[(set (match_operand:GPR 0 "register_operand" "=d")
(match_operand:QI 2 "memory_operand" "m")
(match_operand:GPR 3 "register_operand" "0")]
UNSPEC_LOAD_RIGHT))]
- "!TARGET_MIPS16"
+ "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
"<load>r\t%0,%2"
[(set_attr "type" "load")
(set_attr "mode" "<MODE>")])
(unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
(match_operand:QI 2 "memory_operand" "m")]
UNSPEC_STORE_LEFT))]
- "!TARGET_MIPS16"
+ "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
"<store>l\t%z1,%2"
[(set_attr "type" "store")
(set_attr "mode" "<MODE>")])
(match_operand:QI 2 "memory_operand" "m")
(match_dup 0)]
UNSPEC_STORE_RIGHT))]
- "!TARGET_MIPS16"
+ "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
"<store>r\t%z1,%2"
[(set_attr "type" "store")
(set_attr "mode" "<MODE>")])
-;; An instruction to calculate the high part of a 64-bit SYMBOL_GENERAL.
+;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
;; The required value is:
;;
;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
;; to take effect.
(define_insn_and_split "*lea_high64"
[(set (match_operand:DI 0 "register_operand" "=d")
- (high:DI (match_operand:DI 1 "general_symbolic_operand" "")))]
+ (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
"TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
"#"
- "&& flow2_completed"
+ "&& epilogue_completed"
[(set (match_dup 0) (high:DI (match_dup 2)))
(set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
;; dsll32 op1,op1,0
;; daddu op1,op1,op0
(define_peephole2
- [(match_scratch:DI 0 "d")
- (set (match_operand:DI 1 "register_operand")
- (high:DI (match_operand:DI 2 "general_symbolic_operand")))]
+ [(set (match_operand:DI 1 "register_operand")
+ (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
+ (match_scratch:DI 0 "d")]
"TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
[(set (match_dup 1) (high:DI (match_dup 3)))
(set (match_dup 0) (high:DI (match_dup 4)))
})
;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
-;; SYMBOL_GENERAL X will take 6 cycles. This next pattern allows combine
+;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
;; used once. We can then use the sequence:
;;
;; which takes 4 cycles on most superscalar targets.
(define_insn_and_split "*lea64"
[(set (match_operand:DI 0 "register_operand" "=d")
- (match_operand:DI 1 "general_symbolic_operand" ""))
+ (match_operand:DI 1 "absolute_symbolic_operand" ""))
(clobber (match_scratch:DI 2 "=&d"))]
"TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
"#"
}
[(set_attr "length" "24")])
-;; Insns to fetch a global symbol from a big GOT.
+;; Split HIGHs into:
+;;
+;; li op0,%hi(sym)
+;; sll op0,16
+;;
+;; on MIPS16 targets.
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (high:SI (match_operand:SI 1 "absolute_symbolic_operand" "")))]
+ "TARGET_MIPS16 && reload_completed"
+ [(set (match_dup 0) (match_dup 2))
+ (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
+{
+ operands[2] = mips_unspec_address (operands[1], SYMBOL_32_HIGH);
+})
+
+;; Insns to fetch a symbol from a big GOT.
(define_insn_and_split "*xgot_hi<mode>"
[(set (match_operand:P 0 "register_operand" "=d")
- (high:P (match_operand:P 1 "global_got_operand" "")))]
+ (high:P (match_operand:P 1 "got_disp_operand" "")))]
"TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
"#"
"&& reload_completed"
[(set (match_dup 0) (high:P (match_dup 2)))
(set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
{
- operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_GLOBAL);
+ operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
operands[3] = pic_offset_table_rtx;
}
[(set_attr "got" "xgot_high")
(define_insn_and_split "*xgot_lo<mode>"
[(set (match_operand:P 0 "register_operand" "=d")
(lo_sum:P (match_operand:P 1 "register_operand" "d")
- (match_operand:P 2 "global_got_operand" "")))]
+ (match_operand:P 2 "got_disp_operand" "")))]
"TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
"#"
"&& reload_completed"
[(set (match_dup 0)
(unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
- { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_GLOBAL); }
+ { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
[(set_attr "got" "load")
(set_attr "mode" "<MODE>")])
-;; Insns to fetch a global symbol from a normal GOT.
+;; Insns to fetch a symbol from a normal GOT.
(define_insn_and_split "*got_disp<mode>"
[(set (match_operand:P 0 "register_operand" "=d")
- (match_operand:P 1 "global_got_operand" ""))]
+ (match_operand:P 1 "got_disp_operand" ""))]
"TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
"#"
"&& reload_completed"
(unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
{
operands[2] = pic_offset_table_rtx;
- operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_GLOBAL);
+ operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
}
[(set_attr "got" "load")
(set_attr "mode" "<MODE>")])
-;; Insns for loading the high part of a local symbol.
+;; Insns for loading the "page" part of a page/ofst address from the GOT.
(define_insn_and_split "*got_page<mode>"
[(set (match_operand:P 0 "register_operand" "=d")
- (high:P (match_operand:P 1 "local_got_operand" "")))]
+ (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
"TARGET_EXPLICIT_RELOCS"
"#"
"&& reload_completed"
;; We could use MEMs, but an unspec gives more optimization
;; opportunities.
-(define_insn "*load_got<mode>"
+(define_insn "load_got<mode>"
[(set (match_operand:P 0 "register_operand" "=d")
(unspec:P [(match_operand:P 1 "register_operand" "d")
(match_operand:P 2 "immediate_operand" "")]
UNSPEC_LOAD_GOT))]
- "TARGET_ABICALLS"
+ ""
"<load>\t%0,%R2(%1)"
[(set_attr "type" "load")
(set_attr "mode" "<MODE>")
(set_attr "mode" "<MODE>")
(set_attr "length" "8")])
+;; Allow combine to split complex const_int load sequences, using operand 2
+;; to store the intermediate results. See move_operand for details.
+(define_split
+ [(set (match_operand:GPR 0 "register_operand")
+ (match_operand:GPR 1 "splittable_const_int_operand"))
+ (clobber (match_operand:GPR 2 "register_operand"))]
+ ""
+ [(const_int 0)]
+{
+ mips_move_integer (operands[0], operands[2], INTVAL (operands[1]));
+ DONE;
+})
+
+;; Likewise, for symbolic operands.
+(define_split
+ [(set (match_operand:P 0 "register_operand")
+ (match_operand:P 1))
+ (clobber (match_operand:P 2 "register_operand"))]
+ "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
+ [(set (match_dup 0) (match_dup 3))]
+{
+ mips_split_symbol (operands[2], operands[1],
+ MAX_MACHINE_MODE, &operands[3]);
+})
+
;; 64-bit integer moves
;; Unlike most other insns, the move insns can't be split with
(set_attr "mode" "<MODE>")])
(define_insn "*movdi_32bit"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*x,*d,*B*C*D,*B*C*D,*d,*m")
- (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*x,*d,*m,*B*C*D,*B*C*D"))]
- "!TARGET_64BIT && !TARGET_MIPS16
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*B*C*D,*B*C*D,*d,*m")
+ (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
+ "!TARGET_64BIT && !TARGET_FLOAT64 && !TARGET_MIPS16
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,arith,load,store,mthilo,mfhilo,xfer,load,xfer,store")
+ [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,load,mfc,store")
(set_attr "mode" "DI")
(set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
+(define_insn "*movdi_gp32_fp64"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*f,*d,*m")
+ (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*f,*J*d,*m,*f,*f"))]
+ "!TARGET_64BIT && TARGET_FLOAT64 && !TARGET_MIPS16
+ && (register_operand (operands[0], DImode)
+ || reg_or_0_operand (operands[1], DImode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,fmove,mtc,fpload,mfc,fpstore")
+ (set_attr "mode" "DI")
+ (set_attr "length" "8,16,*,*,8,8,4,8,*,8,*")])
+
(define_insn "*movdi_32bit_mips16"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
(match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
&& (register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,arith,arith,arith,arith,load,store,mfhilo")
+ [(set_attr "type" "multi,multi,multi,multi,multi,load,store,mfhilo")
(set_attr "mode" "DI")
(set_attr "length" "8,8,8,8,12,*,*,8")])
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,mthilo,xfer,load,xfer,store")
+ [(set_attr "type" "move,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
(set_attr "mode" "DI")
(set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,8,*,8,*")])
&& (register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
+ [(set_attr "type" "move,move,move,arith,arith,const,load,store")
(set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
(match_operand:DI 1 "const_int_operand"))))]
"TARGET_64BIT && TARGET_MIPS16 && reload_completed
&& !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
;; in FP registers (off by default, use -mdebugh to enable).
(define_insn "*movsi_internal"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*x,*B*C*D,*B*C*D,*d,*m")
- (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,*J*d,*d,*m,*B*C*D,*B*C*D"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
+ (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
"!TARGET_MIPS16
&& (register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,xfer,xfer,mthilo,xfer,load,xfer,store")
+ [(set_attr "type" "move,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,load,mfc,store")
(set_attr "mode" "SI")
- (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,*,4,*")])
+ (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,*,4,*")])
(define_insn "*movsi_mips16"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
&& (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
+ [(set_attr "type" "move,move,move,arith,arith,const,load,store")
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(const_int 4)
(mem:SI (plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
[(set (match_operand:SI 0 "register_operand")
(match_operand:SI 1 "const_int_operand"))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& INTVAL (operands[1]) >= 0x100
(match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
"ISA_HAS_8CC && TARGET_HARD_FLOAT"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "xfer,arith,load,store,xfer,xfer,fmove,fpload,fpstore")
+ [(set_attr "type" "multi,move,load,store,mfc,mtc,fmove,fpload,fpstore")
(set_attr "mode" "SI")
(set_attr "length" "8,4,*,*,4,4,4,*,*")])
;; the sum of two general registers. We use two versions for each of
;; these four instructions: one where the two general registers are
;; SImode, and one where they are DImode. This is because general
-;; registers will be in SImode when they hold 32 bit values, but,
-;; since the 32 bit values are always sign extended, the [ls][wd]xc1
+;; registers will be in SImode when they hold 32-bit values, but,
+;; since the 32-bit values are always sign extended, the [ls][wd]xc1
;; instructions will still work correctly.
;; ??? Perhaps it would be better to support these instructions by
[(set_attr "type" "fpidxstore")
(set_attr "mode" "<ANYF:UNITMODE>")])
+;; Scaled indexed address load.
+;; Per md.texi, we only need to look for a pattern with multiply in the
+;; address expression, not shift.
+
+(define_insn "*lwxs"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (mem:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
+ (const_int 4))
+ (match_operand:SI 2 "register_operand" "d"))))]
+ "ISA_HAS_LWXS"
+ "lwxs\t%0,%1(%2)"
+ [(set_attr "type" "load")
+ (set_attr "mode" "SI")
+ (set_attr "length" "4")])
+
;; 16-bit Integer moves
;; Unlike most other insns, the move insns can't be split with
mtc1\t%1,%0
mov.s\t%0,%1
mt%0\t%1"
- [(set_attr "type" "arith,arith,load,store,xfer,xfer,fmove,mthilo")
+ [(set_attr "type" "move,arith,load,store,mfc,mtc,fmove,mthilo")
(set_attr "mode" "HI")
(set_attr "length" "4,4,*,*,4,4,4,4")])
#
lhu\t%0,%1
sh\t%1,%0"
- [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
+ [(set_attr "type" "move,move,move,arith,arith,load,store")
(set_attr "mode" "HI")
(set_attr_alternative "length"
[(const_int 4)
(mem:HI (plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
mtc1\t%1,%0
mov.s\t%0,%1
mt%0\t%1"
- [(set_attr "type" "arith,arith,load,store,xfer,xfer,fmove,mthilo")
+ [(set_attr "type" "move,arith,load,store,mfc,mtc,fmove,mthilo")
(set_attr "mode" "QI")
(set_attr "length" "4,4,*,*,4,4,4,4")])
#
lbu\t%0,%1
sb\t%1,%0"
- [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
+ [(set_attr "type" "move,move,move,arith,arith,load,store")
(set_attr "mode" "QI")
(set_attr "length" "4,4,4,4,8,*,*")])
(mem:QI (plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
&& (register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
+ [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
(set_attr "mode" "SF")
(set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
&& (register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,load,store")
+ [(set_attr "type" "move,load,store")
(set_attr "mode" "SF")
(set_attr "length" "4,*,*")])
&& (register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,arith,arith,load,store")
+ [(set_attr "type" "move,move,move,load,store")
(set_attr "mode" "SF")
(set_attr "length" "4,4,4,*,*")])
&& (register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
+ [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
(set_attr "mode" "DF")
(set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
+;; This pattern applies to both !TARGET_FLOAT64 and TARGET_FLOAT64.
(define_insn "*movdf_hardfloat_32bit"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
(match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
&& (register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
+ [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
(set_attr "mode" "DF")
(set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
&& (register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,load,store,xfer,xfer,fmove")
+ [(set_attr "type" "multi,load,store,mfc,mtc,fmove")
(set_attr "mode" "DF")
(set_attr "length" "8,*,*,4,4,4")])
&& (register_operand (operands[0], DFmode)
|| register_operand (operands[1], DFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,arith,arith,load,store")
+ [(set_attr "type" "multi,multi,multi,load,store")
(set_attr "mode" "DF")
(set_attr "length" "8,8,8,*,*")])
&& (register_operand (operands[0], V2SFmode)
|| reg_or_0_operand (operands[1], V2SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
+ [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
(set_attr "mode" "SF")
(set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
;;
;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
;; Operand 1 is the register we want, operand 2 is the other one.
+;;
+;; When generating VR4120 or VR4130 code, we use macc{,hi} and
+;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal
+;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130.
+
+(define_expand "mfhilo_<mode>"
+ [(set (match_operand:GPR 0 "register_operand")
+ (unspec:GPR [(match_operand:GPR 1 "register_operand")
+ (match_operand:GPR 2 "register_operand")]
+ UNSPEC_MFHILO))])
-(define_insn "mfhilo_<mode>"
+(define_insn "*mfhilo_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
(match_operand:GPR 2 "register_operand" "l,h")]
UNSPEC_MFHILO))]
- ""
+ "!ISA_HAS_MACCHI"
"mf%1\t%0"
[(set_attr "type" "mfhilo")
(set_attr "mode" "<MODE>")])
+(define_insn "*mfhilo_<mode>_macc"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
+ (match_operand:GPR 2 "register_operand" "l,h")]
+ UNSPEC_MFHILO))]
+ "ISA_HAS_MACCHI"
+ "@
+ <d>macchi\t%0,%.,%.
+ <d>macc\t%0,%.,%."
+ [(set_attr "type" "mfhilo")
+ (set_attr "mode" "<MODE>")])
+
;; Patterns for loading or storing part of a paired floating point
;; register. We need them because odd-numbered floating-point registers
;; are not fully independent: see mips_split_64bit_move.
operands[0] = mips_subword (operands[0], 0);
return mips_output_move (operands[0], operands[1]);
}
- [(set_attr "type" "xfer,fpload")
+ [(set_attr "type" "mtc,fpload")
(set_attr "mode" "SF")])
;; Load the high word of operand 0 from operand 1, preserving the value
operands[0] = mips_subword (operands[0], 1);
return mips_output_move (operands[0], operands[1]);
}
- [(set_attr "type" "xfer,fpload")
+ [(set_attr "type" "mtc,fpload")
(set_attr "mode" "SF")])
;; Store the high word of operand 1 in operand 0. The corresponding
operands[1] = mips_subword (operands[1], 1);
return mips_output_move (operands[0], operands[1]);
}
- [(set_attr "type" "xfer,fpstore")
+ [(set_attr "type" "mfc,fpstore")
(set_attr "mode" "SF")])
+;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
+;; value in the low word.
+(define_insn "mthc1"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (unspec:DF [(match_operand:SI 1 "general_operand" "dJ")
+ (match_operand:DF 2 "register_operand" "0")]
+ UNSPEC_MTHC1))]
+ "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
+ "mthc1\t%z1,%0"
+ [(set_attr "type" "mtc")
+ (set_attr "mode" "SF")])
+
+;; Move high word of operand 1 to operand 0 using mfhc1. The corresponding
+;; low-word move is done in the normal way.
+(define_insn "mfhc1"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:DF 1 "register_operand" "f")]
+ UNSPEC_MFHC1))]
+ "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
+ "mfhc1\t%0,%1"
+ [(set_attr "type" "mfc")
+ (set_attr "mode" "SF")])
+
+;; Move a constant that satisfies CONST_GP_P into operand 0.
+(define_expand "load_const_gp"
+ [(set (match_operand 0 "register_operand" "=d")
+ (const (unspec [(const_int 0)] UNSPEC_GP)))])
+
;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
;; of _gp from the start of this function. Operand 1 is the incoming
;; function address.
-(define_insn_and_split "loadgp"
+(define_insn_and_split "loadgp_newabi"
[(unspec_volatile [(match_operand 0 "" "")
(match_operand 1 "register_operand" "")] UNSPEC_LOADGP)]
- "TARGET_ABICALLS && TARGET_NEWABI"
+ "mips_current_loadgp_style () == LOADGP_NEWABI"
"#"
""
[(set (match_dup 2) (match_dup 3))
}
[(set_attr "length" "12")])
+;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
+(define_insn_and_split "loadgp_absolute"
+ [(unspec_volatile [(match_operand 0 "" "")] UNSPEC_LOADGP)]
+ "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
+ "#"
+ ""
+ [(const_int 0)]
+{
+ mips_emit_move (pic_offset_table_rtx, operands[0]);
+ DONE;
+}
+ [(set_attr "length" "8")])
+
;; The use of gp is hidden when not using explicit relocations.
;; This blockage instruction prevents the gp load from being
;; scheduled after an implicit use of gp. It also prevents
(set_attr "mode" "none")
(set_attr "length" "0")])
+;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
+;; and operand 1 is the __GOTT_INDEX__ symbol.
+(define_insn "loadgp_rtp"
+ [(unspec_volatile [(match_operand 0 "symbol_ref_operand")
+ (match_operand 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
+ "mips_current_loadgp_style () == LOADGP_RTP"
+ "#"
+ [(set_attr "length" "12")])
+
+(define_split
+ [(unspec_volatile [(match_operand:P 0 "symbol_ref_operand")
+ (match_operand:P 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
+ "mips_current_loadgp_style () == LOADGP_RTP"
+ [(set (match_dup 2) (high:P (match_dup 3)))
+ (set (match_dup 2) (unspec:P [(match_dup 2)
+ (match_dup 3)] UNSPEC_LOAD_GOT))
+ (set (match_dup 2) (unspec:P [(match_dup 2)
+ (match_dup 4)] UNSPEC_LOAD_GOT))]
+{
+ operands[2] = pic_offset_table_rtx;
+ operands[3] = mips_unspec_address (operands[0], SYMBOL_ABSOLUTE);
+ operands[4] = mips_unspec_address (operands[1], SYMBOL_HALF);
+})
+
;; Emit a .cprestore directive, which normally expands to a single store
;; instruction. Note that we continue to use .cprestore for explicit reloc
;; code so that jals inside inline asms will work correctly.
(define_insn "cprestore"
- [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")]
+ [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")
+ (use (reg:SI 28))]
UNSPEC_CPRESTORE)]
""
{
}
[(set_attr "type" "store")
(set_attr "length" "4,12")])
+
+;; Expand in-line code to clear the instruction cache between operand[0] and
+;; operand[1].
+(define_expand "clear_cache"
+ [(match_operand 0 "pmode_register_operand")
+ (match_operand 1 "pmode_register_operand")]
+ ""
+ "
+{
+ if (ISA_HAS_SYNCI)
+ {
+ mips_expand_synci_loop (operands[0], operands[1]);
+ emit_insn (gen_sync ());
+ emit_insn (gen_clear_hazard ());
+ }
+ else if (mips_cache_flush_func && mips_cache_flush_func[0])
+ {
+ rtx len = gen_reg_rtx (Pmode);
+ emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
+ /* Flush both caches. We need to flush the data cache in case
+ the system has a write-back cache. */
+ emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func),
+ 0, VOIDmode, 3, operands[0], Pmode, len, Pmode,
+ GEN_INT (3), TYPE_MODE (integer_type_node));
+ }
+ DONE;
+}")
+
+(define_insn "sync"
+ [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
+ "ISA_HAS_SYNC"
+ "sync")
+
+(define_insn "synci"
+ [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
+ UNSPEC_SYNCI)]
+ "ISA_HAS_SYNCI"
+ "synci\t0(%0)")
+
+(define_insn "rdhwr"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec_volatile [(match_operand:SI 1 "const_int_operand" "n")]
+ UNSPEC_RDHWR))]
+ "ISA_HAS_SYNCI"
+ "rdhwr\t%0,$%1")
+
+(define_insn "clear_hazard"
+ [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
+ (clobber (reg:SI 31))]
+ "ISA_HAS_SYNCI"
+{
+ return ".set\tpush\n"
+ "\t.set\tnoreorder\n"
+ "\t.set\tnomacro\n"
+ "\tbal\t1f\n"
+ "\tnop\n"
+ "1:\taddiu\t$31,$31,12\n"
+ "\tjr.hb\t$31\n"
+ "\tnop\n"
+ "\t.set\tpop";
+}
+ [(set_attr "length" "20")])
+
+;; Atomic memory operations.
+
+(define_expand "memory_barrier"
+ [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
+ "ISA_HAS_SYNC"
+ "")
+
+(define_insn "sync_compare_and_swap<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=&d,d")
+ (match_operand:GPR 1 "memory_operand" "+R,R"))
+ (set (match_dup 1)
+ (unspec_volatile:GPR [(match_operand:GPR 2 "register_operand" "d,d")
+ (match_operand:GPR 3 "arith_operand" "I,d")]
+ UNSPEC_COMPARE_AND_SWAP))]
+ "ISA_HAS_LL_SC"
+{
+ if (which_alternative == 0)
+ return MIPS_COMPARE_AND_SWAP ("<d>", "li");
+ else
+ return MIPS_COMPARE_AND_SWAP ("<d>", "move");
+}
+ [(set_attr "length" "28")])
+
+(define_insn "sync_add<mode>"
+ [(set (match_operand:GPR 0 "memory_operand" "+R,R")
+ (unspec_volatile:GPR
+ [(plus:GPR (match_dup 0)
+ (match_operand:GPR 1 "arith_operand" "I,d"))]
+ UNSPEC_SYNC_OLD_OP))]
+ "ISA_HAS_LL_SC"
+{
+ if (which_alternative == 0)
+ return MIPS_SYNC_OP ("<d>", "<d>addiu");
+ else
+ return MIPS_SYNC_OP ("<d>", "<d>addu");
+}
+ [(set_attr "length" "24")])
+
+(define_insn "sync_sub<mode>"
+ [(set (match_operand:GPR 0 "memory_operand" "+R")
+ (unspec_volatile:GPR
+ [(minus:GPR (match_dup 0)
+ (match_operand:GPR 1 "register_operand" "d"))]
+ UNSPEC_SYNC_OLD_OP))]
+ "ISA_HAS_LL_SC"
+{
+ return MIPS_SYNC_OP ("<d>", "<d>subu");
+}
+ [(set_attr "length" "24")])
+
+(define_insn "sync_old_add<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=&d,d")
+ (match_operand:GPR 1 "memory_operand" "+R,R"))
+ (set (match_dup 1)
+ (unspec_volatile:GPR
+ [(plus:GPR (match_dup 1)
+ (match_operand:GPR 2 "arith_operand" "I,d"))]
+ UNSPEC_SYNC_OLD_OP))]
+ "ISA_HAS_LL_SC"
+{
+ if (which_alternative == 0)
+ return MIPS_SYNC_OLD_OP ("<d>", "<d>addiu");
+ else
+ return MIPS_SYNC_OLD_OP ("<d>", "<d>addu");
+}
+ [(set_attr "length" "24")])
+
+(define_insn "sync_old_sub<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=&d")
+ (match_operand:GPR 1 "memory_operand" "+R"))
+ (set (match_dup 1)
+ (unspec_volatile:GPR
+ [(minus:GPR (match_dup 1)
+ (match_operand:GPR 2 "register_operand" "d"))]
+ UNSPEC_SYNC_OLD_OP))]
+ "ISA_HAS_LL_SC"
+{
+ return MIPS_SYNC_OLD_OP ("<d>", "<d>subu");
+}
+ [(set_attr "length" "24")])
+
+(define_insn "sync_new_add<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=&d,d")
+ (plus:GPR (match_operand:GPR 1 "memory_operand" "+R,R")
+ (match_operand:GPR 2 "arith_operand" "I,d")))
+ (set (match_dup 1)
+ (unspec_volatile:GPR
+ [(plus:GPR (match_dup 1) (match_dup 2))]
+ UNSPEC_SYNC_NEW_OP))]
+ "ISA_HAS_LL_SC"
+{
+ if (which_alternative == 0)
+ return MIPS_SYNC_NEW_OP ("<d>", "<d>addiu");
+ else
+ return MIPS_SYNC_NEW_OP ("<d>", "<d>addu");
+}
+ [(set_attr "length" "24")])
+
+(define_insn "sync_new_sub<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=&d")
+ (minus:GPR (match_operand:GPR 1 "memory_operand" "+R")
+ (match_operand:GPR 2 "register_operand" "d")))
+ (set (match_dup 1)
+ (unspec_volatile:GPR
+ [(minus:GPR (match_dup 1) (match_dup 2))]
+ UNSPEC_SYNC_NEW_OP))]
+ "ISA_HAS_LL_SC"
+{
+ return MIPS_SYNC_NEW_OP ("<d>", "<d>subu");
+}
+ [(set_attr "length" "24")])
+
+(define_insn "sync_<optab><mode>"
+ [(set (match_operand:GPR 0 "memory_operand" "+R,R")
+ (unspec_volatile:GPR
+ [(fetchop_bit:GPR (match_operand:GPR 1 "uns_arith_operand" "K,d")
+ (match_dup 0))]
+ UNSPEC_SYNC_OLD_OP))]
+ "ISA_HAS_LL_SC"
+{
+ if (which_alternative == 0)
+ return MIPS_SYNC_OP ("<d>", "<immediate_insn>");
+ else
+ return MIPS_SYNC_OP ("<d>", "<insn>");
+}
+ [(set_attr "length" "24")])
+
+(define_insn "sync_old_<optab><mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=&d,d")
+ (match_operand:GPR 1 "memory_operand" "+R,R"))
+ (set (match_dup 1)
+ (unspec_volatile:GPR
+ [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
+ (match_dup 1))]
+ UNSPEC_SYNC_OLD_OP))]
+ "ISA_HAS_LL_SC"
+{
+ if (which_alternative == 0)
+ return MIPS_SYNC_OLD_OP ("<d>", "<immediate_insn>");
+ else
+ return MIPS_SYNC_OLD_OP ("<d>", "<insn>");
+}
+ [(set_attr "length" "24")])
+
+(define_insn "sync_new_<optab><mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=&d,d")
+ (match_operand:GPR 1 "memory_operand" "+R,R"))
+ (set (match_dup 1)
+ (unspec_volatile:GPR
+ [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
+ (match_dup 1))]
+ UNSPEC_SYNC_NEW_OP))]
+ "ISA_HAS_LL_SC"
+{
+ if (which_alternative == 0)
+ return MIPS_SYNC_NEW_OP ("<d>", "<immediate_insn>");
+ else
+ return MIPS_SYNC_NEW_OP ("<d>", "<insn>");
+}
+ [(set_attr "length" "24")])
+
+(define_insn "sync_nand<mode>"
+ [(set (match_operand:GPR 0 "memory_operand" "+R,R")
+ (unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")]
+ UNSPEC_SYNC_OLD_OP))]
+ "ISA_HAS_LL_SC"
+{
+ if (which_alternative == 0)
+ return MIPS_SYNC_NAND ("<d>", "andi");
+ else
+ return MIPS_SYNC_NAND ("<d>", "and");
+}
+ [(set_attr "length" "28")])
+
+(define_insn "sync_old_nand<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=&d,d")
+ (match_operand:GPR 1 "memory_operand" "+R,R"))
+ (set (match_dup 1)
+ (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
+ UNSPEC_SYNC_OLD_OP))]
+ "ISA_HAS_LL_SC"
+{
+ if (which_alternative == 0)
+ return MIPS_SYNC_OLD_NAND ("<d>", "andi");
+ else
+ return MIPS_SYNC_OLD_NAND ("<d>", "and");
+}
+ [(set_attr "length" "28")])
+
+(define_insn "sync_new_nand<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=&d,d")
+ (match_operand:GPR 1 "memory_operand" "+R,R"))
+ (set (match_dup 1)
+ (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
+ UNSPEC_SYNC_NEW_OP))]
+ "ISA_HAS_LL_SC"
+{
+ if (which_alternative == 0)
+ return MIPS_SYNC_NEW_NAND ("<d>", "andi");
+ else
+ return MIPS_SYNC_NEW_NAND ("<d>", "and");
+}
+ [(set_attr "length" "28")])
+
+(define_insn "sync_lock_test_and_set<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=&d,d")
+ (match_operand:GPR 1 "memory_operand" "+R,R"))
+ (set (match_dup 1)
+ (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
+ UNSPEC_SYNC_EXCHANGE))]
+ "ISA_HAS_LL_SC"
+{
+ if (which_alternative == 0)
+ return MIPS_SYNC_EXCHANGE ("<d>", "li");
+ else
+ return MIPS_SYNC_EXCHANGE ("<d>", "move");
+}
+ [(set_attr "length" "24")])
\f
;; Block moves, see mips.c for more details.
;; Argument 0 is the destination
[(set (match_operand:GPR 0 "register_operand" "=d")
(rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:SI 2 "arith_operand" "dI")))]
- "ISA_HAS_ROTR_<MODE>"
+ "ISA_HAS_ROR"
{
if (GET_CODE (operands[2]) == CONST_INT)
gcc_assert (INTVAL (operands[2]) >= 0
;; Conditional branches on floating-point equality tests.
-(define_insn "branch_fp"
+(define_insn "*branch_fp"
[(set (pc)
(if_then_else
- (match_operator:CC 0 "comparison_operator"
- [(match_operand:CC 2 "register_operand" "z")
- (const_int 0)])
+ (match_operator 0 "equality_operator"
+ [(match_operand:CC 2 "register_operand" "z")
+ (const_int 0)])
(label_ref (match_operand 1 "" ""))
(pc)))]
"TARGET_HARD_FLOAT"
{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/1,
- /*inverted_p=*/0,
- get_attr_length (insn));
+ return mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("b%F0", "%Z2%1"),
+ MIPS_BRANCH ("b%W0", "%Z2%1"));
}
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
-(define_insn "branch_fp_inverted"
+(define_insn "*branch_fp_inverted"
[(set (pc)
(if_then_else
- (match_operator:CC 0 "comparison_operator"
- [(match_operand:CC 2 "register_operand" "z")
- (const_int 0)])
+ (match_operator 0 "equality_operator"
+ [(match_operand:CC 2 "register_operand" "z")
+ (const_int 0)])
(pc)
(label_ref (match_operand 1 "" ""))))]
"TARGET_HARD_FLOAT"
{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/1,
- /*inverted_p=*/1,
- get_attr_length (insn));
+ return mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("b%W0", "%Z2%1"),
+ MIPS_BRANCH ("b%F0", "%Z2%1"));
}
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
-;; Conditional branches on comparisons with zero.
+;; Conditional branches on ordered comparisons with zero.
-(define_insn "*branch_zero<mode>"
+(define_insn "*branch_order<mode>"
[(set (pc)
(if_then_else
- (match_operator:GPR 0 "comparison_operator"
- [(match_operand:GPR 2 "register_operand" "d")
- (const_int 0)])
+ (match_operator 0 "order_operator"
+ [(match_operand:GPR 2 "register_operand" "d")
+ (const_int 0)])
(label_ref (match_operand 1 "" ""))
(pc)))]
"!TARGET_MIPS16"
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/0,
- /*inverted_p=*/0,
- get_attr_length (insn));
-}
+ { return mips_output_order_conditional_branch (insn, operands, false); }
[(set_attr "type" "branch")
(set_attr "mode" "none")])
-(define_insn "*branch_zero<mode>_inverted"
+(define_insn "*branch_order<mode>_inverted"
[(set (pc)
(if_then_else
- (match_operator:GPR 0 "comparison_operator"
- [(match_operand:GPR 2 "register_operand" "d")
- (const_int 0)])
+ (match_operator 0 "order_operator"
+ [(match_operand:GPR 2 "register_operand" "d")
+ (const_int 0)])
(pc)
(label_ref (match_operand 1 "" ""))))]
"!TARGET_MIPS16"
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/0,
- /*inverted_p=*/1,
- get_attr_length (insn));
-}
+ { return mips_output_order_conditional_branch (insn, operands, true); }
[(set_attr "type" "branch")
(set_attr "mode" "none")])
(define_insn "*branch_equality<mode>"
[(set (pc)
(if_then_else
- (match_operator:GPR 0 "equality_operator"
- [(match_operand:GPR 2 "register_operand" "d")
- (match_operand:GPR 3 "register_operand" "d")])
+ (match_operator 0 "equality_operator"
+ [(match_operand:GPR 2 "register_operand" "d")
+ (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
(label_ref (match_operand 1 "" ""))
(pc)))]
"!TARGET_MIPS16"
{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/1,
- /*float_p=*/0,
- /*inverted_p=*/0,
- get_attr_length (insn));
+ return mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
+ MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
}
[(set_attr "type" "branch")
(set_attr "mode" "none")])
(define_insn "*branch_equality<mode>_inverted"
[(set (pc)
(if_then_else
- (match_operator:GPR 0 "equality_operator"
- [(match_operand:GPR 2 "register_operand" "d")
- (match_operand:GPR 3 "register_operand" "d")])
+ (match_operator 0 "equality_operator"
+ [(match_operand:GPR 2 "register_operand" "d")
+ (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
(pc)
(label_ref (match_operand 1 "" ""))))]
"!TARGET_MIPS16"
{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/1,
- /*float_p=*/0,
- /*inverted_p=*/1,
- get_attr_length (insn));
+ return mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
+ MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
}
[(set_attr "type" "branch")
(set_attr "mode" "none")])
(define_insn "*branch_equality<mode>_mips16"
[(set (pc)
(if_then_else
- (match_operator:GPR 0 "equality_operator"
- [(match_operand:GPR 1 "register_operand" "d,t")
- (const_int 0)])
+ (match_operator 0 "equality_operator"
+ [(match_operand:GPR 1 "register_operand" "d,t")
+ (const_int 0)])
(match_operand 2 "pc_or_label_operand" "")
(match_operand 3 "pc_or_label_operand" "")))]
"TARGET_MIPS16"
gen_conditional_branch (operands, <CODE>);
DONE;
})
+
+;; Used to implement built-in functions.
+(define_expand "condjump"
+ [(set (pc)
+ (if_then_else (match_operand 0)
+ (label_ref (match_operand 1))
+ (pc)))])
\f
;;
;; ....................
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
-(define_insn "sgt_<mode>"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (gt:CC (match_operand:SCALARF 1 "register_operand" "f")
- (match_operand:SCALARF 2 "register_operand" "f")))]
- ""
- "c.lt.<fmt>\t%Z0%2,%1"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sge_<mode>"
+(define_insn "s<code>_<mode>"
[(set (match_operand:CC 0 "register_operand" "=z")
- (ge:CC (match_operand:SCALARF 1 "register_operand" "f")
- (match_operand:SCALARF 2 "register_operand" "f")))]
+ (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
+ (match_operand:SCALARF 2 "register_operand" "f")))]
""
- "c.le.<fmt>\t%Z0%2,%1"
+ "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
\f
(use (label_ref (match_operand 1 "")))]
""
{
- if (TARGET_MIPS16)
+ if (TARGET_MIPS16_SHORT_JUMP_TABLES)
operands[0] = expand_binop (Pmode, add_optab,
convert_to_mode (Pmode, operands[0], false),
gen_rtx_LABEL_REF (Pmode, operands[1]),
else if (TARGET_GPWORD)
operands[0] = expand_binop (Pmode, add_optab, operands[0],
pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
+ else if (TARGET_RTP_PIC)
+ {
+ /* When generating RTP PIC, we use case table entries that are relative
+ to the start of the function. Add the function's address to the
+ value we loaded. */
+ rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
+ operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
+ start, 0, 0, OPTAB_WIDEN);
+ }
if (Pmode == SImode)
emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
[(set_attr "type" "jump")
(set_attr "mode" "none")])
-;; For TARGET_ABICALLS, we save the gp in the jmp_buf as well.
+;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
;; While it is possible to either pull it off the stack (in the
;; o32 case) or recalculate it given t9 and our target label,
;; it takes 3 or 4 insns to do so.
(define_expand "builtin_setjmp_setup"
[(use (match_operand 0 "register_operand"))]
- "TARGET_ABICALLS"
+ "TARGET_USE_GOT"
{
rtx addr;
addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
- emit_move_insn (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
+ mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
DONE;
})
(define_expand "builtin_longjmp"
[(use (match_operand 0 "register_operand"))]
- "TARGET_ABICALLS"
+ "TARGET_USE_GOT"
{
/* The elements of the buffer are, in order: */
int W = GET_MODE_SIZE (Pmode);
/* This bit is similar to expand_builtin_longjmp except that it
restores $gp as well. */
- emit_move_insn (hard_frame_pointer_rtx, fp);
- emit_move_insn (pv, lab);
+ mips_emit_move (hard_frame_pointer_rtx, fp);
+ mips_emit_move (pv, lab);
emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
- emit_move_insn (gp, gpv);
+ mips_emit_move (gp, gpv);
emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
emit_insn (gen_rtx_USE (VOIDmode, gp));
DONE;
})
-(define_insn_and_split "exception_receiver"
+(define_insn_and_split "nonlocal_goto_receiver"
[(set (reg:SI 28)
- (unspec_volatile:SI [(const_int 0)] UNSPEC_EH_RECEIVER))]
- "TARGET_ABICALLS && TARGET_OLDABI"
+ (unspec_volatile:SI [(const_int 0)] UNSPEC_NONLOCAL_GOTO_RECEIVER))]
+ "TARGET_CALL_CLOBBERED_GP"
"#"
"&& reload_completed"
[(const_int 0)]
;; we tell the target-independent code that the address could be changed
;; by any call insn.
(define_insn "load_call<mode>"
- [(set (match_operand:P 0 "register_operand" "=c")
+ [(set (match_operand:P 0 "register_operand" "=d")
(unspec:P [(match_operand:P 1 "register_operand" "r")
(match_operand:P 2 "immediate_operand" "")
(reg:P FAKE_CALL_REGNO)]
UNSPEC_LOAD_CALL))]
- "TARGET_ABICALLS"
+ "TARGET_USE_GOT"
"<load>\t%0,%R2(%1)"
[(set_attr "type" "load")
(set_attr "mode" "<MODE>")
;; constraints.
;; When we use an indirect jump, we need a register that will be
-;; preserved by the epilogue. Since TARGET_ABICALLS forces us to
-;; use $25 for this purpose -- and $25 is never clobbered by the
-;; epilogue -- we might as well use it for !TARGET_ABICALLS as well.
+;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
+;; us to use $25 for this purpose -- and $25 is never clobbered by the
+;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
+;; as well.
(define_expand "sibcall"
[(parallel [(call (match_operand 0 "")
[(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
(match_operand 1 "" ""))]
"TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
- "@
- %*jr\t%0%/
- %*j\t%0%/"
+ { return MIPS_CALL ("j", operands, 0); }
[(set_attr "type" "call")])
(define_expand "sibcall_value"
})
(define_insn "sibcall_value_internal"
- [(set (match_operand 0 "register_operand" "=df,df")
+ [(set (match_operand 0 "register_operand" "")
(call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
(match_operand 2 "" "")))]
"TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
- "@
- %*jr\t%1%/
- %*j\t%1%/"
+ { return MIPS_CALL ("j", operands, 1); }
[(set_attr "type" "call")])
(define_insn "sibcall_value_multiple_internal"
- [(set (match_operand 0 "register_operand" "=df,df")
+ [(set (match_operand 0 "register_operand" "")
(call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
(match_operand 2 "" "")))
- (set (match_operand 3 "register_operand" "=df,df")
+ (set (match_operand 3 "register_operand" "")
(call (mem:SI (match_dup 1))
(match_dup 2)))]
"TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
- "@
- %*jr\t%1%/
- %*j\t%1%/"
+ { return MIPS_CALL ("j", operands, 1); }
[(set_attr "type" "call")])
(define_expand "call"
(match_operand 1 "" ""))
(clobber (reg:SI 31))]
""
- { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%0%/"; }
+ { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
"reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
[(const_int 0)]
{
[(set_attr "jal" "indirect,direct")
(set_attr "extended_mips16" "no,yes")])
+;; A pattern for calls that must be made directly. It is used for
+;; MIPS16 calls that the linker may need to redirect to a hard-float
+;; stub; the linker relies on the call relocation type to detect when
+;; such redirection is needed.
+(define_insn "call_internal_direct"
+ [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
+ (match_operand 1))
+ (const_int 1)
+ (clobber (reg:SI 31))]
+ ""
+ { return MIPS_CALL ("jal", operands, 0); })
+
(define_insn "call_split"
- [(call (mem:SI (match_operand 0 "call_insn_operand" "c"))
+ [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
(match_operand 1 "" ""))
(clobber (reg:SI 31))
(clobber (reg:SI 28))]
"TARGET_SPLIT_CALLS"
- "%*jalr\t%0%/"
+ { return MIPS_CALL ("jal", operands, 0); }
[(set_attr "type" "call")])
(define_expand "call_value"
;; See comment for call_internal.
(define_insn_and_split "call_value_internal"
- [(set (match_operand 0 "register_operand" "=df,df")
+ [(set (match_operand 0 "register_operand" "")
(call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
(match_operand 2 "" "")))
(clobber (reg:SI 31))]
""
- { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%1%/"; }
+ { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
"reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
[(const_int 0)]
{
(set_attr "extended_mips16" "no,yes")])
(define_insn "call_value_split"
- [(set (match_operand 0 "register_operand" "=df")
- (call (mem:SI (match_operand 1 "call_insn_operand" "c"))
+ [(set (match_operand 0 "register_operand" "")
+ (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
(match_operand 2 "" "")))
(clobber (reg:SI 31))
(clobber (reg:SI 28))]
"TARGET_SPLIT_CALLS"
- "%*jalr\t%1%/"
+ { return MIPS_CALL ("jal", operands, 1); }
[(set_attr "type" "call")])
+;; See call_internal_direct.
+(define_insn "call_value_internal_direct"
+ [(set (match_operand 0 "register_operand")
+ (call (mem:SI (match_operand 1 "const_call_insn_operand"))
+ (match_operand 2)))
+ (const_int 1)
+ (clobber (reg:SI 31))]
+ ""
+ { return MIPS_CALL ("jal", operands, 1); })
+
;; See comment for call_internal.
(define_insn_and_split "call_value_multiple_internal"
- [(set (match_operand 0 "register_operand" "=df,df")
+ [(set (match_operand 0 "register_operand" "")
(call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
(match_operand 2 "" "")))
- (set (match_operand 3 "register_operand" "=df,df")
+ (set (match_operand 3 "register_operand" "")
(call (mem:SI (match_dup 1))
(match_dup 2)))
(clobber (reg:SI 31))]
""
- { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%1%/"; }
+ { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
"reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
[(const_int 0)]
{
(set_attr "extended_mips16" "no,yes")])
(define_insn "call_value_multiple_split"
- [(set (match_operand 0 "register_operand" "=df")
- (call (mem:SI (match_operand 1 "call_insn_operand" "c"))
+ [(set (match_operand 0 "register_operand" "")
+ (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
(match_operand 2 "" "")))
- (set (match_operand 3 "register_operand" "=df")
+ (set (match_operand 3 "register_operand" "")
(call (mem:SI (match_dup 1))
(match_dup 2)))
(clobber (reg:SI 31))
(clobber (reg:SI 28))]
"TARGET_SPLIT_CALLS"
- "%*jalr\t%1%/"
+ { return MIPS_CALL ("jal", operands, 1); }
[(set_attr "type" "call")])
;; Call subroutine returning any type.
for (i = 0; i < XVECLEN (operands[2], 0); i++)
{
rtx set = XVECEXP (operands[2], 0, i);
- emit_move_insn (SET_DEST (set), SET_SRC (set));
+ mips_emit_move (SET_DEST (set), SET_SRC (set));
}
emit_insn (gen_blockage ());
"reload_completed"
[(match_dup 0)]
{ operands[0] = mips_rewrite_small_data (operands[0]); })
+
+;;
+;; ....................
+;;
+;; MIPS16e Save/Restore
+;;
+;; ....................
+;;
+
+(define_insn "*mips16e_save_restore"
+ [(match_parallel 0 ""
+ [(set (match_operand:SI 1 "register_operand")
+ (plus:SI (match_dup 1)
+ (match_operand:SI 2 "const_int_operand")))])]
+ "operands[1] == stack_pointer_rtx
+ && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
+ { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
+ [(set_attr "type" "arith")
+ (set_attr "extended_mips16" "yes")])
+
+; Thread-Local Storage
+
+; The TLS base pointer is accessed via "rdhwr $v1, $29". No current
+; MIPS architecture defines this register, and no current
+; implementation provides it; instead, any OS which supports TLS is
+; expected to trap and emulate this instruction. rdhwr is part of the
+; MIPS 32r2 specification, but we use it on any architecture because
+; we expect it to be emulated. Use .set to force the assembler to
+; accept it.
+
+(define_insn "tls_get_tp_<mode>"
+ [(set (match_operand:P 0 "register_operand" "=v")
+ (unspec:P [(const_int 0)]
+ UNSPEC_TLS_GET_TP))]
+ "HAVE_AS_TLS && !TARGET_MIPS16"
+ ".set\tpush\;.set\tmips32r2\t\;rdhwr\t%0,$29\;.set\tpop"
+ [(set_attr "type" "unknown")
+ ; Since rdhwr always generates a trap for now, putting it in a delay
+ ; slot would make the kernel's emulation of it much slower.
+ (set_attr "can_delay" "no")
+ (set_attr "mode" "<MODE>")])
\f
; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
(include "mips-ps-3d.md")
+
+; The MIPS DSP Instructions.
+
+(include "mips-dsp.md")
+
+; The MIPS DSP REV 2 Instructions.
+
+(include "mips-dspr2.md")
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