(UNSPEC_ADDRESS_FIRST 100)
- (FAKE_CALL_REGNO 79)])
+ (FAKE_CALL_REGNO 79)
+
+ ;; For MIPS Paired-Singled Floating Point Instructions.
+
+ (UNSPEC_MOVE_TF_PS 200)
+ (UNSPEC_C 201)
+
+ ;; MIPS64/MIPS32R2 alnv.ps
+ (UNSPEC_ALNV_PS 202)
+
+ ;; MIPS-3D instructions
+ (UNSPEC_CABS 203)
+
+ (UNSPEC_ADDR_PS 204)
+ (UNSPEC_CVT_PW_PS 205)
+ (UNSPEC_CVT_PS_PW 206)
+ (UNSPEC_MULR_PS 207)
+
+ (UNSPEC_RSQRT1 208)
+ (UNSPEC_RSQRT2 209)
+ (UNSPEC_RECIP1 210)
+ (UNSPEC_RECIP2 211)
+ ]
+)
(include "predicates.md")
\f
;; fmadd floating point multiply-add
;; fdiv floating point divide
;; frdiv floating point reciprocal divide
+;; frdiv1 floating point reciprocal divide step 1
+;; frdiv2 floating point reciprocal divide step 2
;; fabs floating point absolute value
;; fneg floating point negation
;; fcmp floating point compare
;; fcvt floating point convert
;; fsqrt floating point square root
;; frsqrt floating point reciprocal square root
+;; frsqrt1 floating point reciprocal square root step1
+;; frsqrt2 floating point reciprocal square root step2
;; multi multiword sequence (or user asm statements)
;; nop no operation
(define_attr "type"
- "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
+ "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
(cond [(eq_attr "jal" "!unset") (const_string "call")
(eq_attr "got" "load") (const_string "load")]
(const_string "unknown")))
;; pointer-sized quantities. Exactly one of the two alternatives will match.
(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
+;; This mode macro allows :MOVECC to be used anywhere that a
+;; conditional-move-type condition is needed.
+(define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
+
+;; This mode macro allows :ANYF to be used wherever a scalar or vector
+;; floating-point mode is allowed.
+(define_mode_macro ANYF [(SF "TARGET_HARD_FLOAT")
+ (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
+ (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
+
+;; Like ANYF, but only applies to scalar modes.
+(define_mode_macro SCALARF [(SF "TARGET_HARD_FLOAT")
+ (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
+
;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
;; 32-bit version and "dsubu" in the 64-bit version.
(define_mode_attr d [(SI "") (DI "d")])
(define_mode_attr load [(SI "lw") (DI "ld")])
(define_mode_attr store [(SI "sw") (DI "sd")])
+;; Similarly for MIPS IV indexed FPR loads and stores.
+(define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1")])
+(define_mode_attr storex [(SF "swxc1") (DF "sdxc1")])
+
;; The unextended ranges of the MIPS16 addiu and daddiu instructions
;; are different. Some forms of unextended addiu have an 8-bit immediate
;; field but the equivalent daddiu has only a 5-bit field.
(define_mode_attr si8_di5 [(SI "8") (DI "5")])
+;; This attribute gives the best constraint to use for registers of
+;; a given mode.
+(define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
+
+;; This attribute gives the format suffix for floating-point operations.
+(define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
+
+;; This attribute gives the upper-case mode name for one unit of a
+;; floating-point mode.
+(define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
+
+;; This attribute works around the early SB-1 rev2 core "F2" erratum:
+;;
+;; In certain cases, div.s and div.ps may have a rounding error
+;; and/or wrong inexact flag.
+;;
+;; Therefore, we only allow div.s if not working around SB-1 rev2
+;; errata or if a slight loss of precision is OK.
+(define_mode_attr divide_condition
+ [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")])
+
;; This code macro allows all branch instructions to be generated from
;; a single define_expand template.
(define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
;; to use the same template.
(define_code_macro any_extend [sign_extend zero_extend])
+;; This code macro allows the three shift instructions to be generated
+;; from the same template.
+(define_code_macro any_shift [ashift ashiftrt lshiftrt])
+
+;; This code macro allows all native floating-point comparisons to be
+;; generated from the same template.
+(define_code_macro fcond [unordered uneq unlt unle eq lt le])
+
;; <u> expands to an empty string when doing a signed operation and
;; "u" when doing an unsigned operation.
(define_code_attr u [(sign_extend "") (zero_extend "u")])
;; <su> is like <u>, but the signed form expands to "s" rather than "".
(define_code_attr su [(sign_extend "s") (zero_extend "u")])
+
+;; <optab> expands to the name of the optab for a particular code.
+(define_code_attr optab [(ashift "ashl")
+ (ashiftrt "ashr")
+ (lshiftrt "lshr")])
+
+;; <insn> expands to the name of the insn that implements a particular code.
+(define_code_attr insn [(ashift "sll")
+ (ashiftrt "sra")
+ (lshiftrt "srl")])
+
+;; <fcond> is the c.cond.fmt condition associated with a particular code.
+(define_code_attr fcond [(unordered "un")
+ (uneq "ueq")
+ (unlt "ult")
+ (unle "ule")
+ (eq "eq")
+ (lt "lt")
+ (le "le")])
\f
;; .........................
;;
else
return "break";
}
- [(set_attr "type" "trap")])
+ [(set_attr "type" "trap")])
(define_expand "conditional_trap"
[(trap_if (match_operator 0 "comparison_operator"
(match_operand 1 "const_int_operand"))]
"ISA_HAS_COND_TRAP"
{
- if (operands[1] == const0_rtx)
+ if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
+ && operands[1] == const0_rtx)
{
mips_gen_conditional_trap (operands);
DONE;
FAIL;
})
-(define_insn ""
- [(trap_if (match_operator 0 "trap_comparison_operator"
- [(match_operand:SI 1 "reg_or_0_operand" "dJ")
- (match_operand:SI 2 "arith_operand" "dI")])
+(define_insn "*conditional_trap<mode>"
+ [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
+ [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
+ (match_operand:GPR 2 "arith_operand" "dI")])
(const_int 0))]
"ISA_HAS_COND_TRAP"
- "t%C0\t%z1,%z2"
- [(set_attr "type" "trap")])
-
-(define_insn ""
- [(trap_if (match_operator 0 "trap_comparison_operator"
- [(match_operand:DI 1 "reg_or_0_operand" "dJ")
- (match_operand:DI 2 "arith_operand" "dI")])
- (const_int 0))]
- "TARGET_64BIT && ISA_HAS_COND_TRAP"
- "t%C0\t%z1,%z2"
- [(set_attr "type" "trap")])
+ "t%C0\t%z1,%2"
+ [(set_attr "type" "trap")])
\f
;;
;; ....................
;; ....................
;;
-(define_insn "adddf3"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (plus:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "add.d\t%0,%1,%2"
- [(set_attr "type" "fadd")
- (set_attr "mode" "DF")])
-
-(define_insn "addsf3"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (plus:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "add.s\t%0,%1,%2"
- [(set_attr "type" "fadd")
- (set_attr "mode" "SF")])
+(define_insn "add<mode>3"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f")))]
+ ""
+ "add.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fadd")
+ (set_attr "mode" "<UNITMODE>")])
(define_expand "add<mode>3"
[(set (match_operand:GPR 0 "register_operand")
;; ....................
;;
-(define_insn "subdf3"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (minus:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "sub.d\t%0,%1,%2"
- [(set_attr "type" "fadd")
- (set_attr "mode" "DF")])
-
-(define_insn "subsf3"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (minus:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "sub.s\t%0,%1,%2"
- [(set_attr "type" "fadd")
- (set_attr "mode" "SF")])
+(define_insn "sub<mode>3"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f")))]
+ ""
+ "sub.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fadd")
+ (set_attr "mode" "<UNITMODE>")])
(define_insn "sub<mode>3"
[(set (match_operand:GPR 0 "register_operand" "=d")
;; ....................
;;
-(define_expand "muldf3"
- [(set (match_operand:DF 0 "register_operand")
- (mult:DF (match_operand:DF 1 "register_operand")
- (match_operand:DF 2 "register_operand")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+(define_expand "mul<mode>3"
+ [(set (match_operand:SCALARF 0 "register_operand")
+ (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
+ (match_operand:SCALARF 2 "register_operand")))]
+ ""
"")
-(define_insn "muldf3_internal"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (mult:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_4300_MUL_FIX"
- "mul.d\t%0,%1,%2"
- [(set_attr "type" "fmul")
- (set_attr "mode" "DF")])
+(define_insn "*mul<mode>3"
+ [(set (match_operand:SCALARF 0 "register_operand" "=f")
+ (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
+ (match_operand:SCALARF 2 "register_operand" "f")))]
+ "!TARGET_4300_MUL_FIX"
+ "mul.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmul")
+ (set_attr "mode" "<MODE>")])
;; Early VR4300 silicon has a CPU bug where multiplies with certain
;; operands may corrupt immediately following multiplies. This is a
;; simple fix to insert NOPs.
-(define_insn "muldf3_r4300"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (mult:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_4300_MUL_FIX"
- "mul.d\t%0,%1,%2\;nop"
- [(set_attr "type" "fmul")
- (set_attr "mode" "DF")
- (set_attr "length" "8")])
-
-(define_expand "mulsf3"
- [(set (match_operand:SF 0 "register_operand")
- (mult:SF (match_operand:SF 1 "register_operand")
- (match_operand:SF 2 "register_operand")))]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "mulsf3_internal"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (mult:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && !TARGET_4300_MUL_FIX"
- "mul.s\t%0,%1,%2"
- [(set_attr "type" "fmul")
- (set_attr "mode" "SF")])
-
-;; See muldf3_r4300.
-
-(define_insn "mulsf3_r4300"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (mult:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_4300_MUL_FIX"
- "mul.s\t%0,%1,%2\;nop"
- [(set_attr "type" "fmul")
- (set_attr "mode" "SF")
- (set_attr "length" "8")])
+(define_insn "*mul<mode>3_r4300"
+ [(set (match_operand:SCALARF 0 "register_operand" "=f")
+ (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
+ (match_operand:SCALARF 2 "register_operand" "f")))]
+ "TARGET_4300_MUL_FIX"
+ "mul.<fmt>\t%0,%1,%2\;nop"
+ [(set_attr "type" "fmul")
+ (set_attr "mode" "<MODE>")
+ (set_attr "length" "8")])
+(define_insn "mulv2sf3"
+ [(set (match_operand:V2SF 0 "register_operand" "=f")
+ (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
+ (match_operand:V2SF 2 "register_operand" "f")))]
+ "TARGET_PAIRED_SINGLE_FLOAT"
+ "mul.ps\t%0,%1,%2"
+ [(set_attr "type" "fmul")
+ (set_attr "mode" "SF")])
;; The original R4000 has a cpu bug. If a double-word or a variable
;; shift executes while an integer multiplication is in progress, the
;; Floating point multiply accumulate instructions.
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f"))
- (match_operand:DF 3 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
- "madd.d\t%0,%3,%1,%2"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f"))
- (match_operand:SF 3 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
- "madd.s\t%0,%3,%1,%2"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f"))
- (match_operand:DF 3 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
- "msub.d\t%0,%3,%1,%2"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f"))
- (match_operand:SF 3 "register_operand" "f")))]
-
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
- "msub.s\t%0,%3,%1,%2"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f"))
- (match_operand:DF 3 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
- && TARGET_FUSED_MADD && HONOR_SIGNED_ZEROS (DFmode)"
- "nmadd.d\t%0,%3,%1,%2"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "f"))
- (match_operand:DF 2 "register_operand" "f"))
- (match_operand:DF 3 "register_operand" "f")))]
- "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
- && TARGET_FUSED_MADD && !HONOR_SIGNED_ZEROS (DFmode)"
- "nmadd.d\t%0,%3,%1,%2"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f"))
- (match_operand:SF 3 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD
- && HONOR_SIGNED_ZEROS (SFmode)"
- "nmadd.s\t%0,%3,%1,%2"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
- (match_operand:SF 2 "register_operand" "f"))
- (match_operand:SF 3 "register_operand" "f")))]
- "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD
- && !HONOR_SIGNED_ZEROS (SFmode)"
- "nmadd.s\t%0,%3,%1,%2"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (minus:DF (mult:DF (match_operand:DF 2 "register_operand" "f")
- (match_operand:DF 3 "register_operand" "f"))
- (match_operand:DF 1 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
- && TARGET_FUSED_MADD && HONOR_SIGNED_ZEROS (DFmode)"
- "nmsub.d\t%0,%1,%2,%3"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (minus:DF (match_operand:DF 1 "register_operand" "f")
- (mult:DF (match_operand:DF 2 "register_operand" "f")
- (match_operand:DF 3 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
- && TARGET_FUSED_MADD && !HONOR_SIGNED_ZEROS (DFmode)"
- "nmsub.d\t%0,%1,%2,%3"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (minus:SF (mult:SF (match_operand:SF 2 "register_operand" "f")
- (match_operand:SF 3 "register_operand" "f"))
- (match_operand:SF 1 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD
- && HONOR_SIGNED_ZEROS (SFmode)"
- "nmsub.s\t%0,%1,%2,%3"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (minus:SF (match_operand:SF 1 "register_operand" "f")
- (mult:SF (match_operand:SF 2 "register_operand" "f")
- (match_operand:SF 3 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD
- && !HONOR_SIGNED_ZEROS (SFmode)"
- "nmsub.s\t%0,%1,%2,%3"
- [(set_attr "type" "fmadd")
- (set_attr "mode" "SF")])
+(define_insn "*madd<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "f")))]
+ "ISA_HAS_FP4 && TARGET_FUSED_MADD"
+ "madd.<fmt>\t%0,%3,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*msub<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "f")))]
+ "ISA_HAS_FP4 && TARGET_FUSED_MADD"
+ "msub.<fmt>\t%0,%3,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmadd<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (neg:ANYF (plus:ANYF
+ (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "f"))))]
+ "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
+ && HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "nmadd.<fmt>\t%0,%3,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmadd<mode>_fastmath"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (minus:ANYF
+ (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "f")))]
+ "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
+ && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "nmadd.<fmt>\t%0,%3,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmsub<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (neg:ANYF (minus:ANYF
+ (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
+ (match_operand:ANYF 3 "register_operand" "f"))
+ (match_operand:ANYF 1 "register_operand" "f"))))]
+ "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
+ && HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "nmsub.<fmt>\t%0,%1,%2,%3"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmsub<mode>_fastmath"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (minus:ANYF
+ (match_operand:ANYF 1 "register_operand" "f")
+ (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
+ (match_operand:ANYF 3 "register_operand" "f"))))]
+ "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
+ && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "nmsub.<fmt>\t%0,%1,%2,%3"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
\f
;;
;; ....................
;; ....................
;;
-(define_expand "divdf3"
- [(set (match_operand:DF 0 "register_operand")
- (div:DF (match_operand:DF 1 "reg_or_1_operand")
- (match_operand:DF 2 "register_operand")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+(define_expand "div<mode>3"
+ [(set (match_operand:SCALARF 0 "register_operand")
+ (div:SCALARF (match_operand:SCALARF 1 "reg_or_1_operand")
+ (match_operand:SCALARF 2 "register_operand")))]
+ "<divide_condition>"
{
- if (const_1_operand (operands[1], DFmode))
+ if (const_1_operand (operands[1], <MODE>mode))
if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
- operands[1] = force_reg (DFmode, operands[1]);
+ operands[1] = force_reg (<MODE>mode, operands[1]);
})
-;; This pattern works around the early SB-1 rev2 core "F1" erratum:
+;; These patterns work around the early SB-1 rev2 core "F1" erratum:
;;
;; If an mfc1 or dmfc1 happens to access the floating point register
;; file at the same time a long latency operation (div, sqrt, recip,
;; The workaround is to insert an unconditional 'mov' from/to the
;; long latency op destination register.
-(define_insn "*divdf3"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (div:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-{
- if (TARGET_FIX_SB1)
- return "div.d\t%0,%1,%2\;mov.d\t%0,%0";
- else
- return "div.d\t%0,%1,%2";
-}
- [(set_attr "type" "fdiv")
- (set_attr "mode" "DF")
- (set (attr "length")
- (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
- (const_int 8)
- (const_int 4)))])
-
-
-;; This pattern works around the early SB-1 rev2 core "F2" erratum:
-;;
-;; In certain cases, div.s and div.ps may have a rounding error
-;; and/or wrong inexact flag.
-;;
-;; Therefore, we only allow div.s if not working around SB-1 rev2
-;; errata, or if working around those errata and a slight loss of
-;; precision is OK (i.e., flag_unsafe_math_optimizations is set).
-(define_expand "divsf3"
- [(set (match_operand:SF 0 "register_operand")
- (div:SF (match_operand:SF 1 "reg_or_1_operand")
- (match_operand:SF 2 "register_operand")))]
- "TARGET_HARD_FLOAT && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)"
-{
- if (const_1_operand (operands[1], SFmode))
- if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
- operands[1] = force_reg (SFmode, operands[1]);
-})
-
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-;;
-;; This pattern works around the early SB-1 rev2 core "F2" erratum (see
-;; "divsf3" comment for details).
-(define_insn "*divsf3"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (div:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)"
-{
- if (TARGET_FIX_SB1)
- return "div.s\t%0,%1,%2\;mov.s\t%0,%0";
- else
- return "div.s\t%0,%1,%2";
-}
- [(set_attr "type" "fdiv")
- (set_attr "mode" "SF")
- (set (attr "length")
- (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
- (const_int 8)
- (const_int 4)))])
-
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (div:DF (match_operand:DF 1 "const_1_operand" "")
- (match_operand:DF 2 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
+(define_insn "*div<mode>3"
+ [(set (match_operand:SCALARF 0 "register_operand" "=f")
+ (div:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
+ (match_operand:SCALARF 2 "register_operand" "f")))]
+ "<divide_condition>"
{
if (TARGET_FIX_SB1)
- return "recip.d\t%0,%2\;mov.d\t%0,%0";
+ return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
else
- return "recip.d\t%0,%2";
+ return "div.<fmt>\t%0,%1,%2";
}
- [(set_attr "type" "frdiv")
- (set_attr "mode" "DF")
+ [(set_attr "type" "fdiv")
+ (set_attr "mode" "<MODE>")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
(const_int 8)
(const_int 4)))])
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (div:SF (match_operand:SF 1 "const_1_operand" "")
- (match_operand:SF 2 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
+(define_insn "*recip<mode>3"
+ [(set (match_operand:SCALARF 0 "register_operand" "=f")
+ (div:SCALARF (match_operand:SCALARF 1 "const_1_operand" "")
+ (match_operand:SCALARF 2 "register_operand" "f")))]
+ "ISA_HAS_FP4 && flag_unsafe_math_optimizations"
{
if (TARGET_FIX_SB1)
- return "recip.s\t%0,%2\;mov.s\t%0,%0";
+ return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
else
- return "recip.s\t%0,%2";
+ return "recip.<fmt>\t%0,%2";
}
- [(set_attr "type" "frdiv")
- (set_attr "mode" "SF")
+ [(set_attr "type" "frdiv")
+ (set_attr "mode" "<MODE>")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
(const_int 8)
;;
;; ....................
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-(define_insn "sqrtdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && HAVE_SQRT_P() && TARGET_DOUBLE_FLOAT"
-{
- if (TARGET_FIX_SB1)
- return "sqrt.d\t%0,%1\;mov.d\t%0,%0";
- else
- return "sqrt.d\t%0,%1";
-}
- [(set_attr "type" "fsqrt")
- (set_attr "mode" "DF")
- (set (attr "length")
- (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
- (const_int 8)
- (const_int 4)))])
-
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-(define_insn "sqrtsf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
-{
- if (TARGET_FIX_SB1)
- return "sqrt.s\t%0,%1\;mov.s\t%0,%0";
- else
- return "sqrt.s\t%0,%1";
-}
- [(set_attr "type" "fsqrt")
- (set_attr "mode" "SF")
- (set (attr "length")
- (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
- (const_int 8)
- (const_int 4)))])
-
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (div:DF (match_operand:DF 1 "const_1_operand" "")
- (sqrt:DF (match_operand:DF 2 "register_operand" "f"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
-{
- if (TARGET_FIX_SB1)
- return "rsqrt.d\t%0,%2\;mov.d\t%0,%0";
- else
- return "rsqrt.d\t%0,%2";
-}
- [(set_attr "type" "frsqrt")
- (set_attr "mode" "DF")
- (set (attr "length")
- (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
- (const_int 8)
- (const_int 4)))])
+;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
+;; "*div[sd]f3" comment for details).
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (div:SF (match_operand:SF 1 "const_1_operand" "")
- (sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
+(define_insn "sqrt<mode>2"
+ [(set (match_operand:SCALARF 0 "register_operand" "=f")
+ (sqrt:SCALARF (match_operand:SCALARF 1 "register_operand" "f")))]
+ "HAVE_SQRT_P()"
{
if (TARGET_FIX_SB1)
- return "rsqrt.s\t%0,%2\;mov.s\t%0,%0";
+ return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
else
- return "rsqrt.s\t%0,%2";
+ return "sqrt.<fmt>\t%0,%1";
}
- [(set_attr "type" "frsqrt")
- (set_attr "mode" "SF")
+ [(set_attr "type" "fsqrt")
+ (set_attr "mode" "<MODE>")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
(const_int 8)
(const_int 4)))])
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (sqrt:DF (div:DF (match_operand:DF 1 "const_1_operand" "")
- (match_operand:DF 2 "register_operand" "f"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
+(define_insn "*rsqrt<mode>a"
+ [(set (match_operand:SCALARF 0 "register_operand" "=f")
+ (div:SCALARF
+ (match_operand:SCALARF 1 "const_1_operand" "")
+ (sqrt:SCALARF (match_operand:SCALARF 2 "register_operand" "f"))))]
+ "ISA_HAS_FP4 && flag_unsafe_math_optimizations"
{
if (TARGET_FIX_SB1)
- return "rsqrt.d\t%0,%2\;mov.d\t%0,%0";
+ return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
else
- return "rsqrt.d\t%0,%2";
+ return "rsqrt.<fmt>\t%0,%2";
}
- [(set_attr "type" "frsqrt")
- (set_attr "mode" "DF")
+ [(set_attr "type" "frsqrt")
+ (set_attr "mode" "<MODE>")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
(const_int 8)
(const_int 4)))])
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (sqrt:SF (div:SF (match_operand:SF 1 "const_1_operand" "")
- (match_operand:SF 2 "register_operand" "f"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
+(define_insn "*rsqrt<mode>b"
+ [(set (match_operand:SCALARF 0 "register_operand" "=f")
+ (sqrt:SCALARF
+ (div:SCALARF (match_operand:SCALARF 1 "const_1_operand" "")
+ (match_operand:SCALARF 2 "register_operand" "f"))))]
+ "ISA_HAS_FP4 && flag_unsafe_math_optimizations"
{
if (TARGET_FIX_SB1)
- return "rsqrt.s\t%0,%2\;mov.s\t%0,%0";
+ return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
else
- return "rsqrt.s\t%0,%2";
+ return "rsqrt.<fmt>\t%0,%2";
}
- [(set_attr "type" "frsqrt")
- (set_attr "mode" "SF")
+ [(set_attr "type" "frsqrt")
+ (set_attr "mode" "<MODE>")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
(const_int 8)
(set_attr "mode" "<MODE>")
(set_attr "length" "12")])
-(define_insn "absdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (abs:DF (match_operand:DF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "abs.d\t%0,%1"
- [(set_attr "type" "fabs")
- (set_attr "mode" "DF")])
-
-(define_insn "abssf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (abs:SF (match_operand:SF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "abs.s\t%0,%1"
- [(set_attr "type" "fabs")
- (set_attr "mode" "SF")])
+(define_insn "abs<mode>2"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
+ ""
+ "abs.<fmt>\t%0,%1"
+ [(set_attr "type" "fabs")
+ (set_attr "mode" "<UNITMODE>")])
\f
;;
;; ....................
[(set_attr "type" "arith")
(set_attr "mode" "DI")])
-(define_insn "negdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (match_operand:DF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "neg.d\t%0,%1"
- [(set_attr "type" "fneg")
- (set_attr "mode" "DF")])
-
-(define_insn "negsf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (match_operand:SF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "neg.s\t%0,%1"
- [(set_attr "type" "fneg")
- (set_attr "mode" "SF")])
+(define_insn "neg<mode>2"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
+ ""
+ "neg.<fmt>\t%0,%1"
+ [(set_attr "type" "fneg")
+ (set_attr "mode" "<UNITMODE>")])
(define_insn "one_cmpl<mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d")
;; dsll op0,op0,16
;; daddiu op0,op0,%hi(op1)
;; dsll op0,op0,16
+;;
+;; The split is deferred until after flow2 to allow the peephole2 below
+;; to take effect.
(define_insn_and_split "*lea_high64"
[(set (match_operand:DI 0 "register_operand" "=d")
(high:DI (match_operand:DI 1 "general_symbolic_operand" "")))]
"TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
"#"
- "&& reload_completed"
+ "&& flow2_completed"
[(set (match_dup 0) (high:DI (match_dup 2)))
(set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
}
[(set_attr "length" "20")])
+;; Use a scratch register to reduce the latency of the above pattern
+;; on superscalar machines. The optimized sequence is:
+;;
+;; lui op1,%highest(op2)
+;; lui op0,%hi(op2)
+;; daddiu op1,op1,%higher(op2)
+;; dsll32 op1,op1,0
+;; daddu op1,op1,op0
+(define_peephole2
+ [(match_scratch:DI 0 "d")
+ (set (match_operand:DI 1 "register_operand")
+ (high:DI (match_operand:DI 2 "general_symbolic_operand")))]
+ "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
+ [(set (match_dup 1) (high:DI (match_dup 3)))
+ (set (match_dup 0) (high:DI (match_dup 4)))
+ (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
+ (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
+ (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
+{
+ operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
+ operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
+})
+
;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
;; SYMBOL_GENERAL X will take 6 cycles. This next pattern allows combine
;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
;; these instructions can only be used to load and store floating
;; point registers, that would probably cause trouble in reload.
-(define_insn "*lwxc1_<mode>"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (mem:SF (plus:P (match_operand:P 1 "register_operand" "d")
- (match_operand:P 2 "register_operand" "d"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
- "lwxc1\t%0,%1(%2)"
- [(set_attr "type" "fpidxload")
- (set_attr "mode" "SF")])
-
-(define_insn "*ldxc1_<mode>"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (mem:DF (plus:P (match_operand:P 1 "register_operand" "d")
- (match_operand:P 2 "register_operand" "d"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "ldxc1\t%0,%1(%2)"
+(define_insn "*<ANYF:loadx>_<P:mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
+ (match_operand:P 2 "register_operand" "d"))))]
+ "ISA_HAS_FP4"
+ "<ANYF:loadx>\t%0,%1(%2)"
[(set_attr "type" "fpidxload")
- (set_attr "mode" "DF")])
-
-(define_insn "*swxc1_<mode>"
- [(set (mem:SF (plus:P (match_operand:P 1 "register_operand" "d")
- (match_operand:P 2 "register_operand" "d")))
- (match_operand:SF 0 "register_operand" "f"))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
- "swxc1\t%0,%1(%2)"
+ (set_attr "mode" "<ANYF:UNITMODE>")])
+
+(define_insn "*<ANYF:storex>_<P:mode>"
+ [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
+ (match_operand:P 2 "register_operand" "d")))
+ (match_operand:ANYF 0 "register_operand" "f"))]
+ "ISA_HAS_FP4"
+ "<ANYF:storex>\t%0,%1(%2)"
[(set_attr "type" "fpidxstore")
- (set_attr "mode" "SF")])
-
-(define_insn "*sdxc1_<mode>"
- [(set (mem:DF (plus:P (match_operand:P 1 "register_operand" "d")
- (match_operand:P 2 "register_operand" "d")))
- (match_operand:DF 0 "register_operand" "f"))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "sdxc1\t%0,%1(%2)"
- [(set_attr "type" "fpidxstore")
- (set_attr "mode" "DF")])
+ (set_attr "mode" "<ANYF:UNITMODE>")])
;; 16-bit Integer moves
operands[3] = GEN_INT (-INTVAL (operands[1]));
})
+;; 64-bit paired-single floating point moves
+
+(define_expand "movv2sf"
+ [(set (match_operand:V2SF 0)
+ (match_operand:V2SF 1))]
+ "TARGET_PAIRED_SINGLE_FLOAT"
+{
+ if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
+ DONE;
+})
+
+(define_insn "movv2sf_hardfloat_64bit"
+ [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m")
+ (match_operand:V2SF 1 "move_operand" "f,YG,m,fYG,*d,*f,*d*YG,*m,*d"))]
+ "TARGET_PAIRED_SINGLE_FLOAT
+ && TARGET_64BIT
+ && (register_operand (operands[0], V2SFmode)
+ || reg_or_0_operand (operands[1], V2SFmode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "type" "fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store")
+ (set_attr "mode" "SF")
+ (set_attr "length" "4,4,*,*,4,4,4,*,*")])
+
;; The HI and LO registers are not truly independent. If we move an mthi
;; instruction before an mflo instruction, it will make the result of the
;; mflo unpredictable. The same goes for mtlo and mfhi.
;;
;; ....................
-;; Many of these instructions use trivial define_expands, because we
-;; want to use a different set of constraints when TARGET_MIPS16.
-
-(define_expand "ashlsi3"
- [(set (match_operand:SI 0 "register_operand")
- (ashift:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "arith_operand")))]
+(define_expand "<optab><mode>3"
+ [(set (match_operand:GPR 0 "register_operand")
+ (any_shift:GPR (match_operand:GPR 1 "register_operand")
+ (match_operand:SI 2 "arith_operand")))]
""
{
/* On the mips16, a shift of more than 8 is a four byte instruction,
&& GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) > 8
&& INTVAL (operands[2]) <= 16
- && ! reload_in_progress
- && ! reload_completed)
+ && !reload_in_progress
+ && !reload_completed)
{
- rtx temp = gen_reg_rtx (SImode);
+ rtx temp = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_ashlsi3_internal2 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_ashlsi3_internal2 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
+ emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
+ emit_insn (gen_<optab><mode>3 (operands[0], temp,
+ GEN_INT (INTVAL (operands[2]) - 8)));
DONE;
}
})
-(define_insn "ashlsi3_internal1"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ashift:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
+(define_insn "*<optab><mode>3"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:SI 2 "arith_operand" "dI")))]
"!TARGET_MIPS16"
{
if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+ operands[2] = GEN_INT (INTVAL (operands[2])
+ & (GET_MODE_BITSIZE (<MODE>mode) - 1));
- return "sll\t%0,%1,%2";
+ return "<d><insn>\t%0,%1,%2";
}
- [(set_attr "type" "shift")
- (set_attr "mode" "SI")])
+ [(set_attr "type" "shift")
+ (set_attr "mode" "<MODE>")])
-(define_insn "ashlsi3_internal1_extend"
+(define_insn "*<optab>si3_extend"
[(set (match_operand:DI 0 "register_operand" "=d")
- (sign_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI"))))]
+ (sign_extend:DI
+ (any_shift:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "arith_operand" "dI"))))]
"TARGET_64BIT && !TARGET_MIPS16"
{
if (GET_CODE (operands[2]) == CONST_INT)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- return "sll\t%0,%1,%2";
+ return "<insn>\t%0,%1,%2";
}
- [(set_attr "type" "shift")
- (set_attr "mode" "DI")])
+ [(set_attr "type" "shift")
+ (set_attr "mode" "SI")])
-
-(define_insn "ashlsi3_internal2"
+(define_insn "*<optab>si3_mips16"
[(set (match_operand:SI 0 "register_operand" "=d,d")
- (ashift:SI (match_operand:SI 1 "register_operand" "0,d")
- (match_operand:SI 2 "arith_operand" "d,I")))]
+ (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
+ (match_operand:SI 2 "arith_operand" "d,I")))]
"TARGET_MIPS16"
{
if (which_alternative == 0)
- return "sll\t%0,%2";
-
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+ return "<insn>\t%0,%2";
- return "sll\t%0,%1,%2";
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+ return "<insn>\t%0,%1,%2";
}
- [(set_attr "type" "shift")
- (set_attr "mode" "SI")
+ [(set_attr "type" "shift")
+ (set_attr "mode" "SI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b")
+ (if_then_else (match_operand 2 "m16_uimm3_b")
(const_int 4)
(const_int 8))])])
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
- [(set (match_operand:SI 0 "register_operand")
- (ashift:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "const_int_operand")))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))]
- { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
-
-(define_expand "ashldi3"
- [(set (match_operand:DI 0 "register_operand")
- (ashift:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "arith_operand")))]
- "TARGET_64BIT"
-{
- /* On the mips16, a shift of more than 8 is a four byte
- instruction, so, for a shift between 8 and 16, it is just as
- fast to do two shifts of 8 or less. If there is a lot of
- shifting going on, we may win in CSE. Otherwise combine will
- put the shifts back together again. This can be called by
- function_arg, so we must be careful not to allocate a new
- register if we've reached the reload pass. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16
- && ! reload_in_progress
- && ! reload_completed)
- {
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_ashldi3_internal (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_ashldi3_internal (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-})
-
-
-(define_insn "ashldi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "TARGET_64BIT && !TARGET_MIPS16"
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
- return "dsll\t%0,%1,%2";
-}
- [(set_attr "type" "shift")
- (set_attr "mode" "DI")])
-
-(define_insn ""
+;; We need separate DImode MIPS16 patterns because of the irregularity
+;; of right shifts.
+(define_insn "*ashldi3_mips16"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(ashift:DI (match_operand:DI 1 "register_operand" "0,d")
(match_operand:SI 2 "arith_operand" "d,I")))]
if (which_alternative == 0)
return "dsll\t%0,%2";
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
return "dsll\t%0,%1,%2";
}
- [(set_attr "type" "shift")
- (set_attr "mode" "DI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b")
- (const_int 4)
- (const_int 8))])])
-
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (ashift:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "const_int_operand")))]
- "TARGET_MIPS16 && TARGET_64BIT && !TARGET_DEBUG_D_MODE
- && reload_completed
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (ashift:DI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))]
- { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
-
-(define_expand "ashrsi3"
- [(set (match_operand:SI 0 "register_operand")
- (ashiftrt:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "arith_operand")))]
- ""
-{
- /* On the mips16, a shift of more than 8 is a four byte instruction,
- so, for a shift between 8 and 16, it is just as fast to do two
- shifts of 8 or less. If there is a lot of shifting going on, we
- may win in CSE. Otherwise combine will put the shifts back
- together again. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16)
- {
- rtx temp = gen_reg_rtx (SImode);
-
- emit_insn (gen_ashrsi3_internal2 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_ashrsi3_internal2 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-})
-
-(define_insn "ashrsi3_internal1"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "!TARGET_MIPS16"
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
- return "sra\t%0,%1,%2";
-}
- [(set_attr "type" "shift")
- (set_attr "mode" "SI")])
-
-(define_insn "ashrsi3_internal2"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
- (match_operand:SI 2 "arith_operand" "d,I")))]
- "TARGET_MIPS16"
-{
- if (which_alternative == 0)
- return "sra\t%0,%2";
-
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
- return "sra\t%0,%1,%2";
-}
- [(set_attr "type" "shift")
- (set_attr "mode" "SI")
+ [(set_attr "type" "shift")
+ (set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b")
+ (if_then_else (match_operand 2 "m16_uimm3_b")
(const_int 4)
(const_int 8))])])
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
- [(set (match_operand:SI 0 "register_operand")
- (ashiftrt:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "const_int_operand")))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
- { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
-
-(define_expand "ashrdi3"
- [(set (match_operand:DI 0 "register_operand")
- (ashiftrt:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "arith_operand")))]
- "TARGET_64BIT"
-{
- /* On the mips16, a shift of more than 8 is a four byte
- instruction, so, for a shift between 8 and 16, it is just as
- fast to do two shifts of 8 or less. If there is a lot of
- shifting going on, we may win in CSE. Otherwise combine will
- put the shifts back together again. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16)
- {
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_ashrdi3_internal (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_ashrdi3_internal (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-})
-
-
-(define_insn "ashrdi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "TARGET_64BIT && !TARGET_MIPS16"
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
- return "dsra\t%0,%1,%2";
-}
- [(set_attr "type" "shift")
- (set_attr "mode" "DI")])
-
-(define_insn ""
+(define_insn "*ashrdi3_mips16"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:SI 2 "arith_operand" "d,I")))]
return "dsra\t%0,%2";
}
- [(set_attr "type" "shift")
- (set_attr "mode" "DI")
+ [(set_attr "type" "shift")
+ (set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b")
+ (if_then_else (match_operand 2 "m16_uimm3_b")
(const_int 4)
(const_int 8))])])
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (ashiftrt:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "const_int_operand")))]
- "TARGET_MIPS16 && TARGET_64BIT && !TARGET_DEBUG_D_MODE
- && reload_completed
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (ashiftrt:DI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (ashiftrt:DI (match_dup 0) (match_dup 2)))]
- { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
-
-(define_expand "lshrsi3"
- [(set (match_operand:SI 0 "register_operand")
- (lshiftrt:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "arith_operand")))]
- ""
-{
- /* On the mips16, a shift of more than 8 is a four byte instruction,
- so, for a shift between 8 and 16, it is just as fast to do two
- shifts of 8 or less. If there is a lot of shifting going on, we
- may win in CSE. Otherwise combine will put the shifts back
- together again. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16)
- {
- rtx temp = gen_reg_rtx (SImode);
-
- emit_insn (gen_lshrsi3_internal2 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_lshrsi3_internal2 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-})
-
-(define_insn "lshrsi3_internal1"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "!TARGET_MIPS16"
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
- return "srl\t%0,%1,%2";
-}
- [(set_attr "type" "shift")
- (set_attr "mode" "SI")])
-
-(define_insn "lshrsi3_internal2"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
+(define_insn "*lshrdi3_mips16"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:SI 2 "arith_operand" "d,I")))]
- "TARGET_MIPS16"
+ "TARGET_64BIT && TARGET_MIPS16"
{
- if (which_alternative == 0)
- return "srl\t%0,%2";
-
if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
- return "srl\t%0,%1,%2";
+ return "dsrl\t%0,%2";
}
- [(set_attr "type" "shift")
- (set_attr "mode" "SI")
+ [(set_attr "type" "shift")
+ (set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b")
+ (if_then_else (match_operand 2 "m16_uimm3_b")
(const_int 4)
(const_int 8))])])
-
;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
(define_split
- [(set (match_operand:SI 0 "register_operand")
- (lshiftrt:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "const_int_operand")))]
+ [(set (match_operand:GPR 0 "register_operand")
+ (any_shift:GPR (match_operand:GPR 1 "register_operand")
+ (match_operand:GPR 2 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
&& GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) > 8
&& INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
+ [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
+ (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
{ operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
;; If we load a byte on the mips16 as a bitfield, the resulting
(set_attr "mode" "SI")
(set_attr "length" "16")])
-(define_expand "lshrdi3"
- [(set (match_operand:DI 0 "register_operand")
- (lshiftrt:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "arith_operand")))]
- "TARGET_64BIT"
-{
- /* On the mips16, a shift of more than 8 is a four byte
- instruction, so, for a shift between 8 and 16, it is just as
- fast to do two shifts of 8 or less. If there is a lot of
- shifting going on, we may win in CSE. Otherwise combine will
- put the shifts back together again. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16)
- {
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_lshrdi3_internal (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_lshrdi3_internal (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-})
-
-
-(define_insn "lshrdi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "TARGET_64BIT && !TARGET_MIPS16"
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
- return "dsrl\t%0,%1,%2";
-}
- [(set_attr "type" "shift")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
- (match_operand:SI 2 "arith_operand" "d,I")))]
- "TARGET_64BIT && TARGET_MIPS16"
+(define_insn "rotr<mode>3"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:SI 2 "arith_operand" "dI")))]
+ "ISA_HAS_ROTR_<MODE>"
{
if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
+ gcc_assert (INTVAL (operands[2]) >= 0
+ && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
- return "dsrl\t%0,%2";
+ return "<d>ror\t%0,%1,%2";
}
- [(set_attr "type" "shift")
- (set_attr "mode" "DI")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b")
- (const_int 4)
- (const_int 8))])])
-
-(define_insn "rotrsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (rotatert:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dn")))]
- "ISA_HAS_ROTR_SI"
-{
- if (TARGET_SR71K && GET_CODE (operands[2]) != CONST_INT)
- return "rorv\t%0,%1,%2";
-
- if ((GET_CODE (operands[2]) == CONST_INT)
- && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) >= 32))
- abort ();
-
- return "ror\t%0,%1,%2";
-}
- [(set_attr "type" "shift")
- (set_attr "mode" "SI")])
-
-(define_insn "rotrdi3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (rotatert:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:DI 2 "arith_operand" "dn")))]
- "ISA_HAS_ROTR_DI"
-{
- if (TARGET_SR71K)
- {
- if (GET_CODE (operands[2]) != CONST_INT)
- return "drorv\t%0,%1,%2";
-
- if (INTVAL (operands[2]) >= 32 && INTVAL (operands[2]) <= 63)
- return "dror32\t%0,%1,%2";
- }
-
- if ((GET_CODE (operands[2]) == CONST_INT)
- && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) >= 64))
- abort ();
-
- return "dror\t%0,%1,%2";
-}
- [(set_attr "type" "shift")
- (set_attr "mode" "DI")])
-
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (lshiftrt:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "const_int_operand")))]
- "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16"
- [(set (match_dup 0) (lshiftrt:DI (match_dup 1) (const_int 8)))
- (set (match_dup 0) (lshiftrt:DI (match_dup 0) (match_dup 2)))]
- { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
+ [(set_attr "type" "shift")
+ (set_attr "mode" "<MODE>")])
\f
;;
;; ....................
DONE;
})
-(define_expand "cmpdf"
- [(set (cc0)
- (compare:CC (match_operand:DF 0 "register_operand")
- (match_operand:DF 1 "register_operand")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-{
- cmp_operands[0] = operands[0];
- cmp_operands[1] = operands[1];
- DONE;
-})
-
-(define_expand "cmpsf"
+(define_expand "cmp<mode>"
[(set (cc0)
- (compare:CC (match_operand:SF 0 "register_operand")
- (match_operand:SF 1 "register_operand")))]
- "TARGET_HARD_FLOAT"
+ (compare:CC (match_operand:SCALARF 0 "register_operand")
+ (match_operand:SCALARF 1 "register_operand")))]
+ ""
{
cmp_operands[0] = operands[0];
cmp_operands[1] = operands[1];
;;
;; ....................
-(define_insn "sunordered_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (unordered:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.un.d\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sunlt_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (unlt:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.ult.d\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "suneq_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (uneq:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.ueq.d\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sunle_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (unle:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.ule.d\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "seq_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (eq:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.eq.d\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "slt_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (lt:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.lt.d\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sle_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (le:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.le.d\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sgt_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (gt:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.lt.d\t%Z0%2,%1"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sge_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (ge:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.le.d\t%Z0%2,%1"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sunordered_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (unordered:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.un.s\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sunlt_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (unlt:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.ult.s\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "suneq_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (uneq:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.ueq.s\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sunle_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (unle:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.ule.s\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "seq_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (eq:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.eq.s\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "slt_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (lt:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.lt.s\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sle_sf"
+(define_insn "s<code>_<mode>"
[(set (match_operand:CC 0 "register_operand" "=z")
- (le:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.le.s\t%Z0%1,%2"
+ (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
+ (match_operand:SCALARF 2 "register_operand" "f")))]
+ ""
+ "c.<fcond>.<fmt>\t%Z0%1,%2"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
-(define_insn "sgt_sf"
+(define_insn "sgt_<mode>"
[(set (match_operand:CC 0 "register_operand" "=z")
- (gt:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.lt.s\t%Z0%2,%1"
+ (gt:CC (match_operand:SCALARF 1 "register_operand" "f")
+ (match_operand:SCALARF 2 "register_operand" "f")))]
+ ""
+ "c.lt.<fmt>\t%Z0%2,%1"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
-(define_insn "sge_sf"
+(define_insn "sge_<mode>"
[(set (match_operand:CC 0 "register_operand" "=z")
- (ge:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.le.s\t%Z0%2,%1"
+ (ge:CC (match_operand:SCALARF 1 "register_operand" "f")
+ (match_operand:SCALARF 2 "register_operand" "f")))]
+ ""
+ "c.le.<fmt>\t%Z0%2,%1"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
\f
;; acts like a GOT version number. By making the register call-clobbered,
;; we tell the target-independent code that the address could be changed
;; by any call insn.
-(define_insn "load_callsi"
- [(set (match_operand:SI 0 "register_operand" "=c")
- (unspec:SI [(match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "immediate_operand" "")
- (reg:SI FAKE_CALL_REGNO)]
- UNSPEC_LOAD_CALL))]
+(define_insn "load_call<mode>"
+ [(set (match_operand:P 0 "register_operand" "=c")
+ (unspec:P [(match_operand:P 1 "register_operand" "r")
+ (match_operand:P 2 "immediate_operand" "")
+ (reg:P FAKE_CALL_REGNO)]
+ UNSPEC_LOAD_CALL))]
"TARGET_ABICALLS"
- "lw\t%0,%R2(%1)"
- [(set_attr "type" "load")
- (set_attr "length" "4")])
-
-(define_insn "load_calldi"
- [(set (match_operand:DI 0 "register_operand" "=c")
- (unspec:DI [(match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "immediate_operand" "")
- (reg:DI FAKE_CALL_REGNO)]
- UNSPEC_LOAD_CALL))]
- "TARGET_ABICALLS"
- "ld\t%0,%R2(%1)"
+ "<load>\t%0,%R2(%1)"
[(set_attr "type" "load")
+ (set_attr "mode" "<MODE>")
(set_attr "length" "4")])
;; Sibling calls. All these patterns use jump instructions.
;;
-(define_expand "prefetch"
- [(prefetch (match_operand 0 "address_operand")
- (match_operand 1 "const_int_operand")
- (match_operand 2 "const_int_operand"))]
- "ISA_HAS_PREFETCH"
+(define_insn "prefetch"
+ [(prefetch (match_operand:QI 0 "address_operand" "p")
+ (match_operand 1 "const_int_operand" "n")
+ (match_operand 2 "const_int_operand" "n"))]
+ "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
{
- if (symbolic_operand (operands[0], GET_MODE (operands[0])))
- operands[0] = force_reg (GET_MODE (operands[0]), operands[0]);
-})
-
-(define_insn "prefetch_si_address"
- [(prefetch (plus:SI (match_operand:SI 0 "register_operand" "r")
- (match_operand:SI 3 "const_int_operand" "I"))
- (match_operand:SI 1 "const_int_operand" "n")
- (match_operand:SI 2 "const_int_operand" "n"))]
- "ISA_HAS_PREFETCH && Pmode == SImode"
- { return mips_emit_prefetch (operands); }
- [(set_attr "type" "prefetch")])
-
-(define_insn "prefetch_indexed_si"
- [(prefetch (plus:SI (match_operand:SI 0 "register_operand" "r")
- (match_operand:SI 3 "register_operand" "r"))
- (match_operand:SI 1 "const_int_operand" "n")
- (match_operand:SI 2 "const_int_operand" "n"))]
- "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && Pmode == SImode"
- { return mips_emit_prefetch (operands); }
- [(set_attr "type" "prefetchx")])
-
-(define_insn "prefetch_si"
- [(prefetch (match_operand:SI 0 "register_operand" "r")
- (match_operand:SI 1 "const_int_operand" "n")
- (match_operand:SI 2 "const_int_operand" "n"))]
- "ISA_HAS_PREFETCH && Pmode == SImode"
-{
- operands[3] = const0_rtx;
- return mips_emit_prefetch (operands);
+ operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
+ return "pref\t%1,%a0";
}
[(set_attr "type" "prefetch")])
-(define_insn "prefetch_di_address"
- [(prefetch (plus:DI (match_operand:DI 0 "register_operand" "r")
- (match_operand:DI 3 "const_int_operand" "I"))
- (match_operand:DI 1 "const_int_operand" "n")
- (match_operand:DI 2 "const_int_operand" "n"))]
- "ISA_HAS_PREFETCH && Pmode == DImode"
- { return mips_emit_prefetch (operands); }
- [(set_attr "type" "prefetch")])
-
-(define_insn "prefetch_indexed_di"
- [(prefetch (plus:DI (match_operand:DI 0 "register_operand" "r")
- (match_operand:DI 3 "register_operand" "r"))
- (match_operand:DI 1 "const_int_operand" "n")
- (match_operand:DI 2 "const_int_operand" "n"))]
- "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && Pmode == DImode"
- { return mips_emit_prefetch (operands); }
- [(set_attr "type" "prefetchx")])
-
-(define_insn "prefetch_di"
- [(prefetch (match_operand:DI 0 "register_operand" "r")
- (match_operand:DI 1 "const_int_operand" "n")
- (match_operand:DI 2 "const_int_operand" "n"))]
- "ISA_HAS_PREFETCH && Pmode == DImode"
+(define_insn "*prefetch_indexed_<mode>"
+ [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
+ (match_operand:P 1 "register_operand" "d"))
+ (match_operand 2 "const_int_operand" "n")
+ (match_operand 3 "const_int_operand" "n"))]
+ "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
{
- operands[3] = const0_rtx;
- return mips_emit_prefetch (operands);
+ operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
+ return "prefx\t%2,%1(%0)";
}
- [(set_attr "type" "prefetch")])
+ [(set_attr "type" "prefetchx")])
(define_insn "nop"
[(const_int 0)]
\f
;; MIPS4 Conditional move instructions.
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (if_then_else:SI
- (match_operator:SI 4 "equality_operator"
- [(match_operand:SI 1 "register_operand" "d,d")
- (const_int 0)])
- (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
- (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
- "@
- mov%B4\t%0,%z2,%1
- mov%b4\t%0,%z3,%1"
- [(set_attr "type" "condmove")
- (set_attr "mode" "SI")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (if_then_else:SI
- (match_operator:DI 4 "equality_operator"
- [(match_operand:DI 1 "register_operand" "d,d")
- (const_int 0)])
- (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
- (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
- "@
- mov%B4\t%0,%z2,%1
- mov%b4\t%0,%z3,%1"
- [(set_attr "type" "condmove")
- (set_attr "mode" "SI")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (if_then_else:SI
- (match_operator:CC 3 "equality_operator"
- [(match_operand:CC 4 "register_operand" "z,z")
- (const_int 0)])
- (match_operand:SI 1 "reg_or_0_operand" "dJ,0")
- (match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
- "@
- mov%T3\t%0,%z1,%4
- mov%t3\t%0,%z2,%4"
- [(set_attr "type" "condmove")
- (set_attr "mode" "SI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (if_then_else:DI
- (match_operator:SI 4 "equality_operator"
- [(match_operand:SI 1 "register_operand" "d,d")
- (const_int 0)])
- (match_operand:DI 2 "reg_or_0_operand" "dJ,0")
- (match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
- "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
- "@
- mov%B4\t%0,%z2,%1
- mov%b4\t%0,%z3,%1"
- [(set_attr "type" "condmove")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (if_then_else:DI
- (match_operator:DI 4 "equality_operator"
- [(match_operand:DI 1 "register_operand" "d,d")
- (const_int 0)])
- (match_operand:DI 2 "reg_or_0_operand" "dJ,0")
- (match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
- "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
- "@
- mov%B4\t%0,%z2,%1
- mov%b4\t%0,%z3,%1"
- [(set_attr "type" "condmove")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (if_then_else:DI
- (match_operator:CC 3 "equality_operator"
- [(match_operand:CC 4 "register_operand" "z,z")
- (const_int 0)])
- (match_operand:DI 1 "reg_or_0_operand" "dJ,0")
- (match_operand:DI 2 "reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_64BIT"
- "@
- mov%T3\t%0,%z1,%4
- mov%t3\t%0,%z2,%4"
- [(set_attr "type" "condmove")
- (set_attr "mode" "DI")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (if_then_else:SF
- (match_operator:SI 4 "equality_operator"
- [(match_operand:SI 1 "register_operand" "d,d")
- (const_int 0)])
- (match_operand:SF 2 "register_operand" "f,0")
- (match_operand:SF 3 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
- "@
- mov%B4.s\t%0,%2,%1
- mov%b4.s\t%0,%3,%1"
- [(set_attr "type" "condmove")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (if_then_else:SF
- (match_operator:DI 4 "equality_operator"
- [(match_operand:DI 1 "register_operand" "d,d")
- (const_int 0)])
- (match_operand:SF 2 "register_operand" "f,0")
- (match_operand:SF 3 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
- "@
- mov%B4.s\t%0,%2,%1
- mov%b4.s\t%0,%3,%1"
- [(set_attr "type" "condmove")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (if_then_else:SF
- (match_operator:CC 3 "equality_operator"
- [(match_operand:CC 4 "register_operand" "z,z")
- (const_int 0)])
- (match_operand:SF 1 "register_operand" "f,0")
- (match_operand:SF 2 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
- "@
- mov%T3.s\t%0,%1,%4
- mov%t3.s\t%0,%2,%4"
- [(set_attr "type" "condmove")
- (set_attr "mode" "SF")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (if_then_else:DF
- (match_operator:SI 4 "equality_operator"
- [(match_operand:SI 1 "register_operand" "d,d")
- (const_int 0)])
- (match_operand:DF 2 "register_operand" "f,0")
- (match_operand:DF 3 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "@
- mov%B4.d\t%0,%2,%1
- mov%b4.d\t%0,%3,%1"
- [(set_attr "type" "condmove")
- (set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (if_then_else:DF
- (match_operator:DI 4 "equality_operator"
- [(match_operand:DI 1 "register_operand" "d,d")
- (const_int 0)])
- (match_operand:DF 2 "register_operand" "f,0")
- (match_operand:DF 3 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+(define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (if_then_else:GPR
+ (match_operator:MOVECC 4 "equality_operator"
+ [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
+ (const_int 0)])
+ (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
+ (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
+ "ISA_HAS_CONDMOVE"
"@
- mov%B4.d\t%0,%2,%1
- mov%b4.d\t%0,%3,%1"
+ mov%T4\t%0,%z2,%1
+ mov%t4\t%0,%z3,%1"
[(set_attr "type" "condmove")
- (set_attr "mode" "DF")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (if_then_else:DF
- (match_operator:CC 3 "equality_operator"
- [(match_operand:CC 4 "register_operand" "z,z")
- (const_int 0)])
- (match_operand:DF 1 "register_operand" "f,0")
- (match_operand:DF 2 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ (set_attr "mode" "<GPR:MODE>")])
+
+(define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
+ [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
+ (if_then_else:SCALARF
+ (match_operator:MOVECC 4 "equality_operator"
+ [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
+ (const_int 0)])
+ (match_operand:SCALARF 2 "register_operand" "f,0")
+ (match_operand:SCALARF 3 "register_operand" "0,f")))]
+ "ISA_HAS_CONDMOVE"
"@
- mov%T3.d\t%0,%1,%4
- mov%t3.d\t%0,%2,%4"
+ mov%T4.<fmt>\t%0,%2,%1
+ mov%t4.<fmt>\t%0,%3,%1"
[(set_attr "type" "condmove")
- (set_attr "mode" "DF")])
+ (set_attr "mode" "<SCALARF:MODE>")])
;; These are the main define_expand's used to make conditional moves.
-(define_expand "movsicc"
+(define_expand "mov<mode>cc"
[(set (match_dup 4) (match_operand 1 "comparison_operator"))
- (set (match_operand:SI 0 "register_operand")
- (if_then_else:SI (match_dup 5)
- (match_operand:SI 2 "reg_or_0_operand")
- (match_operand:SI 3 "reg_or_0_operand")))]
- "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
+ (set (match_operand:GPR 0 "register_operand")
+ (if_then_else:GPR (match_dup 5)
+ (match_operand:GPR 2 "reg_or_0_operand")
+ (match_operand:GPR 3 "reg_or_0_operand")))]
+ "ISA_HAS_CONDMOVE"
{
gen_conditional_move (operands);
DONE;
})
-(define_expand "movdicc"
+(define_expand "mov<mode>cc"
[(set (match_dup 4) (match_operand 1 "comparison_operator"))
- (set (match_operand:DI 0 "register_operand")
- (if_then_else:DI (match_dup 5)
- (match_operand:DI 2 "reg_or_0_operand")
- (match_operand:DI 3 "reg_or_0_operand")))]
- "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
-{
- gen_conditional_move (operands);
- DONE;
-})
-
-(define_expand "movsfcc"
- [(set (match_dup 4) (match_operand 1 "comparison_operator"))
- (set (match_operand:SF 0 "register_operand")
- (if_then_else:SF (match_dup 5)
- (match_operand:SF 2 "register_operand")
- (match_operand:SF 3 "register_operand")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
-{
- gen_conditional_move (operands);
- DONE;
-})
-
-(define_expand "movdfcc"
- [(set (match_dup 4) (match_operand 1 "comparison_operator"))
- (set (match_operand:DF 0 "register_operand")
- (if_then_else:DF (match_dup 5)
- (match_operand:DF 2 "register_operand")
- (match_operand:DF 3 "register_operand")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ (set (match_operand:SCALARF 0 "register_operand")
+ (if_then_else:SCALARF (match_dup 5)
+ (match_operand:SCALARF 2 "register_operand")
+ (match_operand:SCALARF 3 "register_operand")))]
+ "ISA_HAS_CONDMOVE"
{
gen_conditional_move (operands);
DONE;
{
REAL_VALUE_TYPE d;
- if (GET_CODE (operands[0]) != CONST_DOUBLE)
- abort ();
+ gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
assemble_real (d, GET_MODE (operands[0]),
GET_MODE_BITSIZE (GET_MODE (operands[0])));
"reload_completed"
[(match_dup 0)]
{ operands[0] = mips_rewrite_small_data (operands[0]); })
+\f
+; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
+
+(include "mips-ps-3d.md")
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