More MIPS vector cleanup work.

[pf3gnuchains/gcc-fork.git] / gcc / config / mips / mips.h

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 7d83f4f..8862e58 100644 (file)
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -161,6 +161,9 @@ extern const struct mips_cpu_info *mips_tune_info;
 #define MASK_VR4130_ALIGN  0x02000000  /* Perform VR4130 alignment opts.  */
 #define MASK_FP_EXCEPTIONS 0x04000000   /* FP exceptions are enabled.  */
 
+#define MASK_PAIRED_SINGLE 0x10000000   /* Support paired-single FPU.  */
+#define MASK_MIPS3D        0x20000000   /* Support MIPS-3D instructions.  */
+
                                        /* Debug switches, not documented */
 #define MASK_DEBUG     0               /* unused */
 #define MASK_DEBUG_D   0               /* don't do define_split's */
@@ -234,6 +237,10 @@ extern const struct mips_cpu_info *mips_tune_info;
 
 #define TARGET_FP_EXCEPTIONS   ((target_flags & MASK_FP_EXCEPTIONS) != 0)
 
+#define TARGET_PAIRED_SINGLE_FLOAT     \
+                               ((target_flags & MASK_PAIRED_SINGLE) != 0)
+#define TARGET_MIPS3D          ((target_flags & MASK_MIPS3D) != 0)
+
 /* True if we should use NewABI-style relocation operators for
    symbolic addresses.  This is never true for mips16 code,
    which has its own conventions.  */
@@ -404,6 +411,9 @@ extern const struct mips_cpu_info *mips_tune_info;
       if (TARGET_MIPS16)                                       \
        builtin_define ("__mips16");                            \
                                                                \
+      if (TARGET_MIPS3D)                                       \
+       builtin_define ("__mips3d");                            \
+                                                               \
       MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info);   \
       MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info);   \
                                                                \
@@ -452,7 +462,10 @@ extern const struct mips_cpu_info *mips_tune_info;
        builtin_define ("__mips_soft_float");                   \
                                                                \
       if (TARGET_SINGLE_FLOAT)                                 \
-       builtin_define ("__mips_single_float");         \
+       builtin_define ("__mips_single_float");                 \
+                                                               \
+      if (TARGET_PAIRED_SINGLE_FLOAT)                          \
+       builtin_define ("__mips_paired_single_float");          \
                                                                \
       if (TARGET_BIG_ENDIAN)                                   \
        {                                                       \
@@ -575,6 +588,14 @@ extern const struct mips_cpu_info *mips_tune_info;
      N_("Use single (32-bit) FP only")},                               \
   {"double-float",      -MASK_SINGLE_FLOAT,                            \
      N_("Don't use single (32-bit) FP only")},                         \
+  {"paired-single",       MASK_PAIRED_SINGLE,                          \
+     N_("Use paired-single floating point instructions")},             \
+  {"no-paired-single",   -MASK_PAIRED_SINGLE,                          \
+     N_("Use paired-single floating point instructions")},             \
+  {"ips3d",               MASK_MIPS3D,                                 \
+     N_("Use MIPS-3D instructions")},                                  \
+  {"no-mips3d",          -MASK_MIPS3D,                                 \
+     N_("Use MIPS-3D instructions")},                                  \
   {"mad",                MASK_MAD,                                     \
      N_("Use multiply accumulate")},                                   \
   {"no-mad",            -MASK_MAD,                                     \
@@ -779,6 +800,7 @@ extern const struct mips_cpu_info *mips_tune_info;
                                   || TARGET_MIPS5500                    \
                                   || TARGET_MIPS7000                    \
                                   || TARGET_MIPS9000                    \
+                                 || TARGET_MAD                         \
                                   || ISA_MIPS32                                \
                                   || ISA_MIPS32R2                       \
                                   || ISA_MIPS64)                        \
@@ -823,9 +845,6 @@ extern const struct mips_cpu_info *mips_tune_info;
                                  && !TARGET_MIPS5500                    \
                                 && !TARGET_MIPS16)
 
-/* ISA has just the integer condition move instructions (movn,movz) */
-#define ISA_HAS_INT_CONDMOVE     0
-
 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
    branch on CC, and move (both FP and non-FP) on CC.  */
 #define ISA_HAS_8CC            (ISA_MIPS4                              \
@@ -1050,6 +1069,7 @@ extern const struct mips_cpu_info *mips_tune_info;
 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
 %{mips32} %{mips32r2} %{mips64} \
 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
+%{mips3d:-mips3d} \
 %{mfix-vr4120} \
 %(subtarget_asm_optimizing_spec) \
 %(subtarget_asm_debugging_spec) \
@@ -1952,9 +1972,16 @@ extern enum reg_class mips_char_to_class[256];
    `W' is for memory references that are based on a member of BASE_REG_CLASS.
         This is true for all non-mips16 references (although it can sometimes
         be indirect if !TARGET_EXPLICIT_RELOCS).  For mips16, it excludes
-        stack and constant-pool references.  */
+        stack and constant-pool references.
+   `YG' is for 0 valued vector constants.  */
 
-#define EXTRA_CONSTRAINT(OP,CODE)                                      \
+#define EXTRA_CONSTRAINT_Y(OP,STR)                                     \
+  (((STR)[1] == 'G')     ? (GET_CODE (OP) == CONST_VECTOR              \
+                            && (OP) == CONST0_RTX (GET_MODE (OP)))     \
+   : FALSE)
+
+
+#define EXTRA_CONSTRAINT_STR(OP,CODE,STR)                              \
   (((CODE) == 'Q')       ? const_arith_operand (OP, VOIDmode)          \
    : ((CODE) == 'R')     ? (GET_CODE (OP) == MEM                       \
                             && mips_fetch_insns (OP) == 1)             \
@@ -1971,8 +1998,15 @@ extern enum reg_class mips_char_to_class[256];
                             && (!TARGET_MIPS16                         \
                                 || (!stack_operand (OP, VOIDmode)      \
                                     && !CONSTANT_P (XEXP (OP, 0)))))   \
+   : ((CODE) == 'Y')     ? EXTRA_CONSTRAINT_Y (OP, STR)                \
    : FALSE)
 
+/* Y is the only multi-letter constraint, and has length 2.  */
+
+#define CONSTRAINT_LEN(C,STR)                                          \
+  (((C) == 'Y') ? 2                                                    \
+   : DEFAULT_CONSTRAINT_LEN (C, STR))
+
 /* Say which of the above are memory constraints.  */
 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')