/* Subroutines used for MIPS code generation.
Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
- 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
+ 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
Free Software Foundation, Inc.
Contributed by A. Lichnewsky, lich@inria.inria.fr.
Changes by Michael Meissner, meissner@osf.org.
#include "bitmap.h"
#include "diagnostic.h"
-/* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
+/* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
#define UNSPEC_ADDRESS_P(X) \
(GET_CODE (X) == UNSPEC \
&& XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
A signed 16-bit constant address.
ADDRESS_SYMBOLIC:
- A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
+ A constant symbolic address. */
enum mips_address_type {
ADDRESS_REG,
ADDRESS_LO_SUM,
ADDRESS_SYMBOLIC
};
-/* Classifies the prototype of a builtin function. */
-enum mips_function_type
-{
- MIPS_V2SF_FTYPE_V2SF,
- MIPS_V2SF_FTYPE_V2SF_V2SF,
- MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
- MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
- MIPS_V2SF_FTYPE_SF_SF,
- MIPS_INT_FTYPE_V2SF_V2SF,
- MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
- MIPS_INT_FTYPE_SF_SF,
- MIPS_INT_FTYPE_DF_DF,
- MIPS_SF_FTYPE_V2SF,
- MIPS_SF_FTYPE_SF,
- MIPS_SF_FTYPE_SF_SF,
- MIPS_DF_FTYPE_DF,
- MIPS_DF_FTYPE_DF_DF,
-
- /* For MIPS DSP ASE */
- MIPS_DI_FTYPE_DI_SI,
- MIPS_DI_FTYPE_DI_SI_SI,
- MIPS_DI_FTYPE_DI_V2HI_V2HI,
- MIPS_DI_FTYPE_DI_V4QI_V4QI,
- MIPS_SI_FTYPE_DI_SI,
- MIPS_SI_FTYPE_PTR_SI,
- MIPS_SI_FTYPE_SI,
- MIPS_SI_FTYPE_SI_SI,
- MIPS_SI_FTYPE_V2HI,
- MIPS_SI_FTYPE_V2HI_V2HI,
- MIPS_SI_FTYPE_V4QI,
- MIPS_SI_FTYPE_V4QI_V4QI,
- MIPS_SI_FTYPE_VOID,
- MIPS_V2HI_FTYPE_SI,
- MIPS_V2HI_FTYPE_SI_SI,
- MIPS_V2HI_FTYPE_V2HI,
- MIPS_V2HI_FTYPE_V2HI_SI,
- MIPS_V2HI_FTYPE_V2HI_V2HI,
- MIPS_V2HI_FTYPE_V4QI,
- MIPS_V2HI_FTYPE_V4QI_V2HI,
- MIPS_V4QI_FTYPE_SI,
- MIPS_V4QI_FTYPE_V2HI_V2HI,
- MIPS_V4QI_FTYPE_V4QI_SI,
- MIPS_V4QI_FTYPE_V4QI_V4QI,
- MIPS_VOID_FTYPE_SI_SI,
- MIPS_VOID_FTYPE_V2HI_V2HI,
- MIPS_VOID_FTYPE_V4QI_V4QI,
-
- /* For MIPS DSP REV 2 ASE. */
- MIPS_V4QI_FTYPE_V4QI,
- MIPS_SI_FTYPE_SI_SI_SI,
- MIPS_DI_FTYPE_DI_USI_USI,
- MIPS_DI_FTYPE_SI_SI,
- MIPS_DI_FTYPE_USI_USI,
- MIPS_V2HI_FTYPE_SI_SI_SI,
-
- /* The last type. */
+/* Macros to create an enumeration identifier for a function prototype. */
+#define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
+#define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
+#define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
+#define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
+
+/* Classifies the prototype of a built-in function. */
+enum mips_function_type {
+#define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
+#include "config/mips/mips-ftypes.def"
+#undef DEF_MIPS_FTYPE
MIPS_MAX_FTYPE_MAX
};
-/* Specifies how a builtin function should be converted into rtl. */
-enum mips_builtin_type
-{
- /* The builtin corresponds directly to an .md pattern. The return
+/* Specifies how a built-in function should be converted into rtl. */
+enum mips_builtin_type {
+ /* The function corresponds directly to an .md pattern. The return
value is mapped to operand 0 and the arguments are mapped to
operands 1 and above. */
MIPS_BUILTIN_DIRECT,
- /* The builtin corresponds directly to an .md pattern. There is no return
+ /* The function corresponds directly to an .md pattern. There is no return
value and the arguments are mapped to operands 0 and above. */
MIPS_BUILTIN_DIRECT_NO_TARGET,
- /* The builtin corresponds to a comparison instruction followed by
+ /* The function corresponds to a comparison instruction followed by
a mips_cond_move_tf_ps pattern. The first two arguments are the
values to compare and the second two arguments are the vector
operands for the movt.ps or movf.ps instruction (in assembly order). */
MIPS_BUILTIN_MOVF,
MIPS_BUILTIN_MOVT,
- /* The builtin corresponds to a V2SF comparison instruction. Operand 0
+ /* The function corresponds to a V2SF comparison instruction. Operand 0
of this instruction is the result of the comparison, which has mode
CCV2 or CCV4. The function arguments are mapped to operands 1 and
above. The function's return value is an SImode boolean that is
MIPS_BUILTIN_BPOSGE32
};
-/* Invokes MACRO (COND) for each c.cond.fmt condition. */
+/* Invoke MACRO (COND) for each C.cond.fmt condition. */
#define MIPS_FP_CONDITIONS(MACRO) \
MACRO (f), \
MACRO (un), \
MIPS_FP_CONDITIONS (STRINGIFY)
};
-/* A function to save or store a register. The first argument is the
- register and the second is the stack slot. */
-typedef void (*mips_save_restore_fn) (rtx, rtx);
+/* Information about a function's frame layout. */
+struct mips_frame_info GTY(()) {
+ /* The size of the frame in bytes. */
+ HOST_WIDE_INT total_size;
-struct mips16_constant;
-struct mips_arg_info;
-struct mips_address_info;
-struct mips_integer_op;
-struct mips_sim;
-
-static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
-static bool mips_classify_address (struct mips_address_info *, rtx,
- enum machine_mode, int);
-static bool mips_cannot_force_const_mem (rtx);
-static bool mips_use_blocks_for_constant_p (enum machine_mode, const_rtx);
-static int mips_symbol_insns (enum mips_symbol_type, enum machine_mode);
-static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
-static rtx mips_force_temporary (rtx, rtx);
-static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
-static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
-static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
-static unsigned int mips_build_lower (struct mips_integer_op *,
- unsigned HOST_WIDE_INT);
-static unsigned int mips_build_integer (struct mips_integer_op *,
- unsigned HOST_WIDE_INT);
-static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
-static int m16_check_op (rtx, int, int, int);
-static bool mips_rtx_costs (rtx, int, int, int *);
-static int mips_address_cost (rtx);
-static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
-static void mips_load_call_address (rtx, rtx, int);
-static bool mips_function_ok_for_sibcall (tree, tree);
-static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
-static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
-static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
-static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
- tree, int, struct mips_arg_info *);
-static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
-static void mips_set_architecture (const struct mips_cpu_info *);
-static void mips_set_tune (const struct mips_cpu_info *);
-static bool mips_handle_option (size_t, const char *, int);
-static struct machine_function *mips_init_machine_status (void);
-static void print_operand_reloc (FILE *, rtx, enum mips_symbol_context,
- const char **);
-static void mips_file_start (void);
-static int mips_small_data_pattern_1 (rtx *, void *);
-static int mips_rewrite_small_data_1 (rtx *, void *);
-static bool mips_function_has_gp_insn (void);
-static unsigned int mips_global_pointer (void);
-static bool mips_save_reg_p (unsigned int);
-static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
- mips_save_restore_fn);
-static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
-static void mips_output_cplocal (void);
-static void mips_emit_loadgp (void);
-static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
-static void mips_set_frame_expr (rtx);
-static rtx mips_frame_set (rtx, rtx);
-static void mips_save_reg (rtx, rtx);
-static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
-static void mips_restore_reg (rtx, rtx);
-static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
- HOST_WIDE_INT, tree);
-static section *mips_select_rtx_section (enum machine_mode, rtx,
- unsigned HOST_WIDE_INT);
-static section *mips_function_rodata_section (tree);
-static bool mips_in_small_data_p (const_tree);
-static bool mips_use_anchors_for_symbol_p (const_rtx);
-static int mips_fpr_return_fields (const_tree, tree *);
-static bool mips_return_in_msb (const_tree);
-static rtx mips_return_fpr_pair (enum machine_mode mode,
- enum machine_mode mode1, HOST_WIDE_INT,
- enum machine_mode mode2, HOST_WIDE_INT);
-static rtx mips16_gp_pseudo_reg (void);
-static void mips16_fp_args (FILE *, int, int);
-static void build_mips16_function_stub (FILE *);
-static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
-static void dump_constants (struct mips16_constant *, rtx);
-static int mips16_insn_length (rtx);
-static int mips16_rewrite_pool_refs (rtx *, void *);
-static void mips16_lay_out_constants (void);
-static void mips_sim_reset (struct mips_sim *);
-static void mips_sim_init (struct mips_sim *, state_t);
-static void mips_sim_next_cycle (struct mips_sim *);
-static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
-static int mips_sim_wait_regs_2 (rtx *, void *);
-static void mips_sim_wait_regs_1 (rtx *, void *);
-static void mips_sim_wait_regs (struct mips_sim *, rtx);
-static void mips_sim_wait_units (struct mips_sim *, rtx);
-static void mips_sim_wait_insn (struct mips_sim *, rtx);
-static void mips_sim_record_set (rtx, const_rtx, void *);
-static void mips_sim_issue_insn (struct mips_sim *, rtx);
-static void mips_sim_issue_nop (struct mips_sim *);
-static void mips_sim_finish_insn (struct mips_sim *, rtx);
-static void vr4130_avoid_branch_rt_conflict (rtx);
-static void vr4130_align_insns (void);
-static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
-static void mips_avoid_hazards (void);
-static void mips_reorg (void);
-static bool mips_strict_matching_cpu_name_p (const char *, const char *);
-static bool mips_matching_cpu_name_p (const char *, const char *);
-static const struct mips_cpu_info *mips_parse_cpu (const char *);
-static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
-static bool mips_return_in_memory (const_tree, const_tree);
-static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
-static void mips_macc_chains_record (rtx);
-static void mips_macc_chains_reorder (rtx *, int);
-static void vr4130_true_reg_dependence_p_1 (rtx, const_rtx, void *);
-static bool vr4130_true_reg_dependence_p (rtx);
-static bool vr4130_swap_insns_p (rtx, rtx);
-static void vr4130_reorder (rtx *, int);
-static void mips_promote_ready (rtx *, int, int);
-static void mips_sched_init (FILE *, int, int);
-static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
-static int mips_variable_issue (FILE *, int, rtx, int);
-static int mips_adjust_cost (rtx, rtx, rtx, int);
-static int mips_issue_rate (void);
-static int mips_multipass_dfa_lookahead (void);
-static void mips_init_libfuncs (void);
-static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
- tree, int *, int);
-static tree mips_build_builtin_va_list (void);
-static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
-static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
- const_tree, bool);
-static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
- const_tree, bool);
-static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
- tree, bool);
-static bool mips_valid_pointer_mode (enum machine_mode);
-static bool mips_vector_mode_supported_p (enum machine_mode);
-static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree, unsigned int);
-static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
-static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
-static void mips_init_builtins (void);
-static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);
-static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
- enum insn_code, enum mips_fp_condition,
- rtx, tree);
-static rtx mips_expand_builtin_compare (enum mips_builtin_type,
- enum insn_code, enum mips_fp_condition,
- rtx, tree);
-static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
-static void mips_encode_section_info (tree, rtx, int);
-static void mips_extra_live_on_entry (bitmap);
-static int mips_comp_type_attributes (const_tree, const_tree);
-static void mips_set_mips16_mode (int);
-static void mips_set_current_function (tree);
-static int mips_mode_rep_extended (enum machine_mode, enum machine_mode);
-static bool mips_offset_within_alignment_p (rtx, HOST_WIDE_INT);
-static void mips_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
-
-/* Structure to be filled in by compute_frame_size with register
- save masks, and offsets for the current function. */
-
-struct mips_frame_info GTY(())
-{
- HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
- HOST_WIDE_INT var_size; /* # bytes that variables take up */
- HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
- HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
- HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
- HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
- unsigned int mask; /* mask of saved gp registers */
- unsigned int fmask; /* mask of saved fp registers */
- HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
- HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
- HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
- HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
- bool initialized; /* true if frame size already calculated */
- int num_gp; /* number of gp registers saved */
- int num_fp; /* number of fp registers saved */
+ /* The number of bytes allocated to variables. */
+ HOST_WIDE_INT var_size;
+
+ /* The number of bytes allocated to outgoing function arguments. */
+ HOST_WIDE_INT args_size;
+
+ /* The number of bytes allocated to the .cprestore slot, or 0 if there
+ is no such slot. */
+ HOST_WIDE_INT cprestore_size;
+
+ /* Bit X is set if the function saves or restores GPR X. */
+ unsigned int mask;
+
+ /* Likewise FPR X. */
+ unsigned int fmask;
+
+ /* The number of GPRs and FPRs saved. */
+ unsigned int num_gp;
+ unsigned int num_fp;
+
+ /* The offset of the topmost GPR and FPR save slots from the top of
+ the frame, or zero if no such slots are needed. */
+ HOST_WIDE_INT gp_save_offset;
+ HOST_WIDE_INT fp_save_offset;
+
+ /* Likewise, but giving offsets from the bottom of the frame. */
+ HOST_WIDE_INT gp_sp_offset;
+ HOST_WIDE_INT fp_sp_offset;
+
+ /* The offset of arg_pointer_rtx from frame_pointer_rtx. */
+ HOST_WIDE_INT arg_pointer_offset;
+
+ /* The offset of hard_frame_pointer_rtx from frame_pointer_rtx. */
+ HOST_WIDE_INT hard_frame_pointer_offset;
};
struct machine_function GTY(()) {
- /* Pseudo-reg holding the value of $28 in a mips16 function which
- refers to GP relative global variables. */
+ /* The register returned by mips16_gp_pseudo_reg; see there for details. */
rtx mips16_gp_pseudo_rtx;
/* The number of extra stack bytes taken up by register varargs.
This area is allocated by the callee at the very top of the frame. */
int varargs_size;
- /* Current frame information, calculated by compute_frame_size. */
+ /* The current frame information, calculated by mips_compute_frame_info. */
struct mips_frame_info frame;
- /* The register to use as the global pointer within this function. */
+ /* The register to use as the function's global pointer. */
unsigned int global_pointer;
/* True if mips_adjust_insn_length should ignore an instruction's
};
/* Information about a single argument. */
-struct mips_arg_info
-{
+struct mips_arg_info {
/* True if the argument is passed in a floating-point register, or
would have been if we hadn't run out of registers. */
bool fpr_p;
unsigned int stack_offset;
};
-
/* Information about an address described by mips_address_type.
ADDRESS_CONST_INT
REG is the base register and OFFSET is the constant offset.
ADDRESS_LO_SUM
- REG is the register that contains the high part of the address,
- OFFSET is the symbolic address being referenced and SYMBOL_TYPE
- is the type of OFFSET's symbol.
+ REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
+ is the type of symbol it references.
ADDRESS_SYMBOLIC
- SYMBOL_TYPE is the type of symbol being referenced. */
-
-struct mips_address_info
-{
+ SYMBOL_TYPE is the type of symbol that the address references. */
+struct mips_address_info {
enum mips_address_type type;
rtx reg;
rtx offset;
enum mips_symbol_type symbol_type;
};
-
/* One stage in a constant building sequence. These sequences have
the form:
...
where A is an accumulator, each CODE[i] is a binary rtl operation
- and each VALUE[i] is a constant integer. */
+ and each VALUE[i] is a constant integer. CODE[0] is undefined. */
struct mips_integer_op {
enum rtx_code code;
unsigned HOST_WIDE_INT value;
};
-
/* The largest number of operations needed to load an integer constant.
The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
When the lowest bit is clear, we can try, but reject a sequence with
/* Global variables for machine-dependent things. */
-/* Threshold for data being put into the small data/bss area, instead
- of the normal data area. */
-int mips_section_threshold = -1;
+/* The -G setting, or the configuration's default small-data limit if
+ no -G option is given. */
+static unsigned int mips_small_data_threshold;
-/* Count the number of .file directives, so that .loc is up to date. */
-int num_source_filenames = 0;
+/* The number of file directives written by mips_output_filename. */
+int num_source_filenames;
-/* Count the number of sdb related labels are generated (to find block
- start and end boundaries). */
-int sdb_label_count = 0;
+/* The name that appeared in the last .file directive written by
+ mips_output_filename, or "" if mips_output_filename hasn't
+ written anything yet. */
+const char *current_function_file = "";
-/* Next label # for each statement for Silicon Graphics IRIS systems. */
-int sym_lineno = 0;
+/* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
+int sdb_label_count;
-/* Name of the file containing the current function. */
-const char *current_function_file = "";
+/* Arrays that map GCC register numbers to debugger register numbers. */
+int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
+int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
-/* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
+/* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
int set_noreorder;
-int set_noat;
int set_nomacro;
-int set_volatile;
+static int set_noat;
-/* The next branch instruction is a branch likely, not branch normal. */
-int mips_branch_likely;
+/* True if we're writing out a branch-likely instruction rather than a
+ normal branch. */
+static bool mips_branch_likely;
/* The operands passed to the last cmpMM expander. */
rtx cmp_operands[2];
-/* The target cpu for code generation. */
+/* The current instruction-set architecture. */
enum processor_type mips_arch;
const struct mips_cpu_info *mips_arch_info;
-/* The target cpu for optimization and scheduling. */
+/* The processor that we should tune the code for. */
enum processor_type mips_tune;
const struct mips_cpu_info *mips_tune_info;
-/* Which instruction set architecture to use. */
+/* The ISA level associated with mips_arch. */
int mips_isa;
+/* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
+static const struct mips_cpu_info *mips_isa_option_info;
+
/* Which ABI to use. */
int mips_abi = MIPS_ABI_DEFAULT;
-/* Cost information to use. */
+/* Which cost information to use. */
const struct mips_rtx_cost_data *mips_cost;
-/* Remember the ambient target flags, excluding mips16. */
+/* The ambient target flags, excluding MASK_MIPS16. */
static int mips_base_target_flags;
-/* The mips16 command-line target flags only. */
+
+/* True if MIPS16 is the default mode. */
static bool mips_base_mips16;
-/* Similar copies of option settings. */
+
+/* The ambient values of other global variables. */
+static int mips_base_delayed_branch; /* flag_delayed_branch */
static int mips_base_schedule_insns; /* flag_schedule_insns */
static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
static int mips_base_align_loops; /* align_loops */
static int mips_base_align_jumps; /* align_jumps */
static int mips_base_align_functions; /* align_functions */
-static GTY(()) int mips16_flipper;
-/* The -mtext-loads setting. */
+/* The -mcode-readable setting. */
enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
-/* The architecture selected by -mipsN. */
-static const struct mips_cpu_info *mips_isa_info;
-
-/* If TRUE, we split addresses into their high and low parts in the RTL. */
-int mips_split_addresses;
-
-/* Mode used for saving/restoring general purpose registers. */
-static enum machine_mode gpr_mode;
-
-/* Array giving truth value on whether or not a given hard register
- can support a given mode. */
-char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
+/* Index [M][R] is true if register R is allowed to hold a value of mode M. */
+bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
-/* List of all MIPS punctuation characters used by print_operand. */
-char mips_print_operand_punct[256];
-
-/* Map GCC register number to debugger register number. */
-int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
-int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
-
-/* A copy of the original flag_delayed_branch: see override_options. */
-static int mips_flag_delayed_branch;
+/* Index C is true if character C is a valid PRINT_OPERAND punctation
+ character. */
+bool mips_print_operand_punct[256];
static GTY (()) int mips_output_filename_first_time = 1;
/* mips_split_p[X] is true if symbols of type X can be split by
- mips_split_symbol(). */
+ mips_split_symbol. */
bool mips_split_p[NUM_SYMBOL_TYPES];
/* mips_lo_relocs[X] is the relocation to use when a symbol of type X
/* Likewise for HIGHs. */
static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
-/* Map hard register number to register class */
-const enum reg_class mips_regno_to_class[] =
-{
+/* Index R is the smallest register class that contains register R. */
+const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
M16_REGS, M16_REGS, M16_REGS, M16_REGS,
LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
};
-/* Table of machine dependent attributes. */
-const struct attribute_spec mips_attribute_table[] =
-{
+/* The value of TARGET_ATTRIBUTE_TABLE. */
+const struct attribute_spec mips_attribute_table[] = {
+ /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
{ "long_call", 0, 0, false, true, true, NULL },
{ "far", 0, 0, false, true, true, NULL },
{ "near", 0, 0, false, true, true, NULL },
- /* Switch MIPS16 ASE on and off per-function. */
- { "mips16", 0, 0, false, true, true, NULL },
- { "nomips16", 0, 0, false, true, true, NULL },
+ /* We would really like to treat "mips16" and "nomips16" as type
+ attributes, but GCC doesn't provide the hooks we need to support
+ the right conversion rules. As declaration attributes, they affect
+ code generation but don't carry other semantics. */
+ { "mips16", 0, 0, true, false, false, NULL },
+ { "nomips16", 0, 0, true, false, false, NULL },
{ NULL, 0, 0, false, false, false, NULL }
};
\f
-/* A table describing all the processors gcc knows about. Names are
+/* A table describing all the processors GCC knows about. Names are
matched in the order listed. The first mention of an ISA level is
taken as the canonical name for that ISA.
- To ease comparison, please keep this table in the same order as
- gas's mips_cpu_info_table[]. Please also make sure that
- MIPS_ISA_LEVEL_SPEC handles all -march options correctly. */
-const struct mips_cpu_info mips_cpu_info_table[] = {
- /* Entries for generic ISAs */
- { "mips1", PROCESSOR_R3000, 1 },
- { "mips2", PROCESSOR_R6000, 2 },
- { "mips3", PROCESSOR_R4000, 3 },
- { "mips4", PROCESSOR_R8000, 4 },
- { "mips32", PROCESSOR_4KC, 32 },
- { "mips32r2", PROCESSOR_M4K, 33 },
- { "mips64", PROCESSOR_5KC, 64 },
-
- /* MIPS I */
- { "r3000", PROCESSOR_R3000, 1 },
- { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
- { "r3900", PROCESSOR_R3900, 1 },
-
- /* MIPS II */
- { "r6000", PROCESSOR_R6000, 2 },
-
- /* MIPS III */
- { "r4000", PROCESSOR_R4000, 3 },
- { "vr4100", PROCESSOR_R4100, 3 },
- { "vr4111", PROCESSOR_R4111, 3 },
- { "vr4120", PROCESSOR_R4120, 3 },
- { "vr4130", PROCESSOR_R4130, 3 },
- { "vr4300", PROCESSOR_R4300, 3 },
- { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
- { "r4600", PROCESSOR_R4600, 3 },
- { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
- { "r4650", PROCESSOR_R4650, 3 },
-
- /* MIPS IV */
- { "r8000", PROCESSOR_R8000, 4 },
- { "vr5000", PROCESSOR_R5000, 4 },
- { "vr5400", PROCESSOR_R5400, 4 },
- { "vr5500", PROCESSOR_R5500, 4 },
- { "rm7000", PROCESSOR_R7000, 4 },
- { "rm9000", PROCESSOR_R9000, 4 },
-
- /* MIPS32 */
- { "4kc", PROCESSOR_4KC, 32 },
- { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
- { "4kp", PROCESSOR_4KP, 32 },
- { "4ksc", PROCESSOR_4KC, 32 },
-
- /* MIPS32 Release 2 */
- { "m4k", PROCESSOR_M4K, 33 },
- { "4kec", PROCESSOR_4KC, 33 },
- { "4kem", PROCESSOR_4KC, 33 },
- { "4kep", PROCESSOR_4KP, 33 },
- { "4ksd", PROCESSOR_4KC, 33 },
-
- { "24kc", PROCESSOR_24KC, 33 },
- { "24kf2_1", PROCESSOR_24KF2_1, 33 },
- { "24kf", PROCESSOR_24KF2_1, 33 },
- { "24kf1_1", PROCESSOR_24KF1_1, 33 },
- { "24kfx", PROCESSOR_24KF1_1, 33 },
- { "24kx", PROCESSOR_24KF1_1, 33 },
-
- { "24kec", PROCESSOR_24KC, 33 }, /* 24K with DSP */
- { "24kef2_1", PROCESSOR_24KF2_1, 33 },
- { "24kef", PROCESSOR_24KF2_1, 33 },
- { "24kef1_1", PROCESSOR_24KF1_1, 33 },
- { "24kefx", PROCESSOR_24KF1_1, 33 },
- { "24kex", PROCESSOR_24KF1_1, 33 },
-
- { "34kc", PROCESSOR_24KC, 33 }, /* 34K with MT/DSP */
- { "34kf2_1", PROCESSOR_24KF2_1, 33 },
- { "34kf", PROCESSOR_24KF2_1, 33 },
- { "34kf1_1", PROCESSOR_24KF1_1, 33 },
- { "34kfx", PROCESSOR_24KF1_1, 33 },
- { "34kx", PROCESSOR_24KF1_1, 33 },
-
- { "74kc", PROCESSOR_74KC, 33 }, /* 74K with DSPr2 */
- { "74kf2_1", PROCESSOR_74KF2_1, 33 },
- { "74kf", PROCESSOR_74KF2_1, 33 },
- { "74kf1_1", PROCESSOR_74KF1_1, 33 },
- { "74kfx", PROCESSOR_74KF1_1, 33 },
- { "74kx", PROCESSOR_74KF1_1, 33 },
- { "74kf3_2", PROCESSOR_74KF3_2, 33 },
-
- /* MIPS64 */
- { "5kc", PROCESSOR_5KC, 64 },
- { "5kf", PROCESSOR_5KF, 64 },
- { "20kc", PROCESSOR_20KC, 64 },
- { "sb1", PROCESSOR_SB1, 64 },
- { "sb1a", PROCESSOR_SB1A, 64 },
- { "sr71000", PROCESSOR_SR71000, 64 },
-
- /* End marker */
- { 0, 0, 0 }
+ To ease comparison, please keep this table in the same order
+ as GAS's mips_cpu_info_table. Please also make sure that
+ MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
+ options correctly. */
+static const struct mips_cpu_info mips_cpu_info_table[] = {
+ /* Entries for generic ISAs. */
+ { "mips1", PROCESSOR_R3000, 1, 0 },
+ { "mips2", PROCESSOR_R6000, 2, 0 },
+ { "mips3", PROCESSOR_R4000, 3, 0 },
+ { "mips4", PROCESSOR_R8000, 4, 0 },
+ /* Prefer not to use branch-likely instructions for generic MIPS32rX
+ and MIPS64rX code. The instructions were officially deprecated
+ in revisions 2 and earlier, but revision 3 is likely to downgrade
+ that to a recommendation to avoid the instructions in code that
+ isn't tuned to a specific processor. */
+ { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
+ { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
+ { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
+
+ /* MIPS I processors. */
+ { "r3000", PROCESSOR_R3000, 1, 0 },
+ { "r2000", PROCESSOR_R3000, 1, 0 },
+ { "r3900", PROCESSOR_R3900, 1, 0 },
+
+ /* MIPS II processors. */
+ { "r6000", PROCESSOR_R6000, 2, 0 },
+
+ /* MIPS III processors. */
+ { "r4000", PROCESSOR_R4000, 3, 0 },
+ { "vr4100", PROCESSOR_R4100, 3, 0 },
+ { "vr4111", PROCESSOR_R4111, 3, 0 },
+ { "vr4120", PROCESSOR_R4120, 3, 0 },
+ { "vr4130", PROCESSOR_R4130, 3, 0 },
+ { "vr4300", PROCESSOR_R4300, 3, 0 },
+ { "r4400", PROCESSOR_R4000, 3, 0 },
+ { "r4600", PROCESSOR_R4600, 3, 0 },
+ { "orion", PROCESSOR_R4600, 3, 0 },
+ { "r4650", PROCESSOR_R4650, 3, 0 },
+
+ /* MIPS IV processors. */
+ { "r8000", PROCESSOR_R8000, 4, 0 },
+ { "vr5000", PROCESSOR_R5000, 4, 0 },
+ { "vr5400", PROCESSOR_R5400, 4, 0 },
+ { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
+ { "rm7000", PROCESSOR_R7000, 4, 0 },
+ { "rm9000", PROCESSOR_R9000, 4, 0 },
+
+ /* MIPS32 processors. */
+ { "4kc", PROCESSOR_4KC, 32, 0 },
+ { "4km", PROCESSOR_4KC, 32, 0 },
+ { "4kp", PROCESSOR_4KP, 32, 0 },
+ { "4ksc", PROCESSOR_4KC, 32, 0 },
+
+ /* MIPS32 Release 2 processors. */
+ { "m4k", PROCESSOR_M4K, 33, 0 },
+ { "4kec", PROCESSOR_4KC, 33, 0 },
+ { "4kem", PROCESSOR_4KC, 33, 0 },
+ { "4kep", PROCESSOR_4KP, 33, 0 },
+ { "4ksd", PROCESSOR_4KC, 33, 0 },
+
+ { "24kc", PROCESSOR_24KC, 33, 0 },
+ { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
+ { "24kf", PROCESSOR_24KF2_1, 33, 0 },
+ { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
+ { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
+ { "24kx", PROCESSOR_24KF1_1, 33, 0 },
+
+ { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
+ { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
+ { "24kef", PROCESSOR_24KF2_1, 33, 0 },
+ { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
+ { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
+ { "24kex", PROCESSOR_24KF1_1, 33, 0 },
+
+ { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
+ { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
+ { "34kf", PROCESSOR_24KF2_1, 33, 0 },
+ { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
+ { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
+ { "34kx", PROCESSOR_24KF1_1, 33, 0 },
+
+ { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
+ { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
+ { "74kf", PROCESSOR_74KF2_1, 33, 0 },
+ { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
+ { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
+ { "74kx", PROCESSOR_74KF1_1, 33, 0 },
+ { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
+
+ /* MIPS64 processors. */
+ { "5kc", PROCESSOR_5KC, 64, 0 },
+ { "5kf", PROCESSOR_5KF, 64, 0 },
+ { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
+ { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
+ { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
+ { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
};
-/* Default costs. If these are used for a processor we should look
+/* Default costs. If these are used for a processor we should look
up the actual costs. */
#define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
COSTS_N_INSNS (7), /* fp_mult_sf */ \
2, /* branch_cost */ \
4 /* memory_latency */
-/* Need to replace these with the costs of calling the appropriate
- libgcc routine. */
+/* Floating-point costs for processors without an FPU. Just assume that
+ all floating-point libcalls are very expensive. */
#define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
COSTS_N_INSNS (256), /* fp_mult_sf */ \
COSTS_N_INSNS (256), /* fp_mult_df */ \
COSTS_N_INSNS (256), /* fp_div_sf */ \
COSTS_N_INSNS (256) /* fp_div_df */
-static struct mips_rtx_cost_data const mips_rtx_cost_optimize_size =
- {
- COSTS_N_INSNS (1), /* fp_add */
- COSTS_N_INSNS (1), /* fp_mult_sf */
- COSTS_N_INSNS (1), /* fp_mult_df */
- COSTS_N_INSNS (1), /* fp_div_sf */
- COSTS_N_INSNS (1), /* fp_div_df */
- COSTS_N_INSNS (1), /* int_mult_si */
- COSTS_N_INSNS (1), /* int_mult_di */
- COSTS_N_INSNS (1), /* int_div_si */
- COSTS_N_INSNS (1), /* int_div_di */
- 2, /* branch_cost */
- 4 /* memory_latency */
- };
-
-static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
- {
- { /* R3000 */
- COSTS_N_INSNS (2), /* fp_add */
- COSTS_N_INSNS (4), /* fp_mult_sf */
- COSTS_N_INSNS (5), /* fp_mult_df */
- COSTS_N_INSNS (12), /* fp_div_sf */
- COSTS_N_INSNS (19), /* fp_div_df */
- COSTS_N_INSNS (12), /* int_mult_si */
- COSTS_N_INSNS (12), /* int_mult_di */
- COSTS_N_INSNS (35), /* int_div_si */
- COSTS_N_INSNS (35), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
-
- },
- { /* 4KC */
- SOFT_FP_COSTS,
- COSTS_N_INSNS (6), /* int_mult_si */
- COSTS_N_INSNS (6), /* int_mult_di */
- COSTS_N_INSNS (36), /* int_div_si */
- COSTS_N_INSNS (36), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* 4KP */
- SOFT_FP_COSTS,
- COSTS_N_INSNS (36), /* int_mult_si */
- COSTS_N_INSNS (36), /* int_mult_di */
- COSTS_N_INSNS (37), /* int_div_si */
- COSTS_N_INSNS (37), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* 5KC */
- SOFT_FP_COSTS,
- COSTS_N_INSNS (4), /* int_mult_si */
- COSTS_N_INSNS (11), /* int_mult_di */
- COSTS_N_INSNS (36), /* int_div_si */
- COSTS_N_INSNS (68), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* 5KF */
- COSTS_N_INSNS (4), /* fp_add */
- COSTS_N_INSNS (4), /* fp_mult_sf */
- COSTS_N_INSNS (5), /* fp_mult_df */
- COSTS_N_INSNS (17), /* fp_div_sf */
- COSTS_N_INSNS (32), /* fp_div_df */
- COSTS_N_INSNS (4), /* int_mult_si */
- COSTS_N_INSNS (11), /* int_mult_di */
- COSTS_N_INSNS (36), /* int_div_si */
- COSTS_N_INSNS (68), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* 20KC */
- COSTS_N_INSNS (4), /* fp_add */
- COSTS_N_INSNS (4), /* fp_mult_sf */
- COSTS_N_INSNS (5), /* fp_mult_df */
- COSTS_N_INSNS (17), /* fp_div_sf */
- COSTS_N_INSNS (32), /* fp_div_df */
- COSTS_N_INSNS (4), /* int_mult_si */
- COSTS_N_INSNS (7), /* int_mult_di */
- COSTS_N_INSNS (42), /* int_div_si */
- COSTS_N_INSNS (72), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* 24KC */
- SOFT_FP_COSTS,
- COSTS_N_INSNS (5), /* int_mult_si */
- COSTS_N_INSNS (5), /* int_mult_di */
- COSTS_N_INSNS (41), /* int_div_si */
- COSTS_N_INSNS (41), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* 24KF2_1 */
- COSTS_N_INSNS (8), /* fp_add */
- COSTS_N_INSNS (8), /* fp_mult_sf */
- COSTS_N_INSNS (10), /* fp_mult_df */
- COSTS_N_INSNS (34), /* fp_div_sf */
- COSTS_N_INSNS (64), /* fp_div_df */
- COSTS_N_INSNS (5), /* int_mult_si */
- COSTS_N_INSNS (5), /* int_mult_di */
- COSTS_N_INSNS (41), /* int_div_si */
- COSTS_N_INSNS (41), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* 24KF1_1 */
- COSTS_N_INSNS (4), /* fp_add */
- COSTS_N_INSNS (4), /* fp_mult_sf */
- COSTS_N_INSNS (5), /* fp_mult_df */
- COSTS_N_INSNS (17), /* fp_div_sf */
- COSTS_N_INSNS (32), /* fp_div_df */
- COSTS_N_INSNS (5), /* int_mult_si */
- COSTS_N_INSNS (5), /* int_mult_di */
- COSTS_N_INSNS (41), /* int_div_si */
- COSTS_N_INSNS (41), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* 74KC */
- SOFT_FP_COSTS,
- COSTS_N_INSNS (5), /* int_mult_si */
- COSTS_N_INSNS (5), /* int_mult_di */
- COSTS_N_INSNS (41), /* int_div_si */
- COSTS_N_INSNS (41), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* 74KF2_1 */
- COSTS_N_INSNS (8), /* fp_add */
- COSTS_N_INSNS (8), /* fp_mult_sf */
- COSTS_N_INSNS (10), /* fp_mult_df */
- COSTS_N_INSNS (34), /* fp_div_sf */
- COSTS_N_INSNS (64), /* fp_div_df */
- COSTS_N_INSNS (5), /* int_mult_si */
- COSTS_N_INSNS (5), /* int_mult_di */
- COSTS_N_INSNS (41), /* int_div_si */
- COSTS_N_INSNS (41), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* 74KF1_1 */
- COSTS_N_INSNS (4), /* fp_add */
- COSTS_N_INSNS (4), /* fp_mult_sf */
- COSTS_N_INSNS (5), /* fp_mult_df */
- COSTS_N_INSNS (17), /* fp_div_sf */
- COSTS_N_INSNS (32), /* fp_div_df */
- COSTS_N_INSNS (5), /* int_mult_si */
- COSTS_N_INSNS (5), /* int_mult_di */
- COSTS_N_INSNS (41), /* int_div_si */
- COSTS_N_INSNS (41), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* 74KF3_2 */
- COSTS_N_INSNS (6), /* fp_add */
- COSTS_N_INSNS (6), /* fp_mult_sf */
- COSTS_N_INSNS (7), /* fp_mult_df */
- COSTS_N_INSNS (25), /* fp_div_sf */
- COSTS_N_INSNS (48), /* fp_div_df */
- COSTS_N_INSNS (5), /* int_mult_si */
- COSTS_N_INSNS (5), /* int_mult_di */
- COSTS_N_INSNS (41), /* int_div_si */
- COSTS_N_INSNS (41), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* M4k */
- DEFAULT_COSTS
- },
- { /* R3900 */
- COSTS_N_INSNS (2), /* fp_add */
- COSTS_N_INSNS (4), /* fp_mult_sf */
- COSTS_N_INSNS (5), /* fp_mult_df */
- COSTS_N_INSNS (12), /* fp_div_sf */
- COSTS_N_INSNS (19), /* fp_div_df */
- COSTS_N_INSNS (2), /* int_mult_si */
- COSTS_N_INSNS (2), /* int_mult_di */
- COSTS_N_INSNS (35), /* int_div_si */
- COSTS_N_INSNS (35), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* R6000 */
- COSTS_N_INSNS (3), /* fp_add */
- COSTS_N_INSNS (5), /* fp_mult_sf */
- COSTS_N_INSNS (6), /* fp_mult_df */
- COSTS_N_INSNS (15), /* fp_div_sf */
- COSTS_N_INSNS (16), /* fp_div_df */
- COSTS_N_INSNS (17), /* int_mult_si */
- COSTS_N_INSNS (17), /* int_mult_di */
- COSTS_N_INSNS (38), /* int_div_si */
- COSTS_N_INSNS (38), /* int_div_di */
- 2, /* branch_cost */
- 6 /* memory_latency */
- },
- { /* R4000 */
- COSTS_N_INSNS (6), /* fp_add */
- COSTS_N_INSNS (7), /* fp_mult_sf */
- COSTS_N_INSNS (8), /* fp_mult_df */
- COSTS_N_INSNS (23), /* fp_div_sf */
- COSTS_N_INSNS (36), /* fp_div_df */
- COSTS_N_INSNS (10), /* int_mult_si */
- COSTS_N_INSNS (10), /* int_mult_di */
- COSTS_N_INSNS (69), /* int_div_si */
- COSTS_N_INSNS (69), /* int_div_di */
- 2, /* branch_cost */
- 6 /* memory_latency */
- },
- { /* R4100 */
- DEFAULT_COSTS
- },
- { /* R4111 */
- DEFAULT_COSTS
- },
- { /* R4120 */
- DEFAULT_COSTS
- },
- { /* R4130 */
- /* The only costs that appear to be updated here are
- integer multiplication. */
- SOFT_FP_COSTS,
- COSTS_N_INSNS (4), /* int_mult_si */
- COSTS_N_INSNS (6), /* int_mult_di */
- COSTS_N_INSNS (69), /* int_div_si */
- COSTS_N_INSNS (69), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* R4300 */
- DEFAULT_COSTS
- },
- { /* R4600 */
- DEFAULT_COSTS
- },
- { /* R4650 */
- DEFAULT_COSTS
- },
- { /* R5000 */
- COSTS_N_INSNS (6), /* fp_add */
- COSTS_N_INSNS (4), /* fp_mult_sf */
- COSTS_N_INSNS (5), /* fp_mult_df */
- COSTS_N_INSNS (23), /* fp_div_sf */
- COSTS_N_INSNS (36), /* fp_div_df */
- COSTS_N_INSNS (5), /* int_mult_si */
- COSTS_N_INSNS (5), /* int_mult_di */
- COSTS_N_INSNS (36), /* int_div_si */
- COSTS_N_INSNS (36), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* R5400 */
- COSTS_N_INSNS (6), /* fp_add */
- COSTS_N_INSNS (5), /* fp_mult_sf */
- COSTS_N_INSNS (6), /* fp_mult_df */
- COSTS_N_INSNS (30), /* fp_div_sf */
- COSTS_N_INSNS (59), /* fp_div_df */
- COSTS_N_INSNS (3), /* int_mult_si */
- COSTS_N_INSNS (4), /* int_mult_di */
- COSTS_N_INSNS (42), /* int_div_si */
- COSTS_N_INSNS (74), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* R5500 */
- COSTS_N_INSNS (6), /* fp_add */
- COSTS_N_INSNS (5), /* fp_mult_sf */
- COSTS_N_INSNS (6), /* fp_mult_df */
- COSTS_N_INSNS (30), /* fp_div_sf */
- COSTS_N_INSNS (59), /* fp_div_df */
- COSTS_N_INSNS (5), /* int_mult_si */
- COSTS_N_INSNS (9), /* int_mult_di */
- COSTS_N_INSNS (42), /* int_div_si */
- COSTS_N_INSNS (74), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* R7000 */
- /* The only costs that are changed here are
- integer multiplication. */
- COSTS_N_INSNS (6), /* fp_add */
- COSTS_N_INSNS (7), /* fp_mult_sf */
- COSTS_N_INSNS (8), /* fp_mult_df */
- COSTS_N_INSNS (23), /* fp_div_sf */
- COSTS_N_INSNS (36), /* fp_div_df */
- COSTS_N_INSNS (5), /* int_mult_si */
- COSTS_N_INSNS (9), /* int_mult_di */
- COSTS_N_INSNS (69), /* int_div_si */
- COSTS_N_INSNS (69), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* R8000 */
- DEFAULT_COSTS
- },
- { /* R9000 */
- /* The only costs that are changed here are
- integer multiplication. */
- COSTS_N_INSNS (6), /* fp_add */
- COSTS_N_INSNS (7), /* fp_mult_sf */
- COSTS_N_INSNS (8), /* fp_mult_df */
- COSTS_N_INSNS (23), /* fp_div_sf */
- COSTS_N_INSNS (36), /* fp_div_df */
- COSTS_N_INSNS (3), /* int_mult_si */
- COSTS_N_INSNS (8), /* int_mult_di */
- COSTS_N_INSNS (69), /* int_div_si */
- COSTS_N_INSNS (69), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* SB1 */
- /* These costs are the same as the SB-1A below. */
- COSTS_N_INSNS (4), /* fp_add */
- COSTS_N_INSNS (4), /* fp_mult_sf */
- COSTS_N_INSNS (4), /* fp_mult_df */
- COSTS_N_INSNS (24), /* fp_div_sf */
- COSTS_N_INSNS (32), /* fp_div_df */
- COSTS_N_INSNS (3), /* int_mult_si */
- COSTS_N_INSNS (4), /* int_mult_di */
- COSTS_N_INSNS (36), /* int_div_si */
- COSTS_N_INSNS (68), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* SB1-A */
- /* These costs are the same as the SB-1 above. */
- COSTS_N_INSNS (4), /* fp_add */
- COSTS_N_INSNS (4), /* fp_mult_sf */
- COSTS_N_INSNS (4), /* fp_mult_df */
- COSTS_N_INSNS (24), /* fp_div_sf */
- COSTS_N_INSNS (32), /* fp_div_df */
- COSTS_N_INSNS (3), /* int_mult_si */
- COSTS_N_INSNS (4), /* int_mult_di */
- COSTS_N_INSNS (36), /* int_div_si */
- COSTS_N_INSNS (68), /* int_div_di */
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
- { /* SR71000 */
- DEFAULT_COSTS
- },
- };
-
-/* If a MIPS16e SAVE or RESTORE instruction saves or restores register
- mips16e_s2_s8_regs[X], it must also save the registers in indexes
- X + 1 onwards. Likewise mips16e_a0_a3_regs. */
-static const unsigned char mips16e_s2_s8_regs[] = {
- 30, 23, 22, 21, 20, 19, 18
-};
-static const unsigned char mips16e_a0_a3_regs[] = {
- 4, 5, 6, 7
+/* Costs to use when optimizing for size. */
+static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
+ COSTS_N_INSNS (1), /* fp_add */
+ COSTS_N_INSNS (1), /* fp_mult_sf */
+ COSTS_N_INSNS (1), /* fp_mult_df */
+ COSTS_N_INSNS (1), /* fp_div_sf */
+ COSTS_N_INSNS (1), /* fp_div_df */
+ COSTS_N_INSNS (1), /* int_mult_si */
+ COSTS_N_INSNS (1), /* int_mult_di */
+ COSTS_N_INSNS (1), /* int_div_si */
+ COSTS_N_INSNS (1), /* int_div_di */
+ 2, /* branch_cost */
+ 4 /* memory_latency */
};
-/* A list of the registers that can be saved by the MIPS16e SAVE instruction,
- ordered from the uppermost in memory to the lowest in memory. */
-static const unsigned char mips16e_save_restore_regs[] = {
- 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
+/* Costs to use when optimizing for speed, indexed by processor. */
+static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
+ { /* R3000 */
+ COSTS_N_INSNS (2), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult_sf */
+ COSTS_N_INSNS (5), /* fp_mult_df */
+ COSTS_N_INSNS (12), /* fp_div_sf */
+ COSTS_N_INSNS (19), /* fp_div_df */
+ COSTS_N_INSNS (12), /* int_mult_si */
+ COSTS_N_INSNS (12), /* int_mult_di */
+ COSTS_N_INSNS (35), /* int_div_si */
+ COSTS_N_INSNS (35), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* 4KC */
+ SOFT_FP_COSTS,
+ COSTS_N_INSNS (6), /* int_mult_si */
+ COSTS_N_INSNS (6), /* int_mult_di */
+ COSTS_N_INSNS (36), /* int_div_si */
+ COSTS_N_INSNS (36), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* 4KP */
+ SOFT_FP_COSTS,
+ COSTS_N_INSNS (36), /* int_mult_si */
+ COSTS_N_INSNS (36), /* int_mult_di */
+ COSTS_N_INSNS (37), /* int_div_si */
+ COSTS_N_INSNS (37), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* 5KC */
+ SOFT_FP_COSTS,
+ COSTS_N_INSNS (4), /* int_mult_si */
+ COSTS_N_INSNS (11), /* int_mult_di */
+ COSTS_N_INSNS (36), /* int_div_si */
+ COSTS_N_INSNS (68), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* 5KF */
+ COSTS_N_INSNS (4), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult_sf */
+ COSTS_N_INSNS (5), /* fp_mult_df */
+ COSTS_N_INSNS (17), /* fp_div_sf */
+ COSTS_N_INSNS (32), /* fp_div_df */
+ COSTS_N_INSNS (4), /* int_mult_si */
+ COSTS_N_INSNS (11), /* int_mult_di */
+ COSTS_N_INSNS (36), /* int_div_si */
+ COSTS_N_INSNS (68), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* 20KC */
+ COSTS_N_INSNS (4), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult_sf */
+ COSTS_N_INSNS (5), /* fp_mult_df */
+ COSTS_N_INSNS (17), /* fp_div_sf */
+ COSTS_N_INSNS (32), /* fp_div_df */
+ COSTS_N_INSNS (4), /* int_mult_si */
+ COSTS_N_INSNS (7), /* int_mult_di */
+ COSTS_N_INSNS (42), /* int_div_si */
+ COSTS_N_INSNS (72), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* 24KC */
+ SOFT_FP_COSTS,
+ COSTS_N_INSNS (5), /* int_mult_si */
+ COSTS_N_INSNS (5), /* int_mult_di */
+ COSTS_N_INSNS (41), /* int_div_si */
+ COSTS_N_INSNS (41), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* 24KF2_1 */
+ COSTS_N_INSNS (8), /* fp_add */
+ COSTS_N_INSNS (8), /* fp_mult_sf */
+ COSTS_N_INSNS (10), /* fp_mult_df */
+ COSTS_N_INSNS (34), /* fp_div_sf */
+ COSTS_N_INSNS (64), /* fp_div_df */
+ COSTS_N_INSNS (5), /* int_mult_si */
+ COSTS_N_INSNS (5), /* int_mult_di */
+ COSTS_N_INSNS (41), /* int_div_si */
+ COSTS_N_INSNS (41), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* 24KF1_1 */
+ COSTS_N_INSNS (4), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult_sf */
+ COSTS_N_INSNS (5), /* fp_mult_df */
+ COSTS_N_INSNS (17), /* fp_div_sf */
+ COSTS_N_INSNS (32), /* fp_div_df */
+ COSTS_N_INSNS (5), /* int_mult_si */
+ COSTS_N_INSNS (5), /* int_mult_di */
+ COSTS_N_INSNS (41), /* int_div_si */
+ COSTS_N_INSNS (41), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* 74KC */
+ SOFT_FP_COSTS,
+ COSTS_N_INSNS (5), /* int_mult_si */
+ COSTS_N_INSNS (5), /* int_mult_di */
+ COSTS_N_INSNS (41), /* int_div_si */
+ COSTS_N_INSNS (41), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* 74KF2_1 */
+ COSTS_N_INSNS (8), /* fp_add */
+ COSTS_N_INSNS (8), /* fp_mult_sf */
+ COSTS_N_INSNS (10), /* fp_mult_df */
+ COSTS_N_INSNS (34), /* fp_div_sf */
+ COSTS_N_INSNS (64), /* fp_div_df */
+ COSTS_N_INSNS (5), /* int_mult_si */
+ COSTS_N_INSNS (5), /* int_mult_di */
+ COSTS_N_INSNS (41), /* int_div_si */
+ COSTS_N_INSNS (41), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* 74KF1_1 */
+ COSTS_N_INSNS (4), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult_sf */
+ COSTS_N_INSNS (5), /* fp_mult_df */
+ COSTS_N_INSNS (17), /* fp_div_sf */
+ COSTS_N_INSNS (32), /* fp_div_df */
+ COSTS_N_INSNS (5), /* int_mult_si */
+ COSTS_N_INSNS (5), /* int_mult_di */
+ COSTS_N_INSNS (41), /* int_div_si */
+ COSTS_N_INSNS (41), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* 74KF3_2 */
+ COSTS_N_INSNS (6), /* fp_add */
+ COSTS_N_INSNS (6), /* fp_mult_sf */
+ COSTS_N_INSNS (7), /* fp_mult_df */
+ COSTS_N_INSNS (25), /* fp_div_sf */
+ COSTS_N_INSNS (48), /* fp_div_df */
+ COSTS_N_INSNS (5), /* int_mult_si */
+ COSTS_N_INSNS (5), /* int_mult_di */
+ COSTS_N_INSNS (41), /* int_div_si */
+ COSTS_N_INSNS (41), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* M4k */
+ DEFAULT_COSTS
+ },
+ { /* R3900 */
+ COSTS_N_INSNS (2), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult_sf */
+ COSTS_N_INSNS (5), /* fp_mult_df */
+ COSTS_N_INSNS (12), /* fp_div_sf */
+ COSTS_N_INSNS (19), /* fp_div_df */
+ COSTS_N_INSNS (2), /* int_mult_si */
+ COSTS_N_INSNS (2), /* int_mult_di */
+ COSTS_N_INSNS (35), /* int_div_si */
+ COSTS_N_INSNS (35), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* R6000 */
+ COSTS_N_INSNS (3), /* fp_add */
+ COSTS_N_INSNS (5), /* fp_mult_sf */
+ COSTS_N_INSNS (6), /* fp_mult_df */
+ COSTS_N_INSNS (15), /* fp_div_sf */
+ COSTS_N_INSNS (16), /* fp_div_df */
+ COSTS_N_INSNS (17), /* int_mult_si */
+ COSTS_N_INSNS (17), /* int_mult_di */
+ COSTS_N_INSNS (38), /* int_div_si */
+ COSTS_N_INSNS (38), /* int_div_di */
+ 2, /* branch_cost */
+ 6 /* memory_latency */
+ },
+ { /* R4000 */
+ COSTS_N_INSNS (6), /* fp_add */
+ COSTS_N_INSNS (7), /* fp_mult_sf */
+ COSTS_N_INSNS (8), /* fp_mult_df */
+ COSTS_N_INSNS (23), /* fp_div_sf */
+ COSTS_N_INSNS (36), /* fp_div_df */
+ COSTS_N_INSNS (10), /* int_mult_si */
+ COSTS_N_INSNS (10), /* int_mult_di */
+ COSTS_N_INSNS (69), /* int_div_si */
+ COSTS_N_INSNS (69), /* int_div_di */
+ 2, /* branch_cost */
+ 6 /* memory_latency */
+ },
+ { /* R4100 */
+ DEFAULT_COSTS
+ },
+ { /* R4111 */
+ DEFAULT_COSTS
+ },
+ { /* R4120 */
+ DEFAULT_COSTS
+ },
+ { /* R4130 */
+ /* The only costs that appear to be updated here are
+ integer multiplication. */
+ SOFT_FP_COSTS,
+ COSTS_N_INSNS (4), /* int_mult_si */
+ COSTS_N_INSNS (6), /* int_mult_di */
+ COSTS_N_INSNS (69), /* int_div_si */
+ COSTS_N_INSNS (69), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* R4300 */
+ DEFAULT_COSTS
+ },
+ { /* R4600 */
+ DEFAULT_COSTS
+ },
+ { /* R4650 */
+ DEFAULT_COSTS
+ },
+ { /* R5000 */
+ COSTS_N_INSNS (6), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult_sf */
+ COSTS_N_INSNS (5), /* fp_mult_df */
+ COSTS_N_INSNS (23), /* fp_div_sf */
+ COSTS_N_INSNS (36), /* fp_div_df */
+ COSTS_N_INSNS (5), /* int_mult_si */
+ COSTS_N_INSNS (5), /* int_mult_di */
+ COSTS_N_INSNS (36), /* int_div_si */
+ COSTS_N_INSNS (36), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* R5400 */
+ COSTS_N_INSNS (6), /* fp_add */
+ COSTS_N_INSNS (5), /* fp_mult_sf */
+ COSTS_N_INSNS (6), /* fp_mult_df */
+ COSTS_N_INSNS (30), /* fp_div_sf */
+ COSTS_N_INSNS (59), /* fp_div_df */
+ COSTS_N_INSNS (3), /* int_mult_si */
+ COSTS_N_INSNS (4), /* int_mult_di */
+ COSTS_N_INSNS (42), /* int_div_si */
+ COSTS_N_INSNS (74), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* R5500 */
+ COSTS_N_INSNS (6), /* fp_add */
+ COSTS_N_INSNS (5), /* fp_mult_sf */
+ COSTS_N_INSNS (6), /* fp_mult_df */
+ COSTS_N_INSNS (30), /* fp_div_sf */
+ COSTS_N_INSNS (59), /* fp_div_df */
+ COSTS_N_INSNS (5), /* int_mult_si */
+ COSTS_N_INSNS (9), /* int_mult_di */
+ COSTS_N_INSNS (42), /* int_div_si */
+ COSTS_N_INSNS (74), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* R7000 */
+ /* The only costs that are changed here are
+ integer multiplication. */
+ COSTS_N_INSNS (6), /* fp_add */
+ COSTS_N_INSNS (7), /* fp_mult_sf */
+ COSTS_N_INSNS (8), /* fp_mult_df */
+ COSTS_N_INSNS (23), /* fp_div_sf */
+ COSTS_N_INSNS (36), /* fp_div_df */
+ COSTS_N_INSNS (5), /* int_mult_si */
+ COSTS_N_INSNS (9), /* int_mult_di */
+ COSTS_N_INSNS (69), /* int_div_si */
+ COSTS_N_INSNS (69), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* R8000 */
+ DEFAULT_COSTS
+ },
+ { /* R9000 */
+ /* The only costs that are changed here are
+ integer multiplication. */
+ COSTS_N_INSNS (6), /* fp_add */
+ COSTS_N_INSNS (7), /* fp_mult_sf */
+ COSTS_N_INSNS (8), /* fp_mult_df */
+ COSTS_N_INSNS (23), /* fp_div_sf */
+ COSTS_N_INSNS (36), /* fp_div_df */
+ COSTS_N_INSNS (3), /* int_mult_si */
+ COSTS_N_INSNS (8), /* int_mult_di */
+ COSTS_N_INSNS (69), /* int_div_si */
+ COSTS_N_INSNS (69), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* SB1 */
+ /* These costs are the same as the SB-1A below. */
+ COSTS_N_INSNS (4), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult_sf */
+ COSTS_N_INSNS (4), /* fp_mult_df */
+ COSTS_N_INSNS (24), /* fp_div_sf */
+ COSTS_N_INSNS (32), /* fp_div_df */
+ COSTS_N_INSNS (3), /* int_mult_si */
+ COSTS_N_INSNS (4), /* int_mult_di */
+ COSTS_N_INSNS (36), /* int_div_si */
+ COSTS_N_INSNS (68), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* SB1-A */
+ /* These costs are the same as the SB-1 above. */
+ COSTS_N_INSNS (4), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult_sf */
+ COSTS_N_INSNS (4), /* fp_mult_df */
+ COSTS_N_INSNS (24), /* fp_div_sf */
+ COSTS_N_INSNS (32), /* fp_div_df */
+ COSTS_N_INSNS (3), /* int_mult_si */
+ COSTS_N_INSNS (4), /* int_mult_di */
+ COSTS_N_INSNS (36), /* int_div_si */
+ COSTS_N_INSNS (68), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* SR71000 */
+ DEFAULT_COSTS
+ },
};
\f
-/* Nonzero if -march should decide the default value of
- MASK_SOFT_FLOAT_ABI. */
-#ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
-#define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
-#endif
-\f
-/* Initialize the GCC target structure. */
-#undef TARGET_ASM_ALIGNED_HI_OP
-#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
-#undef TARGET_ASM_ALIGNED_SI_OP
-#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
-#undef TARGET_ASM_ALIGNED_DI_OP
-#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
-
-#undef TARGET_ASM_FUNCTION_PROLOGUE
-#define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
-#undef TARGET_ASM_FUNCTION_EPILOGUE
-#define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
-#undef TARGET_ASM_SELECT_RTX_SECTION
-#define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
-#undef TARGET_ASM_FUNCTION_RODATA_SECTION
-#define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
-
-#undef TARGET_SCHED_INIT
-#define TARGET_SCHED_INIT mips_sched_init
-#undef TARGET_SCHED_REORDER
-#define TARGET_SCHED_REORDER mips_sched_reorder
-#undef TARGET_SCHED_REORDER2
-#define TARGET_SCHED_REORDER2 mips_sched_reorder
-#undef TARGET_SCHED_VARIABLE_ISSUE
-#define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
-#undef TARGET_SCHED_ADJUST_COST
-#define TARGET_SCHED_ADJUST_COST mips_adjust_cost
-#undef TARGET_SCHED_ISSUE_RATE
-#define TARGET_SCHED_ISSUE_RATE mips_issue_rate
-#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
-#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
- mips_multipass_dfa_lookahead
-
-#undef TARGET_DEFAULT_TARGET_FLAGS
-#define TARGET_DEFAULT_TARGET_FLAGS \
- (TARGET_DEFAULT \
- | TARGET_CPU_DEFAULT \
- | TARGET_ENDIAN_DEFAULT \
- | TARGET_FP_EXCEPTIONS_DEFAULT \
- | MASK_CHECK_ZERO_DIV \
- | MASK_FUSED_MADD)
-#undef TARGET_HANDLE_OPTION
-#define TARGET_HANDLE_OPTION mips_handle_option
-
-#undef TARGET_FUNCTION_OK_FOR_SIBCALL
-#define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
-
-#undef TARGET_SET_CURRENT_FUNCTION
-#define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
-
-#undef TARGET_VALID_POINTER_MODE
-#define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
-#undef TARGET_RTX_COSTS
-#define TARGET_RTX_COSTS mips_rtx_costs
-#undef TARGET_ADDRESS_COST
-#define TARGET_ADDRESS_COST mips_address_cost
-
-#undef TARGET_IN_SMALL_DATA_P
-#define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
-
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
-
-#undef TARGET_ASM_FILE_START
-#define TARGET_ASM_FILE_START mips_file_start
-#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
-#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
-
-#undef TARGET_INIT_LIBFUNCS
-#define TARGET_INIT_LIBFUNCS mips_init_libfuncs
-
-#undef TARGET_BUILD_BUILTIN_VA_LIST
-#define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
-#undef TARGET_GIMPLIFY_VA_ARG_EXPR
-#define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
-
-#undef TARGET_PROMOTE_FUNCTION_ARGS
-#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
-#undef TARGET_PROMOTE_FUNCTION_RETURN
-#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
-#undef TARGET_PROMOTE_PROTOTYPES
-#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
-
-#undef TARGET_RETURN_IN_MEMORY
-#define TARGET_RETURN_IN_MEMORY mips_return_in_memory
-#undef TARGET_RETURN_IN_MSB
-#define TARGET_RETURN_IN_MSB mips_return_in_msb
-
-#undef TARGET_ASM_OUTPUT_MI_THUNK
-#define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
-#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
-#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
-
-#undef TARGET_SETUP_INCOMING_VARARGS
-#define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
-#undef TARGET_STRICT_ARGUMENT_NAMING
-#define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
-#undef TARGET_MUST_PASS_IN_STACK
-#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
-#undef TARGET_PASS_BY_REFERENCE
-#define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
-#undef TARGET_CALLEE_COPIES
-#define TARGET_CALLEE_COPIES mips_callee_copies
-#undef TARGET_ARG_PARTIAL_BYTES
-#define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
-
-#undef TARGET_MODE_REP_EXTENDED
-#define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
-
-#undef TARGET_VECTOR_MODE_SUPPORTED_P
-#define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
-
-#undef TARGET_INIT_BUILTINS
-#define TARGET_INIT_BUILTINS mips_init_builtins
-#undef TARGET_EXPAND_BUILTIN
-#define TARGET_EXPAND_BUILTIN mips_expand_builtin
-
-#undef TARGET_HAVE_TLS
-#define TARGET_HAVE_TLS HAVE_AS_TLS
-
-#undef TARGET_CANNOT_FORCE_CONST_MEM
-#define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
+/* This hash table keeps track of implicit "mips16" and "nomips16" attributes
+ for -mflip_mips16. It maps decl names onto a boolean mode setting. */
+struct mflip_mips16_entry GTY (()) {
+ const char *name;
+ bool mips16_p;
+};
+static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
-#undef TARGET_ENCODE_SECTION_INFO
-#define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
+/* Hash table callbacks for mflip_mips16_htab. */
-#undef TARGET_ATTRIBUTE_TABLE
-#define TARGET_ATTRIBUTE_TABLE mips_attribute_table
+static hashval_t
+mflip_mips16_htab_hash (const void *entry)
+{
+ return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
+}
-#undef TARGET_EXTRA_LIVE_ON_ENTRY
-#define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
+static int
+mflip_mips16_htab_eq (const void *entry, const void *name)
+{
+ return strcmp (((const struct mflip_mips16_entry *) entry)->name,
+ (const char *) name) == 0;
+}
-#undef TARGET_MIN_ANCHOR_OFFSET
-#define TARGET_MIN_ANCHOR_OFFSET -32768
-#undef TARGET_MAX_ANCHOR_OFFSET
-#define TARGET_MAX_ANCHOR_OFFSET 32767
-#undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
-#define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
-#undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
-#define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
+/* True if -mflip-mips16 should next add an attribute for the default MIPS16
+ mode, false if it should next add an attribute for the opposite mode. */
+static GTY(()) bool mips16_flipper;
-#undef TARGET_COMP_TYPE_ATTRIBUTES
-#define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
+/* DECL is a function that needs a default "mips16" or "nomips16" attribute
+ for -mflip-mips16. Return true if it should use "mips16" and false if
+ it should use "nomips16". */
-#ifdef HAVE_AS_DTPRELWORD
-#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
-#define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
-#endif
+static bool
+mflip_mips16_use_mips16_p (tree decl)
+{
+ struct mflip_mips16_entry *entry;
+ const char *name;
+ hashval_t hash;
+ void **slot;
-struct gcc_target targetm = TARGET_INITIALIZER;
+ /* Use the opposite of the command-line setting for anonymous decls. */
+ if (!DECL_NAME (decl))
+ return !mips_base_mips16;
+ if (!mflip_mips16_htab)
+ mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
+ mflip_mips16_htab_eq, NULL);
+ name = IDENTIFIER_POINTER (DECL_NAME (decl));
+ hash = htab_hash_string (name);
+ slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
+ entry = (struct mflip_mips16_entry *) *slot;
+ if (!entry)
+ {
+ mips16_flipper = !mips16_flipper;
+ entry = GGC_NEW (struct mflip_mips16_entry);
+ entry->name = name;
+ entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
+ *slot = entry;
+ }
+ return entry->mips16_p;
+}
+\f
/* Predicates to test for presence of "near" and "far"/"long_call"
attributes on the given TYPE. */
|| lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
}
-/* Similar predicates for "mips16"/"nomips16" attributes. */
+/* Similar predicates for "mips16"/"nomips16" function attributes. */
+
+static bool
+mips_mips16_decl_p (const_tree decl)
+{
+ return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
+}
static bool
-mips_mips16_type_p (const_tree type)
+mips_nomips16_decl_p (const_tree decl)
{
- return lookup_attribute ("mips16", TYPE_ATTRIBUTES (type)) != NULL;
+ return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
}
+/* Return true if function DECL is a MIPS16 function. Return the ambient
+ setting if DECL is null. */
+
static bool
-mips_nomips16_type_p (const_tree type)
+mips_use_mips16_mode_p (tree decl)
{
- return lookup_attribute ("nomips16", TYPE_ATTRIBUTES (type)) != NULL;
+ if (decl)
+ {
+ /* Nested functions must use the same frame pointer as their
+ parent and must therefore use the same ISA mode. */
+ tree parent = decl_function_context (decl);
+ if (parent)
+ decl = parent;
+ if (mips_mips16_decl_p (decl))
+ return true;
+ if (mips_nomips16_decl_p (decl))
+ return false;
+ }
+ return mips_base_mips16;
}
-/* Return 0 if the attributes for two types are incompatible, 1 if they
- are compatible, and 2 if they are nearly compatible (which causes a
- warning to be generated). */
+/* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
static int
mips_comp_type_attributes (const_tree type1, const_tree type2)
{
- /* Check for mismatch of non-default calling convention. */
- if (TREE_CODE (type1) != FUNCTION_TYPE)
- return 1;
-
/* Disallow mixed near/far attributes. */
if (mips_far_type_p (type1) && mips_near_type_p (type2))
return 0;
if (mips_near_type_p (type1) && mips_far_type_p (type2))
return 0;
+ return 1;
+}
- /* Mips16/nomips16 attributes must match exactly. */
- if (mips_nomips16_type_p (type1) != mips_nomips16_type_p (type2)
- || mips_mips16_type_p (type1) != mips_mips16_type_p (type2))
- return 0;
+/* Implement TARGET_INSERT_ATTRIBUTES. */
- return 1;
+static void
+mips_insert_attributes (tree decl, tree *attributes)
+{
+ const char *name;
+ bool mips16_p, nomips16_p;
+
+ /* Check for "mips16" and "nomips16" attributes. */
+ mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
+ nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
+ if (TREE_CODE (decl) != FUNCTION_DECL)
+ {
+ if (mips16_p)
+ error ("%qs attribute only applies to functions", "mips16");
+ if (nomips16_p)
+ error ("%qs attribute only applies to functions", "nomips16");
+ }
+ else
+ {
+ mips16_p |= mips_mips16_decl_p (decl);
+ nomips16_p |= mips_nomips16_decl_p (decl);
+ if (mips16_p || nomips16_p)
+ {
+ /* DECL cannot be simultaneously "mips16" and "nomips16". */
+ if (mips16_p && nomips16_p)
+ error ("%qs cannot have both %<mips16%> and "
+ "%<nomips16%> attributes",
+ IDENTIFIER_POINTER (DECL_NAME (decl)));
+ }
+ else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
+ {
+ /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
+ "mips16" attribute, arbitrarily pick one. We must pick the same
+ setting for duplicate declarations of a function. */
+ name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
+ *attributes = tree_cons (get_identifier (name), NULL, *attributes);
+ }
+ }
+}
+
+/* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
+
+static tree
+mips_merge_decl_attributes (tree olddecl, tree newdecl)
+{
+ /* The decls' "mips16" and "nomips16" attributes must match exactly. */
+ if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
+ error ("%qs redeclared with conflicting %qs attributes",
+ IDENTIFIER_POINTER (DECL_NAME (newdecl)), "mips16");
+ if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
+ error ("%qs redeclared with conflicting %qs attributes",
+ IDENTIFIER_POINTER (DECL_NAME (newdecl)), "nomips16");
+
+ return merge_attributes (DECL_ATTRIBUTES (olddecl),
+ DECL_ATTRIBUTES (newdecl));
}
\f
/* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
}
}
\f
-/* Return true if SYMBOL_REF X is associated with a global symbol
- (in the STB_GLOBAL sense). */
+static unsigned int mips_build_integer (struct mips_integer_op *,
+ unsigned HOST_WIDE_INT);
-static bool
-mips_global_symbol_p (const_rtx x)
-{
- const_tree const decl = SYMBOL_REF_DECL (x);
+/* A subroutine of mips_build_integer, with the same interface.
+ Assume that the final action in the sequence should be a left shift. */
- if (!decl)
- return !SYMBOL_REF_LOCAL_P (x);
+static unsigned int
+mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
+{
+ unsigned int i, shift;
- /* Weakref symbols are not TREE_PUBLIC, but their targets are global
+ /* Shift VALUE right until its lowest bit is set. Shift arithmetically
+ since signed numbers are easier to load than unsigned ones. */
+ shift = 0;
+ while ((value & 1) == 0)
+ value /= 2, shift++;
+
+ i = mips_build_integer (codes, value);
+ codes[i].code = ASHIFT;
+ codes[i].value = shift;
+ return i + 1;
+}
+
+/* As for mips_build_shift, but assume that the final action will be
+ an IOR or PLUS operation. */
+
+static unsigned int
+mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
+{
+ unsigned HOST_WIDE_INT high;
+ unsigned int i;
+
+ high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
+ if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
+ {
+ /* The constant is too complex to load with a simple LUI/ORI pair,
+ so we want to give the recursive call as many trailing zeros as
+ possible. In this case, we know bit 16 is set and that the
+ low 16 bits form a negative number. If we subtract that number
+ from VALUE, we will clear at least the lowest 17 bits, maybe more. */
+ i = mips_build_integer (codes, CONST_HIGH_PART (value));
+ codes[i].code = PLUS;
+ codes[i].value = CONST_LOW_PART (value);
+ }
+ else
+ {
+ /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
+ bits gives a value with at least 17 trailing zeros. */
+ i = mips_build_integer (codes, high);
+ codes[i].code = IOR;
+ codes[i].value = value & 0xffff;
+ }
+ return i + 1;
+}
+
+/* Fill CODES with a sequence of rtl operations to load VALUE.
+ Return the number of operations needed. */
+
+static unsigned int
+mips_build_integer (struct mips_integer_op *codes,
+ unsigned HOST_WIDE_INT value)
+{
+ if (SMALL_OPERAND (value)
+ || SMALL_OPERAND_UNSIGNED (value)
+ || LUI_OPERAND (value))
+ {
+ /* The value can be loaded with a single instruction. */
+ codes[0].code = UNKNOWN;
+ codes[0].value = value;
+ return 1;
+ }
+ else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
+ {
+ /* Either the constant is a simple LUI/ORI combination or its
+ lowest bit is set. We don't want to shift in this case. */
+ return mips_build_lower (codes, value);
+ }
+ else if ((value & 0xffff) == 0)
+ {
+ /* The constant will need at least three actions. The lowest
+ 16 bits are clear, so the final action will be a shift. */
+ return mips_build_shift (codes, value);
+ }
+ else
+ {
+ /* The final action could be a shift, add or inclusive OR.
+ Rather than use a complex condition to select the best
+ approach, try both mips_build_shift and mips_build_lower
+ and pick the one that gives the shortest sequence.
+ Note that this case is only used once per constant. */
+ struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
+ unsigned int cost, alt_cost;
+
+ cost = mips_build_shift (codes, value);
+ alt_cost = mips_build_lower (alt_codes, value);
+ if (alt_cost < cost)
+ {
+ memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
+ cost = alt_cost;
+ }
+ return cost;
+ }
+}
+\f
+/* Return true if X is a thread-local symbol. */
+
+static bool
+mips_tls_symbol_p (rtx x)
+{
+ return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
+}
+
+/* Return true if SYMBOL_REF X is associated with a global symbol
+ (in the STB_GLOBAL sense). */
+
+static bool
+mips_global_symbol_p (const_rtx x)
+{
+ const_tree decl = SYMBOL_REF_DECL (x);
+
+ if (!decl)
+ return !SYMBOL_REF_LOCAL_P (x);
+
+ /* Weakref symbols are not TREE_PUBLIC, but their targets are global
or weak symbols. Relocations in the object file will be against
the target symbol, so it's that symbol's binding that matters here. */
return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
{
return (!TARGET_EMBEDDED_DATA
&& TARGET_LOCAL_SDATA
- && GET_MODE_SIZE (mode) <= mips_section_threshold);
+ && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
+}
+
+/* Return true if X should not be moved directly into register $25.
+ We need this because many versions of GAS will treat "la $25,foo" as
+ part of a call sequence and so allow a global "foo" to be lazily bound. */
+
+bool
+mips_dangerous_for_la25_p (rtx x)
+{
+ return (!TARGET_EXPLICIT_RELOCS
+ && TARGET_USE_GOT
+ && GET_CODE (x) == SYMBOL_REF
+ && mips_global_symbol_p (x));
}
/* Return the method that should be used to access SYMBOL_REF or
the text section. */
if (TARGET_MIPS16_SHORT_JUMP_TABLES)
return SYMBOL_PC_RELATIVE;
+
if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
return SYMBOL_GOT_PAGE_OFST;
+
return SYMBOL_ABSOLUTE;
}
/* Do not use small-data accesses for weak symbols; they may end up
being zero. */
- if (TARGET_GPOPT
- && SYMBOL_REF_SMALL_P (x)
- && !SYMBOL_REF_WEAK (x))
+ if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
return SYMBOL_GP_RELATIVE;
/* Don't use GOT accesses for locally-binding symbols when -mno-shared
if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
return SYMBOL_FORCE_TO_MEM;
+
return SYMBOL_ABSOLUTE;
}
-/* Classify symbolic expression X, given that it appears in context
- CONTEXT. */
+/* Classify the base of symbolic expression X, given that X appears in
+ context CONTEXT. */
static enum mips_symbol_type
mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
}
/* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
- is the alignment (in bytes) of SYMBOL_REF X. */
+ is the alignment in bytes of SYMBOL_REF X. */
static bool
mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
{
- /* If for some reason we can't get the alignment for the
- symbol, initializing this to one means we will only accept
- a zero offset. */
- HOST_WIDE_INT align = 1;
- tree t;
+ HOST_WIDE_INT align;
- /* Get the alignment of the symbol we're referring to. */
- t = SYMBOL_REF_DECL (x);
- if (t)
- align = DECL_ALIGN_UNIT (t);
-
- return offset >= 0 && offset < align;
+ align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
+ return IN_RANGE (offset, 0, align - 1);
}
/* Return true if X is a symbolic constant that can be used in context
}
gcc_unreachable ();
}
+\f
+/* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
+ single instruction. We rely on the fact that, in the worst case,
+ all instructions involved in a MIPS16 address calculation are usually
+ extended ones. */
-
-/* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
-
-int
-mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
+static int
+mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
{
- if (!HARD_REGISTER_NUM_P (regno))
+ switch (type)
{
- if (!strict)
- return true;
- regno = reg_renumber[regno];
- }
+ case SYMBOL_ABSOLUTE:
+ /* When using 64-bit symbols, we need 5 preparatory instructions,
+ such as:
- /* These fake registers will be eliminated to either the stack or
- hard frame pointer, both of which are usually valid base registers.
- Reload deals with the cases where the eliminated form isn't valid. */
- if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
- return true;
+ lui $at,%highest(symbol)
+ daddiu $at,$at,%higher(symbol)
+ dsll $at,$at,16
+ daddiu $at,$at,%hi(symbol)
+ dsll $at,$at,16
- /* In mips16 mode, the stack pointer can only address word and doubleword
- values, nothing smaller. There are two problems here:
+ The final address is then $at + %lo(symbol). With 32-bit
+ symbols we just need a preparatory LUI for normal mode and
+ a preparatory LI and SLL for MIPS16. */
+ return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
- (a) Instantiating virtual registers can introduce new uses of the
- stack pointer. If these virtual registers are valid addresses,
- the stack pointer should be too.
+ case SYMBOL_GP_RELATIVE:
+ /* Treat GP-relative accesses as taking a single instruction on
+ MIPS16 too; the copy of $gp can often be shared. */
+ return 1;
- (b) Most uses of the stack pointer are not made explicit until
- FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
- We don't know until that stage whether we'll be eliminating to the
- stack pointer (which needs the restriction) or the hard frame
- pointer (which doesn't).
+ case SYMBOL_PC_RELATIVE:
+ /* PC-relative constants can be only be used with ADDIUPC,
+ DADDIUPC, LWPC and LDPC. */
+ if (mode == MAX_MACHINE_MODE
+ || GET_MODE_SIZE (mode) == 4
+ || GET_MODE_SIZE (mode) == 8)
+ return 1;
- All in all, it seems more consistent to only enforce this restriction
- during and after reload. */
- if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
- return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
+ /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
+ return 0;
- return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
+ case SYMBOL_FORCE_TO_MEM:
+ /* LEAs will be converted into constant-pool references by
+ mips_reorg. */
+ if (mode == MAX_MACHINE_MODE)
+ return 1;
+
+ /* The constant must be loaded and then dereferenced. */
+ return 0;
+
+ case SYMBOL_GOT_DISP:
+ /* The constant will have to be loaded from the GOT before it
+ is used in an address. */
+ if (mode != MAX_MACHINE_MODE)
+ return 0;
+
+ /* Fall through. */
+
+ case SYMBOL_GOT_PAGE_OFST:
+ /* Unless -funit-at-a-time is in effect, we can't be sure whether the
+ local/global classification is accurate. The worst cases are:
+
+ (1) For local symbols when generating o32 or o64 code. The assembler
+ will use:
+
+ lw $at,%got(symbol)
+ nop
+
+ ...and the final address will be $at + %lo(symbol).
+
+ (2) For global symbols when -mxgot. The assembler will use:
+
+ lui $at,%got_hi(symbol)
+ (d)addu $at,$at,$gp
+
+ ...and the final address will be $at + %got_lo(symbol). */
+ return 3;
+
+ case SYMBOL_GOTOFF_PAGE:
+ case SYMBOL_GOTOFF_DISP:
+ case SYMBOL_GOTOFF_CALL:
+ case SYMBOL_GOTOFF_LOADGP:
+ case SYMBOL_32_HIGH:
+ case SYMBOL_64_HIGH:
+ case SYMBOL_64_MID:
+ case SYMBOL_64_LOW:
+ case SYMBOL_TLSGD:
+ case SYMBOL_TLSLDM:
+ case SYMBOL_DTPREL:
+ case SYMBOL_GOTTPREL:
+ case SYMBOL_TPREL:
+ case SYMBOL_HALF:
+ /* A 16-bit constant formed by a single relocation, or a 32-bit
+ constant formed from a high 16-bit relocation and a low 16-bit
+ relocation. Use mips_split_p to determine which. 32-bit
+ constants need an "lui; addiu" sequence for normal mode and
+ an "li; sll; addiu" sequence for MIPS16 mode. */
+ return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
+
+ case SYMBOL_TLS:
+ /* We don't treat a bare TLS symbol as a constant. */
+ return 0;
+ }
+ gcc_unreachable ();
}
+/* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
+ to load symbols of type TYPE into a register. Return 0 if the given
+ type of symbol cannot be used as an immediate operand.
-/* Return true if X is a valid base register for the given mode.
- Allow only hard registers if STRICT. */
+ Otherwise, return the number of instructions needed to load or store
+ values of mode MODE to or from addresses of type TYPE. Return 0 if
+ the given type of symbol is not valid in addresses.
-static bool
-mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
-{
- if (!strict && GET_CODE (x) == SUBREG)
- x = SUBREG_REG (x);
+ In both cases, treat extended MIPS16 instructions as two instructions. */
- return (REG_P (x)
- && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
+static int
+mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
+{
+ return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
}
+\f
+/* A for_each_rtx callback. Stop the search if *X references a
+ thread-local symbol. */
+static int
+mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
+{
+ return mips_tls_symbol_p (*x);
+}
-/* Return true if X is a valid address for machine mode MODE. If it is,
- fill in INFO appropriately. STRICT is true if we should only accept
- hard base registers. */
+/* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
static bool
-mips_classify_address (struct mips_address_info *info, rtx x,
- enum machine_mode mode, int strict)
+mips_cannot_force_const_mem (rtx x)
{
- switch (GET_CODE (x))
- {
- case REG:
- case SUBREG:
- info->type = ADDRESS_REG;
- info->reg = x;
- info->offset = const0_rtx;
- return mips_valid_base_register_p (info->reg, mode, strict);
-
- case PLUS:
- info->type = ADDRESS_REG;
- info->reg = XEXP (x, 0);
- info->offset = XEXP (x, 1);
- return (mips_valid_base_register_p (info->reg, mode, strict)
- && const_arith_operand (info->offset, VOIDmode));
-
- case LO_SUM:
- info->type = ADDRESS_LO_SUM;
- info->reg = XEXP (x, 0);
- info->offset = XEXP (x, 1);
- /* We have to trust the creator of the LO_SUM to do something vaguely
- sane. Target-independent code that creates a LO_SUM should also
- create and verify the matching HIGH. Target-independent code that
- adds an offset to a LO_SUM must prove that the offset will not
- induce a carry. Failure to do either of these things would be
- a bug, and we are not required to check for it here. The MIPS
- backend itself should only create LO_SUMs for valid symbolic
- constants, with the high part being either a HIGH or a copy
- of _gp. */
- info->symbol_type
- = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
- return (mips_valid_base_register_p (info->reg, mode, strict)
- && mips_symbol_insns (info->symbol_type, mode) > 0
- && mips_lo_relocs[info->symbol_type] != 0);
-
- case CONST_INT:
- /* Small-integer addresses don't occur very often, but they
- are legitimate if $0 is a valid base register. */
- info->type = ADDRESS_CONST_INT;
- return !TARGET_MIPS16 && SMALL_INT (x);
-
- case CONST:
- case LABEL_REF:
- case SYMBOL_REF:
- info->type = ADDRESS_SYMBOLIC;
- return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
- &info->symbol_type)
- && mips_symbol_insns (info->symbol_type, mode) > 0
- && !mips_split_p[info->symbol_type]);
-
- default:
- return false;
- }
-}
-
-/* Return true if X is a thread-local symbol. */
-
-static bool
-mips_tls_operand_p (rtx x)
-{
- return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
-}
-
-/* Return true if X can not be forced into a constant pool. */
-
-static int
-mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
-{
- return mips_tls_operand_p (*x);
-}
-
-/* Return true if X can not be forced into a constant pool. */
-
-static bool
-mips_cannot_force_const_mem (rtx x)
-{
- rtx base, offset;
-
- if (!TARGET_MIPS16)
+ rtx base, offset;
+
+ if (!TARGET_MIPS16)
{
/* As an optimization, reject constants that mips_legitimize_move
can expand inline.
return true;
}
- if (TARGET_HAVE_TLS && for_each_rtx (&x, &mips_tls_symbol_ref_1, 0))
+ /* TLS symbols must be computed by mips_legitimize_move. */
+ if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
return true;
return false;
return !TARGET_MIPS16_PCREL_LOADS;
}
\f
-/* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
- single instruction. We rely on the fact that, in the worst case,
- all instructions involved in a MIPS16 address calculation are usually
- extended ones. */
+/* Return true if register REGNO is a valid base register for mode MODE.
+ STRICT_P is true if REG_OK_STRICT is in effect. */
-static int
-mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
+int
+mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
+ bool strict_p)
{
- switch (type)
+ if (!HARD_REGISTER_NUM_P (regno))
{
- case SYMBOL_ABSOLUTE:
- /* When using 64-bit symbols, we need 5 preparatory instructions,
- such as:
-
- lui $at,%highest(symbol)
- daddiu $at,$at,%higher(symbol)
- dsll $at,$at,16
- daddiu $at,$at,%hi(symbol)
- dsll $at,$at,16
-
- The final address is then $at + %lo(symbol). With 32-bit
- symbols we just need a preparatory lui for normal mode and
- a preparatory "li; sll" for MIPS16. */
- return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
+ if (!strict_p)
+ return true;
+ regno = reg_renumber[regno];
+ }
- case SYMBOL_GP_RELATIVE:
- /* Treat GP-relative accesses as taking a single instruction on
- MIPS16 too; the copy of $gp can often be shared. */
- return 1;
+ /* These fake registers will be eliminated to either the stack or
+ hard frame pointer, both of which are usually valid base registers.
+ Reload deals with the cases where the eliminated form isn't valid. */
+ if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
+ return true;
- case SYMBOL_PC_RELATIVE:
- /* PC-relative constants can be only be used with addiupc,
- lwpc and ldpc. */
- if (mode == MAX_MACHINE_MODE
- || GET_MODE_SIZE (mode) == 4
- || GET_MODE_SIZE (mode) == 8)
- return 1;
+ /* In MIPS16 mode, the stack pointer can only address word and doubleword
+ values, nothing smaller. There are two problems here:
- /* The constant must be loaded using addiupc first. */
- return 0;
+ (a) Instantiating virtual registers can introduce new uses of the
+ stack pointer. If these virtual registers are valid addresses,
+ the stack pointer should be too.
- case SYMBOL_FORCE_TO_MEM:
- /* The constant must be loaded from the constant pool. */
- return 0;
+ (b) Most uses of the stack pointer are not made explicit until
+ FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
+ We don't know until that stage whether we'll be eliminating to the
+ stack pointer (which needs the restriction) or the hard frame
+ pointer (which doesn't).
- case SYMBOL_GOT_DISP:
- /* The constant will have to be loaded from the GOT before it
- is used in an address. */
- if (mode != MAX_MACHINE_MODE)
- return 0;
+ All in all, it seems more consistent to only enforce this restriction
+ during and after reload. */
+ if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
+ return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
- /* Fall through. */
+ return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
+}
- case SYMBOL_GOT_PAGE_OFST:
- /* Unless -funit-at-a-time is in effect, we can't be sure whether
- the local/global classification is accurate. See override_options
- for details.
+/* Return true if X is a valid base register for mode MODE.
+ STRICT_P is true if REG_OK_STRICT is in effect. */
- The worst cases are:
+static bool
+mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
+{
+ if (!strict_p && GET_CODE (x) == SUBREG)
+ x = SUBREG_REG (x);
- (1) For local symbols when generating o32 or o64 code. The assembler
- will use:
+ return (REG_P (x)
+ && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
+}
- lw $at,%got(symbol)
- nop
+/* Return true if X is a valid address for machine mode MODE. If it is,
+ fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
+ effect. */
- ...and the final address will be $at + %lo(symbol).
+static bool
+mips_classify_address (struct mips_address_info *info, rtx x,
+ enum machine_mode mode, bool strict_p)
+{
+ switch (GET_CODE (x))
+ {
+ case REG:
+ case SUBREG:
+ info->type = ADDRESS_REG;
+ info->reg = x;
+ info->offset = const0_rtx;
+ return mips_valid_base_register_p (info->reg, mode, strict_p);
- (2) For global symbols when -mxgot. The assembler will use:
+ case PLUS:
+ info->type = ADDRESS_REG;
+ info->reg = XEXP (x, 0);
+ info->offset = XEXP (x, 1);
+ return (mips_valid_base_register_p (info->reg, mode, strict_p)
+ && const_arith_operand (info->offset, VOIDmode));
- lui $at,%got_hi(symbol)
- (d)addu $at,$at,$gp
+ case LO_SUM:
+ info->type = ADDRESS_LO_SUM;
+ info->reg = XEXP (x, 0);
+ info->offset = XEXP (x, 1);
+ /* We have to trust the creator of the LO_SUM to do something vaguely
+ sane. Target-independent code that creates a LO_SUM should also
+ create and verify the matching HIGH. Target-independent code that
+ adds an offset to a LO_SUM must prove that the offset will not
+ induce a carry. Failure to do either of these things would be
+ a bug, and we are not required to check for it here. The MIPS
+ backend itself should only create LO_SUMs for valid symbolic
+ constants, with the high part being either a HIGH or a copy
+ of _gp. */
+ info->symbol_type
+ = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
+ return (mips_valid_base_register_p (info->reg, mode, strict_p)
+ && mips_symbol_insns (info->symbol_type, mode) > 0
+ && mips_lo_relocs[info->symbol_type] != 0);
- ...and the final address will be $at + %got_lo(symbol). */
- return 3;
+ case CONST_INT:
+ /* Small-integer addresses don't occur very often, but they
+ are legitimate if $0 is a valid base register. */
+ info->type = ADDRESS_CONST_INT;
+ return !TARGET_MIPS16 && SMALL_INT (x);
- case SYMBOL_GOTOFF_PAGE:
- case SYMBOL_GOTOFF_DISP:
- case SYMBOL_GOTOFF_CALL:
- case SYMBOL_GOTOFF_LOADGP:
- case SYMBOL_32_HIGH:
- case SYMBOL_64_HIGH:
- case SYMBOL_64_MID:
- case SYMBOL_64_LOW:
- case SYMBOL_TLSGD:
- case SYMBOL_TLSLDM:
- case SYMBOL_DTPREL:
- case SYMBOL_GOTTPREL:
- case SYMBOL_TPREL:
- case SYMBOL_HALF:
- /* A 16-bit constant formed by a single relocation, or a 32-bit
- constant formed from a high 16-bit relocation and a low 16-bit
- relocation. Use mips_split_p to determine which. */
- return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
+ case CONST:
+ case LABEL_REF:
+ case SYMBOL_REF:
+ info->type = ADDRESS_SYMBOLIC;
+ return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
+ &info->symbol_type)
+ && mips_symbol_insns (info->symbol_type, mode) > 0
+ && !mips_split_p[info->symbol_type]);
- case SYMBOL_TLS:
- /* We don't treat a bare TLS symbol as a constant. */
- return 0;
+ default:
+ return false;
}
- gcc_unreachable ();
}
-/* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
- to load symbols of type TYPE into a register. Return 0 if the given
- type of symbol cannot be used as an immediate operand.
-
- Otherwise, return the number of instructions needed to load or store
- values of mode MODE to or from addresses of type TYPE. Return 0 if
- the given type of symbol is not valid in addresses.
-
- In both cases, treat extended MIPS16 instructions as two instructions. */
+/* Return true if X is a legitimate address for a memory operand of mode
+ MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
-static int
-mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
+bool
+mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
{
- return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
+ struct mips_address_info addr;
+
+ return mips_classify_address (&addr, x, mode, strict_p);
}
/* Return true if X is a legitimate $sp-based address for mode MDOE. */
&& addr.reg == stack_pointer_rtx);
}
-/* Return true if a value at OFFSET bytes from BASE can be accessed
- using an unextended mips16 instruction. MODE is the mode of the
- value.
+/* Return true if ADDR matches the pattern for the LWXS load scaled indexed
+ address instruction. Note that such addresses are not considered
+ legitimate in the GO_IF_LEGITIMATE_ADDRESS sense, because their use
+ is so restricted. */
+
+static bool
+mips_lwxs_address_p (rtx addr)
+{
+ if (ISA_HAS_LWXS
+ && GET_CODE (addr) == PLUS
+ && REG_P (XEXP (addr, 1)))
+ {
+ rtx offset = XEXP (addr, 0);
+ if (GET_CODE (offset) == MULT
+ && REG_P (XEXP (offset, 0))
+ && GET_CODE (XEXP (offset, 1)) == CONST_INT
+ && INTVAL (XEXP (offset, 1)) == 4)
+ return true;
+ }
+ return false;
+}
+\f
+/* Return true if a value at OFFSET bytes from base register BASE can be
+ accessed using an unextended MIPS16 instruction. MODE is the mode of
+ the value.
Usually the offset in an unextended instruction is a 5-bit field.
- The offset is unsigned and shifted left once for HIs, twice
- for SIs, and so on. An exception is SImode accesses off the
- stack pointer, which have an 8-bit immediate field. */
+ The offset is unsigned and shifted left once for LH and SH, twice
+ for LW and SW, and so on. An exception is LWSP and SWSP, which have
+ an 8-bit immediate field that's shifted left twice. */
static bool
-mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
+mips16_unextended_reference_p (enum machine_mode mode, rtx base,
+ unsigned HOST_WIDE_INT offset)
{
- if (TARGET_MIPS16
- && GET_CODE (offset) == CONST_INT
- && INTVAL (offset) >= 0
- && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
+ if (offset % GET_MODE_SIZE (mode) == 0)
{
if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
- return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
- return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
+ return offset < 256U * GET_MODE_SIZE (mode);
+ return offset < 32U * GET_MODE_SIZE (mode);
}
return false;
}
-
/* Return the number of instructions needed to load or store a value
- of mode MODE at X. Return 0 if X isn't valid for MODE. Assume that
- multiword moves may need to be split into word moves if MIGHT_SPLIT_P,
- otherwise assume that a single load or store is enough.
+ of mode MODE at address X. Return 0 if X isn't valid for MODE.
+ Assume that multiword moves may need to be split into word moves
+ if MIGHT_SPLIT_P, otherwise assume that a single load or store is
+ enough.
- For mips16 code, count extended instructions as two instructions. */
+ For MIPS16 code, count extended instructions as two instructions. */
int
mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
{
case ADDRESS_REG:
if (TARGET_MIPS16
- && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
+ && !mips16_unextended_reference_p (mode, addr.reg,
+ UINTVAL (addr.offset)))
return factor * 2;
return factor;
case ADDRESS_LO_SUM:
- return (TARGET_MIPS16 ? factor * 2 : factor);
+ return TARGET_MIPS16 ? factor * 2 : factor;
case ADDRESS_CONST_INT:
return factor;
return 0;
}
-
-/* Likewise for constant X. */
+/* Return the number of instructions needed to load constant X.
+ Return 0 if X isn't a valid constant. */
int
mips_const_insns (rtx x)
|| !mips_split_p[symbol_type])
return 0;
- /* This is simply an lui for normal mode. It is an extended
- "li" followed by an extended "sll" for MIPS16. */
+ /* This is simply an LUI for normal mode. It is an extended
+ LI followed by an extended SLL for MIPS16. */
return TARGET_MIPS16 ? 4 : 1;
case CONST_INT:
LI instruction. Unsigned 16-bit constants can be loaded
using an extended LI. Negative constants must be loaded
using LI and then negated. */
- return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
+ return (IN_RANGE (INTVAL (x), 0, 255) ? 1
: SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
- : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
+ : IN_RANGE (-INTVAL (x), 0, 255) ? 2
: SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
: 0);
case CONST_DOUBLE:
case CONST_VECTOR:
- return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
+ /* Allow zeros for normal mode, where we can use $0. */
+ return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
case CONST:
if (CONST_GP_P (x))
return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
/* Otherwise try splitting the constant into a base and offset.
- 16-bit offsets can be added using an extra addiu. Larger offsets
+ 16-bit offsets can be added using an extra ADDIU. Larger offsets
must be calculated separately and then added to the base. */
split_const (x, &x, &offset);
if (offset != 0)
}
}
-
/* Return the number of instructions needed to implement INSN,
given that it loads from or stores to MEM. Count extended
- mips16 instructions as two instructions. */
+ MIPS16 instructions as two instructions. */
int
mips_load_store_insns (rtx mem, rtx insn)
return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
}
-
/* Return the number of instructions needed for an integer division. */
int
return count;
}
\f
-/* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
- returns a nonzero value if X is a legitimate address for a memory
- operand of the indicated MODE. STRICT is nonzero if this function
- is called during reload. */
-
-bool
-mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
-{
- struct mips_address_info addr;
-
- return mips_classify_address (&addr, x, mode, strict);
-}
-
/* Emit a move from SRC to DEST. Assume that the move expanders can
handle all moves if !can_create_pseudo_p (). The distinction is
important because, unlike emit_move_insn, the move expanders know
: emit_move_insn_1 (dest, src));
}
-/* Copy VALUE to a register and return that register. If new psuedos
+/* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
+
+static void
+mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
+{
+ emit_insn (gen_rtx_SET (VOIDmode, target,
+ gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
+}
+
+/* Copy VALUE to a register and return that register. If new pseudos
are allowed, copy it into a new register, otherwise use DEST. */
static rtx
return force_reg (Pmode, value);
else
{
- mips_emit_move (copy_rtx (dest), value);
+ mips_emit_move (dest, value);
return dest;
}
}
+/* Emit a call sequence with call pattern PATTERN and return the call
+ instruction itself (which is not necessarily the last instruction
+ emitted). LAZY_P is true if the call address is lazily-bound. */
+
+static rtx
+mips_emit_call_insn (rtx pattern, bool lazy_p)
+{
+ rtx insn;
+
+ insn = emit_call_insn (pattern);
+
+ /* Lazy-binding stubs require $gp to be valid on entry. */
+ if (lazy_p)
+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
+
+ if (TARGET_USE_GOT)
+ {
+ /* See the comment above load_call<mode> for details. */
+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
+ gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
+ emit_insn (gen_update_got_version ());
+ }
+ return insn;
+}
+\f
+/* Return an instruction that copies $gp into register REG. We want
+ GCC to treat the register's value as constant, so that its value
+ can be rematerialized on demand. */
+
+static rtx
+gen_load_const_gp (rtx reg)
+{
+ return (Pmode == SImode
+ ? gen_load_const_gp_si (reg)
+ : gen_load_const_gp_di (reg));
+}
+
+/* Return a pseudo register that contains the value of $gp throughout
+ the current function. Such registers are needed by MIPS16 functions,
+ for which $gp itself is not a valid base register or addition operand. */
+
+static rtx
+mips16_gp_pseudo_reg (void)
+{
+ if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
+ cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
+
+ /* Don't emit an instruction to initialize the pseudo register if
+ we are being called from the tree optimizers' cost-calculation
+ routines. */
+ if (!cfun->machine->initialized_mips16_gp_pseudo_p
+ && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
+ {
+ rtx insn, scan, after;
+
+ insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
+
+ push_topmost_sequence ();
+ /* We need to emit the initialization after the FUNCTION_BEG
+ note, so that it will be integrated. */
+ after = get_insns ();
+ for (scan = after; scan != NULL_RTX; scan = NEXT_INSN (scan))
+ if (NOTE_P (scan) && NOTE_KIND (scan) == NOTE_INSN_FUNCTION_BEG)
+ {
+ after = scan;
+ break;
+ }
+ insn = emit_insn_after (insn, after);
+ pop_topmost_sequence ();
+
+ cfun->machine->initialized_mips16_gp_pseudo_p = true;
+ }
+
+ return cfun->machine->mips16_gp_pseudo_rtx;
+}
/* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
it appears in a MEM of that mode. Return true if ADDR is a legitimate
{
if (!can_create_pseudo_p ())
{
- emit_insn (gen_load_const_gp (copy_rtx (temp)));
+ emit_insn (gen_load_const_gp (temp));
high = temp;
}
else
return true;
}
-
-/* Wrap symbol or label BASE in an unspec address of type SYMBOL_TYPE
- and add CONST_INT OFFSET to the result. */
+/* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
+ then add CONST_INT OFFSET to the result. */
static rtx
mips_unspec_address_offset (rtx base, rtx offset,
return mips_unspec_address_offset (base, offset, symbol_type);
}
-
/* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
high part to BASE and return the result. Just return BASE otherwise.
- TEMP is available as a temporary register if needed.
+ TEMP is as for mips_force_temporary.
The returned expression can be used as the first operand to a LO_SUM. */
{
addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
addr = mips_force_temporary (temp, addr);
- return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
+ base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
}
return base;
}
-
/* Return a legitimate address for REG + OFFSET. TEMP is as for
mips_force_temporary; it is only needed when OFFSET is not a
SMALL_OPERAND. */
if (!SMALL_OPERAND (offset))
{
rtx high;
+
if (TARGET_MIPS16)
{
/* Load the full offset into a register so that we can use
}
return plus_constant (reg, offset);
}
-
-/* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
- referencing, and TYPE is the symbol type to use (either global
- dynamic or local dynamic). V0 is an RTX for the return value
- location. The entire insn sequence is returned. */
-
+\f
+/* The __tls_get_attr symbol. */
static GTY(()) rtx mips_tls_symbol;
+/* Return an instruction sequence that calls __tls_get_addr. SYM is
+ the TLS symbol we are referencing and TYPE is the symbol type to use
+ (either global dynamic or local dynamic). V0 is an RTX for the
+ return value location. */
+
static rtx
mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
{
- rtx insn, loc, tga, a0;
+ rtx insn, loc, a0;
a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
emit_insn (gen_rtx_SET (Pmode, a0,
gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
- tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
- insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
+ insn = mips_expand_call (v0, mips_tls_symbol, const0_rtx, const0_rtx, false);
CONST_OR_PURE_CALL_P (insn) = 1;
- use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
insn = get_insns ();
return insn;
}
-/* Generate the code to access LOC, a thread local SYMBOL_REF. The
- return value will be a valid address and move_operand (either a REG
- or a LO_SUM). */
+/* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
+ its address. The return value will be both a valid address and a valid
+ SET_SRC (either a REG or a LO_SUM). */
static rtx
mips_legitimize_tls_address (rtx loc)
return gen_reg_rtx (Pmode);
}
- v0 = gen_rtx_REG (Pmode, GP_RETURN);
- v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
-
model = SYMBOL_REF_TLS_MODEL (loc);
/* Only TARGET_ABICALLS code can have more than one module; other
code must be be static and should not use a GOT. All TLS models
switch (model)
{
case TLS_MODEL_GLOBAL_DYNAMIC:
+ v0 = gen_rtx_REG (Pmode, GP_RETURN);
insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
dest = gen_reg_rtx (Pmode);
emit_libcall_block (insn, dest, v0, loc);
break;
case TLS_MODEL_LOCAL_DYNAMIC:
+ v0 = gen_rtx_REG (Pmode, GP_RETURN);
insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
tmp1 = gen_reg_rtx (Pmode);
break;
case TLS_MODEL_INITIAL_EXEC:
+ v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
tmp1 = gen_reg_rtx (Pmode);
tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
if (Pmode == DImode)
break;
case TLS_MODEL_LOCAL_EXEC:
+ v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
if (Pmode == DImode)
emit_insn (gen_tls_get_tp_di (v1));
else
default:
gcc_unreachable ();
}
-
return dest;
}
-
+\f
/* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
be legitimized in a way that the generic machinery might not expect,
put the new address in *XLOC and return true. MODE is the mode of
bool
mips_legitimize_address (rtx *xloc, enum machine_mode mode)
{
- if (mips_tls_operand_p (*xloc))
+ rtx base;
+ HOST_WIDE_INT offset;
+
+ if (mips_tls_symbol_p (*xloc))
{
*xloc = mips_legitimize_tls_address (*xloc);
return true;
if (mips_split_symbol (NULL, *xloc, mode, xloc))
return true;
- if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
+ /* Handle BASE + OFFSET using mips_add_offset. */
+ mips_split_plus (*xloc, &base, &offset);
+ if (offset != 0)
{
- /* Handle REG + CONSTANT using mips_add_offset. */
- rtx reg;
-
- reg = XEXP (*xloc, 0);
- if (!mips_valid_base_register_p (reg, mode, 0))
- reg = copy_to_mode_reg (Pmode, reg);
- *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
+ if (!mips_valid_base_register_p (base, mode, false))
+ base = copy_to_mode_reg (Pmode, base);
+ *xloc = mips_add_offset (NULL, base, offset);
return true;
}
-
return false;
}
-
-/* Subroutine of mips_build_integer (with the same interface).
- Assume that the final action in the sequence should be a left shift. */
-
-static unsigned int
-mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
-{
- unsigned int i, shift;
-
- /* Shift VALUE right until its lowest bit is set. Shift arithmetically
- since signed numbers are easier to load than unsigned ones. */
- shift = 0;
- while ((value & 1) == 0)
- value /= 2, shift++;
-
- i = mips_build_integer (codes, value);
- codes[i].code = ASHIFT;
- codes[i].value = shift;
- return i + 1;
-}
-
-
-/* As for mips_build_shift, but assume that the final action will be
- an IOR or PLUS operation. */
-
-static unsigned int
-mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
-{
- unsigned HOST_WIDE_INT high;
- unsigned int i;
-
- high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
- if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
- {
- /* The constant is too complex to load with a simple lui/ori pair
- so our goal is to clear as many trailing zeros as possible.
- In this case, we know bit 16 is set and that the low 16 bits
- form a negative number. If we subtract that number from VALUE,
- we will clear at least the lowest 17 bits, maybe more. */
- i = mips_build_integer (codes, CONST_HIGH_PART (value));
- codes[i].code = PLUS;
- codes[i].value = CONST_LOW_PART (value);
- }
- else
- {
- i = mips_build_integer (codes, high);
- codes[i].code = IOR;
- codes[i].value = value & 0xffff;
- }
- return i + 1;
-}
-
-
-/* Fill CODES with a sequence of rtl operations to load VALUE.
- Return the number of operations needed. */
-
-static unsigned int
-mips_build_integer (struct mips_integer_op *codes,
- unsigned HOST_WIDE_INT value)
-{
- if (SMALL_OPERAND (value)
- || SMALL_OPERAND_UNSIGNED (value)
- || LUI_OPERAND (value))
- {
- /* The value can be loaded with a single instruction. */
- codes[0].code = UNKNOWN;
- codes[0].value = value;
- return 1;
- }
- else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
- {
- /* Either the constant is a simple LUI/ORI combination or its
- lowest bit is set. We don't want to shift in this case. */
- return mips_build_lower (codes, value);
- }
- else if ((value & 0xffff) == 0)
- {
- /* The constant will need at least three actions. The lowest
- 16 bits are clear, so the final action will be a shift. */
- return mips_build_shift (codes, value);
- }
- else
- {
- /* The final action could be a shift, add or inclusive OR.
- Rather than use a complex condition to select the best
- approach, try both mips_build_shift and mips_build_lower
- and pick the one that gives the shortest sequence.
- Note that this case is only used once per constant. */
- struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
- unsigned int cost, alt_cost;
-
- cost = mips_build_shift (codes, value);
- alt_cost = mips_build_lower (alt_codes, value);
- if (alt_cost < cost)
- {
- memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
- cost = alt_cost;
- }
- return cost;
- }
-}
-
-
-/* Load VALUE into DEST, using TEMP as a temporary register if need be. */
+/* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
void
-mips_move_integer (rtx dest, rtx temp, unsigned HOST_WIDE_INT value)
+mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
{
struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
enum machine_mode mode;
- unsigned int i, cost;
+ unsigned int i, num_ops;
rtx x;
mode = GET_MODE (dest);
- cost = mips_build_integer (codes, value);
+ num_ops = mips_build_integer (codes, value);
/* Apply each binary operation to X. Invariant: X is a legitimate
source operand for a SET pattern. */
x = GEN_INT (codes[0].value);
- for (i = 1; i < cost; i++)
+ for (i = 1; i < num_ops; i++)
{
if (!can_create_pseudo_p ())
{
emit_insn (gen_rtx_SET (VOIDmode, dest, x));
}
-
/* Subroutine of mips_legitimize_move. Move constant SRC into register
DEST given that SRC satisfies immediate_operand but doesn't satisfy
move_operand. */
return;
}
- if (mips_tls_operand_p (src))
+ /* Generate the appropriate access sequences for TLS symbols. */
+ if (mips_tls_symbol_p (src))
{
mips_emit_move (dest, mips_legitimize_tls_address (src));
return;
|| (!TARGET_MIPS16 && can_create_pseudo_p ())))
{
base = mips_force_temporary (dest, base);
- mips_emit_move (dest, mips_add_offset (0, base, INTVAL (offset)));
+ mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
return;
}
mips_emit_move (dest, src);
}
-
-/* If (set DEST SRC) is not a valid instruction, emit an equivalent
+/* If (set DEST SRC) is not a valid move instruction, emit an equivalent
sequence that is valid. */
bool
{
int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
if (GET_MODE_SIZE (mode) <= 4)
- emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
- gen_rtx_REG (SImode, REGNO (src)),
+ emit_insn (gen_mfhilo_si (gen_lowpart (SImode, dest),
+ gen_lowpart (SImode, src),
gen_rtx_REG (SImode, other_regno)));
else
- emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
- gen_rtx_REG (DImode, REGNO (src)),
+ emit_insn (gen_mfhilo_di (gen_lowpart (DImode, dest),
+ gen_lowpart (DImode, src),
gen_rtx_REG (DImode, other_regno)));
return true;
}
/* We need to deal with constants that would be legitimate
- immediate_operands but not legitimate move_operands. */
+ immediate_operands but aren't legitimate move_operands. */
if (CONSTANT_P (src) && !move_operand (src, mode))
{
mips_legitimize_const_move (mode, dest, src);
return false;
}
\f
-/* We need a lot of little routines to check constant values on the
- mips16. These are used to figure out how long the instruction will
- be. It would be much better to do this using constraints, but
- there aren't nearly enough letters available. */
+/* Return true if value X in context CONTEXT is a small-data address
+ that can be rewritten as a LO_SUM. */
+
+static bool
+mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
+{
+ enum mips_symbol_type symbol_type;
+
+ return (TARGET_EXPLICIT_RELOCS
+ && mips_symbolic_constant_p (x, context, &symbol_type)
+ && symbol_type == SYMBOL_GP_RELATIVE);
+}
+
+/* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
+ containing MEM, or null if none. */
+
+static int
+mips_small_data_pattern_1 (rtx *loc, void *data)
+{
+ enum mips_symbol_context context;
+
+ if (GET_CODE (*loc) == LO_SUM)
+ return -1;
+
+ if (MEM_P (*loc))
+ {
+ if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
+ return 1;
+ return -1;
+ }
+
+ context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
+ return mips_rewrite_small_data_p (*loc, context);
+}
+
+/* Return true if OP refers to small data symbols directly, not through
+ a LO_SUM. */
+
+bool
+mips_small_data_pattern_p (rtx op)
+{
+ return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
+}
+
+/* A for_each_rtx callback, used by mips_rewrite_small_data.
+ DATA is the containing MEM, or null if none. */
+
+static int
+mips_rewrite_small_data_1 (rtx *loc, void *data)
+{
+ enum mips_symbol_context context;
+
+ if (MEM_P (*loc))
+ {
+ for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
+ return -1;
+ }
+
+ context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
+ if (mips_rewrite_small_data_p (*loc, context))
+ *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
+
+ if (GET_CODE (*loc) == LO_SUM)
+ return -1;
+
+ return 0;
+}
+
+/* Rewrite instruction pattern PATTERN so that it refers to small data
+ using explicit relocations. */
+
+rtx
+mips_rewrite_small_data (rtx pattern)
+{
+ pattern = copy_insn (pattern);
+ for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
+ return pattern;
+}
+\f
+/* We need a lot of little routines to check the range of MIPS16 immediate
+ operands. */
static int
m16_check_op (rtx op, int low, int high, int mask)
{
return (GET_CODE (op) == CONST_INT
- && INTVAL (op) >= low
- && INTVAL (op) <= high
+ && IN_RANGE (INTVAL (op), low, high)
&& (INTVAL (op) & mask) == 0);
}
int
m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
- return m16_check_op (op, - 0x8, 0x7, 0);
+ return m16_check_op (op, -0x8, 0x7, 0);
}
int
m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
- return m16_check_op (op, - 0x7, 0x8, 0);
+ return m16_check_op (op, -0x7, 0x8, 0);
}
int
m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
- return m16_check_op (op, - 0x10, 0xf, 0);
+ return m16_check_op (op, -0x10, 0xf, 0);
}
int
m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
- return m16_check_op (op, - 0xf, 0x10, 0);
+ return m16_check_op (op, -0xf, 0x10, 0);
}
int
m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
- return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
+ return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
}
int
m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
- return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
+ return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
}
int
m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
- return m16_check_op (op, - 0x80, 0x7f, 0);
+ return m16_check_op (op, -0x80, 0x7f, 0);
}
int
m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
- return m16_check_op (op, - 0x7f, 0x80, 0);
+ return m16_check_op (op, -0x7f, 0x80, 0);
}
int
int
m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
- return m16_check_op (op, - 0xff, 0x0, 0);
+ return m16_check_op (op, -0xff, 0x0, 0);
}
int
m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
- return m16_check_op (op, - 0x1, 0xfe, 0);
+ return m16_check_op (op, -0x1, 0xfe, 0);
}
int
int
m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
- return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
+ return m16_check_op (op, -0xff << 2, 0x0, 3);
}
int
m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
- return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
+ return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
}
int
m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
- return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
+ return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
}
\f
-/* Return true if ADDR matches the pattern for the lwxs load scaled indexed
- address instruction. */
+/* The cost of loading values from the constant pool. It should be
+ larger than the cost of any constant we want to synthesize inline. */
+#define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
-static bool
-mips_lwxs_address_p (rtx addr)
+/* Return the cost of X when used as an operand to the MIPS16 instruction
+ that implements CODE. Return -1 if there is no such instruction, or if
+ X is not a valid immediate operand for it. */
+
+static int
+mips16_constant_cost (int code, HOST_WIDE_INT x)
{
- if (ISA_HAS_LWXS
- && GET_CODE (addr) == PLUS
- && REG_P (XEXP (addr, 1)))
+ switch (code)
{
- rtx offset = XEXP (addr, 0);
- if (GET_CODE (offset) == MULT
- && REG_P (XEXP (offset, 0))
- && GET_CODE (XEXP (offset, 1)) == CONST_INT
- && INTVAL (XEXP (offset, 1)) == 4)
- return true;
+ case ASHIFT:
+ case ASHIFTRT:
+ case LSHIFTRT:
+ /* Shifts by between 1 and 8 bits (inclusive) are unextended,
+ other shifts are extended. The shift patterns truncate the shift
+ count to the right size, so there are no out-of-range values. */
+ if (IN_RANGE (x, 1, 8))
+ return 0;
+ return COSTS_N_INSNS (1);
+
+ case PLUS:
+ if (IN_RANGE (x, -128, 127))
+ return 0;
+ if (SMALL_OPERAND (x))
+ return COSTS_N_INSNS (1);
+ return -1;
+
+ case LEU:
+ /* Like LE, but reject the always-true case. */
+ if (x == -1)
+ return -1;
+ case LE:
+ /* We add 1 to the immediate and use SLT. */
+ x += 1;
+ case XOR:
+ /* We can use CMPI for an xor with an unsigned 16-bit X. */
+ case LT:
+ case LTU:
+ if (IN_RANGE (x, 0, 255))
+ return 0;
+ if (SMALL_OPERAND_UNSIGNED (x))
+ return COSTS_N_INSNS (1);
+ return -1;
+
+ case EQ:
+ case NE:
+ /* Equality comparisons with 0 are cheap. */
+ if (x == 0)
+ return 0;
+ return -1;
+
+ default:
+ return -1;
}
- return false;
}
+/* Return true if there is a non-MIPS16 instruction that implements CODE
+ and if that instruction accepts X as an immediate operand. */
+
+static int
+mips_immediate_operand_p (int code, HOST_WIDE_INT x)
+{
+ switch (code)
+ {
+ case ASHIFT:
+ case ASHIFTRT:
+ case LSHIFTRT:
+ /* All shift counts are truncated to a valid constant. */
+ return true;
+
+ case ROTATE:
+ case ROTATERT:
+ /* Likewise rotates, if the target supports rotates at all. */
+ return ISA_HAS_ROR;
+
+ case AND:
+ case IOR:
+ case XOR:
+ /* These instructions take 16-bit unsigned immediates. */
+ return SMALL_OPERAND_UNSIGNED (x);
+
+ case PLUS:
+ case LT:
+ case LTU:
+ /* These instructions take 16-bit signed immediates. */
+ return SMALL_OPERAND (x);
+
+ case EQ:
+ case NE:
+ case GT:
+ case GTU:
+ /* The "immediate" forms of these instructions are really
+ implemented as comparisons with register 0. */
+ return x == 0;
+
+ case GE:
+ case GEU:
+ /* Likewise, meaning that the only valid immediate operand is 1. */
+ return x == 1;
+
+ case LE:
+ /* We add 1 to the immediate and use SLT. */
+ return SMALL_OPERAND (x + 1);
+
+ case LEU:
+ /* Likewise SLTU, but reject the always-true case. */
+ return SMALL_OPERAND (x + 1) && x + 1 != 0;
+
+ case SIGN_EXTRACT:
+ case ZERO_EXTRACT:
+ /* The bit position and size are immediate operands. */
+ return ISA_HAS_EXT_INS;
+
+ default:
+ /* By default assume that $0 can be used for 0. */
+ return x == 0;
+ }
+}
+
+/* Return the cost of binary operation X, given that the instruction
+ sequence for a word-sized or smaller operation has cost SINGLE_COST
+ and that the sequence of a double-word operation has cost DOUBLE_COST. */
+
+static int
+mips_binary_cost (rtx x, int single_cost, int double_cost)
+{
+ int cost;
+
+ if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
+ cost = double_cost;
+ else
+ cost = single_cost;
+ return (cost
+ + rtx_cost (XEXP (x, 0), 0)
+ + rtx_cost (XEXP (x, 1), GET_CODE (x)));
+}
+
+/* Return the cost of floating-point multiplications of mode MODE. */
+
+static int
+mips_fp_mult_cost (enum machine_mode mode)
+{
+ return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
+}
+
+/* Return the cost of floating-point divisions of mode MODE. */
+
+static int
+mips_fp_div_cost (enum machine_mode mode)
+{
+ return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
+}
+
+/* Return the cost of sign-extending OP to mode MODE, not including the
+ cost of OP itself. */
+
+static int
+mips_sign_extend_cost (enum machine_mode mode, rtx op)
+{
+ if (MEM_P (op))
+ /* Extended loads are as cheap as unextended ones. */
+ return 0;
+
+ if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
+ /* A sign extension from SImode to DImode in 64-bit mode is free. */
+ return 0;
+
+ if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
+ /* We can use SEB or SEH. */
+ return COSTS_N_INSNS (1);
+
+ /* We need to use a shift left and a shift right. */
+ return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
+}
+
+/* Return the cost of zero-extending OP to mode MODE, not including the
+ cost of OP itself. */
+
+static int
+mips_zero_extend_cost (enum machine_mode mode, rtx op)
+{
+ if (MEM_P (op))
+ /* Extended loads are as cheap as unextended ones. */
+ return 0;
+
+ if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
+ /* We need a shift left by 32 bits and a shift right by 32 bits. */
+ return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
+
+ if (GENERATE_MIPS16E)
+ /* We can use ZEB or ZEH. */
+ return COSTS_N_INSNS (1);
+
+ if (TARGET_MIPS16)
+ /* We need to load 0xff or 0xffff into a register and use AND. */
+ return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
+
+ /* We can use ANDI. */
+ return COSTS_N_INSNS (1);
+}
+
+/* Implement TARGET_RTX_COSTS. */
+
static bool
mips_rtx_costs (rtx x, int code, int outer_code, int *total)
{
enum machine_mode mode = GET_MODE (x);
bool float_mode_p = FLOAT_MODE_P (mode);
+ int cost;
+ rtx addr;
+
+ /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
+ appear in the instruction stream, and the cost of a comparison is
+ really the cost of the branch or scc condition. At the time of
+ writing, GCC only uses an explicit outer COMPARE code when optabs
+ is testing whether a constant is expensive enough to force into a
+ register. We want optabs to pass such constants through the MIPS
+ expanders instead, so make all constants very cheap here. */
+ if (outer_code == COMPARE)
+ {
+ gcc_assert (CONSTANT_P (x));
+ *total = 0;
+ return true;
+ }
switch (code)
{
case CONST_INT:
- if (TARGET_MIPS16)
- {
- /* A number between 1 and 8 inclusive is efficient for a shift.
- Otherwise, we will need an extended instruction. */
- if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
- || (outer_code) == LSHIFTRT)
- {
- if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
- *total = 0;
- else
- *total = COSTS_N_INSNS (1);
- return true;
- }
-
- /* We can use cmpi for an xor with an unsigned 16-bit value. */
- if ((outer_code) == XOR
- && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
- {
- *total = 0;
- return true;
- }
-
- /* We may be able to use slt or sltu for a comparison with a
- signed 16-bit value. (The boundary conditions aren't quite
- right, but this is just a heuristic anyhow.) */
- if (((outer_code) == LT || (outer_code) == LE
- || (outer_code) == GE || (outer_code) == GT
- || (outer_code) == LTU || (outer_code) == LEU
- || (outer_code) == GEU || (outer_code) == GTU)
- && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
- {
- *total = 0;
- return true;
- }
+ /* Treat *clear_upper32-style ANDs as having zero cost in the
+ second operand. The cost is entirely in the first operand.
+
+ ??? This is needed because we would otherwise try to CSE
+ the constant operand. Although that's the right thing for
+ instructions that continue to be a register operation throughout
+ compilation, it is disastrous for instructions that could
+ later be converted into a memory operation. */
+ if (TARGET_64BIT
+ && outer_code == AND
+ && UINTVAL (x) == 0xffffffff)
+ {
+ *total = 0;
+ return true;
+ }
- /* Equality comparisons with 0 are cheap. */
- if (((outer_code) == EQ || (outer_code) == NE)
- && INTVAL (x) == 0)
+ if (TARGET_MIPS16)
+ {
+ cost = mips16_constant_cost (outer_code, INTVAL (x));
+ if (cost >= 0)
{
- *total = 0;
+ *total = cost;
return true;
}
-
- /* Constants in the range 0...255 can be loaded with an unextended
- instruction. They are therefore as cheap as a register move.
-
- Given the choice between "li R1,0...255" and "move R1,R2"
- (where R2 is a known constant), it is usually better to use "li",
- since we do not want to unnecessarily extend the lifetime
- of R2. */
- if (outer_code == SET
- && INTVAL (x) >= 0
- && INTVAL (x) < 256)
+ }
+ else
+ {
+ /* When not optimizing for size, we care more about the cost
+ of hot code, and hot code is often in a loop. If a constant
+ operand needs to be forced into a register, we will often be
+ able to hoist the constant load out of the loop, so the load
+ should not contribute to the cost. */
+ if (!optimize_size
+ || mips_immediate_operand_p (outer_code, INTVAL (x)))
{
*total = 0;
return true;
}
}
- else
- {
- /* These can be used anywhere. */
- *total = 0;
- return true;
- }
-
- /* Otherwise fall through to the handling below because
- we'll need to construct the constant. */
+ /* Fall through. */
case CONST:
case SYMBOL_REF:
case LABEL_REF:
case CONST_DOUBLE:
- if (LEGITIMATE_CONSTANT_P (x))
+ if (force_to_mem_operand (x, VOIDmode))
{
*total = COSTS_N_INSNS (1);
return true;
}
- else
+ cost = mips_const_insns (x);
+ if (cost > 0)
{
- /* The value will need to be fetched from the constant pool. */
- *total = CONSTANT_POOL_COST;
+ /* If the constant is likely to be stored in a GPR, SETs of
+ single-insn constants are as cheap as register sets; we
+ never want to CSE them.
+
+ Don't reduce the cost of storing a floating-point zero in
+ FPRs. If we have a zero in an FPR for other reasons, we
+ can get better cfg-cleanup and delayed-branch results by
+ using it consistently, rather than using $0 sometimes and
+ an FPR at other times. Also, moves between floating-point
+ registers are sometimes cheaper than (D)MTC1 $0. */
+ if (cost == 1
+ && outer_code == SET
+ && !(float_mode_p && TARGET_HARD_FLOAT))
+ cost = 0;
+ /* When non-MIPS16 code loads a constant N>1 times, we rarely
+ want to CSE the constant itself. It is usually better to
+ have N copies of the last operation in the sequence and one
+ shared copy of the other operations. (Note that this is
+ not true for MIPS16 code, where the final operation in the
+ sequence is often an extended instruction.)
+
+ Also, if we have a CONST_INT, we don't know whether it is
+ for a word or doubleword operation, so we cannot rely on
+ the result of mips_build_integer. */
+ else if (!TARGET_MIPS16
+ && (outer_code == SET || mode == VOIDmode))
+ cost = 1;
+ *total = COSTS_N_INSNS (cost);
return true;
}
+ /* The value will need to be fetched from the constant pool. */
+ *total = CONSTANT_POOL_COST;
+ return true;
case MEM:
- {
- /* If the address is legitimate, return the number of
- instructions it needs. */
- rtx addr = XEXP (x, 0);
- int n = mips_address_insns (addr, GET_MODE (x), true);
- if (n > 0)
- {
- *total = COSTS_N_INSNS (n + 1);
- return true;
- }
- /* Check for scaled indexed address. */
- if (mips_lwxs_address_p (addr))
- {
- *total = COSTS_N_INSNS (2);
- return true;
- }
- /* Otherwise use the default handling. */
- return false;
- }
+ /* If the address is legitimate, return the number of
+ instructions it needs. */
+ addr = XEXP (x, 0);
+ cost = mips_address_insns (addr, mode, true);
+ if (cost > 0)
+ {
+ *total = COSTS_N_INSNS (cost + 1);
+ return true;
+ }
+ /* Check for a scaled indexed address. */
+ if (mips_lwxs_address_p (addr))
+ {
+ *total = COSTS_N_INSNS (2);
+ return true;
+ }
+ /* Otherwise use the default handling. */
+ return false;
case FFS:
*total = COSTS_N_INSNS (6);
- return true;
+ return false;
case NOT:
- *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
- return true;
+ *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
+ return false;
case AND:
+ /* Check for a *clear_upper32 pattern and treat it like a zero
+ extension. See the pattern's comment for details. */
+ if (TARGET_64BIT
+ && mode == DImode
+ && CONST_INT_P (XEXP (x, 1))
+ && UINTVAL (XEXP (x, 1)) == 0xffffffff)
+ {
+ *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
+ + rtx_cost (XEXP (x, 0), 0));
+ return true;
+ }
+ /* Fall through. */
+
case IOR:
case XOR:
- if (mode == DImode && !TARGET_64BIT)
- {
- *total = COSTS_N_INSNS (2);
- return true;
- }
- return false;
+ /* Double-word operations use two single-word operations. */
+ *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
+ return true;
case ASHIFT:
case ASHIFTRT:
case LSHIFTRT:
- if (mode == DImode && !TARGET_64BIT)
- {
- *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
- ? 4 : 12);
- return true;
- }
- return false;
+ case ROTATE:
+ case ROTATERT:
+ if (CONSTANT_P (XEXP (x, 1)))
+ *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
+ else
+ *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
+ return true;
case ABS:
if (float_mode_p)
- *total = COSTS_N_INSNS (1);
+ *total = mips_cost->fp_add;
else
*total = COSTS_N_INSNS (4);
- return true;
+ return false;
case LO_SUM:
- *total = COSTS_N_INSNS (1);
+ /* Low-part immediates need an extended MIPS16 instruction. */
+ *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
+ + rtx_cost (XEXP (x, 0), 0));
+ return true;
+
+ case LT:
+ case LTU:
+ case LE:
+ case LEU:
+ case GT:
+ case GTU:
+ case GE:
+ case GEU:
+ case EQ:
+ case NE:
+ case UNORDERED:
+ case LTGT:
+ /* Branch comparisons have VOIDmode, so use the first operand's
+ mode instead. */
+ mode = GET_MODE (XEXP (x, 0));
+ if (FLOAT_MODE_P (mode))
+ {
+ *total = mips_cost->fp_add;
+ return false;
+ }
+ *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
return true;
- case PLUS:
case MINUS:
+ if (float_mode_p
+ && ISA_HAS_NMADD_NMSUB (mode)
+ && TARGET_FUSED_MADD
+ && !HONOR_NANS (mode)
+ && !HONOR_SIGNED_ZEROS (mode))
+ {
+ /* See if we can use NMADD or NMSUB. See mips.md for the
+ associated patterns. */
+ rtx op0 = XEXP (x, 0);
+ rtx op1 = XEXP (x, 1);
+ if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
+ {
+ *total = (mips_fp_mult_cost (mode)
+ + rtx_cost (XEXP (XEXP (op0, 0), 0), 0)
+ + rtx_cost (XEXP (op0, 1), 0)
+ + rtx_cost (op1, 0));
+ return true;
+ }
+ if (GET_CODE (op1) == MULT)
+ {
+ *total = (mips_fp_mult_cost (mode)
+ + rtx_cost (op0, 0)
+ + rtx_cost (XEXP (op1, 0), 0)
+ + rtx_cost (XEXP (op1, 1), 0));
+ return true;
+ }
+ }
+ /* Fall through. */
+
+ case PLUS:
if (float_mode_p)
{
- *total = mips_cost->fp_add;
- return true;
+ /* If this is part of a MADD or MSUB, treat the PLUS as
+ being free. */
+ if (ISA_HAS_FP4
+ && TARGET_FUSED_MADD
+ && GET_CODE (XEXP (x, 0)) == MULT)
+ *total = 0;
+ else
+ *total = mips_cost->fp_add;
+ return false;
}
- else if (mode == DImode && !TARGET_64BIT)
- {
- *total = COSTS_N_INSNS (4);
- return true;
- }
- return false;
+ /* Double-word operations require three single-word operations and
+ an SLTU. The MIPS16 version then needs to move the result of
+ the SLTU from $24 to a MIPS16 register. */
+ *total = mips_binary_cost (x, COSTS_N_INSNS (1),
+ COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4));
+ return true;
case NEG:
- if (mode == DImode && !TARGET_64BIT)
- {
- *total = COSTS_N_INSNS (4);
- return true;
- }
+ if (float_mode_p
+ && ISA_HAS_NMADD_NMSUB (mode)
+ && TARGET_FUSED_MADD
+ && !HONOR_NANS (mode)
+ && HONOR_SIGNED_ZEROS (mode))
+ {
+ /* See if we can use NMADD or NMSUB. See mips.md for the
+ associated patterns. */
+ rtx op = XEXP (x, 0);
+ if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
+ && GET_CODE (XEXP (op, 0)) == MULT)
+ {
+ *total = (mips_fp_mult_cost (mode)
+ + rtx_cost (XEXP (XEXP (op, 0), 0), 0)
+ + rtx_cost (XEXP (XEXP (op, 0), 1), 0)
+ + rtx_cost (XEXP (op, 1), 0));
+ return true;
+ }
+ }
+
+ if (float_mode_p)
+ *total = mips_cost->fp_add;
+ else
+ *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
return false;
case MULT:
- if (mode == SFmode)
- *total = mips_cost->fp_mult_sf;
-
- else if (mode == DFmode)
- *total = mips_cost->fp_mult_df;
-
- else if (mode == SImode)
- *total = mips_cost->int_mult_si;
-
- else
+ if (float_mode_p)
+ *total = mips_fp_mult_cost (mode);
+ else if (mode == DImode && !TARGET_64BIT)
+ /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
+ where the mulsidi3 always includes an MFHI and an MFLO. */
+ *total = (optimize_size
+ ? COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)
+ : mips_cost->int_mult_si * 3 + 6);
+ else if (optimize_size)
+ *total = (ISA_HAS_MUL3 ? 1 : 2);
+ else if (mode == DImode)
*total = mips_cost->int_mult_di;
-
- return true;
+ else
+ *total = mips_cost->int_mult_si;
+ return false;
case DIV:
- case MOD:
- if (float_mode_p)
+ /* Check for a reciprocal. */
+ if (float_mode_p
+ && ISA_HAS_FP4
+ && flag_unsafe_math_optimizations
+ && XEXP (x, 0) == CONST1_RTX (mode))
{
- if (mode == SFmode)
- *total = mips_cost->fp_div_sf;
+ if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
+ /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
+ division as being free. */
+ *total = rtx_cost (XEXP (x, 1), 0);
else
- *total = mips_cost->fp_div_df;
-
+ *total = mips_fp_div_cost (mode) + rtx_cost (XEXP (x, 1), 0);
return true;
}
/* Fall through. */
+ case SQRT:
+ case MOD:
+ if (float_mode_p)
+ {
+ *total = mips_fp_div_cost (mode);
+ return false;
+ }
+ /* Fall through. */
+
case UDIV:
case UMOD:
- if (mode == DImode)
+ if (optimize_size)
+ {
+ /* It is our responsibility to make division by a power of 2
+ as cheap as 2 register additions if we want the division
+ expanders to be used for such operations; see the setting
+ of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
+ should always produce shorter code than using
+ expand_sdiv2_pow2. */
+ if (TARGET_MIPS16
+ && CONST_INT_P (XEXP (x, 1))
+ && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
+ {
+ *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), 0);
+ return true;
+ }
+ *total = COSTS_N_INSNS (mips_idiv_insns ());
+ }
+ else if (mode == DImode)
*total = mips_cost->int_div_di;
else
*total = mips_cost->int_div_si;
-
- return true;
+ return false;
case SIGN_EXTEND:
- /* A sign extend from SImode to DImode in 64-bit mode is often
- zero instructions, because the result can often be used
- directly by another instruction; we'll call it one. */
- if (TARGET_64BIT && mode == DImode
- && GET_MODE (XEXP (x, 0)) == SImode)
- *total = COSTS_N_INSNS (1);
- else
- *total = COSTS_N_INSNS (2);
- return true;
+ *total = mips_sign_extend_cost (mode, XEXP (x, 0));
+ return false;
case ZERO_EXTEND:
- if (TARGET_64BIT && mode == DImode
- && GET_MODE (XEXP (x, 0)) == SImode)
- *total = COSTS_N_INSNS (2);
- else
- *total = COSTS_N_INSNS (1);
- return true;
+ *total = mips_zero_extend_cost (mode, XEXP (x, 0));
+ return false;
case FLOAT:
case UNSIGNED_FLOAT:
case FIX:
case FLOAT_EXTEND:
case FLOAT_TRUNCATE:
- case SQRT:
*total = mips_cost->fp_add;
- return true;
+ return false;
default:
return false;
}
}
-/* Provide the costs of an addressing mode that contains ADDR.
- If ADDR is not a valid address, its cost is irrelevant. */
+/* Implement TARGET_ADDRESS_COST. */
static int
mips_address_cost (rtx addr)
false to select the low part. */
rtx
-mips_subword (rtx op, int high_p)
+mips_subword (rtx op, bool high_p)
{
- unsigned int byte;
+ unsigned int byte, offset;
enum machine_mode mode;
mode = GET_MODE (op);
byte = 0;
if (FP_REG_RTX_P (op))
- return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
+ {
+ /* Paired FPRs are always ordered little-endian. */
+ offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
+ return gen_rtx_REG (word_mode, REGNO (op) + offset);
+ }
if (MEM_P (op))
return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
return simplify_gen_subreg (word_mode, op, mode, byte);
}
-
/* Return true if a 64-bit move from SRC to DEST should be split into two. */
bool
if (TARGET_64BIT)
return false;
- /* FP->FP moves can be done in a single instruction. */
+ /* FPR-to-FPR moves can be done in a single instruction, if they're
+ allowed at all. */
if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
return false;
- /* Check for floating-point loads and stores. They can be done using
- ldc1 and sdc1 on MIPS II and above. */
- if (mips_isa > 1)
+ /* Check for floating-point loads and stores. */
+ if (ISA_HAS_LDC1_SDC1)
{
if (FP_REG_RTX_P (dest) && MEM_P (src))
return false;
return true;
}
-
-/* Split a 64-bit move from SRC to DEST assuming that
- mips_split_64bit_move_p holds.
-
- Moves into and out of FPRs cause some difficulty here. Such moves
- will always be DFmode, since paired FPRs are not allowed to store
- DImode values. The most natural representation would be two separate
- 32-bit moves, such as:
-
- (set (reg:SI $f0) (mem:SI ...))
- (set (reg:SI $f1) (mem:SI ...))
-
- However, the second insn is invalid because odd-numbered FPRs are
- not allowed to store independent values. Use the patterns load_df_low,
- load_df_high and store_df_high instead. */
+/* Split a doubleword move from SRC to DEST. On 32-bit targets,
+ this function handles 64-bit moves for which mips_split_64bit_move_p
+ holds. For 64-bit targets, this function handles 128-bit moves. */
void
-mips_split_64bit_move (rtx dest, rtx src)
-{
- if (FP_REG_RTX_P (dest))
- {
- /* Loading an FPR from memory or from GPRs. */
- if (ISA_HAS_MXHC1)
- {
- dest = gen_lowpart (DFmode, dest);
- emit_insn (gen_load_df_low (dest, mips_subword (src, 0)));
- emit_insn (gen_mthc1 (dest, mips_subword (src, 1),
- copy_rtx (dest)));
- }
- else
- {
- emit_insn (gen_load_df_low (copy_rtx (dest),
- mips_subword (src, 0)));
- emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
- copy_rtx (dest)));
- }
- }
- else if (FP_REG_RTX_P (src))
- {
- /* Storing an FPR into memory or GPRs. */
- if (ISA_HAS_MXHC1)
- {
- src = gen_lowpart (DFmode, src);
- mips_emit_move (mips_subword (dest, 0), mips_subword (src, 0));
- emit_insn (gen_mfhc1 (mips_subword (dest, 1), src));
- }
+mips_split_doubleword_move (rtx dest, rtx src)
+{
+ if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
+ {
+ if (!TARGET_64BIT && GET_MODE (dest) == DImode)
+ emit_insn (gen_move_doubleword_fprdi (dest, src));
+ else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
+ emit_insn (gen_move_doubleword_fprdf (dest, src));
+ else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
+ emit_insn (gen_move_doubleword_fprv2sf (dest, src));
+ else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
+ emit_insn (gen_move_doubleword_fprtf (dest, src));
else
- {
- mips_emit_move (mips_subword (dest, 0), mips_subword (src, 0));
- emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
- }
+ gcc_unreachable ();
}
else
{
which order to do them. */
rtx low_dest;
- low_dest = mips_subword (dest, 0);
+ low_dest = mips_subword (dest, false);
if (REG_P (low_dest)
&& reg_overlap_mentioned_p (low_dest, src))
{
- mips_emit_move (mips_subword (dest, 1), mips_subword (src, 1));
- mips_emit_move (low_dest, mips_subword (src, 0));
+ mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
+ mips_emit_move (low_dest, mips_subword (src, false));
}
else
{
- mips_emit_move (low_dest, mips_subword (src, 0));
- mips_emit_move (mips_subword (dest, 1), mips_subword (src, 1));
+ mips_emit_move (low_dest, mips_subword (src, false));
+ mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
}
}
}
mips_output_move (rtx dest, rtx src)
{
enum rtx_code dest_code, src_code;
+ enum machine_mode mode;
enum mips_symbol_type symbol_type;
bool dbl_p;
dest_code = GET_CODE (dest);
src_code = GET_CODE (src);
- dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
+ mode = GET_MODE (dest);
+ dbl_p = (GET_MODE_SIZE (mode) == 8);
if (dbl_p && mips_split_64bit_move_p (dest, src))
return "#";
if ((src_code == REG && GP_REG_P (REGNO (src)))
- || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
+ || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
{
if (dest_code == REG)
{
if (DSP_ACC_REG_P (REGNO (dest)))
{
static char retval[] = "mt__\t%z1,%q0";
+
retval[2] = reg_names[REGNO (dest)][4];
retval[3] = reg_names[REGNO (dest)][5];
return retval;
}
if (FP_REG_P (REGNO (dest)))
- return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
+ return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
if (ALL_COP_REG_P (REGNO (dest)))
{
static char retval[] = "dmtc_\t%z1,%0";
retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
- return (dbl_p ? retval : retval + 1);
+ return dbl_p ? retval : retval + 1;
}
}
if (dest_code == MEM)
- return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
+ return dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0";
}
if (dest_code == REG && GP_REG_P (REGNO (dest)))
{
if (src_code == REG)
{
+ /* Handled by separate patterns. */
+ gcc_assert (!MD_REG_P (REGNO (src)));
+
if (DSP_ACC_REG_P (REGNO (src)))
{
static char retval[] = "mf__\t%0,%q1";
+
retval[2] = reg_names[REGNO (src)][4];
retval[3] = reg_names[REGNO (src)][5];
return retval;
}
- if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
- return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
-
if (FP_REG_P (REGNO (src)))
- return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
+ return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
if (ALL_COP_REG_P (REGNO (src)))
{
static char retval[] = "dmfc_\t%0,%1";
retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
- return (dbl_p ? retval : retval + 1);
+ return dbl_p ? retval : retval + 1;
}
+
+ if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
+ return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
}
if (src_code == MEM)
- return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
+ return dbl_p ? "ld\t%0,%1" : "lw\t%0,%1";
if (src_code == CONST_INT)
{
- /* Don't use the X format, because that will give out of
- range numbers for 64-bit hosts and 32-bit targets. */
+ /* Don't use the X format for the operand itself, because that
+ will give out-of-range numbers for 64-bit hosts and 32-bit
+ targets. */
if (!TARGET_MIPS16)
return "li\t%0,%1\t\t\t# %X1";
- if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
+ if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
return "li\t%0,%1";
- if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
+ if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
return "#";
}
gcc_assert (TARGET_MIPS16
? TARGET_MIPS16_TEXT_LOADS
: !TARGET_EXPLICIT_RELOCS);
- return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
+ return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
}
}
if (src_code == REG && FP_REG_P (REGNO (src)))
if (GET_MODE (dest) == V2SFmode)
return "mov.ps\t%0,%1";
else
- return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
+ return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
}
if (dest_code == MEM)
- return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
+ return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
}
if (dest_code == REG && FP_REG_P (REGNO (dest)))
{
if (src_code == MEM)
- return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
+ return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
}
if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
{
gcc_unreachable ();
}
\f
-/* Restore $gp from its save slot. Valid only when using o32 or
- o64 abicalls. */
-
-void
-mips_restore_gp (void)
-{
- rtx address, slot;
-
- gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
-
- address = mips_add_offset (pic_offset_table_rtx,
- frame_pointer_needed
- ? hard_frame_pointer_rtx
- : stack_pointer_rtx,
- current_function_outgoing_args_size);
- slot = gen_rtx_MEM (Pmode, address);
-
- mips_emit_move (pic_offset_table_rtx, slot);
- if (!TARGET_EXPLICIT_RELOCS)
- emit_insn (gen_blockage ());
-}
-\f
-/* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
-
-static void
-mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
-{
- emit_insn (gen_rtx_SET (VOIDmode, target,
- gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
-}
-
-/* Return true if CMP1 is a suitable second operand for relational
- operator CODE. See also the *sCC patterns in mips.md. */
+/* Return true if CMP1 is a suitable second operand for integer ordering
+ test CODE. See also the *sCC patterns in mips.md. */
static bool
-mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
+mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
{
switch (code)
{
}
}
-/* Canonicalize LE or LEU comparisons into LT comparisons when
- possible to avoid extra instructions or inverting the
- comparison. */
+/* Return true if *CMP1 (of mode MODE) is a valid second operand for
+ integer ordering test *CODE, or if an equivalent combination can
+ be formed by adjusting *CODE and *CMP1. When returning true, update
+ *CODE and *CMP1 with the chosen code and operand, otherwise leave
+ them alone. */
static bool
-mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
- enum machine_mode mode)
+mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
+ enum machine_mode mode)
{
- HOST_WIDE_INT original, plus_one;
-
- if (GET_CODE (*cmp1) != CONST_INT)
- return false;
+ HOST_WIDE_INT plus_one;
- original = INTVAL (*cmp1);
- plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
-
- switch (*code)
- {
- case LE:
- if (original < plus_one)
- {
- *code = LT;
- *cmp1 = force_reg (mode, GEN_INT (plus_one));
- return true;
- }
- break;
+ if (mips_int_order_operand_ok_p (*code, *cmp1))
+ return true;
- case LEU:
- if (plus_one != 0)
- {
- *code = LTU;
- *cmp1 = force_reg (mode, GEN_INT (plus_one));
- return true;
- }
- break;
+ if (GET_CODE (*cmp1) == CONST_INT)
+ switch (*code)
+ {
+ case LE:
+ plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
+ if (INTVAL (*cmp1) < plus_one)
+ {
+ *code = LT;
+ *cmp1 = force_reg (mode, GEN_INT (plus_one));
+ return true;
+ }
+ break;
- default:
- return false;
- }
+ case LEU:
+ plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
+ if (plus_one != 0)
+ {
+ *code = LTU;
+ *cmp1 = force_reg (mode, GEN_INT (plus_one));
+ return true;
+ }
+ break;
+ default:
+ break;
+ }
return false;
-
}
-/* Compare CMP0 and CMP1 using relational operator CODE and store the
- result in TARGET. CMP0 and TARGET are register_operands that have
- the same integer mode. If INVERT_PTR is nonnull, it's OK to set
- TARGET to the inverse of the result and flip *INVERT_PTR instead. */
+/* Compare CMP0 and CMP1 using ordering test CODE and store the result
+ in TARGET. CMP0 and TARGET are register_operands that have the same
+ integer mode. If INVERT_PTR is nonnull, it's OK to set TARGET to the
+ inverse of the result and flip *INVERT_PTR instead. */
static void
-mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
+mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
rtx target, rtx cmp0, rtx cmp1)
{
- /* First see if there is a MIPS instruction that can do this operation
- with CMP1 in its current form. If not, try to canonicalize the
- comparison to LT. If that fails, try doing the same for the
- inverse operation. If that also fails, force CMP1 into a register
- and try again. */
- if (mips_relational_operand_ok_p (code, cmp1))
- mips_emit_binary (code, target, cmp0, cmp1);
- else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
+ enum machine_mode mode;
+
+ /* First see if there is a MIPS instruction that can do this operation.
+ If not, try doing the same for the inverse operation. If that also
+ fails, force CMP1 into a register and try again. */
+ mode = GET_MODE (target);
+ if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
mips_emit_binary (code, target, cmp0, cmp1);
else
{
enum rtx_code inv_code = reverse_condition (code);
- if (!mips_relational_operand_ok_p (inv_code, cmp1))
+ if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
{
- cmp1 = force_reg (GET_MODE (cmp0), cmp1);
- mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
+ cmp1 = force_reg (mode, cmp1);
+ mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
}
else if (invert_ptr == 0)
{
- rtx inv_target = gen_reg_rtx (GET_MODE (target));
+ rtx inv_target = gen_reg_rtx (mode);
mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
mips_emit_binary (XOR, target, inv_target, const1_rtx);
}
}
/* Convert *CODE into a code that can be used in a floating-point
- scc instruction (c.<cond>.<fmt>). Return true if the values of
+ scc instruction (C.cond.fmt). Return true if the values of
the condition code registers will be inverted, with 0 indicating
that the condition holds. */
static bool
-mips_reverse_fp_cond_p (enum rtx_code *code)
+mips_reversed_fp_cond (enum rtx_code *code)
{
switch (*code)
{
being compared and *CODE is the code used to compare them.
Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
- If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
+ If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
otherwise any standard branch condition can be used. The standard branch
conditions are:
- - EQ/NE between two registers.
+ - EQ or NE between two registers.
- any comparison between a register and zero. */
static void
result of the scc in *OP0 and compare it against zero. */
bool invert = false;
*op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
- *op1 = const0_rtx;
- mips_emit_int_relational (*code, &invert, *op0,
+ mips_emit_int_order_test (*code, &invert, *op0,
cmp_operands[0], cmp_operands[1]);
*code = (invert ? EQ : NE);
+ *op1 = const0_rtx;
}
}
+ else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_operands[0])))
+ {
+ *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
+ mips_emit_binary (*code, *op0, cmp_operands[0], cmp_operands[1]);
+ *code = NE;
+ *op1 = const0_rtx;
+ }
else
{
enum rtx_code cmp_code;
- /* Floating-point tests use a separate c.cond.fmt comparison to
+ /* Floating-point tests use a separate C.cond.fmt comparison to
set a condition code register. The branch or conditional move
will then compare that register against zero.
Set CMP_CODE to the code of the comparison instruction and
*CODE to the code that the branch or move should use. */
cmp_code = *code;
- *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
+ *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
*op0 = (ISA_HAS_8CC
? gen_reg_rtx (CCmode)
: gen_rtx_REG (CCmode, FPSW_REGNUM));
On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
bool
-mips_emit_scc (enum rtx_code code, rtx target)
+mips_expand_scc (enum rtx_code code, rtx target)
{
if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
return false;
mips_emit_binary (code, target, zie, const0_rtx);
}
else
- mips_emit_int_relational (code, 0, target,
+ mips_emit_int_order_test (code, 0, target,
cmp_operands[0], cmp_operands[1]);
return true;
}
-/* Emit the common code for doing conditional branches.
- operand[0] is the label to jump to.
- The comparison operands are saved away by cmp{si,di,sf,df}. */
+/* Compare cmp_operands[0] with cmp_operands[1] using comparison code
+ CODE and jump to OPERANDS[0] if the condition holds. */
void
-gen_conditional_branch (rtx *operands, enum rtx_code code)
+mips_expand_conditional_branch (rtx *operands, enum rtx_code code)
{
rtx op0, op1, condition;
rtx cmp_result;
bool reversed_p;
- reversed_p = mips_reverse_fp_cond_p (&cond);
+ reversed_p = mips_reversed_fp_cond (&cond);
cmp_result = gen_reg_rtx (CCV2mode);
emit_insn (gen_scc_ps (cmp_result,
gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
cmp_result));
}
-/* Emit the common code for conditional moves. OPERANDS is the array
- of operands passed to the conditional move define_expand. */
+/* Compare cmp_operands[0] with cmp_operands[1] using the code of
+ OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0] if the condition
+ holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
void
-gen_conditional_move (rtx *operands)
+mips_expand_conditional_move (rtx *operands)
{
enum rtx_code code;
- rtx op0, op1;
+ rtx cond, op0, op1;
code = GET_CODE (operands[1]);
mips_emit_compare (&code, &op0, &op1, true);
+ cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1),
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
- gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
- gen_rtx_fmt_ee (code,
- GET_MODE (op0),
- op0, op1),
+ gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
operands[2], operands[3])));
}
-/* Emit a conditional trap. OPERANDS is the array of operands passed to
- the conditional_trap expander. */
+/* Compare cmp_operands[0] with cmp_operands[1] using rtl code CODE,
+ then trap if the condition holds. */
void
-mips_gen_conditional_trap (rtx *operands)
+mips_expand_conditional_trap (enum rtx_code code)
{
rtx op0, op1;
- enum rtx_code cmp_code = GET_CODE (operands[0]);
- enum machine_mode mode = GET_MODE (cmp_operands[0]);
+ enum machine_mode mode;
- /* MIPS conditional trap machine instructions don't have GT or LE
- flavors, so we must invert the comparison and convert to LT and
- GE, respectively. */
- switch (cmp_code)
- {
- case GT: cmp_code = LT; break;
- case LE: cmp_code = GE; break;
- case GTU: cmp_code = LTU; break;
- case LEU: cmp_code = GEU; break;
- default: break;
- }
- if (cmp_code == GET_CODE (operands[0]))
- {
- op0 = cmp_operands[0];
- op1 = cmp_operands[1];
- }
- else
+ /* MIPS conditional trap instructions don't have GT or LE flavors,
+ so we must swap the operands and convert to LT and GE respectively. */
+ switch (code)
{
+ case GT:
+ case LE:
+ case GTU:
+ case LEU:
+ code = swap_condition (code);
op0 = cmp_operands[1];
op1 = cmp_operands[0];
+ break;
+
+ default:
+ op0 = cmp_operands[0];
+ op1 = cmp_operands[1];
+ break;
}
+
+ mode = GET_MODE (cmp_operands[0]);
op0 = force_reg (mode, op0);
if (!arith_operand (op1, mode))
op1 = force_reg (mode, op1);
emit_insn (gen_rtx_TRAP_IF (VOIDmode,
- gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
- operands[1]));
+ gen_rtx_fmt_ee (code, mode, op0, op1),
+ const0_rtx));
}
\f
-/* Return true if calls to X can use R_MIPS_CALL* relocations. */
+/* Initialize *CUM for a call to a function of type FNTYPE. */
-static bool
-mips_ok_for_lazy_binding_p (rtx x)
+void
+mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
{
- return (TARGET_USE_GOT
- && GET_CODE (x) == SYMBOL_REF
- && !mips_symbol_binds_local_p (x));
+ memset (cum, 0, sizeof (*cum));
+ cum->prototype = (fntype && prototype_p (fntype));
+ cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
}
-/* Load function address ADDR into register DEST. SIBCALL_P is true
- if the address is needed for a sibling call. */
+/* Fill INFO with information about a single argument. CUM is the
+ cumulative state for earlier arguments. MODE is the mode of this
+ argument and TYPE is its type (if known). NAMED is true if this
+ is a named (fixed) argument rather than a variable one. */
static void
-mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
+mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
+ enum machine_mode mode, tree type, int named)
{
- /* If we're generating PIC, and this call is to a global function,
- try to allow its address to be resolved lazily. This isn't
- possible if TARGET_CALL_SAVED_GP since the value of $gp on entry
- to the stub would be our caller's gp, not ours. */
- if (TARGET_EXPLICIT_RELOCS
- && !(sibcall_p && TARGET_CALL_SAVED_GP)
- && mips_ok_for_lazy_binding_p (addr))
- {
- rtx high, lo_sum_symbol;
-
- high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
- addr, SYMBOL_GOTOFF_CALL);
- lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
- if (Pmode == SImode)
- emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
- else
- emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
- }
- else
- mips_emit_move (dest, addr);
-}
-
+ bool doubleword_aligned_p;
+ unsigned int num_bytes, num_words, max_regs;
-/* Expand a call or call_value instruction. RESULT is where the
- result will go (null for calls), ADDR is the address of the
- function, ARGS_SIZE is the size of the arguments and AUX is
- the value passed to us by mips_function_arg. SIBCALL_P is true
- if we are expanding a sibling call, false if we're expanding
- a normal call. */
+ /* Work out the size of the argument. */
+ num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
+ num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
-void
-mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
-{
- rtx orig_addr, pattern, insn;
+ /* Decide whether it should go in a floating-point register, assuming
+ one is free. Later code checks for availability.
- orig_addr = addr;
- if (!call_insn_operand (addr, VOIDmode))
+ The checks against UNITS_PER_FPVALUE handle the soft-float and
+ single-float cases. */
+ switch (mips_abi)
{
- addr = gen_reg_rtx (Pmode);
- mips_load_call_address (addr, orig_addr, sibcall_p);
- }
+ case ABI_EABI:
+ /* The EABI conventions have traditionally been defined in terms
+ of TYPE_MODE, regardless of the actual type. */
+ info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
+ || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
+ && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
+ break;
- if (TARGET_MIPS16
- && TARGET_HARD_FLOAT_ABI
- && build_mips16_call_stub (result, addr, args_size,
- aux == 0 ? 0 : (int) GET_MODE (aux)))
- return;
+ case ABI_32:
+ case ABI_O64:
+ /* Only leading floating-point scalars are passed in
+ floating-point registers. We also handle vector floats the same
+ say, which is OK because they are not covered by the standard ABI. */
+ info->fpr_p = (!cum->gp_reg_found
+ && cum->arg_number < 2
+ && (type == 0
+ || SCALAR_FLOAT_TYPE_P (type)
+ || VECTOR_FLOAT_TYPE_P (type))
+ && (GET_MODE_CLASS (mode) == MODE_FLOAT
+ || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
+ && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
+ break;
- if (result == 0)
- pattern = (sibcall_p
- ? gen_sibcall_internal (addr, args_size)
- : gen_call_internal (addr, args_size));
- else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
- {
- rtx reg1, reg2;
+ case ABI_N32:
+ case ABI_64:
+ /* Scalar, complex and vector floating-point types are passed in
+ floating-point registers, as long as this is a named rather
+ than a variable argument. */
+ info->fpr_p = (named
+ && (type == 0 || FLOAT_TYPE_P (type))
+ && (GET_MODE_CLASS (mode) == MODE_FLOAT
+ || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
+ || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
+ && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
- reg1 = XEXP (XVECEXP (result, 0, 0), 0);
- reg2 = XEXP (XVECEXP (result, 0, 1), 0);
- pattern =
- (sibcall_p
- ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
- : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
- }
- else
- pattern = (sibcall_p
- ? gen_sibcall_value_internal (result, addr, args_size)
- : gen_call_value_internal (result, addr, args_size));
+ /* ??? According to the ABI documentation, the real and imaginary
+ parts of complex floats should be passed in individual registers.
+ The real and imaginary parts of stack arguments are supposed
+ to be contiguous and there should be an extra word of padding
+ at the end.
- insn = emit_call_insn (pattern);
+ This has two problems. First, it makes it impossible to use a
+ single "void *" va_list type, since register and stack arguments
+ are passed differently. (At the time of writing, MIPSpro cannot
+ handle complex float varargs correctly.) Second, it's unclear
+ what should happen when there is only one register free.
- /* Lazy-binding stubs require $gp to be valid on entry. */
- if (mips_ok_for_lazy_binding_p (orig_addr))
- use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
-}
+ For now, we assume that named complex floats should go into FPRs
+ if there are two FPRs free, otherwise they should be passed in the
+ same way as a struct containing two floats. */
+ if (info->fpr_p
+ && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
+ && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
+ {
+ if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
+ info->fpr_p = false;
+ else
+ num_words = 2;
+ }
+ break;
+ default:
+ gcc_unreachable ();
+ }
-/* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
+ /* See whether the argument has doubleword alignment. */
+ doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
-static bool
-mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
-{
- if (!TARGET_SIBCALLS)
- return false;
+ /* Set REG_OFFSET to the register count we're interested in.
+ The EABI allocates the floating-point registers separately,
+ but the other ABIs allocate them like integer registers. */
+ info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
+ ? cum->num_fprs
+ : cum->num_gprs);
- /* We can't do a sibcall if the called function is a MIPS16 function
- because there is no direct "jx" instruction equivalent to "jalx" to
- switch the ISA mode. */
- if (decl && SYMBOL_REF_MIPS16_FUNC_P (XEXP (DECL_RTL (decl), 0)))
- return false;
+ /* Advance to an even register if the argument is doubleword-aligned. */
+ if (doubleword_aligned_p)
+ info->reg_offset += info->reg_offset & 1;
- /* Otherwise OK. */
- return true;
-}
-\f
-/* Emit code to move general operand SRC into condition-code
- register DEST. SCRATCH is a scratch TFmode float register.
- The sequence is:
+ /* Work out the offset of a stack argument. */
+ info->stack_offset = cum->stack_words;
+ if (doubleword_aligned_p)
+ info->stack_offset += info->stack_offset & 1;
- FP1 = SRC
- FP2 = 0.0f
- DEST = FP2 < FP1
+ max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
+
+ /* Partition the argument between registers and stack. */
+ info->reg_words = MIN (num_words, max_regs);
+ info->stack_words = num_words - info->reg_words;
+}
- where FP1 and FP2 are single-precision float registers
- taken from SCRATCH. */
+/* INFO describes a register argument that has the normal format for the
+ argument's mode. Return the register it uses, assuming that FPRs are
+ available if HARD_FLOAT_P. */
-void
-mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
+static unsigned int
+mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
{
- rtx fp1, fp2;
-
- /* Change the source to SFmode. */
- if (MEM_P (src))
- src = adjust_address (src, SFmode, 0);
- else if (REG_P (src) || GET_CODE (src) == SUBREG)
- src = gen_rtx_REG (SFmode, true_regnum (src));
+ if (!info->fpr_p || !hard_float_p)
+ return GP_ARG_FIRST + info->reg_offset;
+ else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
+ /* In o32, the second argument is always passed in $f14
+ for TARGET_DOUBLE_FLOAT, regardless of whether the
+ first argument was a word or doubleword. */
+ return FP_ARG_FIRST + 2;
+ else
+ return FP_ARG_FIRST + info->reg_offset;
+}
- fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
- fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
+/* Implement TARGET_STRICT_ARGUMENT_NAMING. */
- mips_emit_move (copy_rtx (fp1), src);
- mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
- emit_insn (gen_slt_sf (dest, fp2, fp1));
+static bool
+mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
+{
+ return !TARGET_OLDABI;
}
-\f
-/* Emit code to change the current function's return address to
- ADDRESS. SCRATCH is available as a scratch register, if needed.
- ADDRESS and SCRATCH are both word-mode GPRs. */
-void
-mips_set_return_address (rtx address, rtx scratch)
+/* Implement FUNCTION_ARG. */
+
+rtx
+mips_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
+ tree type, int named)
{
- rtx slot_address;
+ struct mips_arg_info info;
- compute_frame_size (get_frame_size ());
- gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
- slot_address = mips_add_offset (scratch, stack_pointer_rtx,
- cfun->machine->frame.gp_sp_offset);
+ /* We will be called with a mode of VOIDmode after the last argument
+ has been seen. Whatever we return will be passed to the call expander.
+ If we need a MIPS16 fp_code, return a REG with the code stored as
+ the mode. */
+ if (mode == VOIDmode)
+ {
+ if (TARGET_MIPS16 && cum->fp_code != 0)
+ return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
+ else
+ return NULL;
+ }
- mips_emit_move (gen_rtx_MEM (GET_MODE (address), slot_address), address);
-}
-\f
-/* Emit straight-line code to move LENGTH bytes from SRC to DEST.
- Assume that the areas do not overlap. */
+ mips_get_arg_info (&info, cum, mode, type, named);
-static void
-mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
-{
- HOST_WIDE_INT offset, delta;
- unsigned HOST_WIDE_INT bits;
- int i;
- enum machine_mode mode;
- rtx *regs;
+ /* Return straight away if the whole argument is passed on the stack. */
+ if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
+ return NULL;
- /* Work out how many bits to move at a time. If both operands have
- half-word alignment, it is usually better to move in half words.
- For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
- and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
- Otherwise move word-sized chunks. */
- if (MEM_ALIGN (src) == BITS_PER_WORD / 2
- && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
- bits = BITS_PER_WORD / 2;
- else
- bits = BITS_PER_WORD;
+ /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
+ contains a double in its entirety, then that 64-bit chunk is passed
+ in a floating-point register. */
+ if (TARGET_NEWABI
+ && TARGET_HARD_FLOAT
+ && named
+ && type != 0
+ && TREE_CODE (type) == RECORD_TYPE
+ && TYPE_SIZE_UNIT (type)
+ && host_integerp (TYPE_SIZE_UNIT (type), 1))
+ {
+ tree field;
- mode = mode_for_size (bits, MODE_INT, 0);
- delta = bits / BITS_PER_UNIT;
+ /* First check to see if there is any such field. */
+ for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
+ if (TREE_CODE (field) == FIELD_DECL
+ && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
+ && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
+ && host_integerp (bit_position (field), 0)
+ && int_bit_position (field) % BITS_PER_WORD == 0)
+ break;
- /* Allocate a buffer for the temporary registers. */
- regs = alloca (sizeof (rtx) * length / delta);
+ if (field != 0)
+ {
+ /* Now handle the special case by returning a PARALLEL
+ indicating where each 64-bit chunk goes. INFO.REG_WORDS
+ chunks are passed in registers. */
+ unsigned int i;
+ HOST_WIDE_INT bitpos;
+ rtx ret;
- /* Load as many BITS-sized chunks as possible. Use a normal load if
- the source has enough alignment, otherwise use left/right pairs. */
- for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
+ /* assign_parms checks the mode of ENTRY_PARM, so we must
+ use the actual mode here. */
+ ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
+
+ bitpos = 0;
+ field = TYPE_FIELDS (type);
+ for (i = 0; i < info.reg_words; i++)
+ {
+ rtx reg;
+
+ for (; field; field = TREE_CHAIN (field))
+ if (TREE_CODE (field) == FIELD_DECL
+ && int_bit_position (field) >= bitpos)
+ break;
+
+ if (field
+ && int_bit_position (field) == bitpos
+ && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
+ && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
+ reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
+ else
+ reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
+
+ XVECEXP (ret, 0, i)
+ = gen_rtx_EXPR_LIST (VOIDmode, reg,
+ GEN_INT (bitpos / BITS_PER_UNIT));
+
+ bitpos += BITS_PER_WORD;
+ }
+ return ret;
+ }
+ }
+
+ /* Handle the n32/n64 conventions for passing complex floating-point
+ arguments in FPR pairs. The real part goes in the lower register
+ and the imaginary part goes in the upper register. */
+ if (TARGET_NEWABI
+ && info.fpr_p
+ && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
{
- regs[i] = gen_reg_rtx (mode);
- if (MEM_ALIGN (src) >= bits)
- mips_emit_move (regs[i], adjust_address (src, mode, offset));
+ rtx real, imag;
+ enum machine_mode inner;
+ unsigned int regno;
+
+ inner = GET_MODE_INNER (mode);
+ regno = FP_ARG_FIRST + info.reg_offset;
+ if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
+ {
+ /* Real part in registers, imaginary part on stack. */
+ gcc_assert (info.stack_words == info.reg_words);
+ return gen_rtx_REG (inner, regno);
+ }
else
{
- rtx part = adjust_address (src, BLKmode, offset);
- if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
- gcc_unreachable ();
+ gcc_assert (info.stack_words == 0);
+ real = gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_REG (inner, regno),
+ const0_rtx);
+ imag = gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_REG (inner,
+ regno + info.reg_words / 2),
+ GEN_INT (GET_MODE_SIZE (inner)));
+ return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
}
}
- /* Copy the chunks to the destination. */
- for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
- if (MEM_ALIGN (dest) >= bits)
- mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
- else
- {
- rtx part = adjust_address (dest, BLKmode, offset);
- if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
- gcc_unreachable ();
- }
-
- /* Mop up any left-over bytes. */
- if (offset < length)
- {
- src = adjust_address (src, BLKmode, offset);
- dest = adjust_address (dest, BLKmode, offset);
- move_by_pieces (dest, src, length - offset,
- MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
- }
+ return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
}
-\f
-#define MAX_MOVE_REGS 4
-#define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
-
-
-/* Helper function for doing a loop-based block operation on memory
- reference MEM. Each iteration of the loop will operate on LENGTH
- bytes of MEM.
- Create a new base register for use within the loop and point it to
- the start of MEM. Create a new memory reference that uses this
- register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
+/* Implement FUNCTION_ARG_ADVANCE. */
-static void
-mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
- rtx *loop_reg, rtx *loop_mem)
+void
+mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
+ tree type, int named)
{
- *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
+ struct mips_arg_info info;
- /* Although the new mem does not refer to a known location,
- it does keep up to LENGTH bytes of alignment. */
- *loop_mem = change_address (mem, BLKmode, *loop_reg);
- set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
-}
+ mips_get_arg_info (&info, cum, mode, type, named);
+ if (!info.fpr_p)
+ cum->gp_reg_found = true;
-/* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
- per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
- memory regions do not overlap. */
+ /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
+ an explanation of what this code does. It assumes that we're using
+ either the o32 or the o64 ABI, both of which pass at most 2 arguments
+ in FPRs. */
+ if (cum->arg_number < 2 && info.fpr_p)
+ cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
-static void
-mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
-{
- rtx label, src_reg, dest_reg, final_src;
- HOST_WIDE_INT leftover;
+ /* Advance the register count. This has the effect of setting
+ num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
+ argument required us to skip the final GPR and pass the whole
+ argument on the stack. */
+ if (mips_abi != ABI_EABI || !info.fpr_p)
+ cum->num_gprs = info.reg_offset + info.reg_words;
+ else if (info.reg_words > 0)
+ cum->num_fprs += MAX_FPRS_PER_FMT;
- leftover = length % MAX_MOVE_BYTES;
- length -= leftover;
+ /* Advance the stack word count. */
+ if (info.stack_words > 0)
+ cum->stack_words = info.stack_offset + info.stack_words;
- /* Create registers and memory references for use within the loop. */
- mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
- mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
+ cum->arg_number++;
+}
- /* Calculate the value that SRC_REG should have after the last iteration
- of the loop. */
- final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
- 0, 0, OPTAB_WIDEN);
+/* Implement TARGET_ARG_PARTIAL_BYTES. */
- /* Emit the start of the loop. */
- label = gen_label_rtx ();
- emit_label (label);
+static int
+mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
+ enum machine_mode mode, tree type, bool named)
+{
+ struct mips_arg_info info;
- /* Emit the loop body. */
- mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
+ mips_get_arg_info (&info, cum, mode, type, named);
+ return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
+}
- /* Move on to the next block. */
- mips_emit_move (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
- mips_emit_move (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
+/* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
+ PARM_BOUNDARY bits of alignment, but will be given anything up
+ to STACK_BOUNDARY bits if the type requires it. */
- /* Emit the loop condition. */
- if (Pmode == DImode)
- emit_insn (gen_cmpdi (src_reg, final_src));
- else
- emit_insn (gen_cmpsi (src_reg, final_src));
- emit_jump_insn (gen_bne (label));
+int
+mips_function_arg_boundary (enum machine_mode mode, tree type)
+{
+ unsigned int alignment;
- /* Mop up any left-over bytes. */
- if (leftover)
- mips_block_move_straight (dest, src, leftover);
+ alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
+ if (alignment < PARM_BOUNDARY)
+ alignment = PARM_BOUNDARY;
+ if (alignment > STACK_BOUNDARY)
+ alignment = STACK_BOUNDARY;
+ return alignment;
}
-\f
-/* Expand a loop of synci insns for the address range [BEGIN, END). */
+/* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
+ upward rather than downward. In other words, return true if the
+ first byte of the stack slot has useful data, false if the last
+ byte does. */
-void
-mips_expand_synci_loop (rtx begin, rtx end)
+bool
+mips_pad_arg_upward (enum machine_mode mode, const_tree type)
{
- rtx inc, label, cmp, cmp_result;
-
- /* Load INC with the cache line size (rdhwr INC,$1). */
- inc = gen_reg_rtx (SImode);
- emit_insn (gen_rdhwr (inc, const1_rtx));
-
- /* Loop back to here. */
- label = gen_label_rtx ();
- emit_label (label);
+ /* On little-endian targets, the first byte of every stack argument
+ is passed in the first byte of the stack slot. */
+ if (!BYTES_BIG_ENDIAN)
+ return true;
- emit_insn (gen_synci (begin));
+ /* Otherwise, integral types are padded downward: the last byte of a
+ stack argument is passed in the last byte of the stack slot. */
+ if (type != 0
+ ? (INTEGRAL_TYPE_P (type)
+ || POINTER_TYPE_P (type)
+ || FIXED_POINT_TYPE_P (type))
+ : (SCALAR_INT_MODE_P (mode)
+ || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
+ return false;
- cmp = gen_reg_rtx (Pmode);
- mips_emit_binary (GTU, cmp, begin, end);
+ /* Big-endian o64 pads floating-point arguments downward. */
+ if (mips_abi == ABI_O64)
+ if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
+ return false;
- mips_emit_binary (PLUS, begin, begin, inc);
+ /* Other types are padded upward for o32, o64, n32 and n64. */
+ if (mips_abi != ABI_EABI)
+ return true;
- cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
- emit_jump_insn (gen_condjump (cmp_result, label));
+ /* Arguments smaller than a stack slot are padded downward. */
+ if (mode != BLKmode)
+ return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
+ else
+ return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
}
-\f
-/* Expand a movmemsi instruction. */
+
+/* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
+ if the least significant byte of the register has useful data. Return
+ the opposite if the most significant byte does. */
bool
-mips_expand_block_move (rtx dest, rtx src, rtx length)
+mips_pad_reg_upward (enum machine_mode mode, tree type)
{
- if (GET_CODE (length) == CONST_INT)
- {
- if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
- {
- mips_block_move_straight (dest, src, INTVAL (length));
- return true;
- }
- else if (optimize)
- {
- mips_block_move_loop (dest, src, INTVAL (length));
- return true;
- }
- }
- return false;
+ /* No shifting is required for floating-point arguments. */
+ if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
+ return !BYTES_BIG_ENDIAN;
+
+ /* Otherwise, apply the same padding to register arguments as we do
+ to stack arguments. */
+ return mips_pad_arg_upward (mode, type);
}
-\f
-/* Argument support functions. */
-/* Initialize CUMULATIVE_ARGS for a function. */
+/* Return nonzero when an argument must be passed by reference. */
-void
-init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
- rtx libname ATTRIBUTE_UNUSED)
+static bool
+mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
+ enum machine_mode mode, const_tree type,
+ bool named ATTRIBUTE_UNUSED)
{
- static CUMULATIVE_ARGS zero_cum;
- tree param, next_param;
-
- *cum = zero_cum;
- cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
+ if (mips_abi == ABI_EABI)
+ {
+ int size;
- /* Determine if this function has variable arguments. This is
- indicated by the last argument being 'void_type_mode' if there
- are no variable arguments. The standard MIPS calling sequence
- passes all arguments in the general purpose registers in this case. */
+ /* ??? How should SCmode be handled? */
+ if (mode == DImode || mode == DFmode
+ || mode == DQmode || mode == UDQmode
+ || mode == DAmode || mode == UDAmode)
+ return 0;
- for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
- param != 0; param = next_param)
+ size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
+ return size == -1 || size > UNITS_PER_WORD;
+ }
+ else
{
- next_param = TREE_CHAIN (param);
- if (next_param == 0 && TREE_VALUE (param) != void_type_node)
- cum->gp_reg_found = 1;
+ /* If we have a variable-sized parameter, we have no choice. */
+ return targetm.calls.must_pass_in_stack (mode, type);
}
}
+/* Implement TARGET_CALLEE_COPIES. */
-/* Fill INFO with information about a single argument. CUM is the
- cumulative state for earlier arguments. MODE is the mode of this
- argument and TYPE is its type (if known). NAMED is true if this
- is a named (fixed) argument rather than a variable one. */
-
-static void
-mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
- tree type, int named, struct mips_arg_info *info)
+static bool
+mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
+ enum machine_mode mode ATTRIBUTE_UNUSED,
+ const_tree type ATTRIBUTE_UNUSED, bool named)
{
- bool doubleword_aligned_p;
- unsigned int num_bytes, num_words, max_regs;
-
- /* Work out the size of the argument. */
- num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
- num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
+ return mips_abi == ABI_EABI && named;
+}
+\f
+/* See whether VALTYPE is a record whose fields should be returned in
+ floating-point registers. If so, return the number of fields and
+ list them in FIELDS (which should have two elements). Return 0
+ otherwise.
- /* Decide whether it should go in a floating-point register, assuming
- one is free. Later code checks for availability.
+ For n32 & n64, a structure with one or two fields is returned in
+ floating-point registers as long as every field has a floating-point
+ type. */
- The checks against UNITS_PER_FPVALUE handle the soft-float and
- single-float cases. */
- switch (mips_abi)
- {
- case ABI_EABI:
- /* The EABI conventions have traditionally been defined in terms
- of TYPE_MODE, regardless of the actual type. */
- info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
- || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
- && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
- break;
+static int
+mips_fpr_return_fields (const_tree valtype, tree *fields)
+{
+ tree field;
+ int i;
- case ABI_32:
- case ABI_O64:
- /* Only leading floating-point scalars are passed in
- floating-point registers. We also handle vector floats the same
- say, which is OK because they are not covered by the standard ABI. */
- info->fpr_p = (!cum->gp_reg_found
- && cum->arg_number < 2
- && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
- || VECTOR_FLOAT_TYPE_P (type))
- && (GET_MODE_CLASS (mode) == MODE_FLOAT
- || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
- && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
- break;
+ if (!TARGET_NEWABI)
+ return 0;
- case ABI_N32:
- case ABI_64:
- /* Scalar and complex floating-point types are passed in
- floating-point registers. */
- info->fpr_p = (named
- && (type == 0 || FLOAT_TYPE_P (type))
- && (GET_MODE_CLASS (mode) == MODE_FLOAT
- || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
- || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
- && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
+ if (TREE_CODE (valtype) != RECORD_TYPE)
+ return 0;
- /* ??? According to the ABI documentation, the real and imaginary
- parts of complex floats should be passed in individual registers.
- The real and imaginary parts of stack arguments are supposed
- to be contiguous and there should be an extra word of padding
- at the end.
+ i = 0;
+ for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
+ {
+ if (TREE_CODE (field) != FIELD_DECL)
+ continue;
- This has two problems. First, it makes it impossible to use a
- single "void *" va_list type, since register and stack arguments
- are passed differently. (At the time of writing, MIPSpro cannot
- handle complex float varargs correctly.) Second, it's unclear
- what should happen when there is only one register free.
+ if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
+ return 0;
- For now, we assume that named complex floats should go into FPRs
- if there are two FPRs free, otherwise they should be passed in the
- same way as a struct containing two floats. */
- if (info->fpr_p
- && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
- && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
- {
- if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
- info->fpr_p = false;
- else
- num_words = 2;
- }
- break;
+ if (i == 2)
+ return 0;
- default:
- gcc_unreachable ();
+ fields[i++] = field;
}
+ return i;
+}
- /* See whether the argument has doubleword alignment. */
- doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
+/* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
+ a value in the most significant part of $2/$3 if:
- /* Set REG_OFFSET to the register count we're interested in.
- The EABI allocates the floating-point registers separately,
- but the other ABIs allocate them like integer registers. */
- info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
- ? cum->num_fprs
- : cum->num_gprs);
+ - the target is big-endian;
- /* Advance to an even register if the argument is doubleword-aligned. */
- if (doubleword_aligned_p)
- info->reg_offset += info->reg_offset & 1;
+ - the value has a structure or union type (we generalize this to
+ cover aggregates from other languages too); and
- /* Work out the offset of a stack argument. */
- info->stack_offset = cum->stack_words;
- if (doubleword_aligned_p)
- info->stack_offset += info->stack_offset & 1;
+ - the structure is not returned in floating-point registers. */
- max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
+static bool
+mips_return_in_msb (const_tree valtype)
+{
+ tree fields[2];
- /* Partition the argument between registers and stack. */
- info->reg_words = MIN (num_words, max_regs);
- info->stack_words = num_words - info->reg_words;
+ return (TARGET_NEWABI
+ && TARGET_BIG_ENDIAN
+ && AGGREGATE_TYPE_P (valtype)
+ && mips_fpr_return_fields (valtype, fields) == 0);
}
+/* Return true if the function return value MODE will get returned in a
+ floating-point register. */
-/* INFO describes an argument that is passed in a single-register value.
- Return the register it uses, assuming that FPRs are available if
- HARD_FLOAT_P. */
-
-static unsigned int
-mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
+static bool
+mips_return_mode_in_fpr_p (enum machine_mode mode)
{
- if (!info->fpr_p || !hard_float_p)
- return GP_ARG_FIRST + info->reg_offset;
- else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
- /* In o32, the second argument is always passed in $f14
- for TARGET_DOUBLE_FLOAT, regardless of whether the
- first argument was a word or doubleword. */
- return FP_ARG_FIRST + 2;
- else
- return FP_ARG_FIRST + info->reg_offset;
+ return ((GET_MODE_CLASS (mode) == MODE_FLOAT
+ || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
+ || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
+ && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
}
-/* Implement FUNCTION_ARG_ADVANCE. */
+/* Return the representation of an FPR return register when the
+ value being returned in FP_RETURN has mode VALUE_MODE and the
+ return type itself has mode TYPE_MODE. On NewABI targets,
+ the two modes may be different for structures like:
-void
-function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
- tree type, int named)
+ struct __attribute__((packed)) foo { float f; }
+
+ where we return the SFmode value of "f" in FP_RETURN, but where
+ the structure itself has mode BLKmode. */
+
+static rtx
+mips_return_fpr_single (enum machine_mode type_mode,
+ enum machine_mode value_mode)
{
- struct mips_arg_info info;
+ rtx x;
- mips_arg_info (cum, mode, type, named, &info);
+ x = gen_rtx_REG (value_mode, FP_RETURN);
+ if (type_mode != value_mode)
+ {
+ x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
+ x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
+ }
+ return x;
+}
- if (!info.fpr_p)
- cum->gp_reg_found = true;
+/* Return a composite value in a pair of floating-point registers.
+ MODE1 and OFFSET1 are the mode and byte offset for the first value,
+ likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
+ complete value.
- /* See the comment above the cumulative args structure in mips.h
- for an explanation of what this code does. It assumes the O32
- ABI, which passes at most 2 arguments in float registers. */
- if (cum->arg_number < 2 && info.fpr_p)
- cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
+ For n32 & n64, $f0 always holds the first value and $f2 the second.
+ Otherwise the values are packed together as closely as possible. */
- if (mips_abi != ABI_EABI || !info.fpr_p)
- cum->num_gprs = info.reg_offset + info.reg_words;
- else if (info.reg_words > 0)
- cum->num_fprs += MAX_FPRS_PER_FMT;
+static rtx
+mips_return_fpr_pair (enum machine_mode mode,
+ enum machine_mode mode1, HOST_WIDE_INT offset1,
+ enum machine_mode mode2, HOST_WIDE_INT offset2)
+{
+ int inc;
- if (info.stack_words > 0)
- cum->stack_words = info.stack_offset + info.stack_words;
+ inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
+ return gen_rtx_PARALLEL
+ (mode,
+ gen_rtvec (2,
+ gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_REG (mode1, FP_RETURN),
+ GEN_INT (offset1)),
+ gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_REG (mode2, FP_RETURN + inc),
+ GEN_INT (offset2))));
- cum->arg_number++;
}
-/* Implement FUNCTION_ARG. */
+/* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
+ VALTYPE is the return type and MODE is VOIDmode. For libcalls,
+ VALTYPE is null and MODE is the mode of the return value. */
-struct rtx_def *
-function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
- tree type, int named)
+rtx
+mips_function_value (const_tree valtype, enum machine_mode mode)
{
- struct mips_arg_info info;
-
- /* We will be called with a mode of VOIDmode after the last argument
- has been seen. Whatever we return will be passed to the call
- insn. If we need a mips16 fp_code, return a REG with the code
- stored as the mode. */
- if (mode == VOIDmode)
+ if (valtype)
{
- if (TARGET_MIPS16 && cum->fp_code != 0)
- return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
-
- else
- return 0;
- }
-
- mips_arg_info (cum, mode, type, named, &info);
-
- /* Return straight away if the whole argument is passed on the stack. */
- if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
- return 0;
+ tree fields[2];
+ int unsigned_p;
- if (type != 0
- && TREE_CODE (type) == RECORD_TYPE
- && TARGET_NEWABI
- && TYPE_SIZE_UNIT (type)
- && host_integerp (TYPE_SIZE_UNIT (type), 1)
- && named)
- {
- /* The Irix 6 n32/n64 ABIs say that if any 64-bit chunk of the
- structure contains a double in its entirety, then that 64-bit
- chunk is passed in a floating point register. */
- tree field;
+ mode = TYPE_MODE (valtype);
+ unsigned_p = TYPE_UNSIGNED (valtype);
- /* First check to see if there is any such field. */
- for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
- if (TREE_CODE (field) == FIELD_DECL
- && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
- && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
- && host_integerp (bit_position (field), 0)
- && int_bit_position (field) % BITS_PER_WORD == 0)
- break;
+ /* Since TARGET_PROMOTE_FUNCTION_RETURN unconditionally returns true,
+ we must promote the mode just as PROMOTE_MODE does. */
+ mode = promote_mode (valtype, mode, &unsigned_p, 1);
- if (field != 0)
+ /* Handle structures whose fields are returned in $f0/$f2. */
+ switch (mips_fpr_return_fields (valtype, fields))
{
- /* Now handle the special case by returning a PARALLEL
- indicating where each 64-bit chunk goes. INFO.REG_WORDS
- chunks are passed in registers. */
- unsigned int i;
- HOST_WIDE_INT bitpos;
- rtx ret;
+ case 1:
+ return mips_return_fpr_single (mode,
+ TYPE_MODE (TREE_TYPE (fields[0])));
- /* assign_parms checks the mode of ENTRY_PARM, so we must
- use the actual mode here. */
- ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
+ case 2:
+ return mips_return_fpr_pair (mode,
+ TYPE_MODE (TREE_TYPE (fields[0])),
+ int_byte_position (fields[0]),
+ TYPE_MODE (TREE_TYPE (fields[1])),
+ int_byte_position (fields[1]));
+ }
- bitpos = 0;
- field = TYPE_FIELDS (type);
- for (i = 0; i < info.reg_words; i++)
+ /* If a value is passed in the most significant part of a register, see
+ whether we have to round the mode up to a whole number of words. */
+ if (mips_return_in_msb (valtype))
+ {
+ HOST_WIDE_INT size = int_size_in_bytes (valtype);
+ if (size % UNITS_PER_WORD != 0)
{
- rtx reg;
-
- for (; field; field = TREE_CHAIN (field))
- if (TREE_CODE (field) == FIELD_DECL
- && int_bit_position (field) >= bitpos)
- break;
-
- if (field
- && int_bit_position (field) == bitpos
- && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
- && !TARGET_SOFT_FLOAT
- && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
- reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
- else
- reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
-
- XVECEXP (ret, 0, i)
- = gen_rtx_EXPR_LIST (VOIDmode, reg,
- GEN_INT (bitpos / BITS_PER_UNIT));
-
- bitpos += BITS_PER_WORD;
+ size += UNITS_PER_WORD - size % UNITS_PER_WORD;
+ mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
}
- return ret;
}
+
+ /* For EABI, the class of return register depends entirely on MODE.
+ For example, "struct { some_type x; }" and "union { some_type x; }"
+ are returned in the same way as a bare "some_type" would be.
+ Other ABIs only use FPRs for scalar, complex or vector types. */
+ if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
+ return gen_rtx_REG (mode, GP_RETURN);
}
- /* Handle the n32/n64 conventions for passing complex floating-point
- arguments in FPR pairs. The real part goes in the lower register
- and the imaginary part goes in the upper register. */
- if (TARGET_NEWABI
- && info.fpr_p
- && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
+ if (!TARGET_MIPS16)
{
- rtx real, imag;
- enum machine_mode inner;
- int reg;
+ /* Handle long doubles for n32 & n64. */
+ if (mode == TFmode)
+ return mips_return_fpr_pair (mode,
+ DImode, 0,
+ DImode, GET_MODE_SIZE (mode) / 2);
- inner = GET_MODE_INNER (mode);
- reg = FP_ARG_FIRST + info.reg_offset;
- if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
- {
- /* Real part in registers, imaginary part on stack. */
- gcc_assert (info.stack_words == info.reg_words);
- return gen_rtx_REG (inner, reg);
- }
- else
+ if (mips_return_mode_in_fpr_p (mode))
{
- gcc_assert (info.stack_words == 0);
- real = gen_rtx_EXPR_LIST (VOIDmode,
- gen_rtx_REG (inner, reg),
- const0_rtx);
- imag = gen_rtx_EXPR_LIST (VOIDmode,
- gen_rtx_REG (inner,
- reg + info.reg_words / 2),
- GEN_INT (GET_MODE_SIZE (inner)));
- return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
+ if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
+ return mips_return_fpr_pair (mode,
+ GET_MODE_INNER (mode), 0,
+ GET_MODE_INNER (mode),
+ GET_MODE_SIZE (mode) / 2);
+ else
+ return gen_rtx_REG (mode, FP_RETURN);
}
}
- return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
+ return gen_rtx_REG (mode, GP_RETURN);
}
+/* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
+ all BLKmode objects are returned in memory. Under the n32, n64
+ and embedded ABIs, small structures are returned in a register.
+ Objects with varying size must still be returned in memory, of
+ course. */
-/* Implement TARGET_ARG_PARTIAL_BYTES. */
-
-static int
-mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
- enum machine_mode mode, tree type, bool named)
+static bool
+mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
{
- struct mips_arg_info info;
-
- mips_arg_info (cum, mode, type, named, &info);
- return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
+ return (TARGET_OLDABI
+ ? TYPE_MODE (type) == BLKmode
+ : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
}
+\f
+/* Implement TARGET_SETUP_INCOMING_VARARGS. */
-
-/* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
- PARM_BOUNDARY bits of alignment, but will be given anything up
- to STACK_BOUNDARY bits if the type requires it. */
-
-int
-function_arg_boundary (enum machine_mode mode, tree type)
+static void
+mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
+ tree type, int *pretend_size ATTRIBUTE_UNUSED,
+ int no_rtl)
{
- unsigned int alignment;
+ CUMULATIVE_ARGS local_cum;
+ int gp_saved, fp_saved;
- alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
- if (alignment < PARM_BOUNDARY)
- alignment = PARM_BOUNDARY;
- if (alignment > STACK_BOUNDARY)
- alignment = STACK_BOUNDARY;
- return alignment;
-}
+ /* The caller has advanced CUM up to, but not beyond, the last named
+ argument. Advance a local copy of CUM past the last "real" named
+ argument, to find out how many registers are left over. */
+ local_cum = *cum;
+ FUNCTION_ARG_ADVANCE (local_cum, mode, type, true);
-/* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
- upward rather than downward. In other words, return true if the
- first byte of the stack slot has useful data, false if the last
- byte does. */
+ /* Found out how many registers we need to save. */
+ gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
+ fp_saved = (EABI_FLOAT_VARARGS_P
+ ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
+ : 0);
-bool
-mips_pad_arg_upward (enum machine_mode mode, const_tree type)
-{
- /* On little-endian targets, the first byte of every stack argument
- is passed in the first byte of the stack slot. */
- if (!BYTES_BIG_ENDIAN)
- return true;
-
- /* Otherwise, integral types are padded downward: the last byte of a
- stack argument is passed in the last byte of the stack slot. */
- if (type != 0
- ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
- : GET_MODE_CLASS (mode) == MODE_INT)
- return false;
-
- /* Big-endian o64 pads floating-point arguments downward. */
- if (mips_abi == ABI_O64)
- if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
- return false;
-
- /* Other types are padded upward for o32, o64, n32 and n64. */
- if (mips_abi != ABI_EABI)
- return true;
-
- /* Arguments smaller than a stack slot are padded downward. */
- if (mode != BLKmode)
- return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
- else
- return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
-}
-
-
-/* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
- if the least significant byte of the register has useful data. Return
- the opposite if the most significant byte does. */
-
-bool
-mips_pad_reg_upward (enum machine_mode mode, tree type)
-{
- /* No shifting is required for floating-point arguments. */
- if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
- return !BYTES_BIG_ENDIAN;
-
- /* Otherwise, apply the same padding to register arguments as we do
- to stack arguments. */
- return mips_pad_arg_upward (mode, type);
-}
-\f
-static void
-mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
- tree type, int *pretend_size ATTRIBUTE_UNUSED,
- int no_rtl)
-{
- CUMULATIVE_ARGS local_cum;
- int gp_saved, fp_saved;
-
- /* The caller has advanced CUM up to, but not beyond, the last named
- argument. Advance a local copy of CUM past the last "real" named
- argument, to find out how many registers are left over. */
-
- local_cum = *cum;
- FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
-
- /* Found out how many registers we need to save. */
- gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
- fp_saved = (EABI_FLOAT_VARARGS_P
- ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
- : 0);
-
- if (!no_rtl)
- {
- if (gp_saved > 0)
- {
- rtx ptr, mem;
+ if (!no_rtl)
+ {
+ if (gp_saved > 0)
+ {
+ rtx ptr, mem;
ptr = plus_constant (virtual_incoming_args_rtx,
REG_PARM_STACK_SPACE (cfun->decl)
- gp_saved * UNITS_PER_WORD);
- mem = gen_rtx_MEM (BLKmode, ptr);
+ mem = gen_frame_mem (BLKmode, ptr);
set_mem_alias_set (mem, get_varargs_alias_set ());
move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
/* Set OFF to the offset from virtual_incoming_args_rtx of
the first float register. The FP save area lies below
the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
- off = -gp_saved * UNITS_PER_WORD;
- off &= ~(UNITS_PER_FPVALUE - 1);
+ off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
off -= fp_saved * UNITS_PER_FPREG;
mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
rtx ptr, mem;
ptr = plus_constant (virtual_incoming_args_rtx, off);
- mem = gen_rtx_MEM (mode, ptr);
+ mem = gen_frame_mem (mode, ptr);
set_mem_alias_set (mem, get_varargs_alias_set ());
mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
off += UNITS_PER_HWFPVALUE;
+ fp_saved * UNITS_PER_FPREG);
}
-/* Create the va_list data type.
- We keep 3 pointers, and two offsets.
- Two pointers are to the overflow area, which starts at the CFA.
- One of these is constant, for addressing into the GPR save area below it.
- The other is advanced up the stack through the overflow region.
- The third pointer is to the GPR save area. Since the FPR save area
- is just below it, we can address FPR slots off this pointer.
- We also keep two one-byte offsets, which are to be subtracted from the
- constant pointers to yield addresses in the GPR and FPR save areas.
- These are downcounted as float or non-float arguments are used,
- and when they get to zero, the argument must be obtained from the
- overflow region.
- If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
- pointer is enough. It's started at the GPR save area, and is
- advanced, period.
- Note that the GPR save area is not constant size, due to optimization
- in the prologue. Hence, we can't use a design with two pointers
- and two offsets, although we could have designed this with two pointers
- and three offsets. */
+/* Implement TARGET_BUILTIN_VA_LIST. */
static tree
mips_build_builtin_va_list (void)
{
if (EABI_FLOAT_VARARGS_P)
{
+ /* We keep 3 pointers, and two offsets.
+
+ Two pointers are to the overflow area, which starts at the CFA.
+ One of these is constant, for addressing into the GPR save area
+ below it. The other is advanced up the stack through the
+ overflow region.
+
+ The third pointer is to the bottom of the GPR save area.
+ Since the FPR save area is just below it, we can address
+ FPR slots off this pointer.
+
+ We also keep two one-byte offsets, which are to be subtracted
+ from the constant pointers to yield addresses in the GPR and
+ FPR save areas. These are downcounted as float or non-float
+ arguments are used, and when they get to zero, the argument
+ must be obtained from the overflow region. */
tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
tree array, index;
- record = (*lang_hooks.types.make_type) (RECORD_TYPE);
+ record = lang_hooks.types.make_type (RECORD_TYPE);
f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
- ptr_type_node);
+ ptr_type_node);
f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
- ptr_type_node);
+ ptr_type_node);
f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
- ptr_type_node);
+ ptr_type_node);
f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
- unsigned_char_type_node);
+ unsigned_char_type_node);
f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
- unsigned_char_type_node);
+ unsigned_char_type_node);
/* Explicitly pad to the size of a pointer, so that -Wpadded won't
warn on every user file. */
index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
return ptr_type_node;
}
-/* Implement va_start. */
+/* Implement TARGET_EXPAND_BUILTIN_VA_START. */
-void
+static void
mips_va_start (tree valist, rtx nextarg)
{
if (EABI_FLOAT_VARARGS_P)
down to the next fp-aligned boundary. */
t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
- fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
+ fpr_offset &= -UNITS_PER_FPVALUE;
if (fpr_offset)
t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
size_int (-fpr_offset));
/* Emit code to initialize GOFF, the offset from GTOP of the
next GPR argument. */
t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (goff), goff,
- build_int_cst (NULL_TREE, gpr_save_area_size));
+ build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
/* Likewise emit code to initialize FOFF, the offset from FTOP
of the next FPR argument. */
t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (foff), foff,
- build_int_cst (NULL_TREE, fpr_save_area_size));
+ build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
}
else
std_expand_builtin_va_start (valist, nextarg);
}
}
-\f
-/* Implement va_arg. */
+
+/* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
static tree
mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
{
- HOST_WIDE_INT size, rsize;
tree addr;
- bool indirect;
+ bool indirect_p;
- indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
-
- if (indirect)
+ indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
+ if (indirect_p)
type = build_pointer_type (type);
- size = int_size_in_bytes (type);
- rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
-
- if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
+ if (!EABI_FLOAT_VARARGS_P)
addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
else
{
- /* Not a simple merged stack. */
-
tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
tree ovfl, top, off, align;
- HOST_WIDE_INT osize;
+ HOST_WIDE_INT size, rsize, osize;
tree t, u;
f_ovfl = TYPE_FIELDS (va_list_type_node);
f_goff = TREE_CHAIN (f_ftop);
f_foff = TREE_CHAIN (f_goff);
- /* We maintain separate pointers and offsets for floating-point
- and integer arguments, but we need similar code in both cases.
- Let:
+ /* Let:
- TOP be the top of the register save area;
+ TOP be the top of the GPR or FPR save area;
OFF be the offset from TOP of the next register;
ADDR_RTX be the address of the argument;
+ SIZE be the number of bytes in the argument type;
RSIZE be the number of bytes used to store the argument
- when it's in the register save area;
+ when it's in the register save area; and
OSIZE be the number of bytes used to store it when it's
- in the stack overflow area; and
- PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
+ in the stack overflow area.
The code we want is:
1: off &= -rsize; // round down
2: if (off != 0)
3: {
- 4: addr_rtx = top - off;
- 5: off -= rsize;
+ 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
+ 5: off -= rsize;
6: }
7: else
8: {
- 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
- 10: addr_rtx = ovfl + PADDING;
- 11: ovfl += osize;
- 14: }
+ 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
+ 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
+ 11: ovfl += osize;
+ 14: }
[1] and [9] can sometimes be optimized away. */
ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
NULL_TREE);
+ size = int_size_in_bytes (type);
if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
&& GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
NULL_TREE);
- /* When floating-point registers are saved to the stack,
- each one will take up UNITS_PER_HWFPVALUE bytes, regardless
- of the float's precision. */
+ /* When va_start saves FPR arguments to the stack, each slot
+ takes up UNITS_PER_HWFPVALUE bytes, regardless of the
+ argument's precision. */
rsize = UNITS_PER_HWFPVALUE;
/* Overflow arguments are padded to UNITS_PER_WORD bytes
up 4 bytes of memory, so OSIZE will only be 4.
(2) In combinations such as -mgp64 -msingle-float
- -fshort-double. Doubles passed in registers
- will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
- but those passed on the stack take up
- UNITS_PER_WORD bytes. */
+ -fshort-double. Doubles passed in registers will then take
+ up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
+ stack take up UNITS_PER_WORD bytes. */
osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
}
else
NULL_TREE);
off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
NULL_TREE);
+ rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
if (rsize > UNITS_PER_WORD)
{
/* [1] Emit code for: off &= -rsize. */
addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
/* [5] Emit code for: off -= rsize. We do this as a form of
- post-increment not available to C. Also widen for the
- coming pointer arithmetic. */
+ post-decrement not available to C. */
t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
+
+ /* [4] Emit code for:
+ addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
t = fold_convert (sizetype, t);
t = fold_build1 (NEGATE_EXPR, sizetype, t);
-
- /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
- the argument has RSIZE - SIZE bytes of leading padding. */
t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
if (BYTES_BIG_ENDIAN && rsize > size)
{
if (osize > UNITS_PER_WORD)
{
- /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
+ /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
u = size_int (osize - 1);
t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
t = fold_convert (sizetype, t);
else
align = NULL;
- /* [10, 11]. Emit code to store ovfl in addr_rtx, then
- post-increment ovfl by osize. On big-endian machines,
- the argument has OSIZE - SIZE bytes of leading padding. */
- u = fold_convert (TREE_TYPE (ovfl),
- build_int_cst (NULL_TREE, osize));
+ /* [10, 11] Emit code for:
+ addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
+ ovfl += osize. */
+ u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
if (BYTES_BIG_ENDIAN && osize > size)
{
t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
}
- /* String [9] and [10,11] together. */
+ /* String [9] and [10, 11] together. */
if (align)
t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
COND_EXPR_ELSE (addr) = t;
addr = build_va_arg_indirect_ref (addr);
}
- if (indirect)
+ if (indirect_p)
addr = build_va_arg_indirect_ref (addr);
return addr;
}
\f
-/* Return true if it is possible to use left/right accesses for a
- bitfield of WIDTH bits starting BITPOS bits into *OP. When
- returning true, update *OP, *LEFT and *RIGHT as follows:
+/* A chained list of functions for which mips16_build_call_stub has already
+ generated a stub. NAME is the name of the function and FP_RET_P is true
+ if the function returns a value in floating-point registers. */
+struct mips16_stub {
+ struct mips16_stub *next;
+ char *name;
+ bool fp_ret_p;
+};
+static struct mips16_stub *mips16_stubs;
- *OP is a BLKmode reference to the whole field.
+/* Return the two-character string that identifies floating-point
+ return mode MODE in the name of a MIPS16 function stub. */
- *LEFT is a QImode reference to the first byte if big endian or
- the last byte if little endian. This address can be used in the
- left-side instructions (lwl, swl, ldl, sdl).
+static const char *
+mips16_call_stub_mode_suffix (enum machine_mode mode)
+{
+ if (mode == SFmode)
+ return "sf";
+ else if (mode == DFmode)
+ return "df";
+ else if (mode == SCmode)
+ return "sc";
+ else if (mode == DCmode)
+ return "dc";
+ else if (mode == V2SFmode)
+ return "df";
+ else
+ gcc_unreachable ();
+}
- *RIGHT is a QImode reference to the opposite end of the field and
- can be used in the patterning right-side instruction. */
+/* Write instructions to move a 32-bit value between general register
+ GPREG and floating-point register FPREG. DIRECTION is 't' to move
+ from GPREG to FPREG and 'f' to move in the opposite direction. */
-static bool
-mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
- rtx *left, rtx *right)
+static void
+mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
{
- rtx first, last;
+ fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
+ reg_names[gpreg], reg_names[fpreg]);
+}
- /* Check that the operand really is a MEM. Not all the extv and
- extzv predicates are checked. */
- if (!MEM_P (*op))
- return false;
+/* Likewise for 64-bit values. */
- /* Check that the size is valid. */
- if (width != 32 && (!TARGET_64BIT || width != 64))
- return false;
+static void
+mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
+{
+ if (TARGET_64BIT)
+ fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
+ reg_names[gpreg], reg_names[fpreg]);
+ else if (TARGET_FLOAT64)
+ {
+ fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
+ reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
+ fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
+ reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
+ }
+ else
+ {
+ /* Move the least-significant word. */
+ fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
+ reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
+ /* ...then the most significant word. */
+ fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
+ reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
+ }
+}
- /* We can only access byte-aligned values. Since we are always passed
- a reference to the first byte of the field, it is not necessary to
- do anything with BITPOS after this check. */
- if (bitpos % BITS_PER_UNIT != 0)
- return false;
+/* Write out code to move floating-point arguments into or out of
+ general registers. FP_CODE is the code describing which arguments
+ are present (see the comment above the definition of CUMULATIVE_ARGS
+ in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
- /* Reject aligned bitfields: we want to use a normal load or store
- instead of a left/right pair. */
- if (MEM_ALIGN (*op) >= width)
- return false;
+static void
+mips_output_args_xfer (int fp_code, char direction)
+{
+ unsigned int gparg, fparg, f;
+ CUMULATIVE_ARGS cum;
- /* Adjust *OP to refer to the whole field. This also has the effect
- of legitimizing *OP's address for BLKmode, possibly simplifying it. */
- *op = adjust_address (*op, BLKmode, 0);
- set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
+ /* This code only works for o32 and o64. */
+ gcc_assert (TARGET_OLDABI);
- /* Get references to both ends of the field. We deliberately don't
- use the original QImode *OP for FIRST since the new BLKmode one
- might have a simpler address. */
- first = adjust_address (*op, QImode, 0);
- last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
+ mips_init_cumulative_args (&cum, NULL);
- /* Allocate to LEFT and RIGHT according to endianness. LEFT should
- be the upper word and RIGHT the lower word. */
- if (TARGET_BIG_ENDIAN)
- *left = first, *right = last;
- else
- *left = last, *right = first;
+ for (f = (unsigned int) fp_code; f != 0; f >>= 2)
+ {
+ enum machine_mode mode;
+ struct mips_arg_info info;
- return true;
-}
+ if ((f & 3) == 1)
+ mode = SFmode;
+ else if ((f & 3) == 2)
+ mode = DFmode;
+ else
+ gcc_unreachable ();
+ mips_get_arg_info (&info, &cum, mode, NULL, true);
+ gparg = mips_arg_regno (&info, false);
+ fparg = mips_arg_regno (&info, true);
-/* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
- Return true on success. We only handle cases where zero_extract is
- equivalent to sign_extract. */
+ if (mode == SFmode)
+ mips_output_32bit_xfer (direction, gparg, fparg);
+ else
+ mips_output_64bit_xfer (direction, gparg, fparg);
-bool
-mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
-{
- rtx left, right, temp;
+ mips_function_arg_advance (&cum, mode, NULL, true);
+ }
+}
- /* If TARGET_64BIT, the destination of a 32-bit load will be a
- paradoxical word_mode subreg. This is the only case in which
- we allow the destination to be larger than the source. */
- if (GET_CODE (dest) == SUBREG
- && GET_MODE (dest) == DImode
- && SUBREG_BYTE (dest) == 0
- && GET_MODE (SUBREG_REG (dest)) == SImode)
- dest = SUBREG_REG (dest);
+/* Write a MIPS16 stub for the current function. This stub is used
+ for functions which take arguments in the floating-point registers.
+ It is normal-mode code that moves the floating-point arguments
+ into the general registers and then jumps to the MIPS16 code. */
- /* After the above adjustment, the destination must be the same
- width as the source. */
- if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
- return false;
+static void
+mips16_build_function_stub (void)
+{
+ const char *fnname, *separator;
+ char *secname, *stubname;
+ tree stubdecl;
+ unsigned int f;
- if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
- return false;
+ /* Create the name of the stub, and its unique section. */
+ fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
+ fnname = targetm.strip_name_encoding (fnname);
+ secname = ACONCAT ((".mips16.fn.", fnname, NULL));
+ stubname = ACONCAT (("__fn_stub_", fnname, NULL));
- temp = gen_reg_rtx (GET_MODE (dest));
- if (GET_MODE (dest) == DImode)
+ /* Build a decl for the stub. */
+ stubdecl = build_decl (FUNCTION_DECL, get_identifier (stubname),
+ build_function_type (void_type_node, NULL_TREE));
+ DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
+ DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
+
+ /* Output a comment. */
+ fprintf (asm_out_file, "\t# Stub function for %s (",
+ current_function_name ());
+ separator = "";
+ for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
{
- emit_insn (gen_mov_ldl (temp, src, left));
- emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
+ fprintf (asm_out_file, "%s%s", separator,
+ (f & 3) == 1 ? "float" : "double");
+ separator = ", ";
}
- else
+ fprintf (asm_out_file, ")\n");
+
+ /* Write the preamble leading up to the function declaration. */
+ fprintf (asm_out_file, "\t.set\tnomips16\n");
+ switch_to_section (function_section (stubdecl));
+ ASM_OUTPUT_ALIGN (asm_out_file,
+ floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
+
+ /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
+ within a .ent, and we cannot emit another .ent. */
+ if (!FUNCTION_NAME_ALREADY_DECLARED)
{
- emit_insn (gen_mov_lwl (temp, src, left));
- emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
+ fputs ("\t.ent\t", asm_out_file);
+ assemble_name (asm_out_file, stubname);
+ fputs ("\n", asm_out_file);
}
- return true;
-}
-
-/* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
- true on success. */
+ /* Start the definition proper. */
+ assemble_name (asm_out_file, stubname);
+ fputs (":\n", asm_out_file);
-bool
-mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
-{
- rtx left, right;
- enum machine_mode mode;
+ /* Load the address of the MIPS16 function into $at. Do this first so
+ that targets with coprocessor interlocks can use an MFC1 to fill the
+ delay slot. */
+ fprintf (asm_out_file, "\t.set\tnoat\n");
+ fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
+ assemble_name (asm_out_file, fnname);
+ fprintf (asm_out_file, "\n");
- if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
- return false;
+ /* Move the arguments from floating-point registers to general registers. */
+ mips_output_args_xfer (current_function_args_info.fp_code, 'f');
- mode = mode_for_size (width, MODE_INT, 0);
- src = gen_lowpart (mode, src);
+ /* Jump to the MIPS16 function. */
+ fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
+ fprintf (asm_out_file, "\t.set\tat\n");
- if (mode == DImode)
- {
- emit_insn (gen_mov_sdl (dest, src, left));
- emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
- }
- else
+ if (!FUNCTION_NAME_ALREADY_DECLARED)
{
- emit_insn (gen_mov_swl (dest, src, left));
- emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
+ fputs ("\t.end\t", asm_out_file);
+ assemble_name (asm_out_file, stubname);
+ fputs ("\n", asm_out_file);
}
- return true;
+
+ switch_to_section (function_section (current_function_decl));
}
-/* Return true if X is a MEM with the same size as MODE. */
+/* The current function is a MIPS16 function that returns a value in an FPR.
+ Copy the return value from its soft-float to its hard-float location.
+ libgcc2 has special non-MIPS16 helper functions for each case. */
-bool
-mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
+static void
+mips16_copy_fpr_return_value (void)
{
- rtx size;
+ rtx fn, insn, arg, call;
+ tree id, return_type;
+ enum machine_mode return_mode;
- if (!MEM_P (x))
- return false;
+ return_type = DECL_RESULT (current_function_decl);
+ return_mode = DECL_MODE (return_type);
- size = MEM_SIZE (x);
- return size && INTVAL (size) == GET_MODE_SIZE (mode);
+ id = get_identifier (ACONCAT (("__mips16_ret_",
+ mips16_call_stub_mode_suffix (return_mode),
+ NULL)));
+ fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
+ arg = gen_rtx_REG (return_mode, GP_RETURN);
+ call = gen_call_value_internal (arg, fn, const0_rtx);
+ insn = mips_emit_call_insn (call, false);
+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), arg);
}
-/* Return true if (zero_extract OP SIZE POSITION) can be used as the
- source of an "ext" instruction or the destination of an "ins"
- instruction. OP must be a register operand and the following
- conditions must hold:
+/* Consider building a stub for a MIPS16 call to function FN.
+ RETVAL is the location of the return value, or null if this is
+ a "call" rather than a "call_value". ARGS_SIZE is the size of the
+ arguments and FP_CODE is the code built by mips_function_arg;
+ see the comment above CUMULATIVE_ARGS for details.
- 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
- 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
- 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
+ If a stub was needed, emit the call and return the call insn itself.
+ Return null otherwise.
- Also reject lengths equal to a word as they are better handled
- by the move patterns. */
+ A stub is needed for calls to functions that, in normal mode,
+ receive arguments in FPRs or return values in FPRs. The stub
+ copies the arguments from their soft-float positions to their
+ hard-float positions, calls the real function, then copies the
+ return value from its hard-float position to its soft-float
+ position.
-bool
-mips_use_ins_ext_p (rtx op, rtx size, rtx position)
+ We emit a JAL to FN even when FN might need a stub. If FN turns out
+ to be to a non-MIPS16 function, the linker automatically redirects
+ the JAL to the stub, otherwise the JAL continues to call FN directly. */
+
+static rtx
+mips16_build_call_stub (rtx retval, rtx fn, rtx args_size, int fp_code)
{
- HOST_WIDE_INT len, pos;
+ const char *fnname;
+ bool fp_ret_p;
+ struct mips16_stub *l;
+ rtx insn;
- if (!ISA_HAS_EXT_INS
- || !register_operand (op, VOIDmode)
- || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
- return false;
+ /* We don't need to do anything if we aren't in MIPS16 mode, or if
+ we were invoked with the -msoft-float option. */
+ if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
+ return NULL_RTX;
- len = INTVAL (size);
- pos = INTVAL (position);
+ /* Figure out whether the value might come back in a floating-point
+ register. */
+ fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
- if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
- || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
- return false;
+ /* We don't need to do anything if there were no floating-point
+ arguments and the value will not be returned in a floating-point
+ register. */
+ if (fp_code == 0 && !fp_ret_p)
+ return NULL_RTX;
- return true;
-}
+ /* We don't need to do anything if this is a call to a special
+ MIPS16 support function. */
+ if (GET_CODE (fn) == SYMBOL_REF
+ && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
+ return NULL_RTX;
-/* Set up globals to generate code for the ISA or processor
- described by INFO. */
+ /* This code will only work for o32 and o64 abis. The other ABI's
+ require more sophisticated support. */
+ gcc_assert (TARGET_OLDABI);
-static void
-mips_set_architecture (const struct mips_cpu_info *info)
-{
- if (info != 0)
+ /* If we're calling via a function pointer, use one of the magic
+ libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
+ Each stub expects the function address to arrive in register $2. */
+ if (GET_CODE (fn) != SYMBOL_REF)
{
- mips_arch_info = info;
- mips_arch = info->cpu;
- mips_isa = info->isa;
- }
-}
-
-
-/* Likewise for tuning. */
+ char buf[30];
+ tree id;
+ rtx stub_fn, insn;
-static void
-mips_set_tune (const struct mips_cpu_info *info)
-{
- if (info != 0)
- {
- mips_tune_info = info;
- mips_tune = info->cpu;
- }
-}
+ /* Create a SYMBOL_REF for the libgcc.a function. */
+ if (fp_ret_p)
+ sprintf (buf, "__mips16_call_stub_%s_%d",
+ mips16_call_stub_mode_suffix (GET_MODE (retval)),
+ fp_code);
+ else
+ sprintf (buf, "__mips16_call_stub_%d", fp_code);
+ id = get_identifier (buf);
+ stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
-/* Initialize mips_split_addresses from the associated command-line
- settings.
+ /* Load the target function into $2. */
+ mips_emit_move (gen_rtx_REG (Pmode, 2), fn);
- mips_split_addresses is a half-way house between explicit
- relocations and the traditional assembler macros. It can
- split absolute 32-bit symbolic constants into a high/lo_sum
- pair but uses macros for other sorts of access.
-
- Like explicit relocation support for REL targets, it relies
- on GNU extensions in the assembler and the linker.
+ /* Emit the call. */
+ if (retval == NULL_RTX)
+ insn = gen_call_internal (stub_fn, args_size);
+ else
+ insn = gen_call_value_internal (retval, stub_fn, args_size);
+ insn = mips_emit_call_insn (insn, false);
- Although this code should work for -O0, it has traditionally
- been treated as an optimization. */
+ /* Tell GCC that this call does indeed use the value of $2. */
+ CALL_INSN_FUNCTION_USAGE (insn) =
+ gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
+ CALL_INSN_FUNCTION_USAGE (insn));
-static void
-mips_init_split_addresses (void)
-{
- if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
- && optimize && !flag_pic
- && !ABI_HAS_64BIT_SYMBOLS)
- mips_split_addresses = 1;
- else
- mips_split_addresses = 0;
-}
+ /* If we are handling a floating-point return value, we need to
+ save $18 in the function prologue. Putting a note on the
+ call will mean that df_regs_ever_live_p ($18) will be true if the
+ call is not eliminated, and we can check that in the prologue
+ code. */
+ if (fp_ret_p)
+ CALL_INSN_FUNCTION_USAGE (insn) =
+ gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_USE (VOIDmode,
+ gen_rtx_REG (word_mode, 18)),
+ CALL_INSN_FUNCTION_USAGE (insn));
-/* (Re-)Initialize information about relocs. */
+ return insn;
+ }
-static void
-mips_init_relocs (void)
-{
- memset (mips_split_p, '\0', sizeof (mips_split_p));
- memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
- memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
+ /* We know the function we are going to call. If we have already
+ built a stub, we don't need to do anything further. */
+ fnname = targetm.strip_name_encoding (XSTR (fn, 0));
+ for (l = mips16_stubs; l != NULL; l = l->next)
+ if (strcmp (l->name, fnname) == 0)
+ break;
- if (ABI_HAS_64BIT_SYMBOLS)
+ if (l == NULL)
{
- if (TARGET_EXPLICIT_RELOCS)
- {
- mips_split_p[SYMBOL_64_HIGH] = true;
- mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
- mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
+ const char *separator;
+ char *secname, *stubname;
+ tree stubid, stubdecl;
+ unsigned int f;
- mips_split_p[SYMBOL_64_MID] = true;
- mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
- mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
+ /* If the function does not return in FPRs, the special stub
+ section is named
+ .mips16.call.FNNAME
- mips_split_p[SYMBOL_64_LOW] = true;
- mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
- mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
+ If the function does return in FPRs, the stub section is named
+ .mips16.call.fp.FNNAME
- mips_split_p[SYMBOL_ABSOLUTE] = true;
- mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
+ Build a decl for the stub. */
+ secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
+ fnname, NULL));
+ stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
+ fnname, NULL));
+ stubid = get_identifier (stubname);
+ stubdecl = build_decl (FUNCTION_DECL, stubid,
+ build_function_type (void_type_node, NULL_TREE));
+ DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
+ DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE,
+ void_type_node);
+
+ /* Output a comment. */
+ fprintf (asm_out_file, "\t# Stub function to call %s%s (",
+ (fp_ret_p
+ ? (GET_MODE (retval) == SFmode ? "float " : "double ")
+ : ""),
+ fnname);
+ separator = "";
+ for (f = (unsigned int) fp_code; f != 0; f >>= 2)
+ {
+ fprintf (asm_out_file, "%s%s", separator,
+ (f & 3) == 1 ? "float" : "double");
+ separator = ", ";
}
- }
- else
- {
- if (TARGET_EXPLICIT_RELOCS || mips_split_addresses || TARGET_MIPS16)
+ fprintf (asm_out_file, ")\n");
+
+ /* Write the preamble leading up to the function declaration. */
+ fprintf (asm_out_file, "\t.set\tnomips16\n");
+ assemble_start_function (stubdecl, stubname);
+
+ if (!FUNCTION_NAME_ALREADY_DECLARED)
{
- mips_split_p[SYMBOL_ABSOLUTE] = true;
- mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
- mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
+ fputs ("\t.ent\t", asm_out_file);
+ assemble_name (asm_out_file, stubname);
+ fputs ("\n", asm_out_file);
- mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
+ assemble_name (asm_out_file, stubname);
+ fputs (":\n", asm_out_file);
}
- }
- if (TARGET_MIPS16)
- {
- /* The high part is provided by a pseudo copy of $gp. */
- mips_split_p[SYMBOL_GP_RELATIVE] = true;
- mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
- }
+ if (!fp_ret_p)
+ {
+ /* Load the address of the MIPS16 function into $at. Do this
+ first so that targets with coprocessor interlocks can use
+ an MFC1 to fill the delay slot. */
+ fprintf (asm_out_file, "\t.set\tnoat\n");
+ fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
+ fnname);
+ }
- if (TARGET_EXPLICIT_RELOCS)
- {
- /* Small data constants are kept whole until after reload,
- then lowered by mips_rewrite_small_data. */
- mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
+ /* Move the arguments from general registers to floating-point
+ registers. */
+ mips_output_args_xfer (fp_code, 't');
- mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
- if (TARGET_NEWABI)
+ if (!fp_ret_p)
{
- mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
- mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
+ /* Jump to the previously-loaded address. */
+ fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
+ fprintf (asm_out_file, "\t.set\tat\n");
}
else
{
- mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
- mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
- }
+ /* Save the return address in $18 and call the non-MIPS16 function.
+ The stub's caller knows that $18 might be clobbered, even though
+ $18 is usually a call-saved register. */
+ fprintf (asm_out_file, "\tmove\t%s,%s\n",
+ reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
+ fprintf (asm_out_file, "\tjal\t%s\n", fnname);
- if (TARGET_XGOT)
- {
- /* The HIGH and LO_SUM are matched by special .md patterns. */
- mips_split_p[SYMBOL_GOT_DISP] = true;
+ /* Move the result from floating-point registers to
+ general registers. */
+ switch (GET_MODE (retval))
+ {
+ case SCmode:
+ mips_output_32bit_xfer ('f', GP_RETURN + 1,
+ FP_REG_FIRST + MAX_FPRS_PER_FMT);
+ /* Fall though. */
+ case SFmode:
+ mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
+ if (GET_MODE (retval) == SCmode && TARGET_64BIT)
+ {
+ /* On 64-bit targets, complex floats are returned in
+ a single GPR, such that "sd" on a suitably-aligned
+ target would store the value correctly. */
+ fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
+ reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
+ reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
+ fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
+ reg_names[GP_RETURN],
+ reg_names[GP_RETURN],
+ reg_names[GP_RETURN + 1]);
+ }
+ break;
+
+ case DCmode:
+ mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
+ FP_REG_FIRST + MAX_FPRS_PER_FMT);
+ /* Fall though. */
+ case DFmode:
+ case V2SFmode:
+ mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+ fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
+ }
- mips_split_p[SYMBOL_GOTOFF_DISP] = true;
- mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
- mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
+#ifdef ASM_DECLARE_FUNCTION_SIZE
+ ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
+#endif
- mips_split_p[SYMBOL_GOTOFF_CALL] = true;
- mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
- mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
- }
- else
+ if (!FUNCTION_NAME_ALREADY_DECLARED)
{
- if (TARGET_NEWABI)
- mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
- else
- mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
- mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
+ fputs ("\t.end\t", asm_out_file);
+ assemble_name (asm_out_file, stubname);
+ fputs ("\n", asm_out_file);
}
- }
- if (TARGET_NEWABI)
- {
- mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
- mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
- mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
+ /* Record this stub. */
+ l = XNEW (struct mips16_stub);
+ l->name = xstrdup (fnname);
+ l->fp_ret_p = fp_ret_p;
+ l->next = mips16_stubs;
+ mips16_stubs = l;
}
- /* Thread-local relocation operators. */
- mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
- mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
- mips_split_p[SYMBOL_DTPREL] = 1;
- mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
- mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
- mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
- mips_split_p[SYMBOL_TPREL] = 1;
- mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
- mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
+ /* If we expect a floating-point return value, but we've built a
+ stub which does not expect one, then we're in trouble. We can't
+ use the existing stub, because it won't handle the floating-point
+ value. We can't build a new stub, because the linker won't know
+ which stub to use for the various calls in this object file.
+ Fortunately, this case is illegal, since it means that a function
+ was declared in two different ways in a single compilation. */
+ if (fp_ret_p && !l->fp_ret_p)
+ error ("cannot handle inconsistent calls to %qs", fnname);
- mips_lo_relocs[SYMBOL_HALF] = "%half(";
+ if (retval == NULL_RTX)
+ insn = gen_call_internal_direct (fn, args_size);
+ else
+ insn = gen_call_value_internal_direct (retval, fn, args_size);
+ insn = mips_emit_call_insn (insn, false);
+
+ /* If we are calling a stub which handles a floating-point return
+ value, we need to arrange to save $18 in the prologue. We do this
+ by marking the function call as using the register. The prologue
+ will later see that it is used, and emit code to save it. */
+ if (fp_ret_p)
+ CALL_INSN_FUNCTION_USAGE (insn) =
+ gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
+ CALL_INSN_FUNCTION_USAGE (insn));
+
+ return insn;
}
+\f
+/* Return true if calls to X can use R_MIPS_CALL* relocations. */
-static GTY(()) int was_mips16_p = -1;
+static bool
+mips_ok_for_lazy_binding_p (rtx x)
+{
+ return (TARGET_USE_GOT
+ && GET_CODE (x) == SYMBOL_REF
+ && !mips_symbol_binds_local_p (x));
+}
-/* Set up the target-dependent global state so that it matches the
- current function's ISA mode. */
+/* Load function address ADDR into register DEST. SIBCALL_P is true
+ if the address is needed for a sibling call. Return true if we
+ used an explicit lazy-binding sequence. */
-static void
-mips_set_mips16_mode (int mips16_p)
+static bool
+mips_load_call_address (rtx dest, rtx addr, bool sibcall_p)
{
- if (mips16_p == was_mips16_p)
- return;
-
- /* Restore base settings of various flags. */
- target_flags = mips_base_target_flags;
- align_loops = mips_base_align_loops;
- align_jumps = mips_base_align_jumps;
- align_functions = mips_base_align_functions;
- flag_schedule_insns = mips_base_schedule_insns;
- flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
- flag_move_loop_invariants = mips_base_move_loop_invariants;
- flag_delayed_branch = mips_flag_delayed_branch;
-
- if (mips16_p)
+ /* If we're generating PIC, and this call is to a global function,
+ try to allow its address to be resolved lazily. This isn't
+ possible for sibcalls when $gp is call-saved because the value
+ of $gp on entry to the stub would be our caller's gp, not ours. */
+ if (TARGET_EXPLICIT_RELOCS
+ && !(sibcall_p && TARGET_CALL_SAVED_GP)
+ && mips_ok_for_lazy_binding_p (addr))
{
- /* Select mips16 instruction set. */
- target_flags |= MASK_MIPS16;
-
- /* Don't run the scheduler before reload, since it tends to
- increase register pressure. */
- flag_schedule_insns = 0;
+ rtx high, lo_sum_symbol;
- /* Don't do hot/cold partitioning. The constant layout code expects
- the whole function to be in a single section. */
- flag_reorder_blocks_and_partition = 0;
-
- /* Don't move loop invariants, because it tends to increase
- register pressure. It also introduces an extra move in cases
- where the constant is the first operand in a two-operand binary
- instruction, or when it forms a register argument to a functon
- call. */
- flag_move_loop_invariants = 0;
-
- /* Silently disable -mexplicit-relocs since it doesn't apply
- to mips16 code. Even so, it would overly pedantic to warn
- about "-mips16 -mexplicit-relocs", especially given that
- we use a %gprel() operator. */
- target_flags &= ~MASK_EXPLICIT_RELOCS;
-
- /* Silently disable DSP extensions. */
- target_flags &= ~MASK_DSP;
- target_flags &= ~MASK_DSPR2;
+ high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
+ addr, SYMBOL_GOTOFF_CALL);
+ lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
+ if (Pmode == SImode)
+ emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
+ else
+ emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
+ return true;
}
- else
+ else
{
- /* Reset to select base non-mips16 ISA. */
- target_flags &= ~MASK_MIPS16;
+ mips_emit_move (dest, addr);
+ return false;
+ }
+}
- /* When using explicit relocs, we call dbr_schedule from within
- mips_reorg. */
- if (TARGET_EXPLICIT_RELOCS)
- flag_delayed_branch = 0;
+/* Expand a "call", "sibcall", "call_value" or "sibcall_value" instruction.
+ RESULT is where the result will go (null for "call"s and "sibcall"s),
+ ADDR is the address of the function, ARGS_SIZE is the size of the
+ arguments and AUX is the value passed to us by mips_function_arg.
+ SIBCALL_P is true if we are expanding a sibling call, false if we're
+ expanding a normal call.
- /* Provide default values for align_* for 64-bit targets. */
- if (TARGET_64BIT)
- {
- if (align_loops == 0)
- align_loops = 8;
- if (align_jumps == 0)
- align_jumps = 8;
- if (align_functions == 0)
- align_functions = 8;
- }
- }
+ Return the call itself. */
- /* (Re)initialize mips target internals for new ISA. */
- mips_init_split_addresses ();
- mips_init_relocs ();
+rtx
+mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, bool sibcall_p)
+{
+ rtx orig_addr, pattern, insn;
+ bool lazy_p;
- if (was_mips16_p >= 0)
- /* Reinitialize target-dependent state. */
- target_reinit ();
+ orig_addr = addr;
+ lazy_p = false;
+ if (!call_insn_operand (addr, VOIDmode))
+ {
+ addr = gen_reg_rtx (Pmode);
+ lazy_p = mips_load_call_address (addr, orig_addr, sibcall_p);
+ }
- was_mips16_p = TARGET_MIPS16;
-}
+ insn = mips16_build_call_stub (result, addr, args_size,
+ aux == 0 ? 0 : (int) GET_MODE (aux));
+ if (insn)
+ {
+ gcc_assert (!sibcall_p && !lazy_p);
+ return insn;
+ }
-/* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
- function should use the MIPS16 ISA and switch modes accordingly. */
+ if (result == 0)
+ pattern = (sibcall_p
+ ? gen_sibcall_internal (addr, args_size)
+ : gen_call_internal (addr, args_size));
+ else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
+ {
+ /* Handle return values created by mips_return_fpr_pair. */
+ rtx reg1, reg2;
-static void
-mips_set_current_function (tree fndecl)
-{
- int mips16p;
- if (errorcount || sorrycount)
- /* Avoid generating RTL when fndecl is possibly invalid. Best to fall
- back on non-MIPS16 mode to avoid any strange secondary errors about
- use of unsupported features in MIPS16 mode. */
- mips16p = false;
- else if (fndecl)
- mips16p = SYMBOL_REF_MIPS16_FUNC_P (XEXP (DECL_RTL (fndecl), 0));
+ reg1 = XEXP (XVECEXP (result, 0, 0), 0);
+ reg2 = XEXP (XVECEXP (result, 0, 1), 0);
+ pattern =
+ (sibcall_p
+ ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
+ : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
+ }
else
- mips16p = mips_base_mips16;
- mips_set_mips16_mode (mips16p);
+ {
+ /* Handle return values created by mips_return_fpr_single. */
+ if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
+ result = XEXP (XVECEXP (result, 0, 0), 0);
+ pattern = (sibcall_p
+ ? gen_sibcall_value_internal (result, addr, args_size)
+ : gen_call_value_internal (result, addr, args_size));
+ }
+
+ return mips_emit_call_insn (pattern, lazy_p);
}
-/* Implement TARGET_HANDLE_OPTION. */
+/* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
static bool
-mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
+mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
{
- switch (code)
- {
- case OPT_mabi_:
- if (strcmp (arg, "32") == 0)
- mips_abi = ABI_32;
- else if (strcmp (arg, "o64") == 0)
- mips_abi = ABI_O64;
- else if (strcmp (arg, "n32") == 0)
- mips_abi = ABI_N32;
- else if (strcmp (arg, "64") == 0)
- mips_abi = ABI_64;
- else if (strcmp (arg, "eabi") == 0)
- mips_abi = ABI_EABI;
- else
- return false;
- return true;
-
- case OPT_march_:
- case OPT_mtune_:
- return mips_parse_cpu (arg) != 0;
-
- case OPT_mips:
- mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
- return mips_isa_info != 0;
+ if (!TARGET_SIBCALLS)
+ return false;
- case OPT_mno_flush_func:
- mips_cache_flush_func = NULL;
- return true;
+ /* We can't do a sibcall if the called function is a MIPS16 function
+ because there is no direct "jx" instruction equivalent to "jalx" to
+ switch the ISA mode. We only care about cases where the sibling
+ and normal calls would both be direct. */
+ if (mips_use_mips16_mode_p (decl)
+ && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
+ return false;
- case OPT_mcode_readable_:
- if (strcmp (arg, "yes") == 0)
- mips_code_readable = CODE_READABLE_YES;
- else if (strcmp (arg, "pcrel") == 0)
- mips_code_readable = CODE_READABLE_PCREL;
- else if (strcmp (arg, "no") == 0)
- mips_code_readable = CODE_READABLE_NO;
- else
- return false;
- return true;
+ /* When -minterlink-mips16 is in effect, assume that non-locally-binding
+ functions could be MIPS16 ones unless an attribute explicitly tells
+ us otherwise. */
+ if (TARGET_INTERLINK_MIPS16
+ && decl
+ && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
+ && !mips_nomips16_decl_p (decl)
+ && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
+ return false;
- default:
- return true;
- }
+ /* Otherwise OK. */
+ return true;
}
+\f
+/* Emit code to move general operand SRC into condition-code
+ register DEST given that SCRATCH is a scratch TFmode FPR.
+ The sequence is:
-/* Set up the threshold for data to go into the small data area, instead
- of the normal data area, and detect any conflicts in the switches. */
+ FP1 = SRC
+ FP2 = 0.0f
+ DEST = FP2 < FP1
+
+ where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
void
-override_options (void)
+mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
{
- int i, start, regno;
- enum machine_mode mode;
+ rtx fp1, fp2;
-#ifdef SUBTARGET_OVERRIDE_OPTIONS
- SUBTARGET_OVERRIDE_OPTIONS;
-#endif
+ /* Change the source to SFmode. */
+ if (MEM_P (src))
+ src = adjust_address (src, SFmode, 0);
+ else if (REG_P (src) || GET_CODE (src) == SUBREG)
+ src = gen_rtx_REG (SFmode, true_regnum (src));
- mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
+ fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
+ fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
- /* The following code determines the architecture and register size.
- Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
- The GAS and GCC code should be kept in sync as much as possible. */
+ mips_emit_move (copy_rtx (fp1), src);
+ mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
+ emit_insn (gen_slt_sf (dest, fp2, fp1));
+}
+\f
+/* Emit straight-line code to move LENGTH bytes from SRC to DEST.
+ Assume that the areas do not overlap. */
- if (mips_arch_string != 0)
- mips_set_architecture (mips_parse_cpu (mips_arch_string));
+static void
+mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
+{
+ HOST_WIDE_INT offset, delta;
+ unsigned HOST_WIDE_INT bits;
+ int i;
+ enum machine_mode mode;
+ rtx *regs;
+
+ /* Work out how many bits to move at a time. If both operands have
+ half-word alignment, it is usually better to move in half words.
+ For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
+ and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
+ Otherwise move word-sized chunks. */
+ if (MEM_ALIGN (src) == BITS_PER_WORD / 2
+ && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
+ bits = BITS_PER_WORD / 2;
+ else
+ bits = BITS_PER_WORD;
+
+ mode = mode_for_size (bits, MODE_INT, 0);
+ delta = bits / BITS_PER_UNIT;
+
+ /* Allocate a buffer for the temporary registers. */
+ regs = alloca (sizeof (rtx) * length / delta);
- if (mips_isa_info != 0)
+ /* Load as many BITS-sized chunks as possible. Use a normal load if
+ the source has enough alignment, otherwise use left/right pairs. */
+ for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
{
- if (mips_arch_info == 0)
- mips_set_architecture (mips_isa_info);
- else if (mips_arch_info->isa != mips_isa_info->isa)
- error ("-%s conflicts with the other architecture options, "
- "which specify a %s processor",
- mips_isa_info->name,
- mips_cpu_info_from_isa (mips_arch_info->isa)->name);
+ regs[i] = gen_reg_rtx (mode);
+ if (MEM_ALIGN (src) >= bits)
+ mips_emit_move (regs[i], adjust_address (src, mode, offset));
+ else
+ {
+ rtx part = adjust_address (src, BLKmode, offset);
+ if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
+ gcc_unreachable ();
+ }
}
- if (mips_arch_info == 0)
+ /* Copy the chunks to the destination. */
+ for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
+ if (MEM_ALIGN (dest) >= bits)
+ mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
+ else
+ {
+ rtx part = adjust_address (dest, BLKmode, offset);
+ if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
+ gcc_unreachable ();
+ }
+
+ /* Mop up any left-over bytes. */
+ if (offset < length)
{
-#ifdef MIPS_CPU_STRING_DEFAULT
- mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
-#else
- mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
-#endif
+ src = adjust_address (src, BLKmode, offset);
+ dest = adjust_address (dest, BLKmode, offset);
+ move_by_pieces (dest, src, length - offset,
+ MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
}
+}
- if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
- error ("-march=%s is not compatible with the selected ABI",
- mips_arch_info->name);
+/* Helper function for doing a loop-based block operation on memory
+ reference MEM. Each iteration of the loop will operate on LENGTH
+ bytes of MEM.
- /* Optimize for mips_arch, unless -mtune selects a different processor. */
- if (mips_tune_string != 0)
- mips_set_tune (mips_parse_cpu (mips_tune_string));
+ Create a new base register for use within the loop and point it to
+ the start of MEM. Create a new memory reference that uses this
+ register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
- if (mips_tune_info == 0)
- mips_set_tune (mips_arch_info);
+static void
+mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
+ rtx *loop_reg, rtx *loop_mem)
+{
+ *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
- /* Set cost structure for the processor. */
- if (optimize_size)
- mips_cost = &mips_rtx_cost_optimize_size;
- else
- mips_cost = &mips_rtx_cost_data[mips_tune];
+ /* Although the new mem does not refer to a known location,
+ it does keep up to LENGTH bytes of alignment. */
+ *loop_mem = change_address (mem, BLKmode, *loop_reg);
+ set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
+}
- /* If the user hasn't specified a branch cost, use the processor's
- default. */
- if (mips_branch_cost == 0)
- mips_branch_cost = mips_cost->branch_cost;
+/* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
+ bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
+ the memory regions do not overlap. */
- if ((target_flags_explicit & MASK_64BIT) != 0)
- {
- /* The user specified the size of the integer registers. Make sure
- it agrees with the ABI and ISA. */
- if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
- error ("-mgp64 used with a 32-bit processor");
- else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
- error ("-mgp32 used with a 64-bit ABI");
- else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
- error ("-mgp64 used with a 32-bit ABI");
- }
- else
- {
- /* Infer the integer register size from the ABI and processor.
- Restrict ourselves to 32-bit registers if that's all the
- processor has, or if the ABI cannot handle 64-bit registers. */
- if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
- target_flags &= ~MASK_64BIT;
- else
- target_flags |= MASK_64BIT;
- }
-
- if ((target_flags_explicit & MASK_FLOAT64) != 0)
- {
- /* Really, -mfp32 and -mfp64 are ornamental options. There's
- only one right answer here. */
- if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
- error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
- else if (!TARGET_64BIT && TARGET_FLOAT64
- && !(ISA_HAS_MXHC1 && mips_abi == ABI_32))
- error ("-mgp32 and -mfp64 can only be combined if the target"
- " supports the mfhc1 and mthc1 instructions");
- else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
- error ("unsupported combination: %s", "-mfp64 -msingle-float");
- }
- else
- {
- /* -msingle-float selects 32-bit float registers. Otherwise the
- float registers should be the same size as the integer ones. */
- if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
- target_flags |= MASK_FLOAT64;
- else
- target_flags &= ~MASK_FLOAT64;
- }
-
- /* End of code shared with GAS. */
-
- if ((target_flags_explicit & MASK_LONG64) == 0)
- {
- if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
- target_flags |= MASK_LONG64;
- else
- target_flags &= ~MASK_LONG64;
- }
-
- if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
- && (target_flags_explicit & MASK_SOFT_FLOAT_ABI) == 0)
- {
- /* For some configurations, it is useful to have -march control
- the default setting of MASK_SOFT_FLOAT_ABI. */
- switch ((int) mips_arch)
- {
- case PROCESSOR_R4100:
- case PROCESSOR_R4111:
- case PROCESSOR_R4120:
- case PROCESSOR_R4130:
- target_flags |= MASK_SOFT_FLOAT_ABI;
- break;
+static void
+mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
+ HOST_WIDE_INT bytes_per_iter)
+{
+ rtx label, src_reg, dest_reg, final_src;
+ HOST_WIDE_INT leftover;
- default:
- target_flags &= ~MASK_SOFT_FLOAT_ABI;
- break;
- }
- }
+ leftover = length % bytes_per_iter;
+ length -= leftover;
- if (!TARGET_OLDABI)
- flag_pcc_struct_return = 0;
+ /* Create registers and memory references for use within the loop. */
+ mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
+ mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
- if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
- {
- /* If neither -mbranch-likely nor -mno-branch-likely was given
- on the command line, set MASK_BRANCHLIKELY based on the target
- architecture.
-
- By default, we enable use of Branch Likely instructions on
- all architectures which support them with the following
- exceptions: when creating MIPS32 or MIPS64 code, and when
- tuning for architectures where their use tends to hurt
- performance.
-
- The MIPS32 and MIPS64 architecture specifications say "Software
- is strongly encouraged to avoid use of Branch Likely
- instructions, as they will be removed from a future revision
- of the [MIPS32 and MIPS64] architecture." Therefore, we do not
- issue those instructions unless instructed to do so by
- -mbranch-likely. */
- if (ISA_HAS_BRANCHLIKELY
- && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
- && !(TUNE_MIPS5500 || TUNE_SB1))
- target_flags |= MASK_BRANCHLIKELY;
- else
- target_flags &= ~MASK_BRANCHLIKELY;
- }
- if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
- warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
+ /* Calculate the value that SRC_REG should have after the last iteration
+ of the loop. */
+ final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
+ 0, 0, OPTAB_WIDEN);
- /* The effect of -mabicalls isn't defined for the EABI. */
- if (mips_abi == ABI_EABI && TARGET_ABICALLS)
- {
- error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
- target_flags &= ~MASK_ABICALLS;
- }
+ /* Emit the start of the loop. */
+ label = gen_label_rtx ();
+ emit_label (label);
- /* MIPS16 cannot generate PIC yet. */
- if (TARGET_MIPS16 && (flag_pic || TARGET_ABICALLS))
- {
- sorry ("MIPS16 PIC");
- target_flags &= ~MASK_ABICALLS;
- flag_pic = flag_pie = flag_shlib = 0;
- }
+ /* Emit the loop body. */
+ mips_block_move_straight (dest, src, bytes_per_iter);
- if (TARGET_ABICALLS)
- /* We need to set flag_pic for executables as well as DSOs
- because we may reference symbols that are not defined in
- the final executable. (MIPS does not use things like
- copy relocs, for example.)
+ /* Move on to the next block. */
+ mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
+ mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
- Also, there is a body of code that uses __PIC__ to distinguish
- between -mabicalls and -mno-abicalls code. */
- flag_pic = 1;
+ /* Emit the loop condition. */
+ if (Pmode == DImode)
+ emit_insn (gen_cmpdi (src_reg, final_src));
+ else
+ emit_insn (gen_cmpsi (src_reg, final_src));
+ emit_jump_insn (gen_bne (label));
- /* -mvr4130-align is a "speed over size" optimization: it usually produces
- faster code, but at the expense of more nops. Enable it at -O3 and
- above. */
- if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
- target_flags |= MASK_VR4130_ALIGN;
+ /* Mop up any left-over bytes. */
+ if (leftover)
+ mips_block_move_straight (dest, src, leftover);
+}
- /* Prefer a call to memcpy over inline code when optimizing for size,
- though see MOVE_RATIO in mips.h. */
- if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
- target_flags |= MASK_MEMCPY;
+/* Expand a movmemsi instruction, which copies LENGTH bytes from
+ memory reference SRC to memory reference DEST. */
- /* If we have a nonzero small-data limit, check that the -mgpopt
- setting is consistent with the other target flags. */
- if (mips_section_threshold > 0)
+bool
+mips_expand_block_move (rtx dest, rtx src, rtx length)
+{
+ if (GET_CODE (length) == CONST_INT)
{
- if (!TARGET_GPOPT)
+ if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
{
- if (!TARGET_MIPS16 && !TARGET_EXPLICIT_RELOCS)
- error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
-
- TARGET_LOCAL_SDATA = false;
- TARGET_EXTERN_SDATA = false;
+ mips_block_move_straight (dest, src, INTVAL (length));
+ return true;
}
- else
+ else if (optimize)
{
- if (TARGET_VXWORKS_RTP)
- warning (0, "cannot use small-data accesses for %qs", "-mrtp");
-
- if (TARGET_ABICALLS)
- warning (0, "cannot use small-data accesses for %qs",
- "-mabicalls");
+ mips_block_move_loop (dest, src, INTVAL (length),
+ MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
+ return true;
}
}
+ return false;
+}
+\f
+/* Expand a loop of synci insns for the address range [BEGIN, END). */
-#ifdef MIPS_TFMODE_FORMAT
- REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
-#endif
+void
+mips_expand_synci_loop (rtx begin, rtx end)
+{
+ rtx inc, label, cmp, cmp_result;
- /* Make sure that the user didn't turn off paired single support when
- MIPS-3D support is requested. */
- if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
- && !TARGET_PAIRED_SINGLE_FLOAT)
- error ("-mips3d requires -mpaired-single");
+ /* Load INC with the cache line size (rdhwr INC,$1). */
+ inc = gen_reg_rtx (SImode);
+ emit_insn (gen_rdhwr (inc, const1_rtx));
- /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
- if (TARGET_MIPS3D)
- target_flags |= MASK_PAIRED_SINGLE_FLOAT;
+ /* Loop back to here. */
+ label = gen_label_rtx ();
+ emit_label (label);
- /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
- and TARGET_HARD_FLOAT are both true. */
- if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
- error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
+ emit_insn (gen_synci (begin));
- /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
- enabled. */
- if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
- error ("-mips3d/-mpaired-single must be used with -mips64");
+ cmp = gen_reg_rtx (Pmode);
+ mips_emit_binary (GTU, cmp, begin, end);
- /* If TARGET_DSPR2, enable MASK_DSP. */
- if (TARGET_DSPR2)
- target_flags |= MASK_DSP;
+ mips_emit_binary (PLUS, begin, begin, inc);
- mips_print_operand_punct['?'] = 1;
- mips_print_operand_punct['#'] = 1;
- mips_print_operand_punct['/'] = 1;
- mips_print_operand_punct['&'] = 1;
- mips_print_operand_punct['!'] = 1;
- mips_print_operand_punct['*'] = 1;
- mips_print_operand_punct['@'] = 1;
- mips_print_operand_punct['.'] = 1;
- mips_print_operand_punct['('] = 1;
- mips_print_operand_punct[')'] = 1;
- mips_print_operand_punct['['] = 1;
- mips_print_operand_punct[']'] = 1;
- mips_print_operand_punct['<'] = 1;
- mips_print_operand_punct['>'] = 1;
- mips_print_operand_punct['{'] = 1;
- mips_print_operand_punct['}'] = 1;
- mips_print_operand_punct['^'] = 1;
- mips_print_operand_punct['$'] = 1;
- mips_print_operand_punct['+'] = 1;
- mips_print_operand_punct['~'] = 1;
+ cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
+ emit_jump_insn (gen_condjump (cmp_result, label));
+}
+\f
+/* Return true if it is possible to use left/right accesses for a
+ bitfield of WIDTH bits starting BITPOS bits into *OP. When
+ returning true, update *OP, *LEFT and *RIGHT as follows:
- /* Set up array to map GCC register number to debug register number.
- Ignore the special purpose register numbers. */
+ *OP is a BLKmode reference to the whole field.
- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- {
- mips_dbx_regno[i] = INVALID_REGNUM;
- if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
- mips_dwarf_regno[i] = i;
- else
- mips_dwarf_regno[i] = INVALID_REGNUM;
- }
+ *LEFT is a QImode reference to the first byte if big endian or
+ the last byte if little endian. This address can be used in the
+ left-side instructions (LWL, SWL, LDL, SDL).
- start = GP_DBX_FIRST - GP_REG_FIRST;
- for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
- mips_dbx_regno[i] = i + start;
+ *RIGHT is a QImode reference to the opposite end of the field and
+ can be used in the patterning right-side instruction. */
- start = FP_DBX_FIRST - FP_REG_FIRST;
- for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
- mips_dbx_regno[i] = i + start;
+static bool
+mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
+ rtx *left, rtx *right)
+{
+ rtx first, last;
- /* HI and LO debug registers use big-endian ordering. */
- mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
- mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
- mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
- mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
- for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
- {
- mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
- mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
- }
+ /* Check that the operand really is a MEM. Not all the extv and
+ extzv predicates are checked. */
+ if (!MEM_P (*op))
+ return false;
- /* Set up array giving whether a given register can hold a given mode. */
+ /* Check that the size is valid. */
+ if (width != 32 && (!TARGET_64BIT || width != 64))
+ return false;
- for (mode = VOIDmode;
- mode != MAX_MACHINE_MODE;
- mode = (enum machine_mode) ((int)mode + 1))
- {
- register int size = GET_MODE_SIZE (mode);
- register enum mode_class class = GET_MODE_CLASS (mode);
+ /* We can only access byte-aligned values. Since we are always passed
+ a reference to the first byte of the field, it is not necessary to
+ do anything with BITPOS after this check. */
+ if (bitpos % BITS_PER_UNIT != 0)
+ return false;
- for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
- {
- register int temp;
+ /* Reject aligned bitfields: we want to use a normal load or store
+ instead of a left/right pair. */
+ if (MEM_ALIGN (*op) >= width)
+ return false;
- if (mode == CCV2mode)
- temp = (ISA_HAS_8CC
- && ST_REG_P (regno)
- && (regno - ST_REG_FIRST) % 2 == 0);
+ /* Adjust *OP to refer to the whole field. This also has the effect
+ of legitimizing *OP's address for BLKmode, possibly simplifying it. */
+ *op = adjust_address (*op, BLKmode, 0);
+ set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
- else if (mode == CCV4mode)
- temp = (ISA_HAS_8CC
- && ST_REG_P (regno)
- && (regno - ST_REG_FIRST) % 4 == 0);
+ /* Get references to both ends of the field. We deliberately don't
+ use the original QImode *OP for FIRST since the new BLKmode one
+ might have a simpler address. */
+ first = adjust_address (*op, QImode, 0);
+ last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
- else if (mode == CCmode)
- {
- if (! ISA_HAS_8CC)
- temp = (regno == FPSW_REGNUM);
- else
- temp = (ST_REG_P (regno) || GP_REG_P (regno)
- || FP_REG_P (regno));
- }
+ /* Allocate to LEFT and RIGHT according to endianness. LEFT should
+ correspond to the MSB and RIGHT to the LSB. */
+ if (TARGET_BIG_ENDIAN)
+ *left = first, *right = last;
+ else
+ *left = last, *right = first;
- else if (GP_REG_P (regno))
- temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
-
- else if (FP_REG_P (regno))
- temp = ((((regno % MAX_FPRS_PER_FMT) == 0)
- || (MIN_FPRS_PER_FMT == 1
- && size <= UNITS_PER_FPREG))
- && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
- || class == MODE_VECTOR_FLOAT)
- && size <= UNITS_PER_FPVALUE)
- /* Allow integer modes that fit into a single
- register. We need to put integers into FPRs
- when using instructions like cvt and trunc.
- We can't allow sizes smaller than a word,
- the FPU has no appropriate load/store
- instructions for those. */
- || (class == MODE_INT
- && size >= MIN_UNITS_PER_WORD
- && size <= UNITS_PER_FPREG)
- /* Allow TFmode for CCmode reloads. */
- || (ISA_HAS_8CC && mode == TFmode)));
-
- else if (ACC_REG_P (regno))
- temp = (INTEGRAL_MODE_P (mode)
- && size <= UNITS_PER_WORD * 2
- && (size <= UNITS_PER_WORD
- || regno == MD_REG_FIRST
- || (DSP_ACC_REG_P (regno)
- && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)));
-
- else if (ALL_COP_REG_P (regno))
- temp = (class == MODE_INT && size <= UNITS_PER_WORD);
- else
- temp = 0;
+ return true;
+}
- mips_hard_regno_mode_ok[(int)mode][regno] = temp;
- }
- }
+/* Try to use left/right loads to expand an "extv" or "extzv" pattern.
+ DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
+ the operation is the equivalent of:
- /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
- initialized yet, so we can't use that here. */
- gpr_mode = TARGET_64BIT ? DImode : SImode;
+ (set DEST (*_extract SRC WIDTH BITPOS))
- /* Function to allocate machine-dependent function status. */
- init_machine_status = &mips_init_machine_status;
+ Return true on success. */
- /* Default to working around R4000 errata only if the processor
- was selected explicitly. */
- if ((target_flags_explicit & MASK_FIX_R4000) == 0
- && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
- target_flags |= MASK_FIX_R4000;
+bool
+mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
+ HOST_WIDE_INT bitpos)
+{
+ rtx left, right, temp;
- /* Default to working around R4400 errata only if the processor
- was selected explicitly. */
- if ((target_flags_explicit & MASK_FIX_R4400) == 0
- && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
- target_flags |= MASK_FIX_R4400;
-
- /* Save base state of options. */
- mips_base_mips16 = TARGET_MIPS16;
- mips_base_target_flags = target_flags;
- mips_base_schedule_insns = flag_schedule_insns;
- mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
- mips_base_move_loop_invariants = flag_move_loop_invariants;
- mips_base_align_loops = align_loops;
- mips_base_align_jumps = align_jumps;
- mips_base_align_functions = align_functions;
- mips_flag_delayed_branch = flag_delayed_branch;
-
- /* Now select the mips16 or 32-bit instruction set, as requested. */
- mips_set_mips16_mode (mips_base_mips16);
-}
+ /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
+ be a paradoxical word_mode subreg. This is the only case in which
+ we allow the destination to be larger than the source. */
+ if (GET_CODE (dest) == SUBREG
+ && GET_MODE (dest) == DImode
+ && GET_MODE (SUBREG_REG (dest)) == SImode)
+ dest = SUBREG_REG (dest);
-/* Swap the register information for registers I and I + 1, which
- currently have the wrong endianness. Note that the registers'
- fixedness and call-clobberedness might have been set on the
- command line. */
+ /* After the above adjustment, the destination must be the same
+ width as the source. */
+ if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
+ return false;
-static void
-mips_swap_registers (unsigned int i)
-{
- int tmpi;
- const char *tmps;
+ if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
+ return false;
-#define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
-#define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
+ temp = gen_reg_rtx (GET_MODE (dest));
+ if (GET_MODE (dest) == DImode)
+ {
+ emit_insn (gen_mov_ldl (temp, src, left));
+ emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
+ }
+ else
+ {
+ emit_insn (gen_mov_lwl (temp, src, left));
+ emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
+ }
+ return true;
+}
- SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
- SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
- SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
- SWAP_STRING (reg_names[i], reg_names[i + 1]);
+/* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
+ BITPOS and SRC are the operands passed to the expander; the operation
+ is the equivalent of:
-#undef SWAP_STRING
-#undef SWAP_INT
-}
+ (set (zero_extract DEST WIDTH BITPOS) SRC)
-/* Implement CONDITIONAL_REGISTER_USAGE. */
+ Return true on success. */
-void
-mips_conditional_register_usage (void)
+bool
+mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
+ HOST_WIDE_INT bitpos)
{
- if (!TARGET_DSP)
- {
- int regno;
-
- for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
- fixed_regs[regno] = call_used_regs[regno] = 1;
- }
- if (!TARGET_HARD_FLOAT)
- {
- int regno;
+ rtx left, right;
+ enum machine_mode mode;
- for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
- fixed_regs[regno] = call_used_regs[regno] = 1;
- for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
- fixed_regs[regno] = call_used_regs[regno] = 1;
- }
- else if (! ISA_HAS_8CC)
- {
- int regno;
+ if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
+ return false;
- /* We only have a single condition code register. We
- implement this by hiding all the condition code registers,
- and generating RTL that refers directly to ST_REG_FIRST. */
- for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
- fixed_regs[regno] = call_used_regs[regno] = 1;
- }
- /* In mips16 mode, we permit the $t temporary registers to be used
- for reload. We prohibit the unused $s registers, since they
- are caller saved, and saving them via a mips16 register would
- probably waste more time than just reloading the value. */
- if (TARGET_MIPS16)
- {
- fixed_regs[18] = call_used_regs[18] = 1;
- fixed_regs[19] = call_used_regs[19] = 1;
- fixed_regs[20] = call_used_regs[20] = 1;
- fixed_regs[21] = call_used_regs[21] = 1;
- fixed_regs[22] = call_used_regs[22] = 1;
- fixed_regs[23] = call_used_regs[23] = 1;
- fixed_regs[26] = call_used_regs[26] = 1;
- fixed_regs[27] = call_used_regs[27] = 1;
- fixed_regs[30] = call_used_regs[30] = 1;
- }
- /* fp20-23 are now caller saved. */
- if (mips_abi == ABI_64)
- {
- int regno;
- for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
- call_really_used_regs[regno] = call_used_regs[regno] = 1;
- }
- /* Odd registers from fp21 to fp31 are now caller saved. */
- if (mips_abi == ABI_N32)
+ mode = mode_for_size (width, MODE_INT, 0);
+ src = gen_lowpart (mode, src);
+ if (mode == DImode)
{
- int regno;
- for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
- call_really_used_regs[regno] = call_used_regs[regno] = 1;
+ emit_insn (gen_mov_sdl (dest, src, left));
+ emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
}
- /* Make sure that double-register accumulator values are correctly
- ordered for the current endianness. */
- if (TARGET_LITTLE_ENDIAN)
+ else
{
- int regno;
- mips_swap_registers (MD_REG_FIRST);
- for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
- mips_swap_registers (regno);
+ emit_insn (gen_mov_swl (dest, src, left));
+ emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
}
+ return true;
}
-/* Allocate a chunk of memory for per-function machine-dependent data. */
-static struct machine_function *
-mips_init_machine_status (void)
-{
- return ((struct machine_function *)
- ggc_alloc_cleared (sizeof (struct machine_function)));
-}
-
-/* On the mips16, we want to allocate $24 (T_REG) before other
- registers for instructions for which it is possible. This helps
- avoid shuffling registers around in order to set up for an xor,
- encouraging the compiler to use a cmp instead. */
+/* Return true if X is a MEM with the same size as MODE. */
-void
-mips_order_regs_for_local_alloc (void)
+bool
+mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
{
- register int i;
+ rtx size;
- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- reg_alloc_order[i] = i;
+ if (!MEM_P (x))
+ return false;
- if (TARGET_MIPS16)
- {
- /* It really doesn't matter where we put register 0, since it is
- a fixed register anyhow. */
- reg_alloc_order[0] = 24;
- reg_alloc_order[24] = 0;
- }
+ size = MEM_SIZE (x);
+ return size && INTVAL (size) == GET_MODE_SIZE (mode);
}
-\f
-/* The MIPS debug format wants all automatic variables and arguments
- to be in terms of the virtual frame pointer (stack pointer before
- any adjustment in the function), while the MIPS 3.0 linker wants
- the frame pointer to be the stack pointer after the initial
- adjustment. So, we do the adjustment here. The arg pointer (which
- is eliminated) points to the virtual frame pointer, while the frame
- pointer (which may be eliminated) points to the stack pointer after
- the initial adjustments. */
-
-HOST_WIDE_INT
-mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
-{
- rtx offset2 = const0_rtx;
- rtx reg = eliminate_constant_term (addr, &offset2);
+/* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
+ source of an "ext" instruction or the destination of an "ins"
+ instruction. OP must be a register operand and the following
+ conditions must hold:
- if (offset == 0)
- offset = INTVAL (offset2);
+ 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
+ 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
+ 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
- if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
- || reg == hard_frame_pointer_rtx)
- {
- HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
- ? compute_frame_size (get_frame_size ())
- : cfun->machine->frame.total_size;
+ Also reject lengths equal to a word as they are better handled
+ by the move patterns. */
- /* MIPS16 frame is smaller */
- if (frame_pointer_needed && TARGET_MIPS16)
- frame_size -= cfun->machine->frame.args_size;
+bool
+mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
+{
+ if (!ISA_HAS_EXT_INS
+ || !register_operand (op, VOIDmode)
+ || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
+ return false;
- offset = offset - frame_size;
- }
+ if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
+ return false;
- /* sdbout_parms does not want this to crash for unrecognized cases. */
-#if 0
- else if (reg != arg_pointer_rtx)
- fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
- addr);
-#endif
+ if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
+ return false;
- return offset;
+ return true;
}
\f
-/* If OP is an UNSPEC address, return the address to which it refers,
- otherwise return OP itself. */
-
-static rtx
-mips_strip_unspec_address (rtx op)
-{
- rtx base, offset;
+/* Return true if -msplit-addresses is selected and should be honored.
- split_const (op, &base, &offset);
- if (UNSPEC_ADDRESS_P (base))
- op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
- return op;
-}
+ -msplit-addresses is a half-way house between explicit relocations
+ and the traditional assembler macros. It can split absolute 32-bit
+ symbolic constants into a high/lo_sum pair but uses macros for other
+ sorts of access.
-/* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
+ Like explicit relocation support for REL targets, it relies
+ on GNU extensions in the assembler and the linker.
- 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
- 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
- 'h' OP is HIGH, prints %hi(X),
- 'd' output integer constant in decimal,
- 'z' if the operand is 0, use $0 instead of normal operand.
- 'D' print second part of double-word register or memory operand.
- 'L' print low-order register of double-word register operand.
- 'M' print high-order register of double-word register operand.
- 'C' print part of opcode for a branch condition.
- 'F' print part of opcode for a floating-point branch condition.
- 'N' print part of opcode for a branch condition, inverted.
- 'W' print part of opcode for a floating-point branch condition, inverted.
- 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
- 'z' for (eq:?I ...), 'n' for (ne:?I ...).
- 't' like 'T', but with the EQ/NE cases reversed
- 'Y' for a CONST_INT X, print mips_fp_conditions[X]
- 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
- 'R' print the reloc associated with LO_SUM
- 'q' print DSP accumulator registers
+ Although this code should work for -O0, it has traditionally
+ been treated as an optimization. */
- The punctuation characters are:
+static bool
+mips_split_addresses_p (void)
+{
+ return (TARGET_SPLIT_ADDRESSES
+ && optimize
+ && !TARGET_MIPS16
+ && !flag_pic
+ && !ABI_HAS_64BIT_SYMBOLS);
+}
- '(' Turn on .set noreorder
- ')' Turn on .set reorder
- '[' Turn on .set noat
- ']' Turn on .set at
- '<' Turn on .set nomacro
- '>' Turn on .set macro
- '{' Turn on .set volatile (not GAS)
- '}' Turn on .set novolatile (not GAS)
- '&' Turn on .set noreorder if filling delay slots
- '*' Turn on both .set noreorder and .set nomacro if filling delay slots
- '!' Turn on .set nomacro if filling delay slots
- '#' Print nop if in a .set noreorder section.
- '/' Like '#', but does nothing within a delayed branch sequence
- '?' Print 'l' if we are to use a branch likely instead of normal branch.
- '@' Print the name of the assembler temporary register (at or $1).
- '.' Print the name of the register with a hard-wired zero (zero or $0).
- '^' Print the name of the pic call-through register (t9 or $25).
- '$' Print the name of the stack pointer register (sp or $29).
- '+' Print the name of the gp register (usually gp or $28).
- '~' Output a branch alignment to LABEL_ALIGN(NULL). */
+/* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
-void
-print_operand (FILE *file, rtx op, int letter)
+static void
+mips_init_relocs (void)
{
- register enum rtx_code code;
+ memset (mips_split_p, '\0', sizeof (mips_split_p));
+ memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
+ memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
- if (PRINT_OPERAND_PUNCT_VALID_P (letter))
+ if (ABI_HAS_64BIT_SYMBOLS)
{
- switch (letter)
+ if (TARGET_EXPLICIT_RELOCS)
{
- case '?':
- if (mips_branch_likely)
- putc ('l', file);
- break;
-
- case '@':
- fputs (reg_names [GP_REG_FIRST + 1], file);
- break;
+ mips_split_p[SYMBOL_64_HIGH] = true;
+ mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
+ mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
- case '^':
- fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
- break;
+ mips_split_p[SYMBOL_64_MID] = true;
+ mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
+ mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
- case '.':
- fputs (reg_names [GP_REG_FIRST + 0], file);
- break;
+ mips_split_p[SYMBOL_64_LOW] = true;
+ mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
+ mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
- case '$':
- fputs (reg_names[STACK_POINTER_REGNUM], file);
- break;
+ mips_split_p[SYMBOL_ABSOLUTE] = true;
+ mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
+ }
+ }
+ else
+ {
+ if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
+ {
+ mips_split_p[SYMBOL_ABSOLUTE] = true;
+ mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
+ mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
- case '+':
- fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
- break;
+ mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
+ }
+ }
- case '&':
- if (final_sequence != 0 && set_noreorder++ == 0)
- fputs (".set\tnoreorder\n\t", file);
- break;
+ if (TARGET_MIPS16)
+ {
+ /* The high part is provided by a pseudo copy of $gp. */
+ mips_split_p[SYMBOL_GP_RELATIVE] = true;
+ mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
+ }
- case '*':
- if (final_sequence != 0)
- {
- if (set_noreorder++ == 0)
- fputs (".set\tnoreorder\n\t", file);
+ if (TARGET_EXPLICIT_RELOCS)
+ {
+ /* Small data constants are kept whole until after reload,
+ then lowered by mips_rewrite_small_data. */
+ mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
- if (set_nomacro++ == 0)
- fputs (".set\tnomacro\n\t", file);
- }
- break;
+ mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
+ if (TARGET_NEWABI)
+ {
+ mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
+ mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
+ }
+ else
+ {
+ mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
+ mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
+ }
- case '!':
- if (final_sequence != 0 && set_nomacro++ == 0)
- fputs ("\n\t.set\tnomacro", file);
- break;
+ if (TARGET_XGOT)
+ {
+ /* The HIGH and LO_SUM are matched by special .md patterns. */
+ mips_split_p[SYMBOL_GOT_DISP] = true;
- case '#':
- if (set_noreorder != 0)
- fputs ("\n\tnop", file);
- break;
+ mips_split_p[SYMBOL_GOTOFF_DISP] = true;
+ mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
+ mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
- case '/':
- /* Print an extra newline so that the delayed insn is separated
- from the following ones. This looks neater and is consistent
- with non-nop delayed sequences. */
- if (set_noreorder != 0 && final_sequence == 0)
- fputs ("\n\tnop\n", file);
- break;
+ mips_split_p[SYMBOL_GOTOFF_CALL] = true;
+ mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
+ mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
+ }
+ else
+ {
+ if (TARGET_NEWABI)
+ mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
+ else
+ mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
+ mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
+ }
+ }
- case '(':
- if (set_noreorder++ == 0)
- fputs (".set\tnoreorder\n\t", file);
- break;
+ if (TARGET_NEWABI)
+ {
+ mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
+ mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
+ mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
+ }
- case ')':
- if (set_noreorder == 0)
- error ("internal error: %%) found without a %%( in assembler pattern");
+ mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
+ mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
- else if (--set_noreorder == 0)
- fputs ("\n\t.set\treorder", file);
+ mips_split_p[SYMBOL_DTPREL] = true;
+ mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
+ mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
- break;
+ mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
- case '[':
- if (set_noat++ == 0)
- fputs (".set\tnoat\n\t", file);
- break;
+ mips_split_p[SYMBOL_TPREL] = true;
+ mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
+ mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
- case ']':
- if (set_noat == 0)
- error ("internal error: %%] found without a %%[ in assembler pattern");
- else if (--set_noat == 0)
- fputs ("\n\t.set\tat", file);
+ mips_lo_relocs[SYMBOL_HALF] = "%half(";
+}
- break;
+/* If OP is an UNSPEC address, return the address to which it refers,
+ otherwise return OP itself. */
- case '<':
- if (set_nomacro++ == 0)
- fputs (".set\tnomacro\n\t", file);
- break;
+static rtx
+mips_strip_unspec_address (rtx op)
+{
+ rtx base, offset;
- case '>':
- if (set_nomacro == 0)
- error ("internal error: %%> found without a %%< in assembler pattern");
- else if (--set_nomacro == 0)
- fputs ("\n\t.set\tmacro", file);
+ split_const (op, &base, &offset);
+ if (UNSPEC_ADDRESS_P (base))
+ op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
+ return op;
+}
- break;
+/* Print symbolic operand OP, which is part of a HIGH or LO_SUM
+ in context CONTEXT. RELOCS is the array of relocations to use. */
- case '{':
- if (set_volatile++ == 0)
- fputs ("#.set\tvolatile\n\t", file);
- break;
+static void
+mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
+ const char **relocs)
+{
+ enum mips_symbol_type symbol_type;
+ const char *p;
- case '}':
- if (set_volatile == 0)
- error ("internal error: %%} found without a %%{ in assembler pattern");
- else if (--set_volatile == 0)
- fputs ("\n\t#.set\tnovolatile", file);
+ symbol_type = mips_classify_symbolic_expression (op, context);
+ gcc_assert (relocs[symbol_type]);
- break;
+ fputs (relocs[symbol_type], file);
+ output_addr_const (file, mips_strip_unspec_address (op));
+ for (p = relocs[symbol_type]; *p != 0; p++)
+ if (*p == '(')
+ fputc (')', file);
+}
- case '~':
- {
- if (align_labels_log > 0)
- ASM_OUTPUT_ALIGN (file, align_labels_log);
- }
- break;
+/* Print the text for PRINT_OPERAND punctation character CH to FILE.
+ The punctuation characters are:
- default:
- error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
- break;
- }
+ '(' Start a nested ".set noreorder" block.
+ ')' End a nested ".set noreorder" block.
+ '[' Start a nested ".set noat" block.
+ ']' End a nested ".set noat" block.
+ '<' Start a nested ".set nomacro" block.
+ '>' End a nested ".set nomacro" block.
+ '*' Behave like %(%< if generating a delayed-branch sequence.
+ '#' Print a nop if in a ".set noreorder" block.
+ '/' Like '#', but do nothing within a delayed-branch sequence.
+ '?' Print "l" if mips_branch_likely is true
+ '.' Print the name of the register with a hard-wired zero (zero or $0).
+ '@' Print the name of the assembler temporary register (at or $1).
+ '^' Print the name of the pic call-through register (t9 or $25).
+ '+' Print the name of the gp register (usually gp or $28).
+ '$' Print the name of the stack pointer register (sp or $29).
+ '|' Print ".set push; .set mips2" if !ISA_HAS_LL_SC.
+ '-' Print ".set pop" under the same conditions for '|'.
- return;
- }
+ See also mips_init_print_operand_pucnt. */
- if (! op)
+static void
+mips_print_operand_punctuation (FILE *file, int ch)
+{
+ switch (ch)
{
- error ("PRINT_OPERAND null pointer");
- return;
- }
-
- code = GET_CODE (op);
-
- if (letter == 'C')
- switch (code)
- {
- case EQ: fputs ("eq", file); break;
- case NE: fputs ("ne", file); break;
- case GT: fputs ("gt", file); break;
- case GE: fputs ("ge", file); break;
- case LT: fputs ("lt", file); break;
- case LE: fputs ("le", file); break;
- case GTU: fputs ("gtu", file); break;
- case GEU: fputs ("geu", file); break;
- case LTU: fputs ("ltu", file); break;
- case LEU: fputs ("leu", file); break;
- default:
- fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
- }
-
- else if (letter == 'N')
- switch (code)
- {
- case EQ: fputs ("ne", file); break;
- case NE: fputs ("eq", file); break;
- case GT: fputs ("le", file); break;
- case GE: fputs ("lt", file); break;
- case LT: fputs ("ge", file); break;
- case LE: fputs ("gt", file); break;
- case GTU: fputs ("leu", file); break;
- case GEU: fputs ("ltu", file); break;
- case LTU: fputs ("geu", file); break;
- case LEU: fputs ("gtu", file); break;
- default:
- fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
- }
-
- else if (letter == 'F')
- switch (code)
- {
- case EQ: fputs ("c1f", file); break;
- case NE: fputs ("c1t", file); break;
- default:
- fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
- }
+ case '(':
+ if (set_noreorder++ == 0)
+ fputs (".set\tnoreorder\n\t", file);
+ break;
- else if (letter == 'W')
- switch (code)
- {
- case EQ: fputs ("c1t", file); break;
- case NE: fputs ("c1f", file); break;
- default:
- fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
- }
+ case ')':
+ gcc_assert (set_noreorder > 0);
+ if (--set_noreorder == 0)
+ fputs ("\n\t.set\treorder", file);
+ break;
- else if (letter == 'h')
- {
- if (GET_CODE (op) == HIGH)
- op = XEXP (op, 0);
+ case '[':
+ if (set_noat++ == 0)
+ fputs (".set\tnoat\n\t", file);
+ break;
- print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
- }
+ case ']':
+ gcc_assert (set_noat > 0);
+ if (--set_noat == 0)
+ fputs ("\n\t.set\tat", file);
+ break;
- else if (letter == 'R')
- print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
+ case '<':
+ if (set_nomacro++ == 0)
+ fputs (".set\tnomacro\n\t", file);
+ break;
- else if (letter == 'Y')
- {
- if (GET_CODE (op) == CONST_INT
- && ((unsigned HOST_WIDE_INT) INTVAL (op)
- < ARRAY_SIZE (mips_fp_conditions)))
- fputs (mips_fp_conditions[INTVAL (op)], file);
- else
- output_operand_lossage ("invalid %%Y value");
- }
+ case '>':
+ gcc_assert (set_nomacro > 0);
+ if (--set_nomacro == 0)
+ fputs ("\n\t.set\tmacro", file);
+ break;
- else if (letter == 'Z')
- {
- if (ISA_HAS_8CC)
+ case '*':
+ if (final_sequence != 0)
{
- print_operand (file, op, 0);
- fputc (',', file);
+ mips_print_operand_punctuation (file, '(');
+ mips_print_operand_punctuation (file, '<');
}
- }
-
- else if (letter == 'q')
- {
- int regnum;
-
- if (code != REG)
- fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
-
- regnum = REGNO (op);
- if (MD_REG_P (regnum))
- fprintf (file, "$ac0");
- else if (DSP_ACC_REG_P (regnum))
- fprintf (file, "$ac%c", reg_names[regnum][3]);
- else
- fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
- }
+ break;
- else if (code == REG || code == SUBREG)
- {
- register int regnum;
+ case '#':
+ if (set_noreorder != 0)
+ fputs ("\n\tnop", file);
+ break;
- if (code == REG)
- regnum = REGNO (op);
- else
- regnum = true_regnum (op);
+ case '/':
+ /* Print an extra newline so that the delayed insn is separated
+ from the following ones. This looks neater and is consistent
+ with non-nop delayed sequences. */
+ if (set_noreorder != 0 && final_sequence == 0)
+ fputs ("\n\tnop\n", file);
+ break;
- if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
- || (letter == 'L' && WORDS_BIG_ENDIAN)
- || letter == 'D')
- regnum++;
+ case '?':
+ if (mips_branch_likely)
+ putc ('l', file);
+ break;
- fprintf (file, "%s", reg_names[regnum]);
- }
+ case '.':
+ fputs (reg_names[GP_REG_FIRST + 0], file);
+ break;
- else if (code == MEM)
- {
- if (letter == 'D')
- output_address (plus_constant (XEXP (op, 0), 4));
- else
- output_address (XEXP (op, 0));
- }
+ case '@':
+ fputs (reg_names[GP_REG_FIRST + 1], file);
+ break;
- else if (letter == 'x' && GET_CODE (op) == CONST_INT)
- fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
+ case '^':
+ fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
+ break;
- else if (letter == 'X' && GET_CODE(op) == CONST_INT)
- fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
+ case '+':
+ fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
+ break;
- else if (letter == 'd' && GET_CODE(op) == CONST_INT)
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
+ case '$':
+ fputs (reg_names[STACK_POINTER_REGNUM], file);
+ break;
- else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
- fputs (reg_names[GP_REG_FIRST], file);
+ case '|':
+ if (!ISA_HAS_LL_SC)
+ fputs (".set\tpush\n\t.set\tmips2\n\t", file);
+ break;
- else if (letter == 'd' || letter == 'x' || letter == 'X')
- output_operand_lossage ("invalid use of %%d, %%x, or %%X");
+ case '-':
+ if (!ISA_HAS_LL_SC)
+ fputs ("\n\t.set\tpop", file);
+ break;
- else if (letter == 'T' || letter == 't')
- {
- int truth = (code == NE) == (letter == 'T');
- fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
+ default:
+ gcc_unreachable ();
+ break;
}
-
- else if (CONST_GP_P (op))
- fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
-
- else
- output_addr_const (file, mips_strip_unspec_address (op));
}
-
-/* Print symbolic operand OP, which is part of a HIGH or LO_SUM
- in context CONTEXT. RELOCS is the array of relocations to use. */
+/* Initialize mips_print_operand_punct. */
static void
-print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
- const char **relocs)
+mips_init_print_operand_punct (void)
{
- enum mips_symbol_type symbol_type;
const char *p;
- symbol_type = mips_classify_symbolic_expression (op, context);
- if (relocs[symbol_type] == 0)
- fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
-
- fputs (relocs[symbol_type], file);
- output_addr_const (file, mips_strip_unspec_address (op));
- for (p = relocs[symbol_type]; *p != 0; p++)
- if (*p == '(')
- fputc (')', file);
+ for (p = "()[]<>*#/?.@^+$|-"; *p; p++)
+ mips_print_operand_punct[(unsigned char) *p] = true;
}
-\f
-/* Output address operand X to FILE. */
-void
-print_operand_address (FILE *file, rtx x)
+/* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
+ associated with condition CODE. Print the condition part of the
+ opcode to FILE. */
+
+static void
+mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
{
- struct mips_address_info addr;
+ switch (code)
+ {
+ case EQ:
+ case NE:
+ case GT:
+ case GE:
+ case LT:
+ case LE:
+ case GTU:
+ case GEU:
+ case LTU:
+ case LEU:
+ /* Conveniently, the MIPS names for these conditions are the same
+ as their RTL equivalents. */
+ fputs (GET_RTX_NAME (code), file);
+ break;
- if (mips_classify_address (&addr, x, word_mode, true))
- switch (addr.type)
- {
- case ADDRESS_REG:
- print_operand (file, addr.offset, 0);
- fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
- return;
+ default:
+ output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
+ break;
+ }
+}
- case ADDRESS_LO_SUM:
- print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
- mips_lo_relocs);
- fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
- return;
+/* Likewise floating-point branches. */
- case ADDRESS_CONST_INT:
- output_addr_const (file, x);
- fprintf (file, "(%s)", reg_names[0]);
- return;
+static void
+mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
+{
+ switch (code)
+ {
+ case EQ:
+ fputs ("c1f", file);
+ break;
- case ADDRESS_SYMBOLIC:
- output_addr_const (file, mips_strip_unspec_address (x));
- return;
- }
- gcc_unreachable ();
+ case NE:
+ fputs ("c1t", file);
+ break;
+
+ default:
+ output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
+ break;
+ }
}
-\f
-/* When using assembler macros, keep track of all of small-data externs
- so that mips_file_end can emit the appropriate declarations for them.
- In most cases it would be safe (though pointless) to emit .externs
- for other symbols too. One exception is when an object is within
- the -G limit but declared by the user to be in a section other
- than .sbss or .sdata. */
+/* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
+
+ 'X' Print CONST_INT OP in hexadecimal format.
+ 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
+ 'd' Print CONST_INT OP in decimal.
+ 'h' Print the high-part relocation associated with OP, after stripping
+ any outermost HIGH.
+ 'R' Print the low-part relocation associated with OP.
+ 'C' Print the integer branch condition for comparison OP.
+ 'N' Print the inverse of the integer branch condition for comparison OP.
+ 'F' Print the FPU branch condition for comparison OP.
+ 'W' Print the inverse of the FPU branch condition for comparison OP.
+ 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
+ 'z' for (eq:?I ...), 'n' for (ne:?I ...).
+ 't' Like 'T', but with the EQ/NE cases reversed
+ 'Y' Print mips_fp_conditions[INTVAL (OP)]
+ 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
+ 'q' Print a DSP accumulator register.
+ 'D' Print the second part of a double-word register or memory operand.
+ 'L' Print the low-order register in a double-word register operand.
+ 'M' Print high-order register in a double-word register operand.
+ 'z' Print $0 if OP is zero, otherwise print OP normally. */
void
-mips_output_external (FILE *file, tree decl, const char *name)
+mips_print_operand (FILE *file, rtx op, int letter)
{
- default_elf_asm_output_external (file, decl, name);
+ enum rtx_code code;
- /* We output the name if and only if TREE_SYMBOL_REFERENCED is
- set in order to avoid putting out names that are never really
- used. */
- if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
+ if (PRINT_OPERAND_PUNCT_VALID_P (letter))
{
- if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
- {
- fputs ("\t.extern\t", file);
- assemble_name (file, name);
- fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
- int_size_in_bytes (TREE_TYPE (decl)));
- }
- else if (TARGET_IRIX
- && mips_abi == ABI_32
- && TREE_CODE (decl) == FUNCTION_DECL)
- {
- /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
- `.global name .text' directive for every used but
- undefined function. If we don't, the linker may perform
- an optimization (skipping over the insns that set $gp)
- when it is unsafe. */
- fputs ("\t.globl ", file);
- assemble_name (file, name);
- fputs (" .text\n", file);
- }
+ mips_print_operand_punctuation (file, letter);
+ return;
}
-}
-\f
-/* Emit a new filename to a stream. If we are smuggling stabs, try to
- put out a MIPS ECOFF file and a stab. */
-void
-mips_output_filename (FILE *stream, const char *name)
-{
+ gcc_assert (op);
+ code = GET_CODE (op);
- /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
- directives. */
- if (write_symbols == DWARF2_DEBUG)
- return;
- else if (mips_output_filename_first_time)
+ switch (letter)
{
- mips_output_filename_first_time = 0;
- num_source_filenames += 1;
- current_function_file = name;
- fprintf (stream, "\t.file\t%d ", num_source_filenames);
- output_quoted_string (stream, name);
- putc ('\n', stream);
- }
+ case 'X':
+ if (GET_CODE (op) == CONST_INT)
+ fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
+ else
+ output_operand_lossage ("invalid use of '%%%c'", letter);
+ break;
- /* If we are emitting stabs, let dbxout.c handle this (except for
- the mips_output_filename_first_time case). */
- else if (write_symbols == DBX_DEBUG)
- return;
+ case 'x':
+ if (GET_CODE (op) == CONST_INT)
+ fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
+ else
+ output_operand_lossage ("invalid use of '%%%c'", letter);
+ break;
- else if (name != current_function_file
- && strcmp (name, current_function_file) != 0)
- {
- num_source_filenames += 1;
- current_function_file = name;
- fprintf (stream, "\t.file\t%d ", num_source_filenames);
- output_quoted_string (stream, name);
- putc ('\n', stream);
- }
-}
-\f
-/* Output an ASCII string, in a space-saving way. PREFIX is the string
- that should be written before the opening quote, such as "\t.ascii\t"
- for real string data or "\t# " for a comment. */
+ case 'd':
+ if (GET_CODE (op) == CONST_INT)
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
+ else
+ output_operand_lossage ("invalid use of '%%%c'", letter);
+ break;
-void
-mips_output_ascii (FILE *stream, const char *string_param, size_t len,
- const char *prefix)
-{
- size_t i;
- int cur_pos = 17;
- register const unsigned char *string =
- (const unsigned char *)string_param;
+ case 'h':
+ if (code == HIGH)
+ op = XEXP (op, 0);
+ mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
+ break;
- fprintf (stream, "%s\"", prefix);
- for (i = 0; i < len; i++)
- {
- register int c = string[i];
+ case 'R':
+ mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
+ break;
- if (ISPRINT (c))
- {
- if (c == '\\' || c == '\"')
- {
- putc ('\\', stream);
- cur_pos++;
- }
- putc (c, stream);
- cur_pos++;
- }
- else
- {
- fprintf (stream, "\\%03o", c);
- cur_pos += 4;
- }
+ case 'C':
+ mips_print_int_branch_condition (file, code, letter);
+ break;
- if (cur_pos > 72 && i+1 < len)
- {
- cur_pos = 17;
- fprintf (stream, "\"\n%s\"", prefix);
- }
- }
- fprintf (stream, "\"\n");
-}
-\f
-/* Implement TARGET_ASM_FILE_START. */
+ case 'N':
+ mips_print_int_branch_condition (file, reverse_condition (code), letter);
+ break;
-static void
-mips_file_start (void)
-{
- default_file_start ();
+ case 'F':
+ mips_print_float_branch_condition (file, code, letter);
+ break;
- if (!TARGET_IRIX)
- {
- /* Generate a special section to describe the ABI switches used to
- produce the resultant binary. This used to be done by the assembler
- setting bits in the ELF header's flags field, but we have run out of
- bits. GDB needs this information in order to be able to correctly
- debug these binaries. See the function mips_gdbarch_init() in
- gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
- causes unnecessary IRIX 6 ld warnings. */
- const char * abi_string = NULL;
+ case 'W':
+ mips_print_float_branch_condition (file, reverse_condition (code),
+ letter);
+ break;
+
+ case 'T':
+ case 't':
+ {
+ int truth = (code == NE) == (letter == 'T');
+ fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
+ }
+ break;
- switch (mips_abi)
+ case 'Y':
+ if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
+ fputs (mips_fp_conditions[UINTVAL (op)], file);
+ else
+ output_operand_lossage ("'%%%c' is not a valid operand prefix",
+ letter);
+ break;
+
+ case 'Z':
+ if (ISA_HAS_8CC)
{
- case ABI_32: abi_string = "abi32"; break;
- case ABI_N32: abi_string = "abiN32"; break;
- case ABI_64: abi_string = "abi64"; break;
- case ABI_O64: abi_string = "abiO64"; break;
- case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
- default:
- gcc_unreachable ();
+ mips_print_operand (file, op, 0);
+ fputc (',', file);
}
- /* Note - we use fprintf directly rather than calling switch_to_section
- because in this way we can avoid creating an allocated section. We
- do not want this section to take up any space in the running
- executable. */
- fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
-
- /* There is no ELF header flag to distinguish long32 forms of the
- EABI from long64 forms. Emit a special section to help tools
- such as GDB. Do the same for o64, which is sometimes used with
- -mlong64. */
- if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
- fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
- TARGET_LONG64 ? 64 : 32);
+ break;
- /* Restore the default section. */
- fprintf (asm_out_file, "\t.previous\n");
+ case 'q':
+ if (code == REG && MD_REG_P (REGNO (op)))
+ fprintf (file, "$ac0");
+ else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
+ fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
+ else
+ output_operand_lossage ("invalid use of '%%%c'", letter);
+ break;
-#ifdef HAVE_AS_GNU_ATTRIBUTE
- fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
- TARGET_HARD_FLOAT_ABI ? (TARGET_DOUBLE_FLOAT ? 1 : 2) : 3);
-#endif
- }
+ default:
+ switch (code)
+ {
+ case REG:
+ {
+ unsigned int regno = REGNO (op);
+ if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
+ || (letter == 'L' && TARGET_BIG_ENDIAN)
+ || letter == 'D')
+ regno++;
+ fprintf (file, "%s", reg_names[regno]);
+ }
+ break;
- /* Generate the pseudo ops that System V.4 wants. */
- if (TARGET_ABICALLS)
- fprintf (asm_out_file, "\t.abicalls\n");
+ case MEM:
+ if (letter == 'D')
+ output_address (plus_constant (XEXP (op, 0), 4));
+ else
+ output_address (XEXP (op, 0));
+ break;
- if (flag_verbose_asm)
- fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
- ASM_COMMENT_START,
- mips_section_threshold, mips_arch_info->name, mips_isa);
+ default:
+ if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
+ fputs (reg_names[GP_REG_FIRST], file);
+ else if (CONST_GP_P (op))
+ fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
+ else
+ output_addr_const (file, mips_strip_unspec_address (op));
+ break;
+ }
+ }
}
-#ifdef BSS_SECTION_ASM_OP
-/* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
- in the use of sbss. */
+/* Output address operand X to FILE. */
void
-mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
- unsigned HOST_WIDE_INT size, int align)
+mips_print_operand_address (FILE *file, rtx x)
{
- extern tree last_assemble_variable_decl;
+ struct mips_address_info addr;
- if (mips_in_small_data_p (decl))
- switch_to_section (get_named_section (NULL, ".sbss", 0));
- else
- switch_to_section (bss_section);
- ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
- last_assemble_variable_decl = decl;
- ASM_DECLARE_OBJECT_NAME (stream, name, decl);
- ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
+ if (mips_classify_address (&addr, x, word_mode, true))
+ switch (addr.type)
+ {
+ case ADDRESS_REG:
+ mips_print_operand (file, addr.offset, 0);
+ fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
+ return;
+
+ case ADDRESS_LO_SUM:
+ mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
+ mips_lo_relocs);
+ fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
+ return;
+
+ case ADDRESS_CONST_INT:
+ output_addr_const (file, x);
+ fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
+ return;
+
+ case ADDRESS_SYMBOLIC:
+ output_addr_const (file, mips_strip_unspec_address (x));
+ return;
+ }
+ gcc_unreachable ();
}
-#endif
\f
-/* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
- elfos.h version, but we also need to handle -muninit-const-in-rodata. */
+/* Implement TARGET_ENCODE_SECTION_INFO. */
-void
-mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
- unsigned HOST_WIDE_INT size,
- unsigned int align)
+static void
+mips_encode_section_info (tree decl, rtx rtl, int first)
{
- /* If the target wants uninitialized const declarations in
- .rdata then don't put them in .comm. */
- if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
- && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
- && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
+ default_encode_section_info (decl, rtl, first);
+
+ if (TREE_CODE (decl) == FUNCTION_DECL)
{
- if (TREE_PUBLIC (decl) && DECL_NAME (decl))
- targetm.asm_out.globalize_label (stream, name);
+ rtx symbol = XEXP (rtl, 0);
+ tree type = TREE_TYPE (decl);
- switch_to_section (readonly_data_section);
- ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
- mips_declare_object (stream, name, "",
- ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
- size);
+ /* Encode whether the symbol is short or long. */
+ if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
+ || mips_far_type_p (type))
+ SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
}
- else
- mips_declare_common_object (stream, name, "\n\t.comm\t",
- size, align, true);
}
-/* Declare a common object of SIZE bytes using asm directive INIT_STRING.
- NAME is the name of the object and ALIGN is the required alignment
- in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
- alignment argument. */
+/* Implement TARGET_SELECT_RTX_SECTION. */
-void
-mips_declare_common_object (FILE *stream, const char *name,
- const char *init_string,
- unsigned HOST_WIDE_INT size,
- unsigned int align, bool takes_alignment_p)
+static section *
+mips_select_rtx_section (enum machine_mode mode, rtx x,
+ unsigned HOST_WIDE_INT align)
{
- if (!takes_alignment_p)
- {
- size += (align / BITS_PER_UNIT) - 1;
- size -= size % (align / BITS_PER_UNIT);
- mips_declare_object (stream, name, init_string,
- "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
- }
- else
- mips_declare_object (stream, name, init_string,
- "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
- size, align / BITS_PER_UNIT);
+ /* ??? Consider using mergeable small data sections. */
+ if (mips_rtx_constant_in_small_data_p (mode))
+ return get_named_section (NULL, ".sdata", 0);
+
+ return default_elf_select_rtx_section (mode, x, align);
}
-/* Emit either a label, .comm, or .lcomm directive. When using assembler
- macros, mark the symbol as written so that mips_file_end won't emit an
- .extern for it. STREAM is the output file, NAME is the name of the
- symbol, INIT_STRING is the string that should be written before the
- symbol and FINAL_STRING is the string that should be written after it.
- FINAL_STRING is a printf() format that consumes the remaining arguments. */
+/* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
-void
-mips_declare_object (FILE *stream, const char *name, const char *init_string,
- const char *final_string, ...)
-{
- va_list ap;
+ The complication here is that, with the combination TARGET_ABICALLS
+ && !TARGET_GPWORD, jump tables will use absolute addresses, and should
+ therefore not be included in the read-only part of a DSO. Handle such
+ cases by selecting a normal data section instead of a read-only one.
+ The logic apes that in default_function_rodata_section. */
- fputs (init_string, stream);
- assemble_name (stream, name);
- va_start (ap, final_string);
- vfprintf (stream, final_string, ap);
- va_end (ap);
+static section *
+mips_function_rodata_section (tree decl)
+{
+ if (!TARGET_ABICALLS || TARGET_GPWORD)
+ return default_function_rodata_section (decl);
- if (!TARGET_EXPLICIT_RELOCS)
+ if (decl && DECL_SECTION_NAME (decl))
{
- tree name_tree = get_identifier (name);
- TREE_ASM_WRITTEN (name_tree) = 1;
- }
-}
-
-#ifdef ASM_OUTPUT_SIZE_DIRECTIVE
-extern int size_directive_output;
-
-/* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
- definitions except that it uses mips_declare_object() to emit the label. */
+ const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
+ if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
+ {
+ char *rname = ASTRDUP (name);
+ rname[14] = 'd';
+ return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
+ }
+ else if (flag_function_sections
+ && flag_data_sections
+ && strncmp (name, ".text.", 6) == 0)
+ {
+ char *rname = ASTRDUP (name);
+ memcpy (rname + 1, "data", 4);
+ return get_section (rname, SECTION_WRITE, decl);
+ }
+ }
+ return data_section;
+}
-void
-mips_declare_object_name (FILE *stream, const char *name,
- tree decl ATTRIBUTE_UNUSED)
+/* Implement TARGET_IN_SMALL_DATA_P. */
+
+static bool
+mips_in_small_data_p (const_tree decl)
{
-#ifdef ASM_OUTPUT_TYPE_DIRECTIVE
- ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
-#endif
+ unsigned HOST_WIDE_INT size;
- size_directive_output = 0;
- if (!flag_inhibit_size_directive && DECL_SIZE (decl))
+ if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
+ return false;
+
+ /* We don't yet generate small-data references for -mabicalls
+ or VxWorks RTP code. See the related -G handling in
+ mips_override_options. */
+ if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
+ return false;
+
+ if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
{
- HOST_WIDE_INT size;
+ const char *name;
- size_directive_output = 1;
- size = int_size_in_bytes (TREE_TYPE (decl));
- ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
- }
+ /* Reject anything that isn't in a known small-data section. */
+ name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
+ if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
+ return false;
- mips_declare_object (stream, name, "", ":\n");
-}
+ /* If a symbol is defined externally, the assembler will use the
+ usual -G rules when deciding how to implement macros. */
+ if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
+ return true;
+ }
+ else if (TARGET_EMBEDDED_DATA)
+ {
+ /* Don't put constants into the small data section: we want them
+ to be in ROM rather than RAM. */
+ if (TREE_CODE (decl) != VAR_DECL)
+ return false;
-/* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
+ if (TREE_READONLY (decl)
+ && !TREE_SIDE_EFFECTS (decl)
+ && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
+ return false;
+ }
-void
-mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
-{
- const char *name;
+ /* Enforce -mlocal-sdata. */
+ if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
+ return false;
- name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
- if (!flag_inhibit_size_directive
- && DECL_SIZE (decl) != 0
- && !at_end && top_level
- && DECL_INITIAL (decl) == error_mark_node
- && !size_directive_output)
+ /* Enforce -mextern-sdata. */
+ if (!TARGET_EXTERN_SDATA && DECL_P (decl))
{
- HOST_WIDE_INT size;
-
- size_directive_output = 1;
- size = int_size_in_bytes (TREE_TYPE (decl));
- ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
+ if (DECL_EXTERNAL (decl))
+ return false;
+ if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
+ return false;
}
+
+ /* We have traditionally not treated zero-sized objects as small data,
+ so this is now effectively part of the ABI. */
+ size = int_size_in_bytes (TREE_TYPE (decl));
+ return size > 0 && size <= mips_small_data_threshold;
}
-#endif
-\f
-/* Return true if X in context CONTEXT is a small data address that can
- be rewritten as a LO_SUM. */
+
+/* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
+ anchors for small data: the GP register acts as an anchor in that
+ case. We also don't want to use them for PC-relative accesses,
+ where the PC acts as an anchor. */
static bool
-mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
+mips_use_anchors_for_symbol_p (const_rtx symbol)
{
- enum mips_symbol_type symbol_type;
+ switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
+ {
+ case SYMBOL_PC_RELATIVE:
+ case SYMBOL_GP_RELATIVE:
+ return false;
- return (TARGET_EXPLICIT_RELOCS
- && mips_symbolic_constant_p (x, context, &symbol_type)
- && symbol_type == SYMBOL_GP_RELATIVE);
+ default:
+ return default_use_anchors_for_symbol_p (symbol);
+ }
}
+\f
+/* The MIPS debug format wants all automatic variables and arguments
+ to be in terms of the virtual frame pointer (stack pointer before
+ any adjustment in the function), while the MIPS 3.0 linker wants
+ the frame pointer to be the stack pointer after the initial
+ adjustment. So, we do the adjustment here. The arg pointer (which
+ is eliminated) points to the virtual frame pointer, while the frame
+ pointer (which may be eliminated) points to the stack pointer after
+ the initial adjustments. */
-
-/* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
- containing MEM, or null if none. */
-
-static int
-mips_small_data_pattern_1 (rtx *loc, void *data)
+HOST_WIDE_INT
+mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
{
- enum mips_symbol_context context;
+ rtx offset2 = const0_rtx;
+ rtx reg = eliminate_constant_term (addr, &offset2);
- if (GET_CODE (*loc) == LO_SUM)
- return -1;
+ if (offset == 0)
+ offset = INTVAL (offset2);
- if (MEM_P (*loc))
+ if (reg == stack_pointer_rtx
+ || reg == frame_pointer_rtx
+ || reg == hard_frame_pointer_rtx)
{
- if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
- return 1;
- return -1;
+ offset -= cfun->machine->frame.total_size;
+ if (reg == hard_frame_pointer_rtx)
+ offset += cfun->machine->frame.hard_frame_pointer_offset;
}
- context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
- return mips_rewrite_small_data_p (*loc, context);
-}
-
-/* Return true if OP refers to small data symbols directly, not through
- a LO_SUM. */
+ /* sdbout_parms does not want this to crash for unrecognized cases. */
+#if 0
+ else if (reg != arg_pointer_rtx)
+ fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
+ addr);
+#endif
-bool
-mips_small_data_pattern_p (rtx op)
-{
- return for_each_rtx (&op, mips_small_data_pattern_1, 0);
+ return offset;
}
\f
-/* A for_each_rtx callback, used by mips_rewrite_small_data.
- DATA is the containing MEM, or null if none. */
+/* Implement ASM_OUTPUT_EXTERNAL. */
-static int
-mips_rewrite_small_data_1 (rtx *loc, void *data)
+void
+mips_output_external (FILE *file, tree decl, const char *name)
{
- enum mips_symbol_context context;
+ default_elf_asm_output_external (file, decl, name);
- if (MEM_P (*loc))
+ /* We output the name if and only if TREE_SYMBOL_REFERENCED is
+ set in order to avoid putting out names that are never really
+ used. */
+ if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
{
- for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
- return -1;
+ if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
+ {
+ /* When using assembler macros, emit .extern directives for
+ all small-data externs so that the assembler knows how
+ big they are.
+
+ In most cases it would be safe (though pointless) to emit
+ .externs for other symbols too. One exception is when an
+ object is within the -G limit but declared by the user to
+ be in a section other than .sbss or .sdata. */
+ fputs ("\t.extern\t", file);
+ assemble_name (file, name);
+ fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
+ int_size_in_bytes (TREE_TYPE (decl)));
+ }
+ else if (TARGET_IRIX
+ && mips_abi == ABI_32
+ && TREE_CODE (decl) == FUNCTION_DECL)
+ {
+ /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
+ `.global name .text' directive for every used but
+ undefined function. If we don't, the linker may perform
+ an optimization (skipping over the insns that set $gp)
+ when it is unsafe. */
+ fputs ("\t.globl ", file);
+ assemble_name (file, name);
+ fputs (" .text\n", file);
+ }
}
-
- context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
- if (mips_rewrite_small_data_p (*loc, context))
- *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
-
- if (GET_CODE (*loc) == LO_SUM)
- return -1;
-
- return 0;
}
-/* If possible, rewrite OP so that it refers to small data using
- explicit relocations. */
+/* Implement ASM_OUTPUT_SOURCE_FILENAME. */
-rtx
-mips_rewrite_small_data (rtx op)
+void
+mips_output_filename (FILE *stream, const char *name)
{
- op = copy_insn (op);
- for_each_rtx (&op, mips_rewrite_small_data_1, 0);
- return op;
+ /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
+ directives. */
+ if (write_symbols == DWARF2_DEBUG)
+ return;
+ else if (mips_output_filename_first_time)
+ {
+ mips_output_filename_first_time = 0;
+ num_source_filenames += 1;
+ current_function_file = name;
+ fprintf (stream, "\t.file\t%d ", num_source_filenames);
+ output_quoted_string (stream, name);
+ putc ('\n', stream);
+ }
+ /* If we are emitting stabs, let dbxout.c handle this (except for
+ the mips_output_filename_first_time case). */
+ else if (write_symbols == DBX_DEBUG)
+ return;
+ else if (name != current_function_file
+ && strcmp (name, current_function_file) != 0)
+ {
+ num_source_filenames += 1;
+ current_function_file = name;
+ fprintf (stream, "\t.file\t%d ", num_source_filenames);
+ output_quoted_string (stream, name);
+ putc ('\n', stream);
+ }
}
-\f
-/* Return true if the current function has an insn that implicitly
- refers to $gp. */
-static bool
-mips_function_has_gp_insn (void)
+/* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
+
+static void ATTRIBUTE_UNUSED
+mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
{
- /* Don't bother rechecking if we found one last time. */
- if (!cfun->machine->has_gp_insn_p)
+ switch (size)
{
- rtx insn;
+ case 4:
+ fputs ("\t.dtprelword\t", file);
+ break;
- push_topmost_sequence ();
- for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
- if (INSN_P (insn)
- && GET_CODE (PATTERN (insn)) != USE
- && GET_CODE (PATTERN (insn)) != CLOBBER
- && (get_attr_got (insn) != GOT_UNSET
- || small_data_pattern (PATTERN (insn), VOIDmode)))
- break;
- pop_topmost_sequence ();
+ case 8:
+ fputs ("\t.dtpreldword\t", file);
+ break;
- cfun->machine->has_gp_insn_p = (insn != 0);
+ default:
+ gcc_unreachable ();
}
- return cfun->machine->has_gp_insn_p;
+ output_addr_const (file, x);
+ fputs ("+0x8000", file);
}
+/* Implement TARGET_DWARF_REGISTER_SPAN. */
-/* Return the register that should be used as the global pointer
- within this function. Return 0 if the function doesn't need
- a global pointer. */
-
-static unsigned int
-mips_global_pointer (void)
+static rtx
+mips_dwarf_register_span (rtx reg)
{
- unsigned int regno;
-
- /* $gp is always available unless we're using a GOT. */
- if (!TARGET_USE_GOT)
- return GLOBAL_POINTER_REGNUM;
-
- /* We must always provide $gp when it is used implicitly. */
- if (!TARGET_EXPLICIT_RELOCS)
- return GLOBAL_POINTER_REGNUM;
-
- /* FUNCTION_PROFILER includes a jal macro, so we need to give it
- a valid gp. */
- if (current_function_profile)
- return GLOBAL_POINTER_REGNUM;
+ rtx high, low;
+ enum machine_mode mode;
- /* If the function has a nonlocal goto, $gp must hold the correct
- global pointer for the target function. */
- if (current_function_has_nonlocal_goto)
- return GLOBAL_POINTER_REGNUM;
+ /* By default, GCC maps increasing register numbers to increasing
+ memory locations, but paired FPRs are always little-endian,
+ regardless of the prevailing endianness. */
+ mode = GET_MODE (reg);
+ if (FP_REG_P (REGNO (reg))
+ && TARGET_BIG_ENDIAN
+ && MAX_FPRS_PER_FMT > 1
+ && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
+ {
+ gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
+ high = mips_subword (reg, true);
+ low = mips_subword (reg, false);
+ return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
+ }
- /* If the gp is never referenced, there's no need to initialize it.
- Note that reload can sometimes introduce constant pool references
- into a function that otherwise didn't need them. For example,
- suppose we have an instruction like:
+ return NULL_RTX;
+}
- (set (reg:DF R1) (float:DF (reg:SI R2)))
+/* Implement ASM_OUTPUT_ASCII. */
- If R2 turns out to be constant such as 1, the instruction may have a
- REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
- using this constant if R2 doesn't get allocated to a register.
+void
+mips_output_ascii (FILE *stream, const char *string, size_t len)
+{
+ size_t i;
+ int cur_pos;
- In cases like these, reload will have added the constant to the pool
- but no instruction will yet refer to it. */
- if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM)
- && !current_function_uses_const_pool
- && !mips_function_has_gp_insn ())
- return 0;
+ cur_pos = 17;
+ fprintf (stream, "\t.ascii\t\"");
+ for (i = 0; i < len; i++)
+ {
+ int c;
- /* We need a global pointer, but perhaps we can use a call-clobbered
- register instead of $gp. */
- if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
- for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
- if (!df_regs_ever_live_p (regno)
- && call_used_regs[regno]
- && !fixed_regs[regno]
- && regno != PIC_FUNCTION_ADDR_REGNUM)
- return regno;
+ c = (unsigned char) string[i];
+ if (ISPRINT (c))
+ {
+ if (c == '\\' || c == '\"')
+ {
+ putc ('\\', stream);
+ cur_pos++;
+ }
+ putc (c, stream);
+ cur_pos++;
+ }
+ else
+ {
+ fprintf (stream, "\\%03o", c);
+ cur_pos += 4;
+ }
- return GLOBAL_POINTER_REGNUM;
+ if (cur_pos > 72 && i+1 < len)
+ {
+ cur_pos = 17;
+ fprintf (stream, "\"\n\t.ascii\t\"");
+ }
+ }
+ fprintf (stream, "\"\n");
}
+/* Emit either a label, .comm, or .lcomm directive. When using assembler
+ macros, mark the symbol as written so that mips_asm_output_external
+ won't emit an .extern for it. STREAM is the output file, NAME is the
+ name of the symbol, INIT_STRING is the string that should be written
+ before the symbol and FINAL_STRING is the string that should be
+ written after it. FINAL_STRING is a printf format that consumes the
+ remaining arguments. */
-/* Return true if the function return value MODE will get returned in a
- floating-point register. */
-
-static bool
-mips_return_mode_in_fpr_p (enum machine_mode mode)
+void
+mips_declare_object (FILE *stream, const char *name, const char *init_string,
+ const char *final_string, ...)
{
- return ((GET_MODE_CLASS (mode) == MODE_FLOAT
- || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
- || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
- && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
-}
+ va_list ap;
-/* Return a two-character string representing a function floating-point
- return mode, used to name MIPS16 function stubs. */
+ fputs (init_string, stream);
+ assemble_name (stream, name);
+ va_start (ap, final_string);
+ vfprintf (stream, final_string, ap);
+ va_end (ap);
-static const char *
-mips16_call_stub_mode_suffix (enum machine_mode mode)
-{
- if (mode == SFmode)
- return "sf";
- else if (mode == DFmode)
- return "df";
- else if (mode == SCmode)
- return "sc";
- else if (mode == DCmode)
- return "dc";
- else if (mode == V2SFmode)
- return "df";
- else
- gcc_unreachable ();
+ if (!TARGET_EXPLICIT_RELOCS)
+ {
+ tree name_tree = get_identifier (name);
+ TREE_ASM_WRITTEN (name_tree) = 1;
+ }
}
-/* Return true if the current function returns its value in a floating-point
- register in MIPS16 mode. */
+/* Declare a common object of SIZE bytes using asm directive INIT_STRING.
+ NAME is the name of the object and ALIGN is the required alignment
+ in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
+ alignment argument. */
-static bool
-mips16_cfun_returns_in_fpr_p (void)
+void
+mips_declare_common_object (FILE *stream, const char *name,
+ const char *init_string,
+ unsigned HOST_WIDE_INT size,
+ unsigned int align, bool takes_alignment_p)
{
- tree return_type = DECL_RESULT (current_function_decl);
- return (TARGET_MIPS16
- && TARGET_HARD_FLOAT_ABI
- && !aggregate_value_p (return_type, current_function_decl)
- && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
+ if (!takes_alignment_p)
+ {
+ size += (align / BITS_PER_UNIT) - 1;
+ size -= size % (align / BITS_PER_UNIT);
+ mips_declare_object (stream, name, init_string,
+ "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
+ }
+ else
+ mips_declare_object (stream, name, init_string,
+ "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
+ size, align / BITS_PER_UNIT);
}
+/* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
+ elfos.h version, but we also need to handle -muninit-const-in-rodata. */
-/* Return true if the current function must save REGNO. */
-
-static bool
-mips_save_reg_p (unsigned int regno)
+void
+mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
+ unsigned HOST_WIDE_INT size,
+ unsigned int align)
{
- /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then
- if we have not chosen a call-clobbered substitute. */
- if (regno == GLOBAL_POINTER_REGNUM)
- return TARGET_CALL_SAVED_GP && cfun->machine->global_pointer == regno;
+ /* If the target wants uninitialized const declarations in
+ .rdata then don't put them in .comm. */
+ if (TARGET_EMBEDDED_DATA
+ && TARGET_UNINIT_CONST_IN_RODATA
+ && TREE_CODE (decl) == VAR_DECL
+ && TREE_READONLY (decl)
+ && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
+ {
+ if (TREE_PUBLIC (decl) && DECL_NAME (decl))
+ targetm.asm_out.globalize_label (stream, name);
- /* Check call-saved registers. */
- if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
- return true;
+ switch_to_section (readonly_data_section);
+ ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
+ mips_declare_object (stream, name, "",
+ ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
+ size);
+ }
+ else
+ mips_declare_common_object (stream, name, "\n\t.comm\t",
+ size, align, true);
+}
- /* Save both registers in an FPR pair if either one is used. This is
- needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
- register to be used without the even register. */
- if (FP_REG_P (regno)
- && MAX_FPRS_PER_FMT == 2
- && df_regs_ever_live_p (regno + 1)
- && !call_used_regs[regno + 1])
- return true;
+#ifdef ASM_OUTPUT_SIZE_DIRECTIVE
+extern int size_directive_output;
- /* We need to save the old frame pointer before setting up a new one. */
- if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
- return true;
+/* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
+ definitions except that it uses mips_declare_object to emit the label. */
- /* We need to save the incoming return address if it is ever clobbered
- within the function. */
- if (regno == GP_REG_FIRST + 31 && df_regs_ever_live_p (regno))
- return true;
+void
+mips_declare_object_name (FILE *stream, const char *name,
+ tree decl ATTRIBUTE_UNUSED)
+{
+#ifdef ASM_OUTPUT_TYPE_DIRECTIVE
+ ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
+#endif
- if (TARGET_MIPS16)
+ size_directive_output = 0;
+ if (!flag_inhibit_size_directive && DECL_SIZE (decl))
{
- /* $18 is a special case in mips16 code. It may be used to call
- a function which returns a floating point value, but it is
- marked in call_used_regs. */
- if (regno == GP_REG_FIRST + 18 && df_regs_ever_live_p (regno))
- return true;
+ HOST_WIDE_INT size;
- /* $31 is also a special case. It will be used to copy a return
- value into the floating point registers if the return value is
- floating point. */
- if (regno == GP_REG_FIRST + 31
- && mips16_cfun_returns_in_fpr_p ())
- return true;
+ size_directive_output = 1;
+ size = int_size_in_bytes (TREE_TYPE (decl));
+ ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
}
- return false;
+ mips_declare_object (stream, name, "", ":\n");
}
-/* Return the index of the lowest X in the range [0, SIZE) for which
- bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
+/* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
-static unsigned int
-mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
- unsigned int size)
+void
+mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
{
- unsigned int i;
+ const char *name;
- for (i = 0; i < size; i++)
- if (BITSET_P (mask, regs[i]))
- break;
+ name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
+ if (!flag_inhibit_size_directive
+ && DECL_SIZE (decl) != 0
+ && !at_end
+ && top_level
+ && DECL_INITIAL (decl) == error_mark_node
+ && !size_directive_output)
+ {
+ HOST_WIDE_INT size;
- return i;
+ size_directive_output = 1;
+ size = int_size_in_bytes (TREE_TYPE (decl));
+ ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
+ }
}
+#endif
+\f
+/* Return the FOO in the name of the ".mdebug.FOO" section associated
+ with the current ABI. */
-/* *MASK_PTR is a mask of general purpose registers and *GP_REG_SIZE_PTR
- is the number of bytes that they occupy. If *MASK_PTR contains REGS[X]
- for some X in [0, SIZE), adjust *MASK_PTR and *GP_REG_SIZE_PTR so that
- the same is true for all indexes (X, SIZE). */
-
-static void
-mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
- unsigned int size, HOST_WIDE_INT *gp_reg_size_ptr)
+static const char *
+mips_mdebug_abi_name (void)
{
- unsigned int i;
-
- i = mips16e_find_first_register (*mask_ptr, regs, size);
- for (i++; i < size; i++)
- if (!BITSET_P (*mask_ptr, regs[i]))
- {
- *gp_reg_size_ptr += GET_MODE_SIZE (gpr_mode);
- *mask_ptr |= 1 << regs[i];
- }
+ switch (mips_abi)
+ {
+ case ABI_32:
+ return "abi32";
+ case ABI_O64:
+ return "abiO64";
+ case ABI_N32:
+ return "abiN32";
+ case ABI_64:
+ return "abiN64";
+ case ABI_EABI:
+ return TARGET_64BIT ? "eabi64" : "eabi32";
+ default:
+ gcc_unreachable ();
+ }
}
-/* Return the bytes needed to compute the frame pointer from the current
- stack pointer. SIZE is the size (in bytes) of the local variables.
-
- MIPS stack frames look like:
-
- Before call After call
- high +-----------------------+ +-----------------------+
- mem. | | | |
- | caller's temps. | | caller's temps. |
- | | | |
- +-----------------------+ +-----------------------+
- | | | |
- | arguments on stack. | | arguments on stack. |
- | | | |
- +-----------------------+ +-----------------------+
- | 4 words to save | | 4 words to save |
- | arguments passed | | arguments passed |
- | in registers, even | | in registers, even |
- | if not passed. | | if not passed. |
- SP->+-----------------------+ VFP->+-----------------------+
- (VFP = SP+fp_sp_offset) | |\
- | fp register save | | fp_reg_size
- | |/
- SP+gp_sp_offset->+-----------------------+
- /| |\
- | | gp register save | | gp_reg_size
- gp_reg_rounded | | |/
- | +-----------------------+
- \| alignment padding |
- +-----------------------+
- | |\
- | local variables | | var_size
- | |/
- +-----------------------+
- | |
- | alloca allocations |
- | |
- +-----------------------+
- /| |
- cprestore_size | | GP save for V.4 abi |
- \| |
- +-----------------------+
- | |\
- | arguments on stack | |
- | | |
- +-----------------------+ |
- | 4 words to save | | args_size
- | arguments passed | |
- | in registers, even | |
- | if not passed. | |
- low | (TARGET_OLDABI only) |/
- memory SP->+-----------------------+
-
-*/
+/* Implement TARGET_ASM_FILE_START. */
-HOST_WIDE_INT
-compute_frame_size (HOST_WIDE_INT size)
+static void
+mips_file_start (void)
{
- unsigned int regno;
- HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
- HOST_WIDE_INT var_size; /* # bytes that variables take up */
- HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
- HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
- HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
- HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
- HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
- unsigned int mask; /* mask of saved gp registers */
- unsigned int fmask; /* mask of saved fp registers */
-
- cfun->machine->global_pointer = mips_global_pointer ();
-
- gp_reg_size = 0;
- fp_reg_size = 0;
- mask = 0;
- fmask = 0;
- var_size = MIPS_STACK_ALIGN (size);
- args_size = current_function_outgoing_args_size;
- cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
-
- /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
- functions. If the function has local variables, we're committed
- to allocating it anyway. Otherwise reclaim it here. */
- if (var_size == 0 && current_function_is_leaf)
- cprestore_size = args_size = 0;
-
- /* The MIPS 3.0 linker does not like functions that dynamically
- allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
- looks like we are trying to create a second frame pointer to the
- function, so allocate some stack space to make it happy. */
-
- if (args_size == 0 && current_function_calls_alloca)
- args_size = 4 * UNITS_PER_WORD;
-
- total_size = var_size + args_size + cprestore_size;
-
- /* Calculate space needed for gp registers. */
- for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
- if (mips_save_reg_p (regno))
- {
- gp_reg_size += GET_MODE_SIZE (gpr_mode);
- mask |= 1 << (regno - GP_REG_FIRST);
- }
-
- /* We need to restore these for the handler. */
- if (current_function_calls_eh_return)
- {
- unsigned int i;
- for (i = 0; ; ++i)
- {
- regno = EH_RETURN_DATA_REGNO (i);
- if (regno == INVALID_REGNUM)
- break;
- gp_reg_size += GET_MODE_SIZE (gpr_mode);
- mask |= 1 << (regno - GP_REG_FIRST);
- }
- }
-
- /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
- $a3-$a0 and $s2-$s8. If we save one register in the range, we must
- save all later registers too. */
- if (GENERATE_MIPS16E_SAVE_RESTORE)
- {
- mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
- ARRAY_SIZE (mips16e_s2_s8_regs), &gp_reg_size);
- mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
- ARRAY_SIZE (mips16e_a0_a3_regs), &gp_reg_size);
- }
+ default_file_start ();
- /* This loop must iterate over the same space as its companion in
- mips_for_each_saved_reg. */
- for (regno = (FP_REG_LAST - MAX_FPRS_PER_FMT + 1);
- regno >= FP_REG_FIRST;
- regno -= MAX_FPRS_PER_FMT)
+ /* Generate a special section to describe the ABI switches used to
+ produce the resultant binary. This is unnecessary on IRIX and
+ causes unwanted warnings from the native linker. */
+ if (!TARGET_IRIX)
{
- if (mips_save_reg_p (regno))
- {
- fp_reg_size += MAX_FPRS_PER_FMT * UNITS_PER_FPREG;
- fmask |= ((1 << MAX_FPRS_PER_FMT) - 1) << (regno - FP_REG_FIRST);
- }
- }
+ /* Record the ABI itself. Modern versions of binutils encode
+ this information in the ELF header flags, but GDB needs the
+ information in order to correctly debug binaries produced by
+ older binutils. See the function mips_gdbarch_init in
+ gdb/mips-tdep.c. */
+ fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
+ mips_mdebug_abi_name ());
- gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
- total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
-
- /* Add in the space required for saving incoming register arguments. */
- total_size += current_function_pretend_args_size;
- total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
-
- /* Save other computed information. */
- cfun->machine->frame.total_size = total_size;
- cfun->machine->frame.var_size = var_size;
- cfun->machine->frame.args_size = args_size;
- cfun->machine->frame.cprestore_size = cprestore_size;
- cfun->machine->frame.gp_reg_size = gp_reg_size;
- cfun->machine->frame.fp_reg_size = fp_reg_size;
- cfun->machine->frame.mask = mask;
- cfun->machine->frame.fmask = fmask;
- cfun->machine->frame.initialized = reload_completed;
- cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
- cfun->machine->frame.num_fp = (fp_reg_size
- / (MAX_FPRS_PER_FMT * UNITS_PER_FPREG));
-
- if (mask)
- {
- HOST_WIDE_INT offset;
+ /* There is no ELF header flag to distinguish long32 forms of the
+ EABI from long64 forms. Emit a special section to help tools
+ such as GDB. Do the same for o64, which is sometimes used with
+ -mlong64. */
+ if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
+ fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
+ "\t.previous\n", TARGET_LONG64 ? 64 : 32);
- if (GENERATE_MIPS16E_SAVE_RESTORE)
- /* MIPS16e SAVE and RESTORE instructions require the GP save area
- to be aligned at the high end with any padding at the low end.
- It is only safe to use this calculation for o32, where we never
- have pretend arguments, and where any varargs will be saved in
- the caller-allocated area rather than at the top of the frame. */
- offset = (total_size - GET_MODE_SIZE (gpr_mode));
- else
- offset = (args_size + cprestore_size + var_size
- + gp_reg_size - GET_MODE_SIZE (gpr_mode));
- cfun->machine->frame.gp_sp_offset = offset;
- cfun->machine->frame.gp_save_offset = offset - total_size;
- }
- else
- {
- cfun->machine->frame.gp_sp_offset = 0;
- cfun->machine->frame.gp_save_offset = 0;
+#ifdef HAVE_AS_GNU_ATTRIBUTE
+ fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
+ (TARGET_HARD_FLOAT_ABI
+ ? (TARGET_DOUBLE_FLOAT
+ ? ((!TARGET_64BIT && TARGET_FLOAT64) ? 4 : 1) : 2) : 3));
+#endif
}
- if (fmask)
- {
- HOST_WIDE_INT offset;
-
- offset = (args_size + cprestore_size + var_size
- + gp_reg_rounded + fp_reg_size
- - MAX_FPRS_PER_FMT * UNITS_PER_FPREG);
- cfun->machine->frame.fp_sp_offset = offset;
- cfun->machine->frame.fp_save_offset = offset - total_size;
- }
- else
- {
- cfun->machine->frame.fp_sp_offset = 0;
- cfun->machine->frame.fp_save_offset = 0;
- }
+ /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
+ if (TARGET_ABICALLS)
+ fprintf (asm_out_file, "\t.abicalls\n");
- /* Ok, we're done. */
- return total_size;
+ if (flag_verbose_asm)
+ fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
+ ASM_COMMENT_START,
+ mips_small_data_threshold, mips_arch_info->name, mips_isa);
}
\f
-/* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
- pointer or argument pointer. TO is either the stack pointer or
- hard frame pointer. */
+/* Make the last instruction frame-related and note that it performs
+ the operation described by FRAME_PATTERN. */
-HOST_WIDE_INT
-mips_initial_elimination_offset (int from, int to)
+static void
+mips_set_frame_expr (rtx frame_pattern)
{
- HOST_WIDE_INT offset;
+ rtx insn;
- compute_frame_size (get_frame_size ());
+ insn = get_last_insn ();
+ RTX_FRAME_RELATED_P (insn) = 1;
+ REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
+ frame_pattern,
+ REG_NOTES (insn));
+}
- /* Set OFFSET to the offset from the stack pointer. */
- switch (from)
- {
- case FRAME_POINTER_REGNUM:
- offset = 0;
- break;
+/* Return a frame-related rtx that stores REG at MEM.
+ REG must be a single register. */
- case ARG_POINTER_REGNUM:
- offset = (cfun->machine->frame.total_size
- - current_function_pretend_args_size);
- break;
+static rtx
+mips_frame_set (rtx mem, rtx reg)
+{
+ rtx set;
- default:
- gcc_unreachable ();
- }
+ /* If we're saving the return address register and the DWARF return
+ address column differs from the hard register number, adjust the
+ note reg to refer to the former. */
+ if (REGNO (reg) == GP_REG_FIRST + 31
+ && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
+ reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
- if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
- offset -= cfun->machine->frame.args_size;
+ set = gen_rtx_SET (VOIDmode, mem, reg);
+ RTX_FRAME_RELATED_P (set) = 1;
- return offset;
+ return set;
}
\f
-/* Implement RETURN_ADDR_RTX. Note, we do not support moving
- back to a previous frame. */
-rtx
-mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
-{
- if (count != 0)
- return const0_rtx;
+/* If a MIPS16e SAVE or RESTORE instruction saves or restores register
+ mips16e_s2_s8_regs[X], it must also save the registers in indexes
+ X + 1 onwards. Likewise mips16e_a0_a3_regs. */
+static const unsigned char mips16e_s2_s8_regs[] = {
+ 30, 23, 22, 21, 20, 19, 18
+};
+static const unsigned char mips16e_a0_a3_regs[] = {
+ 4, 5, 6, 7
+};
- return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
-}
-\f
-/* Use FN to save or restore register REGNO. MODE is the register's
- mode and OFFSET is the offset of its save slot from the current
- stack pointer. */
+/* A list of the registers that can be saved by the MIPS16e SAVE instruction,
+ ordered from the uppermost in memory to the lowest in memory. */
+static const unsigned char mips16e_save_restore_regs[] = {
+ 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
+};
-static void
-mips_save_restore_reg (enum machine_mode mode, int regno,
- HOST_WIDE_INT offset, mips_save_restore_fn fn)
+/* Return the index of the lowest X in the range [0, SIZE) for which
+ bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
+
+static unsigned int
+mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
+ unsigned int size)
{
- rtx mem;
+ unsigned int i;
- mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
+ for (i = 0; i < size; i++)
+ if (BITSET_P (mask, regs[i]))
+ break;
- fn (gen_rtx_REG (mode, regno), mem);
+ return i;
}
-
-/* Call FN for each register that is saved by the current function.
- SP_OFFSET is the offset of the current stack pointer from the start
- of the frame. */
+/* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
+ is the number of set bits. If *MASK_PTR contains REGS[X] for some X
+ in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
+ is true for all indexes (X, SIZE). */
static void
-mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
+mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
+ unsigned int size, unsigned int *num_regs_ptr)
{
- enum machine_mode fpr_mode;
- HOST_WIDE_INT offset;
- int regno;
-
- /* Save registers starting from high to low. The debuggers prefer at least
- the return register be stored at func+4, and also it allows us not to
- need a nop in the epilogue if at least one register is reloaded in
- addition to return address. */
- offset = cfun->machine->frame.gp_sp_offset - sp_offset;
- for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
- if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
- {
- mips_save_restore_reg (gpr_mode, regno, offset, fn);
- offset -= GET_MODE_SIZE (gpr_mode);
- }
+ unsigned int i;
- /* This loop must iterate over the same space as its companion in
- compute_frame_size. */
- offset = cfun->machine->frame.fp_sp_offset - sp_offset;
- fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
- for (regno = (FP_REG_LAST - MAX_FPRS_PER_FMT + 1);
- regno >= FP_REG_FIRST;
- regno -= MAX_FPRS_PER_FMT)
- if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
+ i = mips16e_find_first_register (*mask_ptr, regs, size);
+ for (i++; i < size; i++)
+ if (!BITSET_P (*mask_ptr, regs[i]))
{
- mips_save_restore_reg (fpr_mode, regno, offset, fn);
- offset -= GET_MODE_SIZE (fpr_mode);
+ *num_regs_ptr += 1;
+ *mask_ptr |= 1 << regs[i];
}
}
-\f
-/* If we're generating n32 or n64 abicalls, and the current function
- does not use $28 as its global pointer, emit a cplocal directive.
- Use pic_offset_table_rtx as the argument to the directive. */
-static void
-mips_output_cplocal (void)
-{
- if (!TARGET_EXPLICIT_RELOCS
- && cfun->machine->global_pointer > 0
- && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
- output_asm_insn (".cplocal %+", 0);
-}
+/* Return a simplified form of X using the register values in REG_VALUES.
+ REG_VALUES[R] is the last value assigned to hard register R, or null
+ if R has not been modified.
-/* Return the style of GP load sequence that is being used for the
- current function. */
+ This function is rather limited, but is good enough for our purposes. */
-enum mips_loadgp_style
-mips_current_loadgp_style (void)
+static rtx
+mips16e_collect_propagate_value (rtx x, rtx *reg_values)
{
- if (!TARGET_USE_GOT || cfun->machine->global_pointer == 0)
- return LOADGP_NONE;
+ x = avoid_constant_pool_reference (x);
- if (TARGET_RTP_PIC)
- return LOADGP_RTP;
+ if (UNARY_P (x))
+ {
+ rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
+ return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
+ x0, GET_MODE (XEXP (x, 0)));
+ }
- if (TARGET_ABSOLUTE_ABICALLS)
- return LOADGP_ABSOLUTE;
+ if (ARITHMETIC_P (x))
+ {
+ rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
+ rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
+ return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
+ }
- return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
+ if (REG_P (x)
+ && reg_values[REGNO (x)]
+ && !rtx_unstable_p (reg_values[REGNO (x)]))
+ return reg_values[REGNO (x)];
+
+ return x;
}
-/* The __gnu_local_gp symbol. */
+/* Return true if (set DEST SRC) stores an argument register into its
+ caller-allocated save slot, storing the number of that argument
+ register in *REGNO_PTR if so. REG_VALUES is as for
+ mips16e_collect_propagate_value. */
-static GTY(()) rtx mips_gnu_local_gp;
+static bool
+mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
+ unsigned int *regno_ptr)
+{
+ unsigned int argno, regno;
+ HOST_WIDE_INT offset, required_offset;
+ rtx addr, base;
-/* If we're generating n32 or n64 abicalls, emit instructions
- to set up the global pointer. */
+ /* Check that this is a word-mode store. */
+ if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
+ return false;
-static void
-mips_emit_loadgp (void)
-{
- rtx addr, offset, incoming_address, base, index;
+ /* Check that the register being saved is an unmodified argument
+ register. */
+ regno = REGNO (src);
+ if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
+ return false;
+ argno = regno - GP_ARG_FIRST;
- switch (mips_current_loadgp_style ())
- {
- case LOADGP_ABSOLUTE:
- if (mips_gnu_local_gp == NULL)
- {
- mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
- SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
- }
- emit_insn (gen_loadgp_absolute (mips_gnu_local_gp));
- break;
-
- case LOADGP_NEWABI:
- addr = XEXP (DECL_RTL (current_function_decl), 0);
- offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
- incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
- emit_insn (gen_loadgp_newabi (offset, incoming_address));
- if (!TARGET_EXPLICIT_RELOCS)
- emit_insn (gen_loadgp_blockage ());
- break;
-
- case LOADGP_RTP:
- base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
- index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
- emit_insn (gen_loadgp_rtp (base, index));
- if (!TARGET_EXPLICIT_RELOCS)
- emit_insn (gen_loadgp_blockage ());
- break;
+ /* Check whether the address is an appropriate stack-pointer or
+ frame-pointer access. */
+ addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
+ mips_split_plus (addr, &base, &offset);
+ required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
+ if (base == hard_frame_pointer_rtx)
+ required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
+ else if (base != stack_pointer_rtx)
+ return false;
+ if (offset != required_offset)
+ return false;
- default:
- break;
- }
+ *regno_ptr = regno;
+ return true;
}
-/* Set up the stack and frame (if desired) for the function. */
+/* A subroutine of mips_expand_prologue, called only when generating
+ MIPS16e SAVE instructions. Search the start of the function for any
+ instructions that save argument registers into their caller-allocated
+ save slots. Delete such instructions and return a value N such that
+ saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
+ instructions redundant. */
-static void
-mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
+static unsigned int
+mips16e_collect_argument_saves (void)
{
- const char *fnname;
- HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
-
-#ifdef SDB_DEBUGGING_INFO
- if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
- SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
-#endif
-
- /* In mips16 mode, we may need to generate a 32 bit to handle
- floating point arguments. The linker will arrange for any 32-bit
- functions to call this stub, which will then jump to the 16-bit
- function proper. */
- if (TARGET_MIPS16
- && TARGET_HARD_FLOAT_ABI
- && current_function_args_info.fp_code != 0)
- build_mips16_function_stub (file);
-
- /* Select the mips16 mode for this function. */
- if (TARGET_MIPS16)
- fprintf (file, "\t.set\tmips16\n");
- else
- fprintf (file, "\t.set\tnomips16\n");
-
- if (!FUNCTION_NAME_ALREADY_DECLARED)
- {
- /* Get the function name the same way that toplev.c does before calling
- assemble_start_function. This is needed so that the name used here
- exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
- fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
-
- if (!flag_inhibit_size_directive)
- {
- fputs ("\t.ent\t", file);
- assemble_name (file, fnname);
- fputs ("\n", file);
- }
-
- assemble_name (file, fnname);
- fputs (":\n", file);
- }
-
- /* Stop mips_file_end from treating this function as external. */
- if (TARGET_IRIX && mips_abi == ABI_32)
- TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
-
- if (!flag_inhibit_size_directive)
- {
- /* .frame FRAMEREG, FRAMESIZE, RETREG */
- fprintf (file,
- "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
- "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
- ", args= " HOST_WIDE_INT_PRINT_DEC
- ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
- (reg_names[(frame_pointer_needed)
- ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
- ((frame_pointer_needed && TARGET_MIPS16)
- ? tsize - cfun->machine->frame.args_size
- : tsize),
- reg_names[GP_REG_FIRST + 31],
- cfun->machine->frame.var_size,
- cfun->machine->frame.num_gp,
- cfun->machine->frame.num_fp,
- cfun->machine->frame.args_size,
- cfun->machine->frame.cprestore_size);
-
- /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
- fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
- cfun->machine->frame.mask,
- cfun->machine->frame.gp_save_offset);
- fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
- cfun->machine->frame.fmask,
- cfun->machine->frame.fp_save_offset);
-
- /* Require:
- OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
- HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
- }
+ rtx reg_values[FIRST_PSEUDO_REGISTER];
+ rtx insn, next, set, dest, src;
+ unsigned int nargs, regno;
- if (mips_current_loadgp_style () == LOADGP_OLDABI)
+ push_topmost_sequence ();
+ nargs = 0;
+ memset (reg_values, 0, sizeof (reg_values));
+ for (insn = get_insns (); insn; insn = next)
{
- /* Handle the initialization of $gp for SVR4 PIC. */
- if (!cfun->machine->all_noreorder_p)
- output_asm_insn ("%(.cpload\t%^%)", 0);
- else
- output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
- }
- else if (cfun->machine->all_noreorder_p)
- output_asm_insn ("%(%<", 0);
-
- /* Tell the assembler which register we're using as the global
- pointer. This is needed for thunks, since they can use either
- explicit relocs or assembler macros. */
- mips_output_cplocal ();
-}
-\f
-/* Make the last instruction frame related and note that it performs
- the operation described by FRAME_PATTERN. */
-
-static void
-mips_set_frame_expr (rtx frame_pattern)
-{
- rtx insn;
-
- insn = get_last_insn ();
- RTX_FRAME_RELATED_P (insn) = 1;
- REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
- frame_pattern,
- REG_NOTES (insn));
-}
-
-
-/* Return a frame-related rtx that stores REG at MEM.
- REG must be a single register. */
-
-static rtx
-mips_frame_set (rtx mem, rtx reg)
-{
- rtx set;
-
- /* If we're saving the return address register and the dwarf return
- address column differs from the hard register number, adjust the
- note reg to refer to the former. */
- if (REGNO (reg) == GP_REG_FIRST + 31
- && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
- reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
-
- set = gen_rtx_SET (VOIDmode, mem, reg);
- RTX_FRAME_RELATED_P (set) = 1;
-
- return set;
-}
-
-
-/* Save register REG to MEM. Make the instruction frame-related. */
+ next = NEXT_INSN (insn);
+ if (NOTE_P (insn))
+ continue;
-static void
-mips_save_reg (rtx reg, rtx mem)
-{
- if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
- {
- rtx x1, x2;
+ if (!INSN_P (insn))
+ break;
- if (mips_split_64bit_move_p (mem, reg))
- mips_split_64bit_move (mem, reg);
- else
- mips_emit_move (mem, reg);
+ set = PATTERN (insn);
+ if (GET_CODE (set) != SET)
+ break;
- x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
- x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
- mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
- }
- else
- {
- if (TARGET_MIPS16
- && REGNO (reg) != GP_REG_FIRST + 31
- && !M16_REG_P (REGNO (reg)))
+ dest = SET_DEST (set);
+ src = SET_SRC (set);
+ if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
{
- /* Save a non-mips16 register by moving it through a temporary.
- We don't need to do this for $31 since there's a special
- instruction for it. */
- mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
- mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
+ if (!BITSET_P (cfun->machine->frame.mask, regno))
+ {
+ delete_insn (insn);
+ nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
+ }
}
+ else if (REG_P (dest) && GET_MODE (dest) == word_mode)
+ reg_values[REGNO (dest)]
+ = mips16e_collect_propagate_value (src, reg_values);
else
- mips_emit_move (mem, reg);
-
- mips_set_frame_expr (mips_frame_set (mem, reg));
+ break;
}
+ pop_topmost_sequence ();
+
+ return nargs;
}
/* Return a move between register REGNO and memory location SP + OFFSET.
unsigned int i, regno;
int n;
- gcc_assert (cfun->machine->frame.fp_reg_size == 0);
+ gcc_assert (cfun->machine->frame.num_fp == 0);
/* Calculate the number of elements in the PARALLEL. We need one element
for the stack adjustment, one for each argument register save, and one
/* Save the arguments. */
for (i = 0; i < nargs; i++)
{
- offset = top_offset + i * GET_MODE_SIZE (gpr_mode);
+ offset = top_offset + i * UNITS_PER_WORD;
set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
XVECEXP (pattern, 0, n++) = set;
}
}
/* Tell the caller what offset it should use for the remaining registers. */
- *offset_ptr = size + (offset - top_offset) + size;
+ *offset_ptr = size + (offset - top_offset);
gcc_assert (n == XVECLEN (pattern, 0));
mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
struct mips16e_save_restore_info *info)
{
- unsigned int i, nargs, mask;
- HOST_WIDE_INT top_offset, save_offset, offset, extra;
+ unsigned int i, nargs, mask, extra;
+ HOST_WIDE_INT top_offset, save_offset, offset;
rtx set, reg, mem, base;
int n;
top_offset = adjust > 0 ? adjust : 0;
/* Interpret all other members of the PARALLEL. */
- save_offset = top_offset - GET_MODE_SIZE (gpr_mode);
+ save_offset = top_offset - UNITS_PER_WORD;
mask = 0;
nargs = 0;
i = 0;
return false;
/* Check for argument saves. */
- if (offset == top_offset + nargs * GET_MODE_SIZE (gpr_mode)
+ if (offset == top_offset + nargs * UNITS_PER_WORD
&& REGNO (reg) == GP_ARG_FIRST + nargs)
nargs++;
else if (offset == save_offset)
return false;
mask |= 1 << REGNO (reg);
- save_offset -= GET_MODE_SIZE (gpr_mode);
+ save_offset -= UNITS_PER_WORD;
}
else
return false;
return buffer;
}
+\f
+/* Return true if the current function has an insn that implicitly
+ refers to $gp. */
-/* Return a simplified form of X using the register values in REG_VALUES.
- REG_VALUES[R] is the last value assigned to hard register R, or null
- if R has not been modified.
-
- This function is rather limited, but is good enough for our purposes. */
-
-static rtx
-mips16e_collect_propagate_value (rtx x, rtx *reg_values)
+static bool
+mips_function_has_gp_insn (void)
{
- rtx x0, x1;
-
- x = avoid_constant_pool_reference (x);
-
- if (UNARY_P (x))
+ /* Don't bother rechecking if we found one last time. */
+ if (!cfun->machine->has_gp_insn_p)
{
- x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
- return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
- x0, GET_MODE (XEXP (x, 0)));
- }
+ rtx insn;
- if (ARITHMETIC_P (x))
- {
- x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
- x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
- return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
+ push_topmost_sequence ();
+ for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+ if (USEFUL_INSN_P (insn)
+ && (get_attr_got (insn) != GOT_UNSET
+ || mips_small_data_pattern_p (PATTERN (insn))))
+ {
+ cfun->machine->has_gp_insn_p = true;
+ break;
+ }
+ pop_topmost_sequence ();
}
-
- if (REG_P (x)
- && reg_values[REGNO (x)]
- && !rtx_unstable_p (reg_values[REGNO (x)]))
- return reg_values[REGNO (x)];
-
- return x;
+ return cfun->machine->has_gp_insn_p;
}
-/* Return true if (set DEST SRC) stores an argument register into its
- caller-allocated save slot, storing the number of that argument
- register in *REGNO_PTR if so. REG_VALUES is as for
- mips16e_collect_propagate_value. */
+/* Return the register that should be used as the global pointer
+ within this function. Return 0 if the function doesn't need
+ a global pointer. */
-static bool
-mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
- unsigned int *regno_ptr)
+static unsigned int
+mips_global_pointer (void)
{
- unsigned int argno, regno;
- HOST_WIDE_INT offset, required_offset;
- rtx addr, base;
+ unsigned int regno;
- /* Check that this is a word-mode store. */
- if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
- return false;
+ /* $gp is always available unless we're using a GOT. */
+ if (!TARGET_USE_GOT)
+ return GLOBAL_POINTER_REGNUM;
- /* Check that the register being saved is an unmodified argument
- register. */
- regno = REGNO (src);
- if (regno < GP_ARG_FIRST || regno > GP_ARG_LAST || reg_values[regno])
- return false;
- argno = regno - GP_ARG_FIRST;
+ /* We must always provide $gp when it is used implicitly. */
+ if (!TARGET_EXPLICIT_RELOCS)
+ return GLOBAL_POINTER_REGNUM;
- /* Check whether the address is an appropriate stack pointer or
- frame pointer access. The frame pointer is offset from the
- stack pointer by the size of the outgoing arguments. */
- addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
- mips_split_plus (addr, &base, &offset);
- required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
- if (base == hard_frame_pointer_rtx)
- required_offset -= cfun->machine->frame.args_size;
- else if (base != stack_pointer_rtx)
- return false;
- if (offset != required_offset)
- return false;
+ /* FUNCTION_PROFILER includes a jal macro, so we need to give it
+ a valid gp. */
+ if (current_function_profile)
+ return GLOBAL_POINTER_REGNUM;
- *regno_ptr = regno;
- return true;
-}
+ /* If the function has a nonlocal goto, $gp must hold the correct
+ global pointer for the target function. */
+ if (current_function_has_nonlocal_goto)
+ return GLOBAL_POINTER_REGNUM;
-/* A subroutine of mips_expand_prologue, called only when generating
- MIPS16e SAVE instructions. Search the start of the function for any
- instructions that save argument registers into their caller-allocated
- save slots. Delete such instructions and return a value N such that
- saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
- instructions redundant. */
+ /* If the gp is never referenced, there's no need to initialize it.
+ Note that reload can sometimes introduce constant pool references
+ into a function that otherwise didn't need them. For example,
+ suppose we have an instruction like:
-static unsigned int
-mips16e_collect_argument_saves (void)
-{
- rtx reg_values[FIRST_PSEUDO_REGISTER];
- rtx insn, next, set, dest, src;
- unsigned int nargs, regno;
+ (set (reg:DF R1) (float:DF (reg:SI R2)))
- push_topmost_sequence ();
- nargs = 0;
- memset (reg_values, 0, sizeof (reg_values));
- for (insn = get_insns (); insn; insn = next)
- {
- next = NEXT_INSN (insn);
- if (NOTE_P (insn))
- continue;
+ If R2 turns out to be constant such as 1, the instruction may have a
+ REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
+ using this constant if R2 doesn't get allocated to a register.
- if (!INSN_P (insn))
- break;
+ In cases like these, reload will have added the constant to the pool
+ but no instruction will yet refer to it. */
+ if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM)
+ && !current_function_uses_const_pool
+ && !mips_function_has_gp_insn ())
+ return 0;
- set = PATTERN (insn);
- if (GET_CODE (set) != SET)
- break;
+ /* We need a global pointer, but perhaps we can use a call-clobbered
+ register instead of $gp. */
+ if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
+ for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
+ if (!df_regs_ever_live_p (regno)
+ && call_really_used_regs[regno]
+ && !fixed_regs[regno]
+ && regno != PIC_FUNCTION_ADDR_REGNUM)
+ return regno;
- dest = SET_DEST (set);
- src = SET_SRC (set);
- if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
- {
- if (!BITSET_P (cfun->machine->frame.mask, regno))
- {
- delete_insn (insn);
- nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
- }
- }
- else if (REG_P (dest) && GET_MODE (dest) == word_mode)
- reg_values[REGNO (dest)]
- = mips16e_collect_propagate_value (src, reg_values);
- else
- break;
- }
- pop_topmost_sequence ();
+ return GLOBAL_POINTER_REGNUM;
+}
- return nargs;
+/* Return true if the current function returns its value in a floating-point
+ register in MIPS16 mode. */
+
+static bool
+mips16_cfun_returns_in_fpr_p (void)
+{
+ tree return_type = DECL_RESULT (current_function_decl);
+ return (TARGET_MIPS16
+ && TARGET_HARD_FLOAT_ABI
+ && !aggregate_value_p (return_type, current_function_decl)
+ && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
}
-/* Expand the prologue into a bunch of separate insns. */
+/* Return true if the current function must save register REGNO. */
-void
-mips_expand_prologue (void)
+static bool
+mips_save_reg_p (unsigned int regno)
{
- HOST_WIDE_INT size;
- unsigned int nargs;
- rtx insn;
+ /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then
+ if we have not chosen a call-clobbered substitute. */
+ if (regno == GLOBAL_POINTER_REGNUM)
+ return TARGET_CALL_SAVED_GP && cfun->machine->global_pointer == regno;
- if (cfun->machine->global_pointer > 0)
- SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
+ /* Check call-saved registers. */
+ if ((current_function_saves_all_registers || df_regs_ever_live_p (regno))
+ && !call_really_used_regs[regno])
+ return true;
- size = compute_frame_size (get_frame_size ());
+ /* Save both registers in an FPR pair if either one is used. This is
+ needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
+ register to be used without the even register. */
+ if (FP_REG_P (regno)
+ && MAX_FPRS_PER_FMT == 2
+ && df_regs_ever_live_p (regno + 1)
+ && !call_really_used_regs[regno + 1])
+ return true;
- /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
- bytes beforehand; this is enough to cover the register save area
- without going out of range. */
- if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
- {
- HOST_WIDE_INT step1;
+ /* We need to save the old frame pointer before setting up a new one. */
+ if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
+ return true;
- step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
+ /* Check for registers that must be saved for FUNCTION_PROFILER. */
+ if (current_function_profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
+ return true;
- if (GENERATE_MIPS16E_SAVE_RESTORE)
- {
- HOST_WIDE_INT offset;
- unsigned int mask, regno;
+ /* We need to save the incoming return address if it is ever clobbered
+ within the function, if __builtin_eh_return is being used to set a
+ different return address, or if a stub is being used to return a
+ value in FPRs. */
+ if (regno == GP_REG_FIRST + 31
+ && (df_regs_ever_live_p (regno)
+ || current_function_calls_eh_return
+ || mips16_cfun_returns_in_fpr_p ()))
+ return true;
- /* Try to merge argument stores into the save instruction. */
- nargs = mips16e_collect_argument_saves ();
+ return false;
+}
- /* Build the save instruction. */
- mask = cfun->machine->frame.mask;
- insn = mips16e_build_save_restore (false, &mask, &offset,
- nargs, step1);
- RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
- size -= step1;
+/* Populate the current function's mips_frame_info structure.
- /* Check if we need to save other registers. */
- for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
- if (BITSET_P (mask, regno - GP_REG_FIRST))
- {
- offset -= GET_MODE_SIZE (gpr_mode);
- mips_save_restore_reg (gpr_mode, regno, offset, mips_save_reg);
- }
- }
+ MIPS stack frames look like:
+
+ +-------------------------------+
+ | |
+ | incoming stack arguments |
+ | |
+ +-------------------------------+
+ | |
+ | caller-allocated save area |
+ A | for register arguments |
+ | |
+ +-------------------------------+ <-- incoming stack pointer
+ | |
+ | callee-allocated save area |
+ B | for arguments that are |
+ | split between registers and |
+ | the stack |
+ | |
+ +-------------------------------+ <-- arg_pointer_rtx
+ | |
+ C | callee-allocated save area |
+ | for register varargs |
+ | |
+ +-------------------------------+ <-- frame_pointer_rtx + fp_sp_offset
+ | | + UNITS_PER_HWFPVALUE
+ | FPR save area |
+ | |
+ +-------------------------------+ <-- frame_pointer_rtx + gp_sp_offset
+ | | + UNITS_PER_WORD
+ | GPR save area |
+ | |
+ +-------------------------------+
+ | | \
+ | local variables | | var_size
+ | | /
+ +-------------------------------+
+ | | \
+ | $gp save area | | cprestore_size
+ | | /
+ P +-------------------------------+ <-- hard_frame_pointer_rtx for
+ | | MIPS16 code
+ | outgoing stack arguments |
+ | |
+ +-------------------------------+
+ | |
+ | caller-allocated save area |
+ | for register arguments |
+ | |
+ +-------------------------------+ <-- stack_pointer_rtx
+ frame_pointer_rtx
+ hard_frame_pointer_rtx for
+ non-MIPS16 code.
+
+ At least two of A, B and C will be empty.
+
+ Dynamic stack allocations such as alloca insert data at point P.
+ They decrease stack_pointer_rtx but leave frame_pointer_rtx and
+ hard_frame_pointer_rtx unchanged. */
+
+static void
+mips_compute_frame_info (void)
+{
+ struct mips_frame_info *frame;
+ HOST_WIDE_INT offset, size;
+ unsigned int regno, i;
+
+ frame = &cfun->machine->frame;
+ memset (frame, 0, sizeof (*frame));
+ size = get_frame_size ();
+
+ cfun->machine->global_pointer = mips_global_pointer ();
+
+ /* The first STARTING_FRAME_OFFSET bytes contain the outgoing argument
+ area and the $gp save slot. This area isn't needed in leaf functions,
+ but if the target-independent frame size is nonzero, we're committed
+ to allocating it anyway. */
+ if (size == 0 && current_function_is_leaf)
+ {
+ /* The MIPS 3.0 linker does not like functions that dynamically
+ allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
+ looks like we are trying to create a second frame pointer to the
+ function, so allocate some stack space to make it happy. */
+ if (current_function_calls_alloca)
+ frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
else
- {
- insn = gen_add3_insn (stack_pointer_rtx,
- stack_pointer_rtx,
- GEN_INT (-step1));
- RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
- size -= step1;
- mips_for_each_saved_reg (size, mips_save_reg);
- }
+ frame->args_size = 0;
+ frame->cprestore_size = 0;
}
-
- /* Allocate the rest of the frame. */
- if (size > 0)
+ else
{
- if (SMALL_OPERAND (-size))
- RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
- stack_pointer_rtx,
- GEN_INT (-size)))) = 1;
- else
- {
- mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
- if (TARGET_MIPS16)
- {
- /* There are no instructions to add or subtract registers
- from the stack pointer, so use the frame pointer as a
- temporary. We should always be using a frame pointer
- in this case anyway. */
- gcc_assert (frame_pointer_needed);
- mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
- emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
- hard_frame_pointer_rtx,
- MIPS_PROLOGUE_TEMP (Pmode)));
- mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
- }
- else
- emit_insn (gen_sub3_insn (stack_pointer_rtx,
- stack_pointer_rtx,
- MIPS_PROLOGUE_TEMP (Pmode)));
+ frame->args_size = current_function_outgoing_args_size;
+ frame->cprestore_size = STARTING_FRAME_OFFSET - frame->args_size;
+ }
+ offset = frame->args_size + frame->cprestore_size;
- /* Describe the combined effect of the previous instructions. */
- mips_set_frame_expr
- (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
- plus_constant (stack_pointer_rtx, -size)));
- }
+ /* Move above the local variables. */
+ frame->var_size = MIPS_STACK_ALIGN (size);
+ offset += frame->var_size;
+
+ /* Find out which GPRs we need to save. */
+ for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
+ if (mips_save_reg_p (regno))
+ {
+ frame->num_gp++;
+ frame->mask |= 1 << (regno - GP_REG_FIRST);
+ }
+
+ /* If this function calls eh_return, we must also save and restore the
+ EH data registers. */
+ if (current_function_calls_eh_return)
+ for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
+ {
+ frame->num_gp++;
+ frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
+ }
+
+ /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
+ $a3-$a0 and $s2-$s8. If we save one register in the range, we must
+ save all later registers too. */
+ if (GENERATE_MIPS16E_SAVE_RESTORE)
+ {
+ mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
+ ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
+ mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
+ ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
}
- /* Set up the frame pointer, if we're using one. In mips16 code,
- we point the frame pointer ahead of the outgoing argument area.
- This should allow more variables & incoming arguments to be
- accessed with unextended instructions. */
- if (frame_pointer_needed)
+ /* Move above the GPR save area. */
+ if (frame->num_gp > 0)
{
- if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
+ offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
+ frame->gp_sp_offset = offset - UNITS_PER_WORD;
+ }
+
+ /* Find out which FPRs we need to save. This loop must iterate over
+ the same space as its companion in mips_for_each_saved_reg. */
+ if (TARGET_HARD_FLOAT)
+ for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
+ if (mips_save_reg_p (regno))
{
- rtx offset = GEN_INT (cfun->machine->frame.args_size);
- if (SMALL_OPERAND (cfun->machine->frame.args_size))
- RTX_FRAME_RELATED_P
- (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
- stack_pointer_rtx,
- offset))) = 1;
- else
- {
- mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), offset);
- mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
- emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
- hard_frame_pointer_rtx,
- MIPS_PROLOGUE_TEMP (Pmode)));
- mips_set_frame_expr
- (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
- plus_constant (stack_pointer_rtx,
- cfun->machine->frame.args_size)));
- }
+ frame->num_fp += MAX_FPRS_PER_FMT;
+ frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
}
- else
- RTX_FRAME_RELATED_P (mips_emit_move (hard_frame_pointer_rtx,
- stack_pointer_rtx)) = 1;
+
+ /* Move above the FPR save area. */
+ if (frame->num_fp > 0)
+ {
+ offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
+ frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
}
- mips_emit_loadgp ();
+ /* Move above the callee-allocated varargs save area. */
+ offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
+ frame->arg_pointer_offset = offset;
- /* If generating o32/o64 abicalls, save $gp on the stack. */
- if (TARGET_ABICALLS && TARGET_OLDABI && !current_function_is_leaf)
- emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
+ /* Move above the callee-allocated area for pretend stack arguments. */
+ offset += current_function_pretend_args_size;
+ frame->total_size = offset;
- /* If we are profiling, make sure no instructions are scheduled before
- the call to mcount. */
+ /* Work out the offsets of the save areas from the top of the frame. */
+ if (frame->gp_sp_offset > 0)
+ frame->gp_save_offset = frame->gp_sp_offset - offset;
+ if (frame->fp_sp_offset > 0)
+ frame->fp_save_offset = frame->fp_sp_offset - offset;
- if (current_function_profile)
- emit_insn (gen_blockage ());
+ /* MIPS16 code offsets the frame pointer by the size of the outgoing
+ arguments. This tends to increase the chances of using unextended
+ instructions for local variables and incoming arguments. */
+ if (TARGET_MIPS16)
+ frame->hard_frame_pointer_offset = frame->args_size;
}
-\f
-/* Do any necessary cleanup after a function to restore stack, frame,
- and regs. */
-#define RA_MASK BITMASK_HIGH /* 1 << 31 */
+/* Return the style of GP load sequence that is being used for the
+ current function. */
-static void
-mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
- HOST_WIDE_INT size ATTRIBUTE_UNUSED)
+enum mips_loadgp_style
+mips_current_loadgp_style (void)
{
- /* Reinstate the normal $gp. */
- SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
- mips_output_cplocal ();
+ if (!TARGET_USE_GOT || cfun->machine->global_pointer == 0)
+ return LOADGP_NONE;
- if (cfun->machine->all_noreorder_p)
- {
- /* Avoid using %>%) since it adds excess whitespace. */
- output_asm_insn (".set\tmacro", 0);
- output_asm_insn (".set\treorder", 0);
- set_noreorder = set_nomacro = 0;
- }
+ if (TARGET_RTP_PIC)
+ return LOADGP_RTP;
- if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
- {
- const char *fnname;
+ if (TARGET_ABSOLUTE_ABICALLS)
+ return LOADGP_ABSOLUTE;
- /* Get the function name the same way that toplev.c does before calling
- assemble_start_function. This is needed so that the name used here
- exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
- fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
- fputs ("\t.end\t", file);
- assemble_name (file, fnname);
- fputs ("\n", file);
- }
+ return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
}
-\f
-/* Emit instructions to restore register REG from slot MEM. */
-static void
-mips_restore_reg (rtx reg, rtx mem)
+/* Implement FRAME_POINTER_REQUIRED. */
+
+bool
+mips_frame_pointer_required (void)
{
- /* There's no mips16 instruction to load $31 directly. Load into
- $7 instead and adjust the return insn appropriately. */
- if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
- reg = gen_rtx_REG (GET_MODE (reg), 7);
+ /* If the function contains dynamic stack allocations, we need to
+ use the frame pointer to access the static parts of the frame. */
+ if (current_function_calls_alloca)
+ return true;
- if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
+ /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
+ reload may be unable to compute the address of a local variable,
+ since there is no way to add a large constant to the stack pointer
+ without using a second temporary register. */
+ if (TARGET_MIPS16)
{
- /* Can't restore directly; move through a temporary. */
- mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
- mips_emit_move (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
+ mips_compute_frame_info ();
+ if (!SMALL_OPERAND (cfun->machine->frame.total_size))
+ return true;
}
- else
- mips_emit_move (reg, mem);
-}
+ return false;
+}
-/* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
- if this epilogue precedes a sibling call, false if it is for a normal
- "epilogue" pattern. */
+/* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
+ or argument pointer. TO is either the stack pointer or hard frame
+ pointer. */
-void
-mips_expand_epilogue (int sibcall_p)
+HOST_WIDE_INT
+mips_initial_elimination_offset (int from, int to)
{
- HOST_WIDE_INT step1, step2;
- rtx base, target;
+ HOST_WIDE_INT offset;
- if (!sibcall_p && mips_can_use_return_insn ())
- {
- emit_jump_insn (gen_return ());
- return;
- }
-
- /* In mips16 mode, if the return value should go into a floating-point
- register, we need to call a helper routine to copy it over. */
- if (mips16_cfun_returns_in_fpr_p ())
+ mips_compute_frame_info ();
+
+ /* Set OFFSET to the offset from the soft frame pointer, which is also
+ the offset from the end-of-prologue stack pointer. */
+ switch (from)
{
- char *name;
- rtx func;
- rtx insn;
- rtx retval;
- rtx call;
- tree id;
- tree return_type;
- enum machine_mode return_mode;
+ case FRAME_POINTER_REGNUM:
+ offset = 0;
+ break;
- return_type = DECL_RESULT (current_function_decl);
- return_mode = DECL_MODE (return_type);
+ case ARG_POINTER_REGNUM:
+ offset = cfun->machine->frame.arg_pointer_offset;
+ break;
- name = ACONCAT (("__mips16_ret_",
- mips16_call_stub_mode_suffix (return_mode),
- NULL));
- id = get_identifier (name);
- func = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
- retval = gen_rtx_REG (return_mode, GP_RETURN);
- call = gen_call_value_internal (retval, func, const0_rtx);
- insn = emit_call_insn (call);
- use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
+ default:
+ gcc_unreachable ();
}
- /* Split the frame into two. STEP1 is the amount of stack we should
- deallocate before restoring the registers. STEP2 is the amount we
- should deallocate afterwards.
+ if (to == HARD_FRAME_POINTER_REGNUM)
+ offset -= cfun->machine->frame.hard_frame_pointer_offset;
- Start off by assuming that no registers need to be restored. */
- step1 = cfun->machine->frame.total_size;
- step2 = 0;
+ return offset;
+}
+\f
+/* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
- /* Work out which register holds the frame address. Account for the
- frame pointer offset used by mips16 code. */
- if (!frame_pointer_needed)
- base = stack_pointer_rtx;
- else
+static void
+mips_extra_live_on_entry (bitmap regs)
+{
+ if (TARGET_USE_GOT)
{
- base = hard_frame_pointer_rtx;
- if (TARGET_MIPS16)
- step1 -= cfun->machine->frame.args_size;
- }
+ /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
+ the global pointer. */
+ if (!TARGET_ABSOLUTE_ABICALLS)
+ bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
- /* If we need to restore registers, deallocate as much stack as
- possible in the second step without going out of range. */
- if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
- {
- step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
- step1 -= step2;
+ /* See the comment above load_call<mode> for details. */
+ bitmap_set_bit (regs, GOT_VERSION_REGNUM);
}
+}
- /* Set TARGET to BASE + STEP1. */
- target = base;
- if (step1 > 0)
- {
- rtx adjust;
-
- /* Get an rtx for STEP1 that we can add to BASE. */
- adjust = GEN_INT (step1);
- if (!SMALL_OPERAND (step1))
- {
- mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
- adjust = MIPS_EPILOGUE_TEMP (Pmode);
- }
-
- /* Normal mode code can copy the result straight into $sp. */
- if (!TARGET_MIPS16)
- target = stack_pointer_rtx;
-
- emit_insn (gen_add3_insn (target, base, adjust));
- }
+/* Implement RETURN_ADDR_RTX. We do not support moving back to a
+ previous frame. */
- /* Copy TARGET into the stack pointer. */
- if (target != stack_pointer_rtx)
- mips_emit_move (stack_pointer_rtx, target);
+rtx
+mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
+{
+ if (count != 0)
+ return const0_rtx;
- /* If we're using addressing macros, $gp is implicitly used by all
- SYMBOL_REFs. We must emit a blockage insn before restoring $gp
- from the stack. */
- if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
- emit_insn (gen_blockage ());
+ return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
+}
- if (GENERATE_MIPS16E_SAVE_RESTORE && cfun->machine->frame.mask != 0)
- {
- unsigned int regno, mask;
- HOST_WIDE_INT offset;
- rtx restore;
+/* Emit code to change the current function's return address to
+ ADDRESS. SCRATCH is available as a scratch register, if needed.
+ ADDRESS and SCRATCH are both word-mode GPRs. */
- /* Generate the restore instruction. */
- mask = cfun->machine->frame.mask;
- restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
+void
+mips_set_return_address (rtx address, rtx scratch)
+{
+ rtx slot_address;
- /* Restore any other registers manually. */
- for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
- if (BITSET_P (mask, regno - GP_REG_FIRST))
- {
- offset -= GET_MODE_SIZE (gpr_mode);
- mips_save_restore_reg (gpr_mode, regno, offset, mips_restore_reg);
- }
+ gcc_assert (BITSET_P (cfun->machine->frame.mask, 31));
+ slot_address = mips_add_offset (scratch, stack_pointer_rtx,
+ cfun->machine->frame.gp_sp_offset);
+ mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
+}
- /* Restore the remaining registers and deallocate the final bit
- of the frame. */
- emit_insn (restore);
- }
- else
- {
- /* Restore the registers. */
- mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
- mips_restore_reg);
+/* Restore $gp from its save slot. Valid only when using o32 or
+ o64 abicalls. */
- /* Deallocate the final bit of the frame. */
- if (step2 > 0)
- emit_insn (gen_add3_insn (stack_pointer_rtx,
- stack_pointer_rtx,
- GEN_INT (step2)));
- }
+void
+mips_restore_gp (void)
+{
+ rtx base, address;
- /* Add in the __builtin_eh_return stack adjustment. We need to
- use a temporary in mips16 code. */
- if (current_function_calls_eh_return)
- {
- if (TARGET_MIPS16)
- {
- mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
- emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
- MIPS_EPILOGUE_TEMP (Pmode),
- EH_RETURN_STACKADJ_RTX));
- mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
- }
- else
- emit_insn (gen_add3_insn (stack_pointer_rtx,
- stack_pointer_rtx,
- EH_RETURN_STACKADJ_RTX));
- }
+ gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
- if (!sibcall_p)
- {
- /* When generating MIPS16 code, the normal mips_for_each_saved_reg
- path will restore the return address into $7 rather than $31. */
- if (TARGET_MIPS16
- && !GENERATE_MIPS16E_SAVE_RESTORE
- && (cfun->machine->frame.mask & RA_MASK) != 0)
- emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
- GP_REG_FIRST + 7)));
- else
- emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
- GP_REG_FIRST + 31)));
- }
+ base = frame_pointer_needed ? hard_frame_pointer_rtx : stack_pointer_rtx;
+ address = mips_add_offset (pic_offset_table_rtx, base,
+ current_function_outgoing_args_size);
+ mips_emit_move (pic_offset_table_rtx, gen_frame_mem (Pmode, address));
+ if (!TARGET_EXPLICIT_RELOCS)
+ emit_insn (gen_blockage ());
}
\f
-/* Return nonzero if this function is known to have a null epilogue.
- This allows the optimizer to omit jumps to jumps if no stack
- was created. */
+/* A function to save or store a register. The first argument is the
+ register and the second is the stack slot. */
+typedef void (*mips_save_restore_fn) (rtx, rtx);
-int
-mips_can_use_return_insn (void)
+/* Use FN to save or restore register REGNO. MODE is the register's
+ mode and OFFSET is the offset of its save slot from the current
+ stack pointer. */
+
+static void
+mips_save_restore_reg (enum machine_mode mode, int regno,
+ HOST_WIDE_INT offset, mips_save_restore_fn fn)
{
- if (! reload_completed)
- return 0;
+ rtx mem;
- if (df_regs_ever_live_p (31) || current_function_profile)
- return 0;
+ mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
+ fn (gen_rtx_REG (mode, regno), mem);
+}
- /* In mips16 mode, a function that returns a floating point value
- needs to arrange to copy the return value into the floating point
- registers. */
- if (mips16_cfun_returns_in_fpr_p ())
- return 0;
+/* Call FN for each register that is saved by the current function.
+ SP_OFFSET is the offset of the current stack pointer from the start
+ of the frame. */
+
+static void
+mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
+{
+ enum machine_mode fpr_mode;
+ HOST_WIDE_INT offset;
+ int regno;
- if (cfun->machine->frame.initialized)
- return cfun->machine->frame.total_size == 0;
+ /* Save registers starting from high to low. The debuggers prefer at least
+ the return register be stored at func+4, and also it allows us not to
+ need a nop in the epilogue if at least one register is reloaded in
+ addition to return address. */
+ offset = cfun->machine->frame.gp_sp_offset - sp_offset;
+ for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
+ if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
+ {
+ mips_save_restore_reg (word_mode, regno, offset, fn);
+ offset -= UNITS_PER_WORD;
+ }
- return compute_frame_size (get_frame_size ()) == 0;
+ /* This loop must iterate over the same space as its companion in
+ mips_compute_frame_info. */
+ offset = cfun->machine->frame.fp_sp_offset - sp_offset;
+ fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
+ for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
+ regno >= FP_REG_FIRST;
+ regno -= MAX_FPRS_PER_FMT)
+ if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
+ {
+ mips_save_restore_reg (fpr_mode, regno, offset, fn);
+ offset -= GET_MODE_SIZE (fpr_mode);
+ }
}
\f
-/* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
- in order to avoid duplicating too much logic from elsewhere. */
+/* If we're generating n32 or n64 abicalls, and the current function
+ does not use $28 as its global pointer, emit a cplocal directive.
+ Use pic_offset_table_rtx as the argument to the directive. */
static void
-mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
- HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
- tree function)
+mips_output_cplocal (void)
{
- rtx this, temp1, temp2, insn, fnaddr;
-
- /* Pretend to be a post-reload pass while generating rtl. */
- reload_completed = 1;
-
- /* Mark the end of the (empty) prologue. */
- emit_note (NOTE_INSN_PROLOGUE_END);
+ if (!TARGET_EXPLICIT_RELOCS
+ && cfun->machine->global_pointer > 0
+ && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
+ output_asm_insn (".cplocal %+", 0);
+}
- /* Pick a global pointer. Use a call-clobbered register if
- TARGET_CALL_SAVED_GP, so that we can use a sibcall. */
- if (TARGET_USE_GOT)
- {
- cfun->machine->global_pointer =
- TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
+/* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
- SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
- }
+static void
+mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
+{
+ const char *fnname;
- /* Set up the global pointer for n32 or n64 abicalls. If
- LOADGP_ABSOLUTE then the thunk does not use the gp and there is
- no need to load it.*/
- if (mips_current_loadgp_style () != LOADGP_ABSOLUTE
- || !targetm.binds_local_p (function))
- mips_emit_loadgp ();
+#ifdef SDB_DEBUGGING_INFO
+ if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
+ SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
+#endif
- /* We need two temporary registers in some cases. */
- temp1 = gen_rtx_REG (Pmode, 2);
- temp2 = gen_rtx_REG (Pmode, 3);
+ /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
+ floating-point arguments. */
+ if (TARGET_MIPS16
+ && TARGET_HARD_FLOAT_ABI
+ && current_function_args_info.fp_code != 0)
+ mips16_build_function_stub ();
- /* Find out which register contains the "this" pointer. */
- if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
- this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
+ /* Select the MIPS16 mode for this function. */
+ if (TARGET_MIPS16)
+ fprintf (file, "\t.set\tmips16\n");
else
- this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
+ fprintf (file, "\t.set\tnomips16\n");
- /* Add DELTA to THIS. */
- if (delta != 0)
+ if (!FUNCTION_NAME_ALREADY_DECLARED)
{
- rtx offset = GEN_INT (delta);
- if (!SMALL_OPERAND (delta))
+ /* Get the function name the same way that toplev.c does before calling
+ assemble_start_function. This is needed so that the name used here
+ exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
+ fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
+
+ if (!flag_inhibit_size_directive)
{
- mips_emit_move (temp1, offset);
- offset = temp1;
+ fputs ("\t.ent\t", file);
+ assemble_name (file, fnname);
+ fputs ("\n", file);
}
- emit_insn (gen_add3_insn (this, this, offset));
+
+ assemble_name (file, fnname);
+ fputs (":\n", file);
}
- /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
- if (vcall_offset != 0)
+ /* Stop mips_file_end from treating this function as external. */
+ if (TARGET_IRIX && mips_abi == ABI_32)
+ TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
+
+ /* Output MIPS-specific frame information. */
+ if (!flag_inhibit_size_directive)
{
- rtx addr;
+ const struct mips_frame_info *frame;
- /* Set TEMP1 to *THIS. */
- mips_emit_move (temp1, gen_rtx_MEM (Pmode, this));
+ frame = &cfun->machine->frame;
- /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
- addr = mips_add_offset (temp2, temp1, vcall_offset);
+ /* .frame FRAMEREG, FRAMESIZE, RETREG. */
+ fprintf (file,
+ "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
+ "# vars= " HOST_WIDE_INT_PRINT_DEC
+ ", regs= %d/%d"
+ ", args= " HOST_WIDE_INT_PRINT_DEC
+ ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
+ reg_names[frame_pointer_needed
+ ? HARD_FRAME_POINTER_REGNUM
+ : STACK_POINTER_REGNUM],
+ (frame_pointer_needed
+ ? frame->total_size - frame->hard_frame_pointer_offset
+ : frame->total_size),
+ reg_names[GP_REG_FIRST + 31],
+ frame->var_size,
+ frame->num_gp, frame->num_fp,
+ frame->args_size,
+ frame->cprestore_size);
- /* Load the offset and add it to THIS. */
- mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
- emit_insn (gen_add3_insn (this, this, temp1));
+ /* .mask MASK, OFFSET. */
+ fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
+ frame->mask, frame->gp_save_offset);
+
+ /* .fmask MASK, OFFSET. */
+ fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
+ frame->fmask, frame->fp_save_offset);
}
- /* Jump to the target function. Use a sibcall if direct jumps are
- allowed, otherwise load the address into a register first. */
- fnaddr = XEXP (DECL_RTL (function), 0);
- if (TARGET_MIPS16 || TARGET_USE_GOT || SYMBOL_REF_LONG_CALL_P (fnaddr)
- || SYMBOL_REF_MIPS16_FUNC_P (fnaddr))
+ /* Handle the initialization of $gp for SVR4 PIC, if applicable.
+ Also emit the ".set noreorder; .set nomacro" sequence for functions
+ that need it. */
+ if (mips_current_loadgp_style () == LOADGP_OLDABI)
{
- /* This is messy. gas treats "la $25,foo" as part of a call
- sequence and may allow a global "foo" to be lazily bound.
- The general move patterns therefore reject this combination.
+ /* .cpload must be in a .set noreorder but not a .set nomacro block. */
+ if (!cfun->machine->all_noreorder_p)
+ output_asm_insn ("%(.cpload\t%^%)", 0);
+ else
+ output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
+ }
+ else if (cfun->machine->all_noreorder_p)
+ output_asm_insn ("%(%<", 0);
- In this context, lazy binding would actually be OK
- for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
- TARGET_CALL_SAVED_GP; see mips_load_call_address.
- We must therefore load the address via a temporary
- register if mips_dangerous_for_la25_p.
+ /* Tell the assembler which register we're using as the global
+ pointer. This is needed for thunks, since they can use either
+ explicit relocs or assembler macros. */
+ mips_output_cplocal ();
+}
- If we jump to the temporary register rather than $25, the assembler
- can use the move insn to fill the jump's delay slot. */
- if (TARGET_USE_PIC_FN_ADDR_REG
- && !mips_dangerous_for_la25_p (fnaddr))
- temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
- mips_load_call_address (temp1, fnaddr, true);
+/* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
- if (TARGET_USE_PIC_FN_ADDR_REG
- && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
- mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
- emit_jump_insn (gen_indirect_jump (temp1));
- }
- else
+static void
+mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
+ HOST_WIDE_INT size ATTRIBUTE_UNUSED)
+{
+ /* Reinstate the normal $gp. */
+ SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
+ mips_output_cplocal ();
+
+ if (cfun->machine->all_noreorder_p)
{
- insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
- SIBLING_CALL_P (insn) = 1;
+ /* Avoid using %>%) since it adds excess whitespace. */
+ output_asm_insn (".set\tmacro", 0);
+ output_asm_insn (".set\treorder", 0);
+ set_noreorder = set_nomacro = 0;
}
- /* Run just enough of rest_of_compilation. This sequence was
- "borrowed" from alpha.c. */
- insn = get_insns ();
- insn_locators_alloc ();
- split_all_insns_noflow ();
- mips16_lay_out_constants ();
- shorten_branches (insn);
- final_start_function (insn, file, 1);
- final (insn, file, 1);
- final_end_function ();
+ if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
+ {
+ const char *fnname;
- /* Clean up the vars set above. Note that final_end_function resets
- the global pointer for us. */
- reload_completed = 0;
+ /* Get the function name the same way that toplev.c does before calling
+ assemble_start_function. This is needed so that the name used here
+ exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
+ fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
+ fputs ("\t.end\t", file);
+ assemble_name (file, fnname);
+ fputs ("\n", file);
+ }
}
\f
-/* Implement TARGET_SELECT_RTX_SECTION. */
+/* Save register REG to MEM. Make the instruction frame-related. */
-static section *
-mips_select_rtx_section (enum machine_mode mode, rtx x,
- unsigned HOST_WIDE_INT align)
+static void
+mips_save_reg (rtx reg, rtx mem)
{
- /* ??? Consider using mergeable small data sections. */
- if (mips_rtx_constant_in_small_data_p (mode))
- return get_named_section (NULL, ".sdata", 0);
+ if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
+ {
+ rtx x1, x2;
- return default_elf_select_rtx_section (mode, x, align);
+ if (mips_split_64bit_move_p (mem, reg))
+ mips_split_doubleword_move (mem, reg);
+ else
+ mips_emit_move (mem, reg);
+
+ x1 = mips_frame_set (mips_subword (mem, false),
+ mips_subword (reg, false));
+ x2 = mips_frame_set (mips_subword (mem, true),
+ mips_subword (reg, true));
+ mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
+ }
+ else
+ {
+ if (TARGET_MIPS16
+ && REGNO (reg) != GP_REG_FIRST + 31
+ && !M16_REG_P (REGNO (reg)))
+ {
+ /* Save a non-MIPS16 register by moving it through a temporary.
+ We don't need to do this for $31 since there's a special
+ instruction for it. */
+ mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
+ mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
+ }
+ else
+ mips_emit_move (mem, reg);
+
+ mips_set_frame_expr (mips_frame_set (mem, reg));
+ }
}
-/* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
+/* The __gnu_local_gp symbol. */
- The complication here is that, with the combination TARGET_ABICALLS
- && !TARGET_GPWORD, jump tables will use absolute addresses, and should
- therefore not be included in the read-only part of a DSO. Handle such
- cases by selecting a normal data section instead of a read-only one.
- The logic apes that in default_function_rodata_section. */
+static GTY(()) rtx mips_gnu_local_gp;
-static section *
-mips_function_rodata_section (tree decl)
+/* If we're generating n32 or n64 abicalls, emit instructions
+ to set up the global pointer. */
+
+static void
+mips_emit_loadgp (void)
{
- if (!TARGET_ABICALLS || TARGET_GPWORD)
- return default_function_rodata_section (decl);
+ rtx addr, offset, incoming_address, base, index, pic_reg;
- if (decl && DECL_SECTION_NAME (decl))
+ pic_reg = pic_offset_table_rtx;
+ switch (mips_current_loadgp_style ())
{
- const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
- if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
- {
- char *rname = ASTRDUP (name);
- rname[14] = 'd';
- return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
- }
- else if (flag_function_sections && flag_data_sections
- && strncmp (name, ".text.", 6) == 0)
+ case LOADGP_ABSOLUTE:
+ if (mips_gnu_local_gp == NULL)
{
- char *rname = ASTRDUP (name);
- memcpy (rname + 1, "data", 4);
- return get_section (rname, SECTION_WRITE, decl);
+ mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
+ SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
}
+ emit_insn (Pmode == SImode
+ ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
+ : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
+ break;
+
+ case LOADGP_NEWABI:
+ addr = XEXP (DECL_RTL (current_function_decl), 0);
+ offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
+ incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
+ emit_insn (Pmode == SImode
+ ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
+ : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
+ if (!TARGET_EXPLICIT_RELOCS)
+ emit_insn (gen_loadgp_blockage ());
+ break;
+
+ case LOADGP_RTP:
+ base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
+ index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
+ emit_insn (Pmode == SImode
+ ? gen_loadgp_rtp_si (pic_reg, base, index)
+ : gen_loadgp_rtp_di (pic_reg, base, index));
+ if (!TARGET_EXPLICIT_RELOCS)
+ emit_insn (gen_loadgp_blockage ());
+ break;
+
+ default:
+ break;
}
- return data_section;
}
-/* Implement TARGET_IN_SMALL_DATA_P. This function controls whether
- locally-defined objects go in a small data section. It also controls
- the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
- mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */
+/* Expand the "prologue" pattern. */
-static bool
-mips_in_small_data_p (const_tree decl)
+void
+mips_expand_prologue (void)
{
+ const struct mips_frame_info *frame;
HOST_WIDE_INT size;
+ unsigned int nargs;
+ rtx insn;
- if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
- return false;
+ if (cfun->machine->global_pointer > 0)
+ SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
- /* We don't yet generate small-data references for -mabicalls or
- VxWorks RTP code. See the related -G handling in override_options. */
- if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
- return false;
+ frame = &cfun->machine->frame;
+ size = frame->total_size;
- if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
- {
- const char *name;
+ /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
+ bytes beforehand; this is enough to cover the register save area
+ without going out of range. */
+ if ((frame->mask | frame->fmask) != 0)
+ {
+ HOST_WIDE_INT step1;
- /* Reject anything that isn't in a known small-data section. */
- name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
- if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
- return false;
+ step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
+ if (GENERATE_MIPS16E_SAVE_RESTORE)
+ {
+ HOST_WIDE_INT offset;
+ unsigned int mask, regno;
- /* If a symbol is defined externally, the assembler will use the
- usual -G rules when deciding how to implement macros. */
- if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
- return true;
+ /* Try to merge argument stores into the save instruction. */
+ nargs = mips16e_collect_argument_saves ();
+
+ /* Build the save instruction. */
+ mask = frame->mask;
+ insn = mips16e_build_save_restore (false, &mask, &offset,
+ nargs, step1);
+ RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
+ size -= step1;
+
+ /* Check if we need to save other registers. */
+ for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
+ if (BITSET_P (mask, regno - GP_REG_FIRST))
+ {
+ offset -= UNITS_PER_WORD;
+ mips_save_restore_reg (word_mode, regno,
+ offset, mips_save_reg);
+ }
+ }
+ else
+ {
+ insn = gen_add3_insn (stack_pointer_rtx,
+ stack_pointer_rtx,
+ GEN_INT (-step1));
+ RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
+ size -= step1;
+ mips_for_each_saved_reg (size, mips_save_reg);
+ }
}
- else if (TARGET_EMBEDDED_DATA)
+
+ /* Allocate the rest of the frame. */
+ if (size > 0)
{
- /* Don't put constants into the small data section: we want them
- to be in ROM rather than RAM. */
- if (TREE_CODE (decl) != VAR_DECL)
- return false;
+ if (SMALL_OPERAND (-size))
+ RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
+ stack_pointer_rtx,
+ GEN_INT (-size)))) = 1;
+ else
+ {
+ mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
+ if (TARGET_MIPS16)
+ {
+ /* There are no instructions to add or subtract registers
+ from the stack pointer, so use the frame pointer as a
+ temporary. We should always be using a frame pointer
+ in this case anyway. */
+ gcc_assert (frame_pointer_needed);
+ mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
+ emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
+ hard_frame_pointer_rtx,
+ MIPS_PROLOGUE_TEMP (Pmode)));
+ mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
+ }
+ else
+ emit_insn (gen_sub3_insn (stack_pointer_rtx,
+ stack_pointer_rtx,
+ MIPS_PROLOGUE_TEMP (Pmode)));
- if (TREE_READONLY (decl)
- && !TREE_SIDE_EFFECTS (decl)
- && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
- return false;
+ /* Describe the combined effect of the previous instructions. */
+ mips_set_frame_expr
+ (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
+ plus_constant (stack_pointer_rtx, -size)));
+ }
}
- /* Enforce -mlocal-sdata. */
- if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
- return false;
-
- /* Enforce -mextern-sdata. */
- if (!TARGET_EXTERN_SDATA && DECL_P (decl))
+ /* Set up the frame pointer, if we're using one. */
+ if (frame_pointer_needed)
{
- if (DECL_EXTERNAL (decl))
- return false;
- if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
- return false;
+ HOST_WIDE_INT offset;
+
+ offset = frame->hard_frame_pointer_offset;
+ if (offset == 0)
+ {
+ insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
+ RTX_FRAME_RELATED_P (insn) = 1;
+ }
+ else if (SMALL_OPERAND (offset))
+ {
+ insn = gen_add3_insn (hard_frame_pointer_rtx,
+ stack_pointer_rtx, GEN_INT (offset));
+ RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
+ }
+ else
+ {
+ mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
+ mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
+ emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
+ hard_frame_pointer_rtx,
+ MIPS_PROLOGUE_TEMP (Pmode)));
+ mips_set_frame_expr
+ (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
+ plus_constant (stack_pointer_rtx, offset)));
+ }
}
- size = int_size_in_bytes (TREE_TYPE (decl));
- return (size > 0 && size <= mips_section_threshold);
-}
+ mips_emit_loadgp ();
-/* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
- anchors for small data: the GP register acts as an anchor in that
- case. We also don't want to use them for PC-relative accesses,
- where the PC acts as an anchor. */
+ /* Initialize the $gp save slot. */
+ if (frame->cprestore_size > 0)
+ emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
-static bool
-mips_use_anchors_for_symbol_p (const_rtx symbol)
+ /* If we are profiling, make sure no instructions are scheduled before
+ the call to mcount. */
+ if (current_function_profile)
+ emit_insn (gen_blockage ());
+}
+\f
+/* Emit instructions to restore register REG from slot MEM. */
+
+static void
+mips_restore_reg (rtx reg, rtx mem)
{
- switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
- {
- case SYMBOL_PC_RELATIVE:
- case SYMBOL_GP_RELATIVE:
- return false;
+ /* There's no MIPS16 instruction to load $31 directly. Load into
+ $7 instead and adjust the return insn appropriately. */
+ if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
+ reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
- default:
- return true;
+ if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
+ {
+ /* Can't restore directly; move through a temporary. */
+ mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
+ mips_emit_move (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
}
+ else
+ mips_emit_move (reg, mem);
}
-\f
-/* See whether VALTYPE is a record whose fields should be returned in
- floating-point registers. If so, return the number of fields and
- list them in FIELDS (which should have two elements). Return 0
- otherwise.
- For n32 & n64, a structure with one or two fields is returned in
- floating-point registers as long as every field has a floating-point
- type. */
+/* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
+ says which. */
-static int
-mips_fpr_return_fields (const_tree valtype, tree *fields)
+void
+mips_expand_epilogue (bool sibcall_p)
{
- tree field;
- int i;
-
- if (!TARGET_NEWABI)
- return 0;
-
- if (TREE_CODE (valtype) != RECORD_TYPE)
- return 0;
+ const struct mips_frame_info *frame;
+ HOST_WIDE_INT step1, step2;
+ rtx base, target;
- i = 0;
- for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
+ if (!sibcall_p && mips_can_use_return_insn ())
{
- if (TREE_CODE (field) != FIELD_DECL)
- continue;
+ emit_jump_insn (gen_return ());
+ return;
+ }
- if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
- return 0;
+ /* In MIPS16 mode, if the return value should go into a floating-point
+ register, we need to call a helper routine to copy it over. */
+ if (mips16_cfun_returns_in_fpr_p ())
+ mips16_copy_fpr_return_value ();
- if (i == 2)
- return 0;
+ /* Split the frame into two. STEP1 is the amount of stack we should
+ deallocate before restoring the registers. STEP2 is the amount we
+ should deallocate afterwards.
- fields[i++] = field;
+ Start off by assuming that no registers need to be restored. */
+ frame = &cfun->machine->frame;
+ step1 = frame->total_size;
+ step2 = 0;
+
+ /* Work out which register holds the frame address. */
+ if (!frame_pointer_needed)
+ base = stack_pointer_rtx;
+ else
+ {
+ base = hard_frame_pointer_rtx;
+ step1 -= frame->hard_frame_pointer_offset;
}
- return i;
-}
+ /* If we need to restore registers, deallocate as much stack as
+ possible in the second step without going out of range. */
+ if ((frame->mask | frame->fmask) != 0)
+ {
+ step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
+ step1 -= step2;
+ }
-/* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
- a value in the most significant part of $2/$3 if:
+ /* Set TARGET to BASE + STEP1. */
+ target = base;
+ if (step1 > 0)
+ {
+ rtx adjust;
- - the target is big-endian;
+ /* Get an rtx for STEP1 that we can add to BASE. */
+ adjust = GEN_INT (step1);
+ if (!SMALL_OPERAND (step1))
+ {
+ mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
+ adjust = MIPS_EPILOGUE_TEMP (Pmode);
+ }
- - the value has a structure or union type (we generalize this to
- cover aggregates from other languages too); and
+ /* Normal mode code can copy the result straight into $sp. */
+ if (!TARGET_MIPS16)
+ target = stack_pointer_rtx;
- - the structure is not returned in floating-point registers. */
+ emit_insn (gen_add3_insn (target, base, adjust));
+ }
-static bool
-mips_return_in_msb (const_tree valtype)
-{
- tree fields[2];
+ /* Copy TARGET into the stack pointer. */
+ if (target != stack_pointer_rtx)
+ mips_emit_move (stack_pointer_rtx, target);
- return (TARGET_NEWABI
- && TARGET_BIG_ENDIAN
- && AGGREGATE_TYPE_P (valtype)
- && mips_fpr_return_fields (valtype, fields) == 0);
-}
+ /* If we're using addressing macros, $gp is implicitly used by all
+ SYMBOL_REFs. We must emit a blockage insn before restoring $gp
+ from the stack. */
+ if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
+ emit_insn (gen_blockage ());
+ if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
+ {
+ unsigned int regno, mask;
+ HOST_WIDE_INT offset;
+ rtx restore;
-/* Return a composite value in a pair of floating-point registers.
- MODE1 and OFFSET1 are the mode and byte offset for the first value,
- likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
- complete value.
+ /* Generate the restore instruction. */
+ mask = frame->mask;
+ restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
- For n32 & n64, $f0 always holds the first value and $f2 the second.
- Otherwise the values are packed together as closely as possible. */
+ /* Restore any other registers manually. */
+ for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
+ if (BITSET_P (mask, regno - GP_REG_FIRST))
+ {
+ offset -= UNITS_PER_WORD;
+ mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
+ }
-static rtx
-mips_return_fpr_pair (enum machine_mode mode,
- enum machine_mode mode1, HOST_WIDE_INT offset1,
- enum machine_mode mode2, HOST_WIDE_INT offset2)
-{
- int inc;
+ /* Restore the remaining registers and deallocate the final bit
+ of the frame. */
+ emit_insn (restore);
+ }
+ else
+ {
+ /* Restore the registers. */
+ mips_for_each_saved_reg (frame->total_size - step2, mips_restore_reg);
- inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
- return gen_rtx_PARALLEL
- (mode,
- gen_rtvec (2,
- gen_rtx_EXPR_LIST (VOIDmode,
- gen_rtx_REG (mode1, FP_RETURN),
- GEN_INT (offset1)),
- gen_rtx_EXPR_LIST (VOIDmode,
- gen_rtx_REG (mode2, FP_RETURN + inc),
- GEN_INT (offset2))));
+ /* Deallocate the final bit of the frame. */
+ if (step2 > 0)
+ emit_insn (gen_add3_insn (stack_pointer_rtx,
+ stack_pointer_rtx,
+ GEN_INT (step2)));
+ }
+
+ /* Add in the __builtin_eh_return stack adjustment. We need to
+ use a temporary in MIPS16 code. */
+ if (current_function_calls_eh_return)
+ {
+ if (TARGET_MIPS16)
+ {
+ mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
+ emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
+ MIPS_EPILOGUE_TEMP (Pmode),
+ EH_RETURN_STACKADJ_RTX));
+ mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
+ }
+ else
+ emit_insn (gen_add3_insn (stack_pointer_rtx,
+ stack_pointer_rtx,
+ EH_RETURN_STACKADJ_RTX));
+ }
+
+ if (!sibcall_p)
+ {
+ unsigned int regno;
+ /* When generating MIPS16 code, the normal mips_for_each_saved_reg
+ path will restore the return address into $7 rather than $31. */
+ if (TARGET_MIPS16
+ && !GENERATE_MIPS16E_SAVE_RESTORE
+ && BITSET_P (frame->mask, 31))
+ regno = GP_REG_FIRST + 7;
+ else
+ regno = GP_REG_FIRST + 31;
+ emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
+ }
}
+\f
+/* Return nonzero if this function is known to have a null epilogue.
+ This allows the optimizer to omit jumps to jumps if no stack
+ was created. */
+bool
+mips_can_use_return_insn (void)
+{
+ if (!reload_completed)
+ return false;
-/* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
- VALTYPE is the return type and MODE is VOIDmode. For libcalls,
- VALTYPE is null and MODE is the mode of the return value. */
+ if (current_function_profile)
+ return false;
-rtx
-mips_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
- enum machine_mode mode)
+ /* In MIPS16 mode, a function that returns a floating-point value
+ needs to arrange to copy the return value into the floating-point
+ registers. */
+ if (mips16_cfun_returns_in_fpr_p ())
+ return false;
+
+ return cfun->machine->frame.total_size == 0;
+}
+\f
+/* Return true if register REGNO can store a value of mode MODE.
+ The result of this function is cached in mips_hard_regno_mode_ok. */
+
+static bool
+mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
{
- if (valtype)
+ unsigned int size;
+ enum mode_class class;
+
+ if (mode == CCV2mode)
+ return (ISA_HAS_8CC
+ && ST_REG_P (regno)
+ && (regno - ST_REG_FIRST) % 2 == 0);
+
+ if (mode == CCV4mode)
+ return (ISA_HAS_8CC
+ && ST_REG_P (regno)
+ && (regno - ST_REG_FIRST) % 4 == 0);
+
+ if (mode == CCmode)
{
- tree fields[2];
- int unsignedp;
+ if (!ISA_HAS_8CC)
+ return regno == FPSW_REGNUM;
- mode = TYPE_MODE (valtype);
- unsignedp = TYPE_UNSIGNED (valtype);
+ return (ST_REG_P (regno)
+ || GP_REG_P (regno)
+ || FP_REG_P (regno));
+ }
- /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
- true, we must promote the mode just as PROMOTE_MODE does. */
- mode = promote_mode (valtype, mode, &unsignedp, 1);
+ size = GET_MODE_SIZE (mode);
+ class = GET_MODE_CLASS (mode);
- /* Handle structures whose fields are returned in $f0/$f2. */
- switch (mips_fpr_return_fields (valtype, fields))
- {
- case 1:
- return gen_rtx_REG (mode, FP_RETURN);
+ if (GP_REG_P (regno))
+ return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
- case 2:
- return mips_return_fpr_pair (mode,
- TYPE_MODE (TREE_TYPE (fields[0])),
- int_byte_position (fields[0]),
- TYPE_MODE (TREE_TYPE (fields[1])),
- int_byte_position (fields[1]));
- }
+ if (FP_REG_P (regno)
+ && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
+ || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
+ {
+ /* Allow TFmode for CCmode reloads. */
+ if (mode == TFmode && ISA_HAS_8CC)
+ return true;
- /* If a value is passed in the most significant part of a register, see
- whether we have to round the mode up to a whole number of words. */
- if (mips_return_in_msb (valtype))
- {
- HOST_WIDE_INT size = int_size_in_bytes (valtype);
- if (size % UNITS_PER_WORD != 0)
- {
- size += UNITS_PER_WORD - size % UNITS_PER_WORD;
- mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
- }
- }
+ if (class == MODE_FLOAT
+ || class == MODE_COMPLEX_FLOAT
+ || class == MODE_VECTOR_FLOAT)
+ return size <= UNITS_PER_FPVALUE;
- /* For EABI, the class of return register depends entirely on MODE.
- For example, "struct { some_type x; }" and "union { some_type x; }"
- are returned in the same way as a bare "some_type" would be.
- Other ABIs only use FPRs for scalar, complex or vector types. */
- if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
- return gen_rtx_REG (mode, GP_RETURN);
+ /* Allow integer modes that fit into a single register. We need
+ to put integers into FPRs when using instructions like CVT
+ and TRUNC. There's no point allowing sizes smaller than a word,
+ because the FPU has no appropriate load/store instructions. */
+ if (class == MODE_INT)
+ return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
}
- if (!TARGET_MIPS16)
+ if (ACC_REG_P (regno)
+ && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
{
- /* Handle long doubles for n32 & n64. */
- if (mode == TFmode)
- return mips_return_fpr_pair (mode,
- DImode, 0,
- DImode, GET_MODE_SIZE (mode) / 2);
+ if (size <= UNITS_PER_WORD)
+ return true;
- if (mips_return_mode_in_fpr_p (mode))
- {
- if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
- return mips_return_fpr_pair (mode,
- GET_MODE_INNER (mode), 0,
- GET_MODE_INNER (mode),
- GET_MODE_SIZE (mode) / 2);
- else
- return gen_rtx_REG (mode, FP_RETURN);
- }
+ if (size <= UNITS_PER_WORD * 2)
+ return (DSP_ACC_REG_P (regno)
+ ? ((regno - DSP_ACC_REG_FIRST) & 1) == 0
+ : regno == MD_REG_FIRST);
}
- return gen_rtx_REG (mode, GP_RETURN);
+ if (ALL_COP_REG_P (regno))
+ return class == MODE_INT && size <= UNITS_PER_WORD;
+
+ if (regno == GOT_VERSION_REGNUM)
+ return mode == SImode;
+
+ return false;
}
-/* Return nonzero when an argument must be passed by reference. */
+/* Implement HARD_REGNO_NREGS. */
-static bool
-mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
- enum machine_mode mode, const_tree type,
- bool named ATTRIBUTE_UNUSED)
+unsigned int
+mips_hard_regno_nregs (int regno, enum machine_mode mode)
{
- if (mips_abi == ABI_EABI)
- {
- int size;
+ if (ST_REG_P (regno))
+ /* The size of FP status registers is always 4, because they only hold
+ CCmode values, and CCmode is always considered to be 4 bytes wide. */
+ return (GET_MODE_SIZE (mode) + 3) / 4;
- /* ??? How should SCmode be handled? */
- if (mode == DImode || mode == DFmode)
- return 0;
+ if (FP_REG_P (regno))
+ return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
- size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
- return size == -1 || size > UNITS_PER_WORD;
+ /* All other registers are word-sized. */
+ return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
+}
+
+/* Implement CLASS_MAX_NREGS, taking the maximum of the cases
+ in mips_hard_regno_nregs. */
+
+int
+mips_class_max_nregs (enum reg_class class, enum machine_mode mode)
+{
+ int size;
+ HARD_REG_SET left;
+
+ size = 0x8000;
+ COPY_HARD_REG_SET (left, reg_class_contents[(int) class]);
+ if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
+ {
+ size = MIN (size, 4);
+ AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
}
- else
+ if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
{
- /* If we have a variable-sized parameter, we have no choice. */
- return targetm.calls.must_pass_in_stack (mode, type);
+ size = MIN (size, UNITS_PER_FPREG);
+ AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
}
+ if (!hard_reg_set_empty_p (left))
+ size = MIN (size, UNITS_PER_WORD);
+ return (GET_MODE_SIZE (mode) + size - 1) / size;
}
-static bool
-mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
- enum machine_mode mode ATTRIBUTE_UNUSED,
- const_tree type ATTRIBUTE_UNUSED, bool named)
+/* Implement CANNOT_CHANGE_MODE_CLASS. */
+
+bool
+mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
+ enum machine_mode to ATTRIBUTE_UNUSED,
+ enum reg_class class)
{
- return mips_abi == ABI_EABI && named;
+ /* There are several problems with changing the modes of values
+ in floating-point registers:
+
+ - When a multi-word value is stored in paired floating-point
+ registers, the first register always holds the low word.
+ We therefore can't allow FPRs to change between single-word
+ and multi-word modes on big-endian targets.
+
+ - GCC assumes that each word of a multiword register can be accessed
+ individually using SUBREGs. This is not true for floating-point
+ registers if they are bigger than a word.
+
+ - Loading a 32-bit value into a 64-bit floating-point register
+ will not sign-extend the value, despite what LOAD_EXTEND_OP says.
+ We can't allow FPRs to change from SImode to to a wider mode on
+ 64-bit targets.
+
+ - If the FPU has already interpreted a value in one format, we must
+ not ask it to treat the value as having a different format.
+
+ We therefore disallow all mode changes involving FPRs. */
+ return reg_classes_intersect_p (FP_REGS, class);
}
-/* Return true if registers of class CLASS cannot change from mode FROM
- to mode TO. */
+/* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
-bool
-mips_cannot_change_mode_class (enum machine_mode from,
- enum machine_mode to, enum reg_class class)
+static bool
+mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
{
- if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
- && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
+ switch (mode)
{
- if (TARGET_BIG_ENDIAN)
- {
- /* When a multi-word value is stored in paired floating-point
- registers, the first register always holds the low word.
- We therefore can't allow FPRs to change between single-word
- and multi-word modes. */
- if (MAX_FPRS_PER_FMT > 1 && reg_classes_intersect_p (FP_REGS, class))
- return true;
- }
- }
+ case SFmode:
+ return TARGET_HARD_FLOAT;
- /* gcc assumes that each word of a multiword register can be accessed
- individually using SUBREGs. This is not true for floating-point
- registers if they are bigger than a word. */
- if (UNITS_PER_FPREG > UNITS_PER_WORD
- && GET_MODE_SIZE (from) > UNITS_PER_WORD
- && GET_MODE_SIZE (to) < UNITS_PER_FPREG
- && reg_classes_intersect_p (FP_REGS, class))
- return true;
+ case DFmode:
+ return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
- /* Loading a 32-bit value into a 64-bit floating-point register
- will not sign-extend the value, despite what LOAD_EXTEND_OP says.
- We can't allow 64-bit float registers to change from SImode to
- to a wider mode. */
- if (TARGET_64BIT
- && TARGET_FLOAT64
- && from == SImode
- && GET_MODE_SIZE (to) >= UNITS_PER_WORD
- && reg_classes_intersect_p (FP_REGS, class))
- return true;
+ case V2SFmode:
+ return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
- return false;
+ default:
+ return false;
+ }
}
-/* Return true if X should not be moved directly into register $25.
- We need this because many versions of GAS will treat "la $25,foo" as
- part of a call sequence and so allow a global "foo" to be lazily bound. */
+/* Implement MODES_TIEABLE_P. */
bool
-mips_dangerous_for_la25_p (rtx x)
+mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
{
- return (!TARGET_EXPLICIT_RELOCS
- && TARGET_USE_GOT
- && GET_CODE (x) == SYMBOL_REF
- && mips_global_symbol_p (x));
+ /* FPRs allow no mode punning, so it's not worth tying modes if we'd
+ prefer to put one of them in FPRs. */
+ return (mode1 == mode2
+ || (!mips_mode_ok_for_mov_fmt_p (mode1)
+ && !mips_mode_ok_for_mov_fmt_p (mode2)));
}
/* Implement PREFERRED_RELOAD_CLASS. */
if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
return LEA_REGS;
- if (TARGET_HARD_FLOAT
- && FLOAT_MODE_P (GET_MODE (x))
- && reg_class_subset_p (FP_REGS, class))
+ if (reg_class_subset_p (FP_REGS, class)
+ && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
return FP_REGS;
if (reg_class_subset_p (GR_REGS, class))
return class;
}
-/* This function returns the register class required for a secondary
- register when copying between one of the registers in CLASS, and X,
- using MODE. If IN_P is nonzero, the copy is going from X to the
- register, otherwise the register is the source. A return value of
- NO_REGS means that no secondary register is required. */
+/* Implement REGISTER_MOVE_COST. */
-enum reg_class
-mips_secondary_reload_class (enum reg_class class,
- enum machine_mode mode, rtx x, int in_p)
+int
+mips_register_move_cost (enum machine_mode mode,
+ enum reg_class to, enum reg_class from)
{
- enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
- int regno = -1;
- int gp_reg_p;
+ if (TARGET_MIPS16)
+ {
+ /* ??? We cannot move general registers into HI and LO because
+ MIPS16 has no MTHI and MTLO instructions. Make the cost of
+ moves in the opposite direction just as high, which stops the
+ register allocators from using HI and LO for pseudos. */
+ if (reg_class_subset_p (from, GENERAL_REGS)
+ && reg_class_subset_p (to, GENERAL_REGS))
+ {
+ if (reg_class_subset_p (from, M16_REGS)
+ || reg_class_subset_p (to, M16_REGS))
+ return 2;
+ /* Two MOVEs. */
+ return 4;
+ }
+ }
+ else if (reg_class_subset_p (from, GENERAL_REGS))
+ {
+ if (reg_class_subset_p (to, GENERAL_REGS))
+ return 2;
+ if (reg_class_subset_p (to, FP_REGS))
+ return 4;
+ if (reg_class_subset_p (to, ALL_COP_AND_GR_REGS))
+ return 5;
+ if (reg_class_subset_p (to, ACC_REGS))
+ return 6;
+ }
+ else if (reg_class_subset_p (to, GENERAL_REGS))
+ {
+ if (reg_class_subset_p (from, FP_REGS))
+ return 4;
+ if (reg_class_subset_p (from, ST_REGS))
+ /* LUI followed by MOVF. */
+ return 4;
+ if (reg_class_subset_p (from, ALL_COP_AND_GR_REGS))
+ return 5;
+ if (reg_class_subset_p (from, ACC_REGS))
+ return 6;
+ }
+ else if (reg_class_subset_p (from, FP_REGS))
+ {
+ if (reg_class_subset_p (to, FP_REGS)
+ && mips_mode_ok_for_mov_fmt_p (mode))
+ return 4;
+ if (reg_class_subset_p (to, ST_REGS))
+ /* An expensive sequence. */
+ return 8;
+ }
+
+ return 12;
+}
- if (REG_P (x)|| GET_CODE (x) == SUBREG)
- regno = true_regnum (x);
+/* Return the register class required for a secondary register when
+ copying between one of the registers in CLASS and value X, which
+ has mode MODE. X is the source of the move if IN_P, otherwise it
+ is the destination. Return NO_REGS if no secondary register is
+ needed. */
- gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
+enum reg_class
+mips_secondary_reload_class (enum reg_class class,
+ enum machine_mode mode, rtx x, bool in_p)
+{
+ int regno;
+ /* If X is a constant that cannot be loaded into $25, it must be loaded
+ into some other GPR. No other register class allows a direct move. */
if (mips_dangerous_for_la25_p (x))
+ return reg_class_subset_p (class, LEA_REGS) ? NO_REGS : LEA_REGS;
+
+ regno = true_regnum (x);
+ if (TARGET_MIPS16)
{
- gr_regs = LEA_REGS;
- if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
- return gr_regs;
+ /* In MIPS16 mode, every move must involve a member of M16_REGS. */
+ if (!reg_class_subset_p (class, M16_REGS) && !M16_REG_P (regno))
+ return M16_REGS;
+
+ /* We can't really copy to HI or LO at all in MIPS16 mode. */
+ if (in_p ? reg_classes_intersect_p (class, ACC_REGS) : ACC_REG_P (regno))
+ return M16_REGS;
+
+ return NO_REGS;
}
- /* Copying from HI or LO to anywhere other than a general register
- requires a general register.
- This rule applies to both the original HI/LO pair and the new
- DSP accumulators. */
+ /* Copying from accumulator registers to anywhere other than a general
+ register requires a temporary general register. */
if (reg_class_subset_p (class, ACC_REGS))
- {
- if (TARGET_MIPS16 && in_p)
- {
- /* We can't really copy to HI or LO at all in mips16 mode. */
- return M16_REGS;
- }
- return gp_reg_p ? NO_REGS : gr_regs;
- }
+ return GP_REG_P (regno) ? NO_REGS : GR_REGS;
if (ACC_REG_P (regno))
- {
- if (TARGET_MIPS16 && ! in_p)
- {
- /* We can't really copy to HI or LO at all in mips16 mode. */
- return M16_REGS;
- }
- return class == gr_regs ? NO_REGS : gr_regs;
- }
+ return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
/* We can only copy a value to a condition code register from a
- floating point register, and even then we require a scratch
- floating point register. We can only copy a value out of a
- condition code register into a general register. */
- if (class == ST_REGS)
+ floating-point register, and even then we require a scratch
+ floating-point register. We can only copy a value out of a
+ condition-code register into a general register. */
+ if (reg_class_subset_p (class, ST_REGS))
{
if (in_p)
return FP_REGS;
- return gp_reg_p ? NO_REGS : gr_regs;
+ return GP_REG_P (regno) ? NO_REGS : GR_REGS;
}
if (ST_REG_P (regno))
{
- if (! in_p)
+ if (!in_p)
return FP_REGS;
- return class == gr_regs ? NO_REGS : gr_regs;
+ return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
}
- if (class == FP_REGS)
+ if (reg_class_subset_p (class, FP_REGS))
{
- if (MEM_P (x))
- {
- /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
- return NO_REGS;
- }
- else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
- {
- /* We can use the l.s and l.d macros to load floating-point
- constants. ??? For l.s, we could probably get better
- code by returning GR_REGS here. */
- return NO_REGS;
- }
- else if (gp_reg_p || x == CONST0_RTX (mode))
- {
- /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
- return NO_REGS;
- }
- else if (FP_REG_P (regno))
- {
- /* In this case we can use mov.s or mov.d. */
- return NO_REGS;
- }
- else
- {
- /* Otherwise, we need to reload through an integer register. */
- return gr_regs;
- }
- }
+ if (MEM_P (x)
+ && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
+ /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
+ pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
+ return NO_REGS;
- /* In mips16 mode, going between memory and anything but M16_REGS
- requires an M16_REG. */
- if (TARGET_MIPS16)
- {
- if (class != M16_REGS && class != M16_NA_REGS)
- {
- if (gp_reg_p)
- return NO_REGS;
- return M16_REGS;
- }
- if (! gp_reg_p)
- {
- if (class == M16_REGS || class == M16_NA_REGS)
- return NO_REGS;
- return M16_REGS;
- }
- }
+ if (GP_REG_P (regno) || x == CONST0_RTX (mode))
+ /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
+ return NO_REGS;
- return NO_REGS;
-}
+ if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
+ /* We can force the constant to memory and use lwc1
+ and ldc1. As above, we will use pairs of lwc1s if
+ ldc1 is not supported. */
+ return NO_REGS;
-/* Implement CLASS_MAX_NREGS.
+ if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
+ /* In this case we can use mov.fmt. */
+ return NO_REGS;
- - UNITS_PER_FPREG controls the number of registers needed by FP_REGS.
+ /* Otherwise, we need to reload through an integer register. */
+ return GR_REGS;
+ }
+ if (FP_REG_P (regno))
+ return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
- - ST_REGS are always hold CCmode values, and CCmode values are
- considered to be 4 bytes wide.
+ return NO_REGS;
+}
- All other register classes are covered by UNITS_PER_WORD. Note that
- this is true even for unions of integer and float registers when the
- latter are smaller than the former. The only supported combination
- in which case this occurs is -mgp64 -msingle-float, which has 64-bit
- words but 32-bit float registers. A word-based calculation is correct
- in that case since -msingle-float disallows multi-FPR values. */
+/* Implement TARGET_MODE_REP_EXTENDED. */
-int
-mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
- enum machine_mode mode)
+static int
+mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
{
- if (class == ST_REGS)
- return (GET_MODE_SIZE (mode) + 3) / 4;
- else if (class == FP_REGS)
- return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
- else
- return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
+ /* On 64-bit targets, SImode register values are sign-extended to DImode. */
+ if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
+ return SIGN_EXTEND;
+
+ return UNKNOWN;
}
+\f
+/* Implement TARGET_VALID_POINTER_MODE. */
static bool
mips_valid_pointer_mode (enum machine_mode mode)
{
- return (mode == SImode || (TARGET_64BIT && mode == DImode));
+ return mode == SImode || (TARGET_64BIT && mode == DImode);
}
-/* Target hook for vector_mode_supported_p. */
+/* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
static bool
mips_vector_mode_supported_p (enum machine_mode mode)
case V2HImode:
case V4QImode:
+ case V2HQmode:
+ case V2UHQmode:
+ case V2HAmode:
+ case V2UHAmode:
+ case V4QQmode:
+ case V4UQQmode:
return TARGET_DSP;
default:
return false;
}
}
-\f
-/* If we can access small data directly (using gp-relative relocation
- operators) return the small data pointer, otherwise return null.
- For each mips16 function which refers to GP relative symbols, we
- use a pseudo register, initialized at the start of the function, to
- hold the $gp value. */
+/* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
-static rtx
-mips16_gp_pseudo_reg (void)
+static bool
+mips_scalar_mode_supported_p (enum machine_mode mode)
{
- if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
- cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
-
- /* Don't initialize the pseudo register if we are being called from
- the tree optimizers' cost-calculation routines. */
- if (!cfun->machine->initialized_mips16_gp_pseudo_p
- && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
- {
- rtx insn, scan;
-
- /* We want to initialize this to a value which gcc will believe
- is constant. */
- insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
-
- push_topmost_sequence ();
- /* We need to emit the initialization after the FUNCTION_BEG
- note, so that it will be integrated. */
- for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
- if (NOTE_P (scan)
- && NOTE_KIND (scan) == NOTE_INSN_FUNCTION_BEG)
- break;
- if (scan == NULL_RTX)
- scan = get_insns ();
- insn = emit_insn_after (insn, scan);
- pop_topmost_sequence ();
-
- cfun->machine->initialized_mips16_gp_pseudo_p = true;
- }
+ if (ALL_FIXED_POINT_MODE_P (mode)
+ && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
+ return true;
- return cfun->machine->mips16_gp_pseudo_rtx;
+ return default_scalar_mode_supported_p (mode);
}
+\f
+/* Implement TARGET_INIT_LIBFUNCS. */
-/* Write out code to move floating point arguments in or out of
- general registers. Output the instructions to FILE. FP_CODE is
- the code describing which arguments are present (see the comment at
- the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
- we are copying from the floating point registers. */
+#include "config/gofast.h"
static void
-mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
+mips_init_libfuncs (void)
{
- const char *s;
- int gparg, fparg;
- unsigned int f;
- CUMULATIVE_ARGS cum;
-
- /* This code only works for the original 32-bit ABI and the O64 ABI. */
- gcc_assert (TARGET_OLDABI);
-
- if (from_fp_p)
- s = "mfc1";
- else
- s = "mtc1";
-
- init_cumulative_args (&cum, NULL, NULL);
+ if (TARGET_FIX_VR4120)
+ {
+ /* Register the special divsi3 and modsi3 functions needed to work
+ around VR4120 division errata. */
+ set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
+ set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
+ }
- for (f = (unsigned int) fp_code; f != 0; f >>= 2)
+ if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
{
- enum machine_mode mode;
- struct mips_arg_info info;
+ /* Register the MIPS16 -mhard-float stubs. */
+ set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
+ set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
+ set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
+ set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
- if ((f & 3) == 1)
- mode = SFmode;
- else if ((f & 3) == 2)
- mode = DFmode;
- else
- gcc_unreachable ();
+ set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
+ set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
+ set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
+ set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
+ set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
+ set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
+ set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
- mips_arg_info (&cum, mode, NULL, true, &info);
- gparg = mips_arg_regno (&info, false);
- fparg = mips_arg_regno (&info, true);
+ set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
+ set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
+ set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
- if (mode == SFmode)
- fprintf (file, "\t%s\t%s,%s\n", s,
- reg_names[gparg], reg_names[fparg]);
- else if (TARGET_64BIT)
- fprintf (file, "\td%s\t%s,%s\n", s,
- reg_names[gparg], reg_names[fparg]);
- else if (ISA_HAS_MXHC1)
- /* -mips32r2 -mfp64 */
- fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n",
- s,
- reg_names[gparg + (WORDS_BIG_ENDIAN ? 1 : 0)],
- reg_names[fparg],
- from_fp_p ? "mfhc1" : "mthc1",
- reg_names[gparg + (WORDS_BIG_ENDIAN ? 0 : 1)],
- reg_names[fparg]);
- else if (TARGET_BIG_ENDIAN)
- fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
- reg_names[gparg], reg_names[fparg + 1], s,
- reg_names[gparg + 1], reg_names[fparg]);
- else
- fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
- reg_names[gparg], reg_names[fparg], s,
- reg_names[gparg + 1], reg_names[fparg + 1]);
+ if (TARGET_DOUBLE_FLOAT)
+ {
+ set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
+ set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
+ set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
+ set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
+
+ set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
+ set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
+ set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
+ set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
+ set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
+ set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
+ set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
- function_arg_advance (&cum, mode, NULL, true);
+ set_conv_libfunc (sext_optab, DFmode, SFmode,
+ "__mips16_extendsfdf2");
+ set_conv_libfunc (trunc_optab, SFmode, DFmode,
+ "__mips16_truncdfsf2");
+ set_conv_libfunc (sfix_optab, SImode, DFmode,
+ "__mips16_fix_truncdfsi");
+ set_conv_libfunc (sfloat_optab, DFmode, SImode,
+ "__mips16_floatsidf");
+ set_conv_libfunc (ufloat_optab, DFmode, SImode,
+ "__mips16_floatunsidf");
+ }
}
+ else
+ /* Register the gofast functions if selected using --enable-gofast. */
+ gofast_maybe_init_libfuncs ();
}
-/* Build a mips16 function stub. This is used for functions which
- take arguments in the floating point registers. It is 32-bit code
- that moves the floating point args into the general registers, and
- then jumps to the 16-bit code. */
+/* Return the length of INSN. LENGTH is the initial length computed by
+ attributes in the machine-description file. */
-static void
-build_mips16_function_stub (FILE *file)
+int
+mips_adjust_insn_length (rtx insn, int length)
{
- const char *fnname;
- char *secname, *stubname;
- tree stubid, stubdecl;
- int need_comma;
- unsigned int f;
-
- fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
- secname = (char *) alloca (strlen (fnname) + 20);
- sprintf (secname, ".mips16.fn.%s", fnname);
- stubname = (char *) alloca (strlen (fnname) + 20);
- sprintf (stubname, "__fn_stub_%s", fnname);
- stubid = get_identifier (stubname);
- stubdecl = build_decl (FUNCTION_DECL, stubid,
- build_function_type (void_type_node, NULL_TREE));
- DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
- DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
-
- fprintf (file, "\t# Stub function for %s (", current_function_name ());
- need_comma = 0;
- for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
- {
- fprintf (file, "%s%s",
- need_comma ? ", " : "",
- (f & 3) == 1 ? "float" : "double");
- need_comma = 1;
- }
- fprintf (file, ")\n");
+ /* A unconditional jump has an unfilled delay slot if it is not part
+ of a sequence. A conditional jump normally has a delay slot, but
+ does not on MIPS16. */
+ if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
+ length += 4;
- fprintf (file, "\t.set\tnomips16\n");
- switch_to_section (function_section (stubdecl));
- ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
+ /* See how many nops might be needed to avoid hardware hazards. */
+ if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
+ switch (get_attr_hazard (insn))
+ {
+ case HAZARD_NONE:
+ break;
- /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
- within a .ent, and we cannot emit another .ent. */
- if (!FUNCTION_NAME_ALREADY_DECLARED)
- {
- fputs ("\t.ent\t", file);
- assemble_name (file, stubname);
- fputs ("\n", file);
- }
+ case HAZARD_DELAY:
+ length += 4;
+ break;
- assemble_name (file, stubname);
- fputs (":\n", file);
+ case HAZARD_HILO:
+ length += 8;
+ break;
+ }
- /* We don't want the assembler to insert any nops here. */
- fprintf (file, "\t.set\tnoreorder\n");
+ /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
+ the .md file length attributes are 4-based for both modes.
+ Adjust the MIPS16 ones here. */
+ if (TARGET_MIPS16)
+ length /= 2;
- mips16_fp_args (file, current_function_args_info.fp_code, 1);
+ return length;
+}
- fprintf (asm_out_file, "\t.set\tnoat\n");
- fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
- assemble_name (file, fnname);
- fprintf (file, "\n");
- fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
- fprintf (asm_out_file, "\t.set\tat\n");
+/* Return an asm sequence to start a noat block and load the address
+ of a label into $1. */
- /* Unfortunately, we can't fill the jump delay slot. We can't fill
- with one of the mfc1 instructions, because the result is not
- available for one instruction, so if the very first instruction
- in the function refers to the register, it will see the wrong
- value. */
- fprintf (file, "\tnop\n");
+const char *
+mips_output_load_label (void)
+{
+ if (TARGET_EXPLICIT_RELOCS)
+ switch (mips_abi)
+ {
+ case ABI_N32:
+ return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
- fprintf (file, "\t.set\treorder\n");
+ case ABI_64:
+ return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
- if (!FUNCTION_NAME_ALREADY_DECLARED)
+ default:
+ if (ISA_HAS_LOAD_DELAY)
+ return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
+ return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
+ }
+ else
{
- fputs ("\t.end\t", file);
- assemble_name (file, stubname);
- fputs ("\n", file);
+ if (Pmode == DImode)
+ return "%[dla\t%@,%0";
+ else
+ return "%[la\t%@,%0";
}
-
- switch_to_section (function_section (current_function_decl));
}
-/* We keep a list of functions for which we have already built stubs
- in build_mips16_call_stub. */
+/* Return the assembly code for INSN, which has the operands given by
+ OPERANDS, and which branches to OPERANDS[1] if some condition is true.
+ BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
+ is in range of a direct branch. BRANCH_IF_FALSE is an inverted
+ version of BRANCH_IF_TRUE. */
-struct mips16_stub
+const char *
+mips_output_conditional_branch (rtx insn, rtx *operands,
+ const char *branch_if_true,
+ const char *branch_if_false)
{
- struct mips16_stub *next;
- char *name;
- int fpret;
-};
+ unsigned int length;
+ rtx taken, not_taken;
-static struct mips16_stub *mips16_stubs;
+ length = get_attr_length (insn);
+ if (length <= 8)
+ {
+ /* Just a simple conditional branch. */
+ mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
+ return branch_if_true;
+ }
-/* Emit code to return a double value from a mips16 stub. GPREG is the
- first GP reg to use, FPREG is the first FP reg to use. */
+ /* Generate a reversed branch around a direct jump. This fallback does
+ not use branch-likely instructions. */
+ mips_branch_likely = false;
+ not_taken = gen_label_rtx ();
+ taken = operands[1];
-static void
-mips16_fpret_double (int gpreg, int fpreg)
-{
- if (TARGET_64BIT)
- fprintf (asm_out_file, "\tdmfc1\t%s,%s\n",
- reg_names[gpreg], reg_names[fpreg]);
- else if (TARGET_FLOAT64)
+ /* Generate the reversed branch to NOT_TAKEN. */
+ operands[1] = not_taken;
+ output_asm_insn (branch_if_false, operands);
+
+ /* If INSN has a delay slot, we must provide delay slots for both the
+ branch to NOT_TAKEN and the conditional jump. We must also ensure
+ that INSN's delay slot is executed in the appropriate cases. */
+ if (final_sequence)
{
- fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
- reg_names[gpreg + WORDS_BIG_ENDIAN],
- reg_names[fpreg]);
- fprintf (asm_out_file, "\tmfhc1\t%s,%s\n",
- reg_names[gpreg + !WORDS_BIG_ENDIAN],
- reg_names[fpreg]);
+ /* This first delay slot will always be executed, so use INSN's
+ delay slot if is not annulled. */
+ if (!INSN_ANNULLED_BRANCH_P (insn))
+ {
+ final_scan_insn (XVECEXP (final_sequence, 0, 1),
+ asm_out_file, optimize, 1, NULL);
+ INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
+ }
+ else
+ output_asm_insn ("nop", 0);
+ fprintf (asm_out_file, "\n");
}
+
+ /* Output the unconditional branch to TAKEN. */
+ if (length <= 16)
+ output_asm_insn ("j\t%0%/", &taken);
else
{
- if (TARGET_BIG_ENDIAN)
- {
- fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
- reg_names[gpreg + 0],
- reg_names[fpreg + 1]);
- fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
- reg_names[gpreg + 1],
- reg_names[fpreg + 0]);
- }
- else
- {
- fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
- reg_names[gpreg + 0],
- reg_names[fpreg + 0]);
- fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
- reg_names[gpreg + 1],
- reg_names[fpreg + 1]);
- }
+ output_asm_insn (mips_output_load_label (), &taken);
+ output_asm_insn ("jr\t%@%]%/", 0);
}
-}
-/* Build a call stub for a mips16 call. A stub is needed if we are
- passing any floating point values which should go into the floating
- point registers. If we are, and the call turns out to be to a
- 32-bit function, the stub will be used to move the values into the
- floating point registers before calling the 32-bit function. The
- linker will magically adjust the function call to either the 16-bit
- function or the 32-bit stub, depending upon where the function call
- is actually defined.
+ /* Now deal with its delay slot; see above. */
+ if (final_sequence)
+ {
+ /* This delay slot will only be executed if the branch is taken.
+ Use INSN's delay slot if is annulled. */
+ if (INSN_ANNULLED_BRANCH_P (insn))
+ {
+ final_scan_insn (XVECEXP (final_sequence, 0, 1),
+ asm_out_file, optimize, 1, NULL);
+ INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
+ }
+ else
+ output_asm_insn ("nop", 0);
+ fprintf (asm_out_file, "\n");
+ }
- Similarly, we need a stub if the return value might come back in a
- floating point register.
+ /* Output NOT_TAKEN. */
+ targetm.asm_out.internal_label (asm_out_file, "L",
+ CODE_LABEL_NUMBER (not_taken));
+ return "";
+}
- RETVAL is the location of the return value, or null if this is
- a call rather than a call_value. FN is the address of the
- function and ARG_SIZE is the size of the arguments. FP_CODE
- is the code built by function_arg. This function returns a nonzero
- value if it builds the call instruction itself. */
+/* Return the assembly code for INSN, which branches to OPERANDS[1]
+ if some ordering condition is true. The condition is given by
+ OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
+ OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
+ its second is always zero. */
-int
-build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
+const char *
+mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
{
- int fpret = 0;
- const char *fnname;
- char *secname, *stubname;
- struct mips16_stub *l;
- tree stubid, stubdecl;
- int need_comma;
- unsigned int f;
-
- /* We don't need to do anything if we aren't in mips16 mode, or if
- we were invoked with the -msoft-float option. */
- if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
- return 0;
-
- /* Figure out whether the value might come back in a floating point
- register. */
- if (retval)
- fpret = mips_return_mode_in_fpr_p (GET_MODE (retval));
-
- /* We don't need to do anything if there were no floating point
- arguments and the value will not be returned in a floating point
- register. */
- if (fp_code == 0 && ! fpret)
- return 0;
-
- /* We don't need to do anything if this is a call to a special
- mips16 support function. */
- if (GET_CODE (fn) == SYMBOL_REF
- && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
- return 0;
+ const char *branch[2];
- /* This code will only work for o32 and o64 abis. The other ABI's
- require more sophisticated support. */
- gcc_assert (TARGET_OLDABI);
+ /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
+ Make BRANCH[0] branch on the inverse condition. */
+ switch (GET_CODE (operands[0]))
+ {
+ /* These cases are equivalent to comparisons against zero. */
+ case LEU:
+ inverted_p = !inverted_p;
+ /* Fall through. */
+ case GTU:
+ branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
+ branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
+ break;
- /* If we're calling via a function pointer, then we must always call
- via a stub. There are magic stubs provided in libgcc.a for each
- of the required cases. Each of them expects the function address
- to arrive in register $2. */
+ /* These cases are always true or always false. */
+ case LTU:
+ inverted_p = !inverted_p;
+ /* Fall through. */
+ case GEU:
+ branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
+ branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
+ break;
- if (GET_CODE (fn) != SYMBOL_REF)
- {
- char buf[30];
- tree id;
- rtx stub_fn, insn;
+ default:
+ branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
+ branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
+ break;
+ }
+ return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
+}
+\f
+/* Return the assembly code for DIV or DDIV instruction DIVISION, which has
+ the operands given by OPERANDS. Add in a divide-by-zero check if needed.
- /* ??? If this code is modified to support other ABI's, we need
- to handle PARALLEL return values here. */
+ When working around R4000 and R4400 errata, we need to make sure that
+ the division is not immediately followed by a shift[1][2]. We also
+ need to stop the division from being put into a branch delay slot[3].
+ The easiest way to avoid both problems is to add a nop after the
+ division. When a divide-by-zero check is needed, this nop can be
+ used to fill the branch delay slot.
- if (fpret)
- sprintf (buf, "__mips16_call_stub_%s_%d",
- mips16_call_stub_mode_suffix (GET_MODE (retval)),
- fp_code);
- else
- sprintf (buf, "__mips16_call_stub_%d",
- fp_code);
+ [1] If a double-word or a variable shift executes immediately
+ after starting an integer division, the shift may give an
+ incorrect result. See quotations of errata #16 and #28 from
+ "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
+ in mips.md for details.
- id = get_identifier (buf);
- stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
+ [2] A similar bug to [1] exists for all revisions of the
+ R4000 and the R4400 when run in an MC configuration.
+ From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
- mips_emit_move (gen_rtx_REG (Pmode, 2), fn);
+ "19. In this following sequence:
- if (retval == NULL_RTX)
- insn = gen_call_internal (stub_fn, arg_size);
- else
- insn = gen_call_value_internal (retval, stub_fn, arg_size);
- insn = emit_call_insn (insn);
+ ddiv (or ddivu or div or divu)
+ dsll32 (or dsrl32, dsra32)
- /* Put the register usage information on the CALL. */
- CALL_INSN_FUNCTION_USAGE (insn) =
- gen_rtx_EXPR_LIST (VOIDmode,
- gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
- CALL_INSN_FUNCTION_USAGE (insn));
+ if an MPT stall occurs, while the divide is slipping the cpu
+ pipeline, then the following double shift would end up with an
+ incorrect result.
- /* If we are handling a floating point return value, we need to
- save $18 in the function prologue. Putting a note on the
- call will mean that df_regs_ever_live_p ($18) will be true if the
- call is not eliminated, and we can check that in the prologue
- code. */
- if (fpret)
- CALL_INSN_FUNCTION_USAGE (insn) =
- gen_rtx_EXPR_LIST (VOIDmode,
- gen_rtx_USE (VOIDmode,
- gen_rtx_REG (word_mode, 18)),
- CALL_INSN_FUNCTION_USAGE (insn));
+ Workaround: The compiler needs to avoid generating any
+ sequence with divide followed by extended double shift."
- /* Return 1 to tell the caller that we've generated the call
- insn. */
- return 1;
- }
+ This erratum is also present in "MIPS R4400MC Errata, Processor
+ Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
+ & 3.0" as errata #10 and #4, respectively.
- /* We know the function we are going to call. If we have already
- built a stub, we don't need to do anything further. */
+ [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
+ (also valid for MIPS R4000MC processors):
- fnname = XSTR (fn, 0);
- for (l = mips16_stubs; l != NULL; l = l->next)
- if (strcmp (l->name, fnname) == 0)
- break;
+ "52. R4000SC: This bug does not apply for the R4000PC.
- if (l == NULL)
- {
- /* Build a special purpose stub. When the linker sees a
- function call in mips16 code, it will check where the target
- is defined. If the target is a 32-bit call, the linker will
- search for the section defined here. It can tell which
- symbol this section is associated with by looking at the
- relocation information (the name is unreliable, since this
- might be a static function). If such a section is found, the
- linker will redirect the call to the start of the magic
- section.
-
- If the function does not return a floating point value, the
- special stub section is named
- .mips16.call.FNNAME
+ There are two flavors of this bug:
- If the function does return a floating point value, the stub
- section is named
- .mips16.call.fp.FNNAME
- */
+ 1) If the instruction just after divide takes an RF exception
+ (tlb-refill, tlb-invalid) and gets an instruction cache
+ miss (both primary and secondary) and the line which is
+ currently in secondary cache at this index had the first
+ data word, where the bits 5..2 are set, then R4000 would
+ get a wrong result for the div.
- secname = (char *) alloca (strlen (fnname) + 40);
- sprintf (secname, ".mips16.call.%s%s",
- fpret ? "fp." : "",
- fnname);
- stubname = (char *) alloca (strlen (fnname) + 20);
- sprintf (stubname, "__call_stub_%s%s",
- fpret ? "fp_" : "",
- fnname);
- stubid = get_identifier (stubname);
- stubdecl = build_decl (FUNCTION_DECL, stubid,
- build_function_type (void_type_node, NULL_TREE));
- DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
- DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
+ ##1
+ nop
+ div r8, r9
+ ------------------- # end-of page. -tlb-refill
+ nop
+ ##2
+ nop
+ div r8, r9
+ ------------------- # end-of page. -tlb-invalid
+ nop
- fprintf (asm_out_file, "\t# Stub function to call %s%s (",
- (fpret
- ? (GET_MODE (retval) == SFmode ? "float " : "double ")
- : ""),
- fnname);
- need_comma = 0;
- for (f = (unsigned int) fp_code; f != 0; f >>= 2)
- {
- fprintf (asm_out_file, "%s%s",
- need_comma ? ", " : "",
- (f & 3) == 1 ? "float" : "double");
- need_comma = 1;
- }
- fprintf (asm_out_file, ")\n");
+ 2) If the divide is in the taken branch delay slot, where the
+ target takes RF exception and gets an I-cache miss for the
+ exception vector or where I-cache miss occurs for the
+ target address, under the above mentioned scenarios, the
+ div would get wrong results.
- fprintf (asm_out_file, "\t.set\tnomips16\n");
- assemble_start_function (stubdecl, stubname);
+ ##1
+ j r2 # to next page mapped or unmapped
+ div r8,r9 # this bug would be there as long
+ # as there is an ICache miss and
+ nop # the "data pattern" is present
- if (!FUNCTION_NAME_ALREADY_DECLARED)
- {
- fputs ("\t.ent\t", asm_out_file);
- assemble_name (asm_out_file, stubname);
- fputs ("\n", asm_out_file);
+ ##2
+ beq r0, r0, NextPage # to Next page
+ div r8,r9
+ nop
- assemble_name (asm_out_file, stubname);
- fputs (":\n", asm_out_file);
- }
+ This bug is present for div, divu, ddiv, and ddivu
+ instructions.
- /* We build the stub code by hand. That's the only way we can
- do it, since we can't generate 32-bit code during a 16-bit
- compilation. */
+ Workaround: For item 1), OS could make sure that the next page
+ after the divide instruction is also mapped. For item 2), the
+ compiler could make sure that the divide instruction is not in
+ the branch delay slot."
- /* We don't want the assembler to insert any nops here. */
- fprintf (asm_out_file, "\t.set\tnoreorder\n");
+ These processors have PRId values of 0x00004220 and 0x00004300 for
+ the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
- mips16_fp_args (asm_out_file, fp_code, 0);
+const char *
+mips_output_division (const char *division, rtx *operands)
+{
+ const char *s;
- if (! fpret)
+ s = division;
+ if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
+ {
+ output_asm_insn (s, operands);
+ s = "nop";
+ }
+ if (TARGET_CHECK_ZERO_DIV)
+ {
+ if (TARGET_MIPS16)
{
- fprintf (asm_out_file, "\t.set\tnoat\n");
- fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
- fnname);
- fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
- fprintf (asm_out_file, "\t.set\tat\n");
- /* Unfortunately, we can't fill the jump delay slot. We
- can't fill with one of the mtc1 instructions, because the
- result is not available for one instruction, so if the
- very first instruction in the function refers to the
- register, it will see the wrong value. */
- fprintf (asm_out_file, "\tnop\n");
+ output_asm_insn (s, operands);
+ s = "bnez\t%2,1f\n\tbreak\t7\n1:";
}
+ else if (GENERATE_DIVIDE_TRAPS)
+ {
+ output_asm_insn (s, operands);
+ s = "teq\t%2,%.,7";
+ }
else
{
- fprintf (asm_out_file, "\tmove\t%s,%s\n",
- reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
- fprintf (asm_out_file, "\tjal\t%s\n", fnname);
- /* As above, we can't fill the delay slot. */
- fprintf (asm_out_file, "\tnop\n");
- if (GET_MODE (retval) == SFmode)
- fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
- reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
- else if (GET_MODE (retval) == SCmode)
- {
- fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
- reg_names[GP_REG_FIRST + 2],
- reg_names[FP_REG_FIRST + 0]);
- fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
- reg_names[GP_REG_FIRST + 3],
- reg_names[FP_REG_FIRST + MAX_FPRS_PER_FMT]);
- }
- else if (GET_MODE (retval) == DFmode
- || GET_MODE (retval) == V2SFmode)
- {
- mips16_fpret_double (GP_REG_FIRST + 2, FP_REG_FIRST + 0);
- }
- else if (GET_MODE (retval) == DCmode)
- {
- mips16_fpret_double (GP_REG_FIRST + 2,
- FP_REG_FIRST + 0);
- mips16_fpret_double (GP_REG_FIRST + 4,
- FP_REG_FIRST + MAX_FPRS_PER_FMT);
- }
- else
- {
- if (TARGET_BIG_ENDIAN)
- {
- fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
- reg_names[GP_REG_FIRST + 2],
- reg_names[FP_REG_FIRST + 1]);
- fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
- reg_names[GP_REG_FIRST + 3],
- reg_names[FP_REG_FIRST + 0]);
- }
- else
- {
- fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
- reg_names[GP_REG_FIRST + 2],
- reg_names[FP_REG_FIRST + 0]);
- fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
- reg_names[GP_REG_FIRST + 3],
- reg_names[FP_REG_FIRST + 1]);
- }
- }
- fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
- /* As above, we can't fill the delay slot. */
- fprintf (asm_out_file, "\tnop\n");
+ output_asm_insn ("%(bne\t%2,%.,1f", operands);
+ output_asm_insn (s, operands);
+ s = "break\t7%)\n1:";
}
+ }
+ return s;
+}
+\f
+/* Return true if IN_INSN is a multiply-add or multiply-subtract
+ instruction and if OUT_INSN assigns to the accumulator operand. */
- fprintf (asm_out_file, "\t.set\treorder\n");
+bool
+mips_linked_madd_p (rtx out_insn, rtx in_insn)
+{
+ rtx x;
-#ifdef ASM_DECLARE_FUNCTION_SIZE
- ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
-#endif
+ x = single_set (in_insn);
+ if (x == 0)
+ return false;
- if (!FUNCTION_NAME_ALREADY_DECLARED)
- {
- fputs ("\t.end\t", asm_out_file);
- assemble_name (asm_out_file, stubname);
- fputs ("\n", asm_out_file);
- }
+ x = SET_SRC (x);
- /* Record this stub. */
- l = (struct mips16_stub *) xmalloc (sizeof *l);
- l->name = xstrdup (fnname);
- l->fpret = fpret;
- l->next = mips16_stubs;
- mips16_stubs = l;
- }
-
- /* If we expect a floating point return value, but we've built a
- stub which does not expect one, then we're in trouble. We can't
- use the existing stub, because it won't handle the floating point
- value. We can't build a new stub, because the linker won't know
- which stub to use for the various calls in this object file.
- Fortunately, this case is illegal, since it means that a function
- was declared in two different ways in a single compilation. */
- if (fpret && ! l->fpret)
- error ("cannot handle inconsistent calls to %qs", fnname);
-
- /* If we are calling a stub which handles a floating point return
- value, we need to arrange to save $18 in the prologue. We do
- this by marking the function call as using the register. The
- prologue will later see that it is used, and emit code to save
- it. */
-
- if (l->fpret)
- {
- rtx insn;
-
- if (retval == NULL_RTX)
- insn = gen_call_internal (fn, arg_size);
- else
- insn = gen_call_value_internal (retval, fn, arg_size);
- insn = emit_call_insn (insn);
-
- CALL_INSN_FUNCTION_USAGE (insn) =
- gen_rtx_EXPR_LIST (VOIDmode,
- gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
- CALL_INSN_FUNCTION_USAGE (insn));
+ if (GET_CODE (x) == PLUS
+ && GET_CODE (XEXP (x, 0)) == MULT
+ && reg_set_p (XEXP (x, 1), out_insn))
+ return true;
- /* Return 1 to tell the caller that we've generated the call
- insn. */
- return 1;
- }
+ if (GET_CODE (x) == MINUS
+ && GET_CODE (XEXP (x, 1)) == MULT
+ && reg_set_p (XEXP (x, 0), out_insn))
+ return true;
- /* Return 0 to let the caller generate the call insn. */
- return 0;
+ return false;
}
-/* An entry in the mips16 constant pool. VALUE is the pool constant,
- MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
+/* True if the dependency between OUT_INSN and IN_INSN is on the store
+ data rather than the address. We need this because the cprestore
+ pattern is type "store", but is defined using an UNSPEC_VOLATILE,
+ which causes the default routine to abort. We just return false
+ for that case. */
-struct mips16_constant {
- struct mips16_constant *next;
- rtx value;
- rtx label;
- enum machine_mode mode;
-};
+bool
+mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
+{
+ if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
+ return false;
-/* Information about an incomplete mips16 constant pool. FIRST is the
- first constant, HIGHEST_ADDRESS is the highest address that the first
- byte of the pool can have, and INSN_ADDRESS is the current instruction
- address. */
+ return !store_data_bypass_p (out_insn, in_insn);
+}
+\f
+/* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
+ dependencies have no cost, except on the 20Kc where output-dependence
+ is treated like input-dependence. */
-struct mips16_constant_pool {
- struct mips16_constant *first;
- int highest_address;
- int insn_address;
-};
+static int
+mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
+ rtx dep ATTRIBUTE_UNUSED, int cost)
+{
+ if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
+ && TUNE_20KC)
+ return cost;
+ if (REG_NOTE_KIND (link) != 0)
+ return 0;
+ return cost;
+}
-/* Add constant VALUE to POOL and return its label. MODE is the
- value's mode (used for CONST_INTs, etc.). */
+/* Return the number of instructions that can be issued per cycle. */
-static rtx
-add_constant (struct mips16_constant_pool *pool,
- rtx value, enum machine_mode mode)
+static int
+mips_issue_rate (void)
{
- struct mips16_constant **p, *c;
- bool first_of_size_p;
+ switch (mips_tune)
+ {
+ case PROCESSOR_74KC:
+ case PROCESSOR_74KF2_1:
+ case PROCESSOR_74KF1_1:
+ case PROCESSOR_74KF3_2:
+ /* The 74k is not strictly quad-issue cpu, but can be seen as one
+ by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
+ but in reality only a maximum of 3 insns can be issued as
+ floating-point loads and stores also require a slot in the
+ AGEN pipe. */
+ return 4;
- /* See whether the constant is already in the pool. If so, return the
- existing label, otherwise leave P pointing to the place where the
- constant should be added.
+ case PROCESSOR_20KC:
+ case PROCESSOR_R4130:
+ case PROCESSOR_R5400:
+ case PROCESSOR_R5500:
+ case PROCESSOR_R7000:
+ case PROCESSOR_R9000:
+ return 2;
- Keep the pool sorted in increasing order of mode size so that we can
- reduce the number of alignments needed. */
- first_of_size_p = true;
- for (p = &pool->first; *p != 0; p = &(*p)->next)
- {
- if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
- return (*p)->label;
- if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
- break;
- if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
- first_of_size_p = false;
+ case PROCESSOR_SB1:
+ case PROCESSOR_SB1A:
+ /* This is actually 4, but we get better performance if we claim 3.
+ This is partly because of unwanted speculative code motion with the
+ larger number, and partly because in most common cases we can't
+ reach the theoretical max of 4. */
+ return 3;
+
+ default:
+ return 1;
}
+}
- /* In the worst case, the constant needed by the earliest instruction
- will end up at the end of the pool. The entire pool must then be
- accessible from that instruction.
+/* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
+ be as wide as the scheduling freedom in the DFA. */
- When adding the first constant, set the pool's highest address to
- the address of the first out-of-range byte. Adjust this address
- downwards each time a new constant is added. */
- if (pool->first == 0)
- /* For pc-relative lw, addiu and daddiu instructions, the base PC value
- is the address of the instruction with the lowest two bits clear.
- The base PC value for ld has the lowest three bits clear. Assume
- the worst case here. */
- pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
- pool->highest_address -= GET_MODE_SIZE (mode);
- if (first_of_size_p)
- /* Take into account the worst possible padding due to alignment. */
- pool->highest_address -= GET_MODE_SIZE (mode) - 1;
+static int
+mips_multipass_dfa_lookahead (void)
+{
+ /* Can schedule up to 4 of the 6 function units in any one cycle. */
+ if (TUNE_SB1)
+ return 4;
- /* Create a new entry. */
- c = (struct mips16_constant *) xmalloc (sizeof *c);
- c->value = value;
- c->mode = mode;
- c->label = gen_label_rtx ();
- c->next = *p;
- *p = c;
+ return 0;
+}
+\f
+/* Remove the instruction at index LOWER from ready queue READY and
+ reinsert it in front of the instruction at index HIGHER. LOWER must
+ be <= HIGHER. */
- return c->label;
+static void
+mips_promote_ready (rtx *ready, int lower, int higher)
+{
+ rtx new_head;
+ int i;
+
+ new_head = ready[lower];
+ for (i = lower; i < higher; i++)
+ ready[i] = ready[i + 1];
+ ready[i] = new_head;
}
-/* Output constant VALUE after instruction INSN and return the last
- instruction emitted. MODE is the mode of the constant. */
+/* If the priority of the instruction at POS2 in the ready queue READY
+ is within LIMIT units of that of the instruction at POS1, swap the
+ instructions if POS2 is not already less than POS1. */
-static rtx
-dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
+static void
+mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
{
- switch (GET_MODE_CLASS (mode))
+ if (pos1 < pos2
+ && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
{
- case MODE_INT:
- {
- rtx size = GEN_INT (GET_MODE_SIZE (mode));
- return emit_insn_after (gen_consttable_int (value, size), insn);
- }
-
- case MODE_FLOAT:
- return emit_insn_after (gen_consttable_float (value), insn);
-
- case MODE_VECTOR_FLOAT:
- case MODE_VECTOR_INT:
- {
- int i;
- for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
- insn = dump_constants_1 (GET_MODE_INNER (mode),
- CONST_VECTOR_ELT (value, i), insn);
- return insn;
- }
+ rtx temp;
- default:
- gcc_unreachable ();
+ temp = ready[pos1];
+ ready[pos1] = ready[pos2];
+ ready[pos2] = temp;
}
}
+\f
+/* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
+ that may clobber hi or lo. */
+static rtx mips_macc_chains_last_hilo;
+/* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
+ been scheduled, updating mips_macc_chains_last_hilo appropriately. */
-/* Dump out the constants in CONSTANTS after INSN. */
+static void
+mips_macc_chains_record (rtx insn)
+{
+ if (get_attr_may_clobber_hilo (insn))
+ mips_macc_chains_last_hilo = insn;
+}
+
+/* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
+ has NREADY elements, looking for a multiply-add or multiply-subtract
+ instruction that is cumulative with mips_macc_chains_last_hilo.
+ If there is one, promote it ahead of anything else that might
+ clobber hi or lo. */
static void
-dump_constants (struct mips16_constant *constants, rtx insn)
+mips_macc_chains_reorder (rtx *ready, int nready)
{
- struct mips16_constant *c, *next;
- int align;
+ int i, j;
- align = 0;
- for (c = constants; c != NULL; c = next)
- {
- /* If necessary, increase the alignment of PC. */
- if (align < GET_MODE_SIZE (c->mode))
+ if (mips_macc_chains_last_hilo != 0)
+ for (i = nready - 1; i >= 0; i--)
+ if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
{
- int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
- insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
+ for (j = nready - 1; j > i; j--)
+ if (recog_memoized (ready[j]) >= 0
+ && get_attr_may_clobber_hilo (ready[j]))
+ {
+ mips_promote_ready (ready, i, j);
+ break;
+ }
+ break;
}
- align = GET_MODE_SIZE (c->mode);
+}
+\f
+/* The last instruction to be scheduled. */
+static rtx vr4130_last_insn;
- insn = emit_label_after (c->label, insn);
- insn = dump_constants_1 (c->mode, c->value, insn);
+/* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
+ points to an rtx that is initially an instruction. Nullify the rtx
+ if the instruction uses the value of register X. */
- next = c->next;
- free (c);
- }
+static void
+vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
+ void *data)
+{
+ rtx *insn_ptr;
- emit_barrier_after (insn);
+ insn_ptr = (rtx *) data;
+ if (REG_P (x)
+ && *insn_ptr != 0
+ && reg_referenced_p (x, PATTERN (*insn_ptr)))
+ *insn_ptr = 0;
}
-/* Return the length of instruction INSN. */
+/* Return true if there is true register dependence between vr4130_last_insn
+ and INSN. */
-static int
-mips16_insn_length (rtx insn)
+static bool
+vr4130_true_reg_dependence_p (rtx insn)
{
- if (JUMP_P (insn))
- {
- rtx body = PATTERN (insn);
- if (GET_CODE (body) == ADDR_VEC)
- return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
- if (GET_CODE (body) == ADDR_DIFF_VEC)
- return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
- }
- return get_attr_length (insn);
+ note_stores (PATTERN (vr4130_last_insn),
+ vr4130_true_reg_dependence_p_1, &insn);
+ return insn == 0;
}
-/* Rewrite *X so that constant pool references refer to the constant's
- label instead. DATA points to the constant pool structure. */
+/* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
+ the ready queue and that INSN2 is the instruction after it, return
+ true if it is worth promoting INSN2 ahead of INSN1. Look for cases
+ in which INSN1 and INSN2 can probably issue in parallel, but for
+ which (INSN2, INSN1) should be less sensitive to instruction
+ alignment than (INSN1, INSN2). See 4130.md for more details. */
-static int
-mips16_rewrite_pool_refs (rtx *x, void *data)
+static bool
+vr4130_swap_insns_p (rtx insn1, rtx insn2)
{
- struct mips16_constant_pool *pool = data;
- rtx base, offset, label;
-
- if (MEM_P (*x))
- x = &XEXP (*x, 0);
- else if (!TARGET_MIPS16_TEXT_LOADS)
- return 0;
-
- split_const (*x, &base, &offset);
- if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
- {
- label = add_constant (pool, get_pool_constant (base),
- get_pool_mode (base));
- base = gen_rtx_LABEL_REF (Pmode, label);
- *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
- return -1;
- }
- return GET_CODE (*x) == CONST ? -1 : 0;
-}
+ sd_iterator_def sd_it;
+ dep_t dep;
-/* Build MIPS16 constant pools. */
+ /* Check for the following case:
-static void
-mips16_lay_out_constants (void)
-{
- struct mips16_constant_pool pool;
- rtx insn, barrier;
+ 1) there is some other instruction X with an anti dependence on INSN1;
+ 2) X has a higher priority than INSN2; and
+ 3) X is an arithmetic instruction (and thus has no unit restrictions).
- if (!TARGET_MIPS16_PCREL_LOADS)
- return;
+ If INSN1 is the last instruction blocking X, it would better to
+ choose (INSN1, X) over (INSN2, INSN1). */
+ FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
+ if (DEP_TYPE (dep) == REG_DEP_ANTI
+ && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
+ && recog_memoized (DEP_CON (dep)) >= 0
+ && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
+ return false;
- barrier = 0;
- memset (&pool, 0, sizeof (pool));
- for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+ if (vr4130_last_insn != 0
+ && recog_memoized (insn1) >= 0
+ && recog_memoized (insn2) >= 0)
{
- /* Rewrite constant pool references in INSN. */
- if (INSN_P (insn))
- for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
-
- pool.insn_address += mips16_insn_length (insn);
-
- if (pool.first != NULL)
+ /* See whether INSN1 and INSN2 use different execution units,
+ or if they are both ALU-type instructions. If so, they can
+ probably execute in parallel. */
+ enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
+ enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
+ if (class1 != class2 || class1 == VR4130_CLASS_ALU)
{
- /* If there are no natural barriers between the first user of
- the pool and the highest acceptable address, we'll need to
- create a new instruction to jump around the constant pool.
- In the worst case, this instruction will be 4 bytes long.
-
- If it's too late to do this transformation after INSN,
- do it immediately before INSN. */
- if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
- {
- rtx label, jump;
-
- label = gen_label_rtx ();
-
- jump = emit_jump_insn_before (gen_jump (label), insn);
- JUMP_LABEL (jump) = label;
- LABEL_NUSES (label) = 1;
- barrier = emit_barrier_after (jump);
-
- emit_label_after (label, barrier);
- pool.insn_address += 4;
- }
+ /* If only one of the instructions has a dependence on
+ vr4130_last_insn, prefer to schedule the other one first. */
+ bool dep1_p = vr4130_true_reg_dependence_p (insn1);
+ bool dep2_p = vr4130_true_reg_dependence_p (insn2);
+ if (dep1_p != dep2_p)
+ return dep1_p;
- /* See whether the constant pool is now out of range of the first
- user. If so, output the constants after the previous barrier.
- Note that any instructions between BARRIER and INSN (inclusive)
- will use negative offsets to refer to the pool. */
- if (pool.insn_address > pool.highest_address)
- {
- dump_constants (pool.first, barrier);
- pool.first = NULL;
- barrier = 0;
- }
- else if (BARRIER_P (insn))
- barrier = insn;
+ /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
+ is not an ALU-type instruction and if INSN1 uses the same
+ execution unit. (Note that if this condition holds, we already
+ know that INSN2 uses a different execution unit.) */
+ if (class1 != VR4130_CLASS_ALU
+ && recog_memoized (vr4130_last_insn) >= 0
+ && class1 == get_attr_vr4130_class (vr4130_last_insn))
+ return true;
}
}
- dump_constants (pool.first, get_last_insn ());
+ return false;
}
-\f
-/* A temporary variable used by for_each_rtx callbacks, etc. */
-static rtx mips_sim_insn;
-
-/* A structure representing the state of the processor pipeline.
- Used by the mips_sim_* family of functions. */
-struct mips_sim {
- /* The maximum number of instructions that can be issued in a cycle.
- (Caches mips_issue_rate.) */
- unsigned int issue_rate;
-
- /* The current simulation time. */
- unsigned int time;
-
- /* How many more instructions can be issued in the current cycle. */
- unsigned int insns_left;
-
- /* LAST_SET[X].INSN is the last instruction to set register X.
- LAST_SET[X].TIME is the time at which that instruction was issued.
- INSN is null if no instruction has yet set register X. */
- struct {
- rtx insn;
- unsigned int time;
- } last_set[FIRST_PSEUDO_REGISTER];
-
- /* The pipeline's current DFA state. */
- state_t dfa_state;
-};
-/* Reset STATE to the initial simulation state. */
+/* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
+ queue with at least two instructions. Swap the first two if
+ vr4130_swap_insns_p says that it could be worthwhile. */
static void
-mips_sim_reset (struct mips_sim *state)
+vr4130_reorder (rtx *ready, int nready)
{
- state->time = 0;
- state->insns_left = state->issue_rate;
- memset (&state->last_set, 0, sizeof (state->last_set));
- state_reset (state->dfa_state);
+ if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
+ mips_promote_ready (ready, nready - 2, nready - 1);
}
+\f
+/* Record whether last 74k AGEN instruction was a load or store. */
+static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
-/* Initialize STATE before its first use. DFA_STATE points to an
- allocated but uninitialized DFA state. */
+/* Initialize mips_last_74k_agen_insn from INSN. A null argument
+ resets to TYPE_UNKNOWN state. */
static void
-mips_sim_init (struct mips_sim *state, state_t dfa_state)
+mips_74k_agen_init (rtx insn)
{
- state->issue_rate = mips_issue_rate ();
- state->dfa_state = dfa_state;
- mips_sim_reset (state);
+ if (!insn || !NONJUMP_INSN_P (insn))
+ mips_last_74k_agen_insn = TYPE_UNKNOWN;
+ else
+ {
+ enum attr_type type = get_attr_type (insn);
+ if (type == TYPE_LOAD || type == TYPE_STORE)
+ mips_last_74k_agen_insn = type;
+ }
}
-/* Advance STATE by one clock cycle. */
+/* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
+ loads to be grouped together, and multiple stores to be grouped
+ together. Swap things around in the ready queue to make this happen. */
static void
-mips_sim_next_cycle (struct mips_sim *state)
+mips_74k_agen_reorder (rtx *ready, int nready)
{
- state->time++;
- state->insns_left = state->issue_rate;
- state_transition (state->dfa_state, 0);
-}
+ int i;
+ int store_pos, load_pos;
-/* Advance simulation state STATE until instruction INSN can read
- register REG. */
+ store_pos = -1;
+ load_pos = -1;
-static void
-mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
-{
- unsigned int i;
+ for (i = nready - 1; i >= 0; i--)
+ {
+ rtx insn = ready[i];
+ if (USEFUL_INSN_P (insn))
+ switch (get_attr_type (insn))
+ {
+ case TYPE_STORE:
+ if (store_pos == -1)
+ store_pos = i;
+ break;
- for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
- if (state->last_set[REGNO (reg) + i].insn != 0)
- {
- unsigned int t;
+ case TYPE_LOAD:
+ if (load_pos == -1)
+ load_pos = i;
+ break;
- t = state->last_set[REGNO (reg) + i].time;
- t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
- while (state->time < t)
- mips_sim_next_cycle (state);
+ default:
+ break;
+ }
}
-}
-/* A for_each_rtx callback. If *X is a register, advance simulation state
- DATA until mips_sim_insn can read the register's value. */
+ if (load_pos == -1 || store_pos == -1)
+ return;
-static int
-mips_sim_wait_regs_2 (rtx *x, void *data)
-{
- if (REG_P (*x))
- mips_sim_wait_reg (data, mips_sim_insn, *x);
- return 0;
+ switch (mips_last_74k_agen_insn)
+ {
+ case TYPE_UNKNOWN:
+ /* Prefer to schedule loads since they have a higher latency. */
+ case TYPE_LOAD:
+ /* Swap loads to the front of the queue. */
+ mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
+ break;
+ case TYPE_STORE:
+ /* Swap stores to the front of the queue. */
+ mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
+ break;
+ default:
+ break;
+ }
}
-
-/* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
+\f
+/* Implement TARGET_SCHED_INIT. */
static void
-mips_sim_wait_regs_1 (rtx *x, void *data)
+mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
+ int max_ready ATTRIBUTE_UNUSED)
{
- for_each_rtx (x, mips_sim_wait_regs_2, data);
+ mips_macc_chains_last_hilo = 0;
+ vr4130_last_insn = 0;
+ mips_74k_agen_init (NULL_RTX);
}
-/* Advance simulation state STATE until all of INSN's register
- dependencies are satisfied. */
+/* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
-static void
-mips_sim_wait_regs (struct mips_sim *state, rtx insn)
+static int
+mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
+ rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
{
- mips_sim_insn = insn;
- note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
-}
-
-/* Advance simulation state STATE until the units required by
- instruction INSN are available. */
-
-static void
-mips_sim_wait_units (struct mips_sim *state, rtx insn)
-{
- state_t tmp_state;
+ if (!reload_completed
+ && TUNE_MACC_CHAINS
+ && *nreadyp > 0)
+ mips_macc_chains_reorder (ready, *nreadyp);
- tmp_state = alloca (state_size ());
- while (state->insns_left == 0
- || (memcpy (tmp_state, state->dfa_state, state_size ()),
- state_transition (tmp_state, insn) >= 0))
- mips_sim_next_cycle (state);
-}
+ if (reload_completed
+ && TUNE_MIPS4130
+ && !TARGET_VR4130_ALIGN
+ && *nreadyp > 1)
+ vr4130_reorder (ready, *nreadyp);
-/* Advance simulation state STATE until INSN is ready to issue. */
+ if (TUNE_74K)
+ mips_74k_agen_reorder (ready, *nreadyp);
-static void
-mips_sim_wait_insn (struct mips_sim *state, rtx insn)
-{
- mips_sim_wait_regs (state, insn);
- mips_sim_wait_units (state, insn);
+ return mips_issue_rate ();
}
-/* mips_sim_insn has just set X. Update the LAST_SET array
- in simulation state DATA. */
+/* Implement TARGET_SCHED_VARIABLE_ISSUE. */
-static void
-mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
+static int
+mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
+ rtx insn, int more)
{
- struct mips_sim *state;
- unsigned int i;
-
- state = data;
- if (REG_P (x))
- for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
- {
- state->last_set[REGNO (x) + i].insn = mips_sim_insn;
- state->last_set[REGNO (x) + i].time = state->time;
- }
+ /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
+ if (USEFUL_INSN_P (insn))
+ {
+ more--;
+ if (!reload_completed && TUNE_MACC_CHAINS)
+ mips_macc_chains_record (insn);
+ vr4130_last_insn = insn;
+ if (TUNE_74K)
+ mips_74k_agen_init (insn);
+ }
+ return more;
}
+\f
+/* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
+ return the first operand of the associated PREF or PREFX insn. */
-/* Issue instruction INSN in scheduler state STATE. Assume that INSN
- can issue immediately (i.e., that mips_sim_wait_insn has already
- been called). */
-
-static void
-mips_sim_issue_insn (struct mips_sim *state, rtx insn)
+rtx
+mips_prefetch_cookie (rtx write, rtx locality)
{
- state_transition (state->dfa_state, insn);
- state->insns_left--;
-
- mips_sim_insn = insn;
- note_stores (PATTERN (insn), mips_sim_record_set, state);
-}
+ /* store_streamed / load_streamed. */
+ if (INTVAL (locality) <= 0)
+ return GEN_INT (INTVAL (write) + 4);
-/* Simulate issuing a NOP in state STATE. */
+ /* store / load. */
+ if (INTVAL (locality) <= 2)
+ return write;
-static void
-mips_sim_issue_nop (struct mips_sim *state)
-{
- if (state->insns_left == 0)
- mips_sim_next_cycle (state);
- state->insns_left--;
+ /* store_retained / load_retained. */
+ return GEN_INT (INTVAL (write) + 6);
}
+\f
+/* This structure describes a single built-in function. */
+struct mips_builtin_description {
+ /* The code of the main .md file instruction. See mips_builtin_type
+ for more information. */
+ enum insn_code icode;
-/* Update simulation state STATE so that it's ready to accept the instruction
- after INSN. INSN should be part of the main rtl chain, not a member of a
- SEQUENCE. */
+ /* The floating-point comparison code to use with ICODE, if any. */
+ enum mips_fp_condition cond;
-static void
-mips_sim_finish_insn (struct mips_sim *state, rtx insn)
-{
- /* If INSN is a jump with an implicit delay slot, simulate a nop. */
- if (JUMP_P (insn))
- mips_sim_issue_nop (state);
+ /* The name of the built-in function. */
+ const char *name;
- switch (GET_CODE (SEQ_BEGIN (insn)))
- {
- case CODE_LABEL:
- case CALL_INSN:
- /* We can't predict the processor state after a call or label. */
- mips_sim_reset (state);
- break;
+ /* Specifies how the function should be expanded. */
+ enum mips_builtin_type builtin_type;
- case JUMP_INSN:
- /* The delay slots of branch likely instructions are only executed
- when the branch is taken. Therefore, if the caller has simulated
- the delay slot instruction, STATE does not really reflect the state
- of the pipeline for the instruction after the delay slot. Also,
- branch likely instructions tend to incur a penalty when not taken,
- so there will probably be an extra delay between the branch and
- the instruction after the delay slot. */
- if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
- mips_sim_reset (state);
- break;
+ /* The function's prototype. */
+ enum mips_function_type function_type;
- default:
- break;
- }
-}
-\f
-/* The VR4130 pipeline issues aligned pairs of instructions together,
- but it stalls the second instruction if it depends on the first.
- In order to cut down the amount of logic required, this dependence
- check is not based on a full instruction decode. Instead, any non-SPECIAL
- instruction is assumed to modify the register specified by bits 20-16
- (which is usually the "rt" field).
+ /* The target flags required for this function. */
+ int target_flags;
+};
- In beq, beql, bne and bnel instructions, the rt field is actually an
- input, so we can end up with a false dependence between the branch
- and its delay slot. If this situation occurs in instruction INSN,
- try to avoid it by swapping rs and rt. */
+/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
+ FUNCTION_TYPE and TARGET_FLAGS are mips_builtin_description fields. */
+#define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+ { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
+ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
-static void
-vr4130_avoid_branch_rt_conflict (rtx insn)
-{
- rtx first, second;
+/* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
+ require TARGET_FLAGS. */
+#define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
+ { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
+ "__builtin_mips_" #INSN "_" #COND "_s", \
+ MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
+ { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
+ "__builtin_mips_" #INSN "_" #COND "_d", \
+ MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
- first = SEQ_BEGIN (insn);
- second = SEQ_END (insn);
- if (JUMP_P (first)
- && NONJUMP_INSN_P (second)
- && GET_CODE (PATTERN (first)) == SET
- && GET_CODE (SET_DEST (PATTERN (first))) == PC
- && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
- {
- /* Check for the right kind of condition. */
- rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
- if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
- && REG_P (XEXP (cond, 0))
- && REG_P (XEXP (cond, 1))
- && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
- && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
- {
- /* SECOND mentions the rt register but not the rs register. */
- rtx tmp = XEXP (cond, 0);
- XEXP (cond, 0) = XEXP (cond, 1);
- XEXP (cond, 1) = tmp;
- }
- }
-}
+/* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
+ The lower and upper forms require TARGET_FLAGS while the any and all
+ forms require MASK_MIPS3D. */
+#define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
+ { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
+ "__builtin_mips_any_" #INSN "_" #COND "_ps", \
+ MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
+ { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
+ "__builtin_mips_all_" #INSN "_" #COND "_ps", \
+ MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
+ { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
+ "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
+ MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
+ { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
+ "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
+ MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
-/* Implement -mvr4130-align. Go through each basic block and simulate the
- processor pipeline. If we find that a pair of instructions could execute
- in parallel, and the first of those instruction is not 8-byte aligned,
- insert a nop to make it aligned. */
+/* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
+ require MASK_MIPS3D. */
+#define CMP_4S_BUILTINS(INSN, COND) \
+ { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
+ "__builtin_mips_any_" #INSN "_" #COND "_4s", \
+ MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
+ MASK_MIPS3D }, \
+ { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
+ "__builtin_mips_all_" #INSN "_" #COND "_4s", \
+ MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
+ MASK_MIPS3D }
-static void
-vr4130_align_insns (void)
-{
- struct mips_sim state;
- rtx insn, subinsn, last, last2, next;
- bool aligned_p;
+/* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
+ instruction requires TARGET_FLAGS. */
+#define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
+ { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
+ "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
+ MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
+ TARGET_FLAGS }, \
+ { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
+ "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
+ MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
+ TARGET_FLAGS }
- dfa_start ();
+/* Define all the built-in functions related to C.cond.fmt condition COND. */
+#define CMP_BUILTINS(COND) \
+ MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
+ MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
+ CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
+ CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
+ CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
+ CMP_4S_BUILTINS (c, COND), \
+ CMP_4S_BUILTINS (cabs, COND)
- /* LAST is the last instruction before INSN to have a nonzero length.
- LAST2 is the last such instruction before LAST. */
- last = 0;
- last2 = 0;
+static const struct mips_builtin_description mips_ps_bdesc[] = {
+ DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
+ DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
+ DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
+ DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
+ DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
+ DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
+ DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
+ DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
- /* ALIGNED_P is true if INSN is known to be at an aligned address. */
- aligned_p = true;
+ DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
+ MASK_PAIRED_SINGLE_FLOAT),
+ DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
+ DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
+ DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
+ DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
- mips_sim_init (&state, alloca (state_size ()));
- for (insn = get_insns (); insn != 0; insn = next)
- {
- unsigned int length;
+ DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
+ DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
+ DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
+ DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
+ DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
+ DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
- next = NEXT_INSN (insn);
+ DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
+ DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
+ DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
+ DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
+ DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
+ DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
- /* See the comment above vr4130_avoid_branch_rt_conflict for details.
- This isn't really related to the alignment pass, but we do it on
- the fly to avoid a separate instruction walk. */
- vr4130_avoid_branch_rt_conflict (insn);
+ MIPS_FP_CONDITIONS (CMP_BUILTINS)
+};
- if (USEFUL_INSN_P (insn))
- FOR_EACH_SUBINSN (subinsn, insn)
- {
- mips_sim_wait_insn (&state, subinsn);
+/* Built-in functions for the SB-1 processor. */
- /* If we want this instruction to issue in parallel with the
- previous one, make sure that the previous instruction is
- aligned. There are several reasons why this isn't worthwhile
- when the second instruction is a call:
+#define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
- - Calls are less likely to be performance critical,
- - There's a good chance that the delay slot can execute
- in parallel with the call.
- - The return address would then be unaligned.
+static const struct mips_builtin_description mips_sb1_bdesc[] = {
+ DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
+};
- In general, if we're going to insert a nop between instructions
- X and Y, it's better to insert it immediately after X. That
- way, if the nop makes Y aligned, it will also align any labels
- between X and Y. */
- if (state.insns_left != state.issue_rate
- && !CALL_P (subinsn))
- {
- if (subinsn == SEQ_BEGIN (insn) && aligned_p)
- {
- /* SUBINSN is the first instruction in INSN and INSN is
- aligned. We want to align the previous instruction
- instead, so insert a nop between LAST2 and LAST.
+/* Built-in functions for the DSP ASE. */
- Note that LAST could be either a single instruction
- or a branch with a delay slot. In the latter case,
- LAST, like INSN, is already aligned, but the delay
- slot must have some extra delay that stops it from
- issuing at the same time as the branch. We therefore
- insert a nop before the branch in order to align its
- delay slot. */
- emit_insn_after (gen_nop (), last2);
- aligned_p = false;
- }
- else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
- {
- /* SUBINSN is the delay slot of INSN, but INSN is
- currently unaligned. Insert a nop between
- LAST and INSN to align it. */
- emit_insn_after (gen_nop (), last);
- aligned_p = true;
- }
- }
- mips_sim_issue_insn (&state, subinsn);
- }
- mips_sim_finish_insn (&state, insn);
+#define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
+#define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
+#define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
+#define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
+#define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
- /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
- length = get_attr_length (insn);
- if (length > 0)
- {
- /* If the instruction is an asm statement or multi-instruction
- mips.md patern, the length is only an estimate. Insert an
- 8 byte alignment after it so that the following instructions
- can be handled correctly. */
- if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
- && (recog_memoized (insn) < 0 || length >= 8))
- {
- next = emit_insn_after (gen_align (GEN_INT (3)), insn);
- next = NEXT_INSN (next);
- mips_sim_next_cycle (&state);
- aligned_p = true;
- }
- else if (length & 4)
- aligned_p = !aligned_p;
- last2 = last;
- last = insn;
- }
+/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
+ CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
+ mips_builtin_description fields. */
+#define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+ { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
+ MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
- /* See whether INSN is an aligned label. */
- if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
- aligned_p = true;
- }
- dfa_finish ();
-}
-\f
-/* Subroutine of mips_reorg. If there is a hazard between INSN
- and a previous instruction, avoid it by inserting nops after
- instruction AFTER.
+/* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
+ branch instruction. TARGET_FLAGS is a mips_builtin_description field. */
+#define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
+ { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
+ MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
- *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
- this point. If *DELAYED_REG is non-null, INSN must wait a cycle
- before using the value of that register. *HILO_DELAY counts the
- number of instructions since the last hilo hazard (that is,
- the number of instructions since the last mflo or mfhi).
+static const struct mips_builtin_description mips_dsp_bdesc[] = {
+ DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
+ DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
+ DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
+ DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
+ DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
+ DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
+ DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
+ DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
+ DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
+ DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
+ DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
+ DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
+ DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
+ DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
+ DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
+ DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
+ DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
+ DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
+ DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
+ DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
+ DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
+ DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
+ DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
+ DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
+ DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
+ DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
+ DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
+ DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
+ DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, MASK_DSP),
+ DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, MASK_DSP),
+ DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, MASK_DSP),
+ BPOSGE_BUILTIN (32, MASK_DSP),
- After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
- for the next instruction.
+ /* The following are for the MIPS DSP ASE REV 2. */
+ DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, MASK_DSPR2),
+ DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
+ DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
+ DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
+ DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
+ DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
+ DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
+ DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
+ DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
+ DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
+ DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
+ DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
+ DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
+ DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
+ DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
+ DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSPR2),
+ DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
+ DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
+ DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
+ DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
+ DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
+ DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2)
+};
- LO_REG is an rtx for the LO register, used in dependence checking. */
+static const struct mips_builtin_description mips_dsp_32only_bdesc[] = {
+ DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
+ DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
+ DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
+ DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
+ DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
+ DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
+ DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
+ DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
+ DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
+ DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
+ DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
+ DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
-static void
-mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
- rtx *delayed_reg, rtx lo_reg)
+ /* The following are for the MIPS DSP ASE REV 2. */
+ DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
+ DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
+ DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
+ DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
+ DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, MASK_DSPR2),
+ DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, MASK_DSPR2),
+ DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
+ DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2)
+};
+
+/* This structure describes an array of mips_builtin_description entries. */
+struct mips_bdesc_map {
+ /* The array that this entry describes. */
+ const struct mips_builtin_description *bdesc;
+
+ /* The number of entries in BDESC. */
+ unsigned int size;
+
+ /* The target processor that supports the functions in BDESC.
+ PROCESSOR_MAX means we enable them for all processors. */
+ enum processor_type proc;
+
+ /* The functions in BDESC are not supported if any of these
+ target flags are set. */
+ int unsupported_target_flags;
+};
+
+/* All MIPS-specific built-in functions. */
+static const struct mips_bdesc_map mips_bdesc_arrays[] = {
+ { mips_ps_bdesc, ARRAY_SIZE (mips_ps_bdesc), PROCESSOR_MAX, 0 },
+ { mips_sb1_bdesc, ARRAY_SIZE (mips_sb1_bdesc), PROCESSOR_SB1, 0 },
+ { mips_dsp_bdesc, ARRAY_SIZE (mips_dsp_bdesc), PROCESSOR_MAX, 0 },
+ { mips_dsp_32only_bdesc, ARRAY_SIZE (mips_dsp_32only_bdesc),
+ PROCESSOR_MAX, MASK_64BIT }
+};
+
+/* MODE is a vector mode whose elements have type TYPE. Return the type
+ of the vector itself. */
+
+static tree
+mips_builtin_vector_type (tree type, enum machine_mode mode)
{
- rtx pattern, set;
- int nops, ninsns;
+ static tree types[(int) MAX_MACHINE_MODE];
- if (!INSN_P (insn))
- return;
+ if (types[(int) mode] == NULL_TREE)
+ types[(int) mode] = build_vector_type_for_mode (type, mode);
+ return types[(int) mode];
+}
- pattern = PATTERN (insn);
+/* Source-level argument types. */
+#define MIPS_ATYPE_VOID void_type_node
+#define MIPS_ATYPE_INT integer_type_node
+#define MIPS_ATYPE_POINTER ptr_type_node
- /* Do not put the whole function in .set noreorder if it contains
- an asm statement. We don't know whether there will be hazards
- between the asm statement and the gcc-generated code. */
- if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
- cfun->machine->all_noreorder_p = false;
+/* Standard mode-based argument types. */
+#define MIPS_ATYPE_SI intSI_type_node
+#define MIPS_ATYPE_USI unsigned_intSI_type_node
+#define MIPS_ATYPE_DI intDI_type_node
+#define MIPS_ATYPE_SF float_type_node
+#define MIPS_ATYPE_DF double_type_node
- /* Ignore zero-length instructions (barriers and the like). */
- ninsns = get_attr_length (insn) / 4;
- if (ninsns == 0)
- return;
+/* Vector argument types. */
+#define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
+#define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
+#define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
- /* Work out how many nops are needed. Note that we only care about
- registers that are explicitly mentioned in the instruction's pattern.
- It doesn't matter that calls use the argument registers or that they
- clobber hi and lo. */
- if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
- nops = 2 - *hilo_delay;
- else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
- nops = 1;
- else
- nops = 0;
+/* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
+ their associated MIPS_ATYPEs. */
+#define MIPS_FTYPE_ATYPES1(A, B) \
+ MIPS_ATYPE_##A, MIPS_ATYPE_##B
- /* Insert the nops between this instruction and the previous one.
- Each new nop takes us further from the last hilo hazard. */
- *hilo_delay += nops;
- while (nops-- > 0)
- emit_insn_after (gen_hazard_nop (), after);
+#define MIPS_FTYPE_ATYPES2(A, B, C) \
+ MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
- /* Set up the state for the next instruction. */
- *hilo_delay += ninsns;
- *delayed_reg = 0;
- if (INSN_CODE (insn) >= 0)
- switch (get_attr_hazard (insn))
- {
- case HAZARD_NONE:
- break;
+#define MIPS_FTYPE_ATYPES3(A, B, C, D) \
+ MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
- case HAZARD_HILO:
- *hilo_delay = 0;
- break;
+#define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
+ MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
+ MIPS_ATYPE_##E
- case HAZARD_DELAY:
- set = single_set (insn);
- gcc_assert (set != 0);
- *delayed_reg = SET_DEST (set);
- break;
+/* Return the function type associated with function prototype TYPE. */
+
+static tree
+mips_build_function_type (enum mips_function_type type)
+{
+ static tree types[(int) MIPS_MAX_FTYPE_MAX];
+
+ if (types[(int) type] == NULL_TREE)
+ switch (type)
+ {
+#define DEF_MIPS_FTYPE(NUM, ARGS) \
+ case MIPS_FTYPE_NAME##NUM ARGS: \
+ types[(int) type] \
+ = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
+ NULL_TREE); \
+ break;
+#include "config/mips/mips-ftypes.def"
+#undef DEF_MIPS_FTYPE
+ default:
+ gcc_unreachable ();
}
-}
+ return types[(int) type];
+}
-/* Go through the instruction stream and insert nops where necessary.
- See if the whole function can then be put into .set noreorder &
- .set nomacro. */
+/* Implement TARGET_INIT_BUILTINS. */
static void
-mips_avoid_hazards (void)
+mips_init_builtins (void)
{
- rtx insn, last_insn, lo_reg, delayed_reg;
- int hilo_delay, i;
+ const struct mips_builtin_description *d;
+ const struct mips_bdesc_map *m;
+ unsigned int offset;
- /* Force all instructions to be split into their final form. */
- split_all_insns_noflow ();
+ /* Iterate through all of the bdesc arrays, initializing all of the
+ builtin functions. */
+ offset = 0;
+ for (m = mips_bdesc_arrays;
+ m < &mips_bdesc_arrays[ARRAY_SIZE (mips_bdesc_arrays)];
+ m++)
+ {
+ if ((m->proc == PROCESSOR_MAX || m->proc == mips_arch)
+ && (m->unsupported_target_flags & target_flags) == 0)
+ for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
+ if ((d->target_flags & target_flags) == d->target_flags)
+ add_builtin_function (d->name,
+ mips_build_function_type (d->function_type),
+ d - m->bdesc + offset,
+ BUILT_IN_MD, NULL, NULL);
+ offset += m->size;
+ }
+}
- /* Recalculate instruction lengths without taking nops into account. */
- cfun->machine->ignore_hazard_length_p = true;
- shorten_branches (get_insns ());
+/* Take argument ARGNO from EXP's argument list and convert it into a
+ form suitable for input operand OPNO of instruction ICODE. Return the
+ value. */
- cfun->machine->all_noreorder_p = true;
+static rtx
+mips_prepare_builtin_arg (enum insn_code icode,
+ unsigned int opno, tree exp, unsigned int argno)
+{
+ rtx value;
+ enum machine_mode mode;
- /* Profiled functions can't be all noreorder because the profiler
- support uses assembler macros. */
- if (current_function_profile)
- cfun->machine->all_noreorder_p = false;
+ value = expand_normal (CALL_EXPR_ARG (exp, argno));
+ mode = insn_data[icode].operand[opno].mode;
+ if (!insn_data[icode].operand[opno].predicate (value, mode))
+ {
+ value = copy_to_mode_reg (mode, value);
+ /* Check the predicate again. */
+ if (!insn_data[icode].operand[opno].predicate (value, mode))
+ {
+ error ("invalid argument to built-in function");
+ return const0_rtx;
+ }
+ }
- /* Code compiled with -mfix-vr4120 can't be all noreorder because
- we rely on the assembler to work around some errata. */
- if (TARGET_FIX_VR4120)
- cfun->machine->all_noreorder_p = false;
+ return value;
+}
- /* The same is true for -mfix-vr4130 if we might generate mflo or
- mfhi instructions. Note that we avoid using mflo and mfhi if
- the VR4130 macc and dmacc instructions are available instead;
- see the *mfhilo_{si,di}_macc patterns. */
- if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
- cfun->machine->all_noreorder_p = false;
+/* Return an rtx suitable for output operand OP of instruction ICODE.
+ If TARGET is non-null, try to use it where possible. */
- last_insn = 0;
- hilo_delay = 2;
- delayed_reg = 0;
- lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
+static rtx
+mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
+{
+ enum machine_mode mode;
- for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
- if (INSN_P (insn))
- {
- if (GET_CODE (PATTERN (insn)) == SEQUENCE)
- for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
- mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
- &hilo_delay, &delayed_reg, lo_reg);
- else
- mips_avoid_hazard (last_insn, insn, &hilo_delay,
- &delayed_reg, lo_reg);
-
- last_insn = insn;
- }
+ mode = insn_data[icode].operand[op].mode;
+ if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
+ target = gen_reg_rtx (mode);
+
+ return target;
}
+/* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
+ HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
+ and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
+ suggests a good place to put the result. */
-/* Implement TARGET_MACHINE_DEPENDENT_REORG. */
+static rtx
+mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
+ bool has_target_p)
+{
+ rtx ops[MAX_RECOG_OPERANDS];
+ int opno, argno;
-static void
-mips_reorg (void)
+ /* Map any target to operand 0. */
+ opno = 0;
+ if (has_target_p)
+ {
+ ops[opno] = mips_prepare_builtin_target (icode, opno, target);
+ opno++;
+ }
+
+ /* Map the arguments to the other operands. The n_operands value
+ for an expander includes match_dups and match_scratches as well as
+ match_operands, so n_operands is only an upper bound on the number
+ of arguments to the expander function. */
+ gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
+ for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
+ ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
+
+ switch (opno)
+ {
+ case 2:
+ emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
+ break;
+
+ case 3:
+ emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
+ break;
+
+ case 4:
+ emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+ return target;
+}
+
+/* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
+ function; TYPE says which. EXP is the CALL_EXPR that calls the
+ function, ICODE is the instruction that should be used to compare
+ the first two arguments, and COND is the condition it should test.
+ TARGET, if nonnull, suggests a good place to put the result. */
+
+static rtx
+mips_expand_builtin_movtf (enum mips_builtin_type type,
+ enum insn_code icode, enum mips_fp_condition cond,
+ rtx target, tree exp)
{
- mips16_lay_out_constants ();
- if (TARGET_EXPLICIT_RELOCS)
+ rtx cmp_result, op0, op1;
+
+ cmp_result = mips_prepare_builtin_target (icode, 0, 0);
+ op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
+ op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
+ emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
+
+ icode = CODE_FOR_mips_cond_move_tf_ps;
+ target = mips_prepare_builtin_target (icode, 0, target);
+ if (type == MIPS_BUILTIN_MOVT)
{
- if (mips_flag_delayed_branch)
- dbr_schedule (get_insns ());
- mips_avoid_hazards ();
- if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
- vr4130_align_insns ();
+ op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
+ op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
}
+ else
+ {
+ op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
+ op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
+ }
+ emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
+ return target;
}
-/* This function does three things:
+/* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
+ into TARGET otherwise. Return TARGET. */
+
+static rtx
+mips_builtin_branch_and_move (rtx condition, rtx target,
+ rtx value_if_true, rtx value_if_false)
+{
+ rtx true_label, done_label;
+
+ true_label = gen_label_rtx ();
+ done_label = gen_label_rtx ();
+
+ /* First assume that CONDITION is false. */
+ mips_emit_move (target, value_if_false);
+
+ /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
+ emit_jump_insn (gen_condjump (condition, true_label));
+ emit_jump_insn (gen_jump (done_label));
+ emit_barrier ();
+
+ /* Fix TARGET if CONDITION is true. */
+ emit_label (true_label);
+ mips_emit_move (target, value_if_true);
+
+ emit_label (done_label);
+ return target;
+}
+
+/* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
+ the CALL_EXPR that calls the function, ICODE is the code of the
+ comparison instruction, and COND is the condition it should test.
+ TARGET, if nonnull, suggests a good place to put the boolean result. */
+
+static rtx
+mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
+ enum insn_code icode, enum mips_fp_condition cond,
+ rtx target, tree exp)
+{
+ rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
+ int argno;
+
+ if (target == 0 || GET_MODE (target) != SImode)
+ target = gen_reg_rtx (SImode);
+
+ /* The instruction should have a target operand, an operand for each
+ argument, and an operand for COND. */
+ gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
+
+ /* Prepare the operands to the comparison. */
+ cmp_result = mips_prepare_builtin_target (icode, 0, 0);
+ for (argno = 0; argno < call_expr_nargs (exp); argno++)
+ args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
- - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
- - Register the mips16 hardware floating point stubs.
- - Register the gofast functions if selected using --enable-gofast. */
+ switch (insn_data[icode].n_operands)
+ {
+ case 4:
+ emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
+ GEN_INT (cond)));
+ break;
-#include "config/gofast.h"
+ case 6:
+ emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
+ args[2], args[3], GEN_INT (cond)));
+ break;
-static void
-mips_init_libfuncs (void)
-{
- if (TARGET_FIX_VR4120)
- {
- set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
- set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
+ default:
+ gcc_unreachable ();
}
- if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
+ /* If the comparison sets more than one register, we define the result
+ to be 0 if all registers are false and -1 if all registers are true.
+ The value of the complete result is indeterminate otherwise. */
+ switch (builtin_type)
{
- set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
- set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
- set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
- set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
+ case MIPS_BUILTIN_CMP_ALL:
+ condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
+ return mips_builtin_branch_and_move (condition, target,
+ const0_rtx, const1_rtx);
- set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
- set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
- set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
- set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
- set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
- set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
- set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
+ case MIPS_BUILTIN_CMP_UPPER:
+ case MIPS_BUILTIN_CMP_LOWER:
+ offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
+ condition = gen_single_cc (cmp_result, offset);
+ return mips_builtin_branch_and_move (condition, target,
+ const1_rtx, const0_rtx);
- set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
- set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
- set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
+ default:
+ condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
+ return mips_builtin_branch_and_move (condition, target,
+ const1_rtx, const0_rtx);
+ }
+}
- if (TARGET_DOUBLE_FLOAT)
- {
- set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
- set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
- set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
- set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
+/* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
+ if nonnull, suggests a good place to put the boolean result. */
- set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
- set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
- set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
- set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
- set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
- set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
- set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
+static rtx
+mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
+{
+ rtx condition, cmp_result;
+ int cmp_value;
+
+ if (target == 0 || GET_MODE (target) != SImode)
+ target = gen_reg_rtx (SImode);
- set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
- set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
+ cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
- set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
- set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
- set_conv_libfunc (ufloat_optab, DFmode, SImode, "__mips16_floatunsidf");
- }
- }
+ if (builtin_type == MIPS_BUILTIN_BPOSGE32)
+ cmp_value = 32;
else
- gofast_maybe_init_libfuncs ();
+ gcc_assert (0);
+
+ condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
+ return mips_builtin_branch_and_move (condition, target,
+ const1_rtx, const0_rtx);
}
-/* Return a number assessing the cost of moving a register in class
- FROM to class TO. The classes are expressed using the enumeration
- values such as `GENERAL_REGS'. A value of 2 is the default; other
- values are interpreted relative to that.
-
- It is not required that the cost always equal 2 when FROM is the
- same as TO; on some machines it is expensive to move between
- registers if they are not general registers.
-
- If reload sees an insn consisting of a single `set' between two
- hard registers, and if `REGISTER_MOVE_COST' applied to their
- classes returns a value of 2, reload does not check to ensure that
- the constraints of the insn are met. Setting a cost of other than
- 2 will allow reload to verify that the constraints are met. You
- should do this if the `movM' pattern's constraints do not allow
- such copying.
-
- ??? We make the cost of moving from HI/LO into general
- registers the same as for one of moving general registers to
- HI/LO for TARGET_MIPS16 in order to prevent allocating a
- pseudo to HI/LO. This might hurt optimizations though, it
- isn't clear if it is wise. And it might not work in all cases. We
- could solve the DImode LO reg problem by using a multiply, just
- like reload_{in,out}si. We could solve the SImode/HImode HI reg
- problem by using divide instructions. divu puts the remainder in
- the HI reg, so doing a divide by -1 will move the value in the HI
- reg for all values except -1. We could handle that case by using a
- signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
- a compare/branch to test the input value to see which instruction
- we need to use. This gets pretty messy, but it is feasible. */
+/* EXP is a CALL_EXPR that calls the function described by BDESC.
+ Expand the call and return an rtx for its return value.
+ TARGET, if nonnull, suggests a good place to put this value. */
-int
-mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
- enum reg_class to, enum reg_class from)
+static rtx
+mips_expand_builtin_1 (const struct mips_builtin_description *bdesc,
+ tree exp, rtx target)
{
- if (from == M16_REGS && reg_class_subset_p (to, GENERAL_REGS))
- return 2;
- else if (from == M16_NA_REGS && reg_class_subset_p (to, GENERAL_REGS))
- return 2;
- else if (reg_class_subset_p (from, GENERAL_REGS))
- {
- if (to == M16_REGS)
- return 2;
- else if (to == M16_NA_REGS)
- return 2;
- else if (reg_class_subset_p (to, GENERAL_REGS))
- {
- if (TARGET_MIPS16)
- return 4;
- else
- return 2;
- }
- else if (to == FP_REGS)
- return 4;
- else if (reg_class_subset_p (to, ACC_REGS))
- {
- if (TARGET_MIPS16)
- return 12;
- else
- return 6;
- }
- else if (reg_class_subset_p (to, ALL_COP_REGS))
- {
- return 5;
- }
- }
- else if (from == FP_REGS)
- {
- if (reg_class_subset_p (to, GENERAL_REGS))
- return 4;
- else if (to == FP_REGS)
- return 2;
- else if (to == ST_REGS)
- return 8;
- }
- else if (reg_class_subset_p (from, ACC_REGS))
- {
- if (reg_class_subset_p (to, GENERAL_REGS))
- {
- if (TARGET_MIPS16)
- return 12;
- else
- return 6;
- }
- }
- else if (from == ST_REGS && reg_class_subset_p (to, GENERAL_REGS))
- return 4;
- else if (reg_class_subset_p (from, ALL_COP_REGS))
+ switch (bdesc->builtin_type)
{
- return 5;
- }
-
- /* Fall through.
- ??? What cases are these? Shouldn't we return 2 here? */
+ case MIPS_BUILTIN_DIRECT:
+ return mips_expand_builtin_direct (bdesc->icode, target, exp, true);
- return 12;
-}
+ case MIPS_BUILTIN_DIRECT_NO_TARGET:
+ return mips_expand_builtin_direct (bdesc->icode, target, exp, false);
-/* Return the length of INSN. LENGTH is the initial length computed by
- attributes in the machine-description file. */
+ case MIPS_BUILTIN_MOVT:
+ case MIPS_BUILTIN_MOVF:
+ return mips_expand_builtin_movtf (bdesc->builtin_type, bdesc->icode,
+ bdesc->cond, target, exp);
-int
-mips_adjust_insn_length (rtx insn, int length)
-{
- /* A unconditional jump has an unfilled delay slot if it is not part
- of a sequence. A conditional jump normally has a delay slot, but
- does not on MIPS16. */
- if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
- length += 4;
+ case MIPS_BUILTIN_CMP_ANY:
+ case MIPS_BUILTIN_CMP_ALL:
+ case MIPS_BUILTIN_CMP_UPPER:
+ case MIPS_BUILTIN_CMP_LOWER:
+ case MIPS_BUILTIN_CMP_SINGLE:
+ return mips_expand_builtin_compare (bdesc->builtin_type, bdesc->icode,
+ bdesc->cond, target, exp);
- /* See how many nops might be needed to avoid hardware hazards. */
- if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
- switch (get_attr_hazard (insn))
- {
- case HAZARD_NONE:
- break;
+ case MIPS_BUILTIN_BPOSGE32:
+ return mips_expand_builtin_bposge (bdesc->builtin_type, target);
+ }
+ gcc_unreachable ();
+}
- case HAZARD_DELAY:
- length += 4;
- break;
+/* Implement TARGET_EXPAND_BUILTIN. */
- case HAZARD_HILO:
- length += 8;
- break;
- }
+static rtx
+mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
+ enum machine_mode mode ATTRIBUTE_UNUSED,
+ int ignore ATTRIBUTE_UNUSED)
+{
+ tree fndecl;
+ unsigned int fcode;
+ const struct mips_bdesc_map *m;
- /* All MIPS16 instructions are a measly two bytes. */
+ fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
+ fcode = DECL_FUNCTION_CODE (fndecl);
if (TARGET_MIPS16)
- length /= 2;
+ {
+ error ("built-in function %qs not supported for MIPS16",
+ IDENTIFIER_POINTER (DECL_NAME (fndecl)));
+ return const0_rtx;
+ }
- return length;
+ for (m = mips_bdesc_arrays;
+ m < &mips_bdesc_arrays[ARRAY_SIZE (mips_bdesc_arrays)];
+ m++)
+ {
+ if (fcode < m->size)
+ return mips_expand_builtin_1 (m->bdesc + fcode, exp, target);
+ fcode -= m->size;
+ }
+ gcc_unreachable ();
}
+\f
+/* An entry in the MIPS16 constant pool. VALUE is the pool constant,
+ MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
+struct mips16_constant {
+ struct mips16_constant *next;
+ rtx value;
+ rtx label;
+ enum machine_mode mode;
+};
+/* Information about an incomplete MIPS16 constant pool. FIRST is the
+ first constant, HIGHEST_ADDRESS is the highest address that the first
+ byte of the pool can have, and INSN_ADDRESS is the current instruction
+ address. */
+struct mips16_constant_pool {
+ struct mips16_constant *first;
+ int highest_address;
+ int insn_address;
+};
-/* Return an asm sequence to start a noat block and load the address
- of a label into $1. */
+/* Add constant VALUE to POOL and return its label. MODE is the
+ value's mode (used for CONST_INTs, etc.). */
-const char *
-mips_output_load_label (void)
+static rtx
+mips16_add_constant (struct mips16_constant_pool *pool,
+ rtx value, enum machine_mode mode)
{
- if (TARGET_EXPLICIT_RELOCS)
- switch (mips_abi)
- {
- case ABI_N32:
- return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
+ struct mips16_constant **p, *c;
+ bool first_of_size_p;
- case ABI_64:
- return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
+ /* See whether the constant is already in the pool. If so, return the
+ existing label, otherwise leave P pointing to the place where the
+ constant should be added.
- default:
- if (ISA_HAS_LOAD_DELAY)
- return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
- return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
- }
- else
+ Keep the pool sorted in increasing order of mode size so that we can
+ reduce the number of alignments needed. */
+ first_of_size_p = true;
+ for (p = &pool->first; *p != 0; p = &(*p)->next)
{
- if (Pmode == DImode)
- return "%[dla\t%@,%0";
- else
- return "%[la\t%@,%0";
+ if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
+ return (*p)->label;
+ if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
+ break;
+ if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
+ first_of_size_p = false;
}
+
+ /* In the worst case, the constant needed by the earliest instruction
+ will end up at the end of the pool. The entire pool must then be
+ accessible from that instruction.
+
+ When adding the first constant, set the pool's highest address to
+ the address of the first out-of-range byte. Adjust this address
+ downwards each time a new constant is added. */
+ if (pool->first == 0)
+ /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
+ of the instruction with the lowest two bits clear. The base PC
+ value for LDPC has the lowest three bits clear. Assume the worst
+ case here; namely that the PC-relative instruction occupies the
+ last 2 bytes in an aligned word. */
+ pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
+ pool->highest_address -= GET_MODE_SIZE (mode);
+ if (first_of_size_p)
+ /* Take into account the worst possible padding due to alignment. */
+ pool->highest_address -= GET_MODE_SIZE (mode) - 1;
+
+ /* Create a new entry. */
+ c = XNEW (struct mips16_constant);
+ c->value = value;
+ c->mode = mode;
+ c->label = gen_label_rtx ();
+ c->next = *p;
+ *p = c;
+
+ return c->label;
}
-/* Return the assembly code for INSN, which has the operands given by
- OPERANDS, and which branches to OPERANDS[1] if some condition is true.
- BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
- is in range of a direct branch. BRANCH_IF_FALSE is an inverted
- version of BRANCH_IF_TRUE. */
+/* Output constant VALUE after instruction INSN and return the last
+ instruction emitted. MODE is the mode of the constant. */
-const char *
-mips_output_conditional_branch (rtx insn, rtx *operands,
- const char *branch_if_true,
- const char *branch_if_false)
+static rtx
+mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
{
- unsigned int length;
- rtx taken, not_taken;
-
- length = get_attr_length (insn);
- if (length <= 8)
+ if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
{
- /* Just a simple conditional branch. */
- mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
- return branch_if_true;
+ rtx size = GEN_INT (GET_MODE_SIZE (mode));
+ return emit_insn_after (gen_consttable_int (value, size), insn);
}
- /* Generate a reversed branch around a direct jump. This fallback does
- not use branch-likely instructions. */
- mips_branch_likely = false;
- not_taken = gen_label_rtx ();
- taken = operands[1];
-
- /* Generate the reversed branch to NOT_TAKEN. */
- operands[1] = not_taken;
- output_asm_insn (branch_if_false, operands);
+ if (SCALAR_FLOAT_MODE_P (mode))
+ return emit_insn_after (gen_consttable_float (value), insn);
- /* If INSN has a delay slot, we must provide delay slots for both the
- branch to NOT_TAKEN and the conditional jump. We must also ensure
- that INSN's delay slot is executed in the appropriate cases. */
- if (final_sequence)
+ if (VECTOR_MODE_P (mode))
{
- /* This first delay slot will always be executed, so use INSN's
- delay slot if is not annulled. */
- if (!INSN_ANNULLED_BRANCH_P (insn))
- {
- final_scan_insn (XVECEXP (final_sequence, 0, 1),
- asm_out_file, optimize, 1, NULL);
- INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
- }
- else
- output_asm_insn ("nop", 0);
- fprintf (asm_out_file, "\n");
- }
+ int i;
- /* Output the unconditional branch to TAKEN. */
- if (length <= 16)
- output_asm_insn ("j\t%0%/", &taken);
- else
- {
- output_asm_insn (mips_output_load_label (), &taken);
- output_asm_insn ("jr\t%@%]%/", 0);
+ for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
+ insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
+ CONST_VECTOR_ELT (value, i), insn);
+ return insn;
}
- /* Now deal with its delay slot; see above. */
- if (final_sequence)
+ gcc_unreachable ();
+}
+
+/* Dump out the constants in CONSTANTS after INSN. */
+
+static void
+mips16_emit_constants (struct mips16_constant *constants, rtx insn)
+{
+ struct mips16_constant *c, *next;
+ int align;
+
+ align = 0;
+ for (c = constants; c != NULL; c = next)
{
- /* This delay slot will only be executed if the branch is taken.
- Use INSN's delay slot if is annulled. */
- if (INSN_ANNULLED_BRANCH_P (insn))
+ /* If necessary, increase the alignment of PC. */
+ if (align < GET_MODE_SIZE (c->mode))
{
- final_scan_insn (XVECEXP (final_sequence, 0, 1),
- asm_out_file, optimize, 1, NULL);
- INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
+ int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
+ insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
}
- else
- output_asm_insn ("nop", 0);
- fprintf (asm_out_file, "\n");
+ align = GET_MODE_SIZE (c->mode);
+
+ insn = emit_label_after (c->label, insn);
+ insn = mips16_emit_constants_1 (c->mode, c->value, insn);
+
+ next = c->next;
+ free (c);
}
- /* Output NOT_TAKEN. */
- (*targetm.asm_out.internal_label) (asm_out_file, "L",
- CODE_LABEL_NUMBER (not_taken));
- return "";
+ emit_barrier_after (insn);
}
-/* Return the assembly code for INSN, which branches to OPERANDS[1]
- if some ordered condition is true. The condition is given by
- OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
- OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
- its second is always zero. */
+/* Return the length of instruction INSN. */
-const char *
-mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
+static int
+mips16_insn_length (rtx insn)
{
- const char *branch[2];
-
- /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
- Make BRANCH[0] branch on the inverse condition. */
- switch (GET_CODE (operands[0]))
+ if (JUMP_P (insn))
{
- /* These cases are equivalent to comparisons against zero. */
- case LEU:
- inverted_p = !inverted_p;
- /* Fall through. */
- case GTU:
- branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
- branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
- break;
-
- /* These cases are always true or always false. */
- case LTU:
- inverted_p = !inverted_p;
- /* Fall through. */
- case GEU:
- branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
- branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
- break;
-
- default:
- branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
- branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
- break;
+ rtx body = PATTERN (insn);
+ if (GET_CODE (body) == ADDR_VEC)
+ return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
+ if (GET_CODE (body) == ADDR_DIFF_VEC)
+ return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
}
- return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
+ return get_attr_length (insn);
}
-\f
-/* Used to output div or ddiv instruction DIVISION, which has the operands
- given by OPERANDS. Add in a divide-by-zero check if needed.
- When working around R4000 and R4400 errata, we need to make sure that
- the division is not immediately followed by a shift[1][2]. We also
- need to stop the division from being put into a branch delay slot[3].
- The easiest way to avoid both problems is to add a nop after the
- division. When a divide-by-zero check is needed, this nop can be
- used to fill the branch delay slot.
+/* If *X is a symbolic constant that refers to the constant pool, add
+ the constant to POOL and rewrite *X to use the constant's label. */
- [1] If a double-word or a variable shift executes immediately
- after starting an integer division, the shift may give an
- incorrect result. See quotations of errata #16 and #28 from
- "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
- in mips.md for details.
+static void
+mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
+{
+ rtx base, offset, label;
- [2] A similar bug to [1] exists for all revisions of the
- R4000 and the R4400 when run in an MC configuration.
- From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
+ split_const (*x, &base, &offset);
+ if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
+ {
+ label = mips16_add_constant (pool, get_pool_constant (base),
+ get_pool_mode (base));
+ base = gen_rtx_LABEL_REF (Pmode, label);
+ *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
+ }
+}
- "19. In this following sequence:
+/* This structure is used to communicate with mips16_rewrite_pool_refs.
+ INSN is the instruction we're rewriting and POOL points to the current
+ constant pool. */
+struct mips16_rewrite_pool_refs_info {
+ rtx insn;
+ struct mips16_constant_pool *pool;
+};
- ddiv (or ddivu or div or divu)
- dsll32 (or dsrl32, dsra32)
+/* Rewrite *X so that constant pool references refer to the constant's
+ label instead. DATA points to a mips16_rewrite_pool_refs_info
+ structure. */
- if an MPT stall occurs, while the divide is slipping the cpu
- pipeline, then the following double shift would end up with an
- incorrect result.
+static int
+mips16_rewrite_pool_refs (rtx *x, void *data)
+{
+ struct mips16_rewrite_pool_refs_info *info = data;
- Workaround: The compiler needs to avoid generating any
- sequence with divide followed by extended double shift."
+ if (force_to_mem_operand (*x, Pmode))
+ {
+ rtx mem = force_const_mem (GET_MODE (*x), *x);
+ validate_change (info->insn, x, mem, false);
+ }
- This erratum is also present in "MIPS R4400MC Errata, Processor
- Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
- & 3.0" as errata #10 and #4, respectively.
+ if (MEM_P (*x))
+ {
+ mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
+ return -1;
+ }
- [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
- (also valid for MIPS R4000MC processors):
+ if (TARGET_MIPS16_TEXT_LOADS)
+ mips16_rewrite_pool_constant (info->pool, x);
- "52. R4000SC: This bug does not apply for the R4000PC.
+ return GET_CODE (*x) == CONST ? -1 : 0;
+}
- There are two flavors of this bug:
+/* Build MIPS16 constant pools. */
- 1) If the instruction just after divide takes an RF exception
- (tlb-refill, tlb-invalid) and gets an instruction cache
- miss (both primary and secondary) and the line which is
- currently in secondary cache at this index had the first
- data word, where the bits 5..2 are set, then R4000 would
- get a wrong result for the div.
+static void
+mips16_lay_out_constants (void)
+{
+ struct mips16_constant_pool pool;
+ struct mips16_rewrite_pool_refs_info info;
+ rtx insn, barrier;
- ##1
- nop
- div r8, r9
- ------------------- # end-of page. -tlb-refill
- nop
- ##2
- nop
- div r8, r9
- ------------------- # end-of page. -tlb-invalid
- nop
+ if (!TARGET_MIPS16_PCREL_LOADS)
+ return;
- 2) If the divide is in the taken branch delay slot, where the
- target takes RF exception and gets an I-cache miss for the
- exception vector or where I-cache miss occurs for the
- target address, under the above mentioned scenarios, the
- div would get wrong results.
+ barrier = 0;
+ memset (&pool, 0, sizeof (pool));
+ for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+ {
+ /* Rewrite constant pool references in INSN. */
+ if (INSN_P (insn))
+ {
+ info.insn = insn;
+ info.pool = &pool;
+ for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
+ }
- ##1
- j r2 # to next page mapped or unmapped
- div r8,r9 # this bug would be there as long
- # as there is an ICache miss and
- nop # the "data pattern" is present
+ pool.insn_address += mips16_insn_length (insn);
- ##2
- beq r0, r0, NextPage # to Next page
- div r8,r9
- nop
+ if (pool.first != NULL)
+ {
+ /* If there are no natural barriers between the first user of
+ the pool and the highest acceptable address, we'll need to
+ create a new instruction to jump around the constant pool.
+ In the worst case, this instruction will be 4 bytes long.
- This bug is present for div, divu, ddiv, and ddivu
- instructions.
+ If it's too late to do this transformation after INSN,
+ do it immediately before INSN. */
+ if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
+ {
+ rtx label, jump;
- Workaround: For item 1), OS could make sure that the next page
- after the divide instruction is also mapped. For item 2), the
- compiler could make sure that the divide instruction is not in
- the branch delay slot."
+ label = gen_label_rtx ();
- These processors have PRId values of 0x00004220 and 0x00004300 for
- the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
+ jump = emit_jump_insn_before (gen_jump (label), insn);
+ JUMP_LABEL (jump) = label;
+ LABEL_NUSES (label) = 1;
+ barrier = emit_barrier_after (jump);
-const char *
-mips_output_division (const char *division, rtx *operands)
-{
- const char *s;
+ emit_label_after (label, barrier);
+ pool.insn_address += 4;
+ }
- s = division;
- if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
- {
- output_asm_insn (s, operands);
- s = "nop";
- }
- if (TARGET_CHECK_ZERO_DIV)
- {
- if (TARGET_MIPS16)
- {
- output_asm_insn (s, operands);
- s = "bnez\t%2,1f\n\tbreak\t7\n1:";
- }
- else if (GENERATE_DIVIDE_TRAPS)
- {
- output_asm_insn (s, operands);
- s = "teq\t%2,%.,7";
- }
- else
- {
- output_asm_insn ("%(bne\t%2,%.,1f", operands);
- output_asm_insn (s, operands);
- s = "break\t7%)\n1:";
+ /* See whether the constant pool is now out of range of the first
+ user. If so, output the constants after the previous barrier.
+ Note that any instructions between BARRIER and INSN (inclusive)
+ will use negative offsets to refer to the pool. */
+ if (pool.insn_address > pool.highest_address)
+ {
+ mips16_emit_constants (pool.first, barrier);
+ pool.first = NULL;
+ barrier = 0;
+ }
+ else if (BARRIER_P (insn))
+ barrier = insn;
}
}
- return s;
+ mips16_emit_constants (pool.first, get_last_insn ());
}
\f
-/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
- with a final "000" replaced by "k". Ignore case.
+/* A temporary variable used by for_each_rtx callbacks, etc. */
+static rtx mips_sim_insn;
- Note: this function is shared between GCC and GAS. */
+/* A structure representing the state of the processor pipeline.
+ Used by the mips_sim_* family of functions. */
+struct mips_sim {
+ /* The maximum number of instructions that can be issued in a cycle.
+ (Caches mips_issue_rate.) */
+ unsigned int issue_rate;
-static bool
-mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
-{
- while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
- given++, canonical++;
+ /* The current simulation time. */
+ unsigned int time;
- return ((*given == 0 && *canonical == 0)
- || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
-}
+ /* How many more instructions can be issued in the current cycle. */
+ unsigned int insns_left;
+ /* LAST_SET[X].INSN is the last instruction to set register X.
+ LAST_SET[X].TIME is the time at which that instruction was issued.
+ INSN is null if no instruction has yet set register X. */
+ struct {
+ rtx insn;
+ unsigned int time;
+ } last_set[FIRST_PSEUDO_REGISTER];
-/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
- CPU name. We've traditionally allowed a lot of variation here.
+ /* The pipeline's current DFA state. */
+ state_t dfa_state;
+};
- Note: this function is shared between GCC and GAS. */
+/* Reset STATE to the initial simulation state. */
-static bool
-mips_matching_cpu_name_p (const char *canonical, const char *given)
+static void
+mips_sim_reset (struct mips_sim *state)
{
- /* First see if the name matches exactly, or with a final "000"
- turned into "k". */
- if (mips_strict_matching_cpu_name_p (canonical, given))
- return true;
-
- /* If not, try comparing based on numerical designation alone.
- See if GIVEN is an unadorned number, or 'r' followed by a number. */
- if (TOLOWER (*given) == 'r')
- given++;
- if (!ISDIGIT (*given))
- return false;
+ state->time = 0;
+ state->insns_left = state->issue_rate;
+ memset (&state->last_set, 0, sizeof (state->last_set));
+ state_reset (state->dfa_state);
+}
- /* Skip over some well-known prefixes in the canonical name,
- hoping to find a number there too. */
- if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
- canonical += 2;
- else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
- canonical += 2;
- else if (TOLOWER (canonical[0]) == 'r')
- canonical += 1;
+/* Initialize STATE before its first use. DFA_STATE points to an
+ allocated but uninitialized DFA state. */
- return mips_strict_matching_cpu_name_p (canonical, given);
+static void
+mips_sim_init (struct mips_sim *state, state_t dfa_state)
+{
+ state->issue_rate = mips_issue_rate ();
+ state->dfa_state = dfa_state;
+ mips_sim_reset (state);
}
+/* Advance STATE by one clock cycle. */
-/* Return the mips_cpu_info entry for the processor or ISA given
- by CPU_STRING. Return null if the string isn't recognized.
+static void
+mips_sim_next_cycle (struct mips_sim *state)
+{
+ state->time++;
+ state->insns_left = state->issue_rate;
+ state_transition (state->dfa_state, 0);
+}
- A similar function exists in GAS. */
+/* Advance simulation state STATE until instruction INSN can read
+ register REG. */
-static const struct mips_cpu_info *
-mips_parse_cpu (const char *cpu_string)
+static void
+mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
{
- const struct mips_cpu_info *p;
- const char *s;
+ unsigned int regno, end_regno;
- /* In the past, we allowed upper-case CPU names, but it doesn't
- work well with the multilib machinery. */
- for (s = cpu_string; *s != 0; s++)
- if (ISUPPER (*s))
+ end_regno = END_REGNO (reg);
+ for (regno = REGNO (reg); regno < end_regno; regno++)
+ if (state->last_set[regno].insn != 0)
{
- warning (0, "the cpu name must be lower case");
- break;
- }
-
- /* 'from-abi' selects the most compatible architecture for the given
- ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
- EABIs, we have to decide whether we're using the 32-bit or 64-bit
- version. Look first at the -mgp options, if given, otherwise base
- the choice on MASK_64BIT in TARGET_DEFAULT. */
- if (strcasecmp (cpu_string, "from-abi") == 0)
- return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
- : ABI_NEEDS_64BIT_REGS ? 3
- : (TARGET_64BIT ? 3 : 1));
+ unsigned int t;
- /* 'default' has traditionally been a no-op. Probably not very useful. */
- if (strcasecmp (cpu_string, "default") == 0)
- return 0;
+ t = (state->last_set[regno].time
+ + insn_latency (state->last_set[regno].insn, insn));
+ while (state->time < t)
+ mips_sim_next_cycle (state);
+ }
+}
- for (p = mips_cpu_info_table; p->name != 0; p++)
- if (mips_matching_cpu_name_p (p->name, cpu_string))
- return p;
+/* A for_each_rtx callback. If *X is a register, advance simulation state
+ DATA until mips_sim_insn can read the register's value. */
+static int
+mips_sim_wait_regs_2 (rtx *x, void *data)
+{
+ if (REG_P (*x))
+ mips_sim_wait_reg (data, mips_sim_insn, *x);
return 0;
}
+/* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
-/* Return the processor associated with the given ISA level, or null
- if the ISA isn't valid. */
-
-static const struct mips_cpu_info *
-mips_cpu_info_from_isa (int isa)
+static void
+mips_sim_wait_regs_1 (rtx *x, void *data)
{
- const struct mips_cpu_info *p;
-
- for (p = mips_cpu_info_table; p->name != 0; p++)
- if (p->isa == isa)
- return p;
-
- return 0;
+ for_each_rtx (x, mips_sim_wait_regs_2, data);
}
-\f
-/* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
- by UNITS_PER_FPREG. The size of FP status registers is always 4, because
- they only hold condition code modes, and CCmode is always considered to
- be 4 bytes wide. All other registers are word sized. */
-unsigned int
-mips_hard_regno_nregs (int regno, enum machine_mode mode)
+/* Advance simulation state STATE until all of INSN's register
+ dependencies are satisfied. */
+
+static void
+mips_sim_wait_regs (struct mips_sim *state, rtx insn)
{
- if (ST_REG_P (regno))
- return ((GET_MODE_SIZE (mode) + 3) / 4);
- else if (! FP_REG_P (regno))
- return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
- else
- return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
+ mips_sim_insn = insn;
+ note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
}
-/* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
- all BLKmode objects are returned in memory. Under the new (N32 and
- 64-bit MIPS ABIs) small structures are returned in a register.
- Objects with varying size must still be returned in memory, of
- course. */
+/* Advance simulation state STATE until the units required by
+ instruction INSN are available. */
-static bool
-mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
+static void
+mips_sim_wait_units (struct mips_sim *state, rtx insn)
{
- if (TARGET_OLDABI)
- return (TYPE_MODE (type) == BLKmode);
- else
- return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
- || (int_size_in_bytes (type) == -1));
+ state_t tmp_state;
+
+ tmp_state = alloca (state_size ());
+ while (state->insns_left == 0
+ || (memcpy (tmp_state, state->dfa_state, state_size ()),
+ state_transition (tmp_state, insn) >= 0))
+ mips_sim_next_cycle (state);
}
-static bool
-mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
+/* Advance simulation state STATE until INSN is ready to issue. */
+
+static void
+mips_sim_wait_insn (struct mips_sim *state, rtx insn)
{
- return !TARGET_OLDABI;
+ mips_sim_wait_regs (state, insn);
+ mips_sim_wait_units (state, insn);
}
-\f
-/* Return true if INSN is a multiply-add or multiply-subtract
- instruction and PREV assigns to the accumulator operand. */
-bool
-mips_linked_madd_p (rtx prev, rtx insn)
-{
- rtx x;
+/* mips_sim_insn has just set X. Update the LAST_SET array
+ in simulation state DATA. */
- x = single_set (insn);
- if (x == 0)
- return false;
+static void
+mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
+{
+ struct mips_sim *state;
- x = SET_SRC (x);
+ state = data;
+ if (REG_P (x))
+ {
+ unsigned int regno, end_regno;
- if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 0)) == MULT
- && reg_set_p (XEXP (x, 1), prev))
- return true;
+ end_regno = END_REGNO (x);
+ for (regno = REGNO (x); regno < end_regno; regno++)
+ {
+ state->last_set[regno].insn = mips_sim_insn;
+ state->last_set[regno].time = state->time;
+ }
+ }
+}
- if (GET_CODE (x) == MINUS
- && GET_CODE (XEXP (x, 1)) == MULT
- && reg_set_p (XEXP (x, 0), prev))
- return true;
+/* Issue instruction INSN in scheduler state STATE. Assume that INSN
+ can issue immediately (i.e., that mips_sim_wait_insn has already
+ been called). */
- return false;
-}
-\f
-/* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
- that may clobber hi or lo. */
+static void
+mips_sim_issue_insn (struct mips_sim *state, rtx insn)
+{
+ state_transition (state->dfa_state, insn);
+ state->insns_left--;
-static rtx mips_macc_chains_last_hilo;
+ mips_sim_insn = insn;
+ note_stores (PATTERN (insn), mips_sim_record_set, state);
+}
-/* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
- been scheduled, updating mips_macc_chains_last_hilo appropriately. */
+/* Simulate issuing a NOP in state STATE. */
static void
-mips_macc_chains_record (rtx insn)
+mips_sim_issue_nop (struct mips_sim *state)
{
- if (get_attr_may_clobber_hilo (insn))
- mips_macc_chains_last_hilo = insn;
+ if (state->insns_left == 0)
+ mips_sim_next_cycle (state);
+ state->insns_left--;
}
-/* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
- has NREADY elements, looking for a multiply-add or multiply-subtract
- instruction that is cumulative with mips_macc_chains_last_hilo.
- If there is one, promote it ahead of anything else that might
- clobber hi or lo. */
+/* Update simulation state STATE so that it's ready to accept the instruction
+ after INSN. INSN should be part of the main rtl chain, not a member of a
+ SEQUENCE. */
static void
-mips_macc_chains_reorder (rtx *ready, int nready)
+mips_sim_finish_insn (struct mips_sim *state, rtx insn)
{
- int i, j;
+ /* If INSN is a jump with an implicit delay slot, simulate a nop. */
+ if (JUMP_P (insn))
+ mips_sim_issue_nop (state);
- if (mips_macc_chains_last_hilo != 0)
- for (i = nready - 1; i >= 0; i--)
- if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
- {
- for (j = nready - 1; j > i; j--)
- if (recog_memoized (ready[j]) >= 0
- && get_attr_may_clobber_hilo (ready[j]))
- {
- mips_promote_ready (ready, i, j);
- break;
- }
- break;
- }
+ switch (GET_CODE (SEQ_BEGIN (insn)))
+ {
+ case CODE_LABEL:
+ case CALL_INSN:
+ /* We can't predict the processor state after a call or label. */
+ mips_sim_reset (state);
+ break;
+
+ case JUMP_INSN:
+ /* The delay slots of branch likely instructions are only executed
+ when the branch is taken. Therefore, if the caller has simulated
+ the delay slot instruction, STATE does not really reflect the state
+ of the pipeline for the instruction after the delay slot. Also,
+ branch likely instructions tend to incur a penalty when not taken,
+ so there will probably be an extra delay between the branch and
+ the instruction after the delay slot. */
+ if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
+ mips_sim_reset (state);
+ break;
+
+ default:
+ break;
+ }
}
\f
-/* The last instruction to be scheduled. */
-
-static rtx vr4130_last_insn;
+/* The VR4130 pipeline issues aligned pairs of instructions together,
+ but it stalls the second instruction if it depends on the first.
+ In order to cut down the amount of logic required, this dependence
+ check is not based on a full instruction decode. Instead, any non-SPECIAL
+ instruction is assumed to modify the register specified by bits 20-16
+ (which is usually the "rt" field).
-/* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
- points to an rtx that is initially an instruction. Nullify the rtx
- if the instruction uses the value of register X. */
+ In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
+ input, so we can end up with a false dependence between the branch
+ and its delay slot. If this situation occurs in instruction INSN,
+ try to avoid it by swapping rs and rt. */
static void
-vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
+vr4130_avoid_branch_rt_conflict (rtx insn)
{
- rtx *insn_ptr = data;
- if (REG_P (x)
- && *insn_ptr != 0
- && reg_referenced_p (x, PATTERN (*insn_ptr)))
- *insn_ptr = 0;
-}
-
-/* Return true if there is true register dependence between vr4130_last_insn
- and INSN. */
+ rtx first, second;
-static bool
-vr4130_true_reg_dependence_p (rtx insn)
-{
- note_stores (PATTERN (vr4130_last_insn),
- vr4130_true_reg_dependence_p_1, &insn);
- return insn == 0;
+ first = SEQ_BEGIN (insn);
+ second = SEQ_END (insn);
+ if (JUMP_P (first)
+ && NONJUMP_INSN_P (second)
+ && GET_CODE (PATTERN (first)) == SET
+ && GET_CODE (SET_DEST (PATTERN (first))) == PC
+ && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
+ {
+ /* Check for the right kind of condition. */
+ rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
+ if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
+ && REG_P (XEXP (cond, 0))
+ && REG_P (XEXP (cond, 1))
+ && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
+ && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
+ {
+ /* SECOND mentions the rt register but not the rs register. */
+ rtx tmp = XEXP (cond, 0);
+ XEXP (cond, 0) = XEXP (cond, 1);
+ XEXP (cond, 1) = tmp;
+ }
+ }
}
-/* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
- the ready queue and that INSN2 is the instruction after it, return
- true if it is worth promoting INSN2 ahead of INSN1. Look for cases
- in which INSN1 and INSN2 can probably issue in parallel, but for
- which (INSN2, INSN1) should be less sensitive to instruction
- alignment than (INSN1, INSN2). See 4130.md for more details. */
+/* Implement -mvr4130-align. Go through each basic block and simulate the
+ processor pipeline. If we find that a pair of instructions could execute
+ in parallel, and the first of those instructions is not 8-byte aligned,
+ insert a nop to make it aligned. */
-static bool
-vr4130_swap_insns_p (rtx insn1, rtx insn2)
+static void
+vr4130_align_insns (void)
{
- sd_iterator_def sd_it;
- dep_t dep;
+ struct mips_sim state;
+ rtx insn, subinsn, last, last2, next;
+ bool aligned_p;
- /* Check for the following case:
+ dfa_start ();
- 1) there is some other instruction X with an anti dependence on INSN1;
- 2) X has a higher priority than INSN2; and
- 3) X is an arithmetic instruction (and thus has no unit restrictions).
+ /* LAST is the last instruction before INSN to have a nonzero length.
+ LAST2 is the last such instruction before LAST. */
+ last = 0;
+ last2 = 0;
- If INSN1 is the last instruction blocking X, it would better to
- choose (INSN1, X) over (INSN2, INSN1). */
- FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
- if (DEP_TYPE (dep) == REG_DEP_ANTI
- && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
- && recog_memoized (DEP_CON (dep)) >= 0
- && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
- return false;
+ /* ALIGNED_P is true if INSN is known to be at an aligned address. */
+ aligned_p = true;
- if (vr4130_last_insn != 0
- && recog_memoized (insn1) >= 0
- && recog_memoized (insn2) >= 0)
+ mips_sim_init (&state, alloca (state_size ()));
+ for (insn = get_insns (); insn != 0; insn = next)
{
- /* See whether INSN1 and INSN2 use different execution units,
- or if they are both ALU-type instructions. If so, they can
- probably execute in parallel. */
- enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
- enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
- if (class1 != class2 || class1 == VR4130_CLASS_ALU)
- {
- /* If only one of the instructions has a dependence on
- vr4130_last_insn, prefer to schedule the other one first. */
- bool dep1 = vr4130_true_reg_dependence_p (insn1);
- bool dep2 = vr4130_true_reg_dependence_p (insn2);
- if (dep1 != dep2)
- return dep1;
+ unsigned int length;
- /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
- is not an ALU-type instruction and if INSN1 uses the same
- execution unit. (Note that if this condition holds, we already
- know that INSN2 uses a different execution unit.) */
- if (class1 != VR4130_CLASS_ALU
- && recog_memoized (vr4130_last_insn) >= 0
- && class1 == get_attr_vr4130_class (vr4130_last_insn))
- return true;
+ next = NEXT_INSN (insn);
+
+ /* See the comment above vr4130_avoid_branch_rt_conflict for details.
+ This isn't really related to the alignment pass, but we do it on
+ the fly to avoid a separate instruction walk. */
+ vr4130_avoid_branch_rt_conflict (insn);
+
+ if (USEFUL_INSN_P (insn))
+ FOR_EACH_SUBINSN (subinsn, insn)
+ {
+ mips_sim_wait_insn (&state, subinsn);
+
+ /* If we want this instruction to issue in parallel with the
+ previous one, make sure that the previous instruction is
+ aligned. There are several reasons why this isn't worthwhile
+ when the second instruction is a call:
+
+ - Calls are less likely to be performance critical,
+ - There's a good chance that the delay slot can execute
+ in parallel with the call.
+ - The return address would then be unaligned.
+
+ In general, if we're going to insert a nop between instructions
+ X and Y, it's better to insert it immediately after X. That
+ way, if the nop makes Y aligned, it will also align any labels
+ between X and Y. */
+ if (state.insns_left != state.issue_rate
+ && !CALL_P (subinsn))
+ {
+ if (subinsn == SEQ_BEGIN (insn) && aligned_p)
+ {
+ /* SUBINSN is the first instruction in INSN and INSN is
+ aligned. We want to align the previous instruction
+ instead, so insert a nop between LAST2 and LAST.
+
+ Note that LAST could be either a single instruction
+ or a branch with a delay slot. In the latter case,
+ LAST, like INSN, is already aligned, but the delay
+ slot must have some extra delay that stops it from
+ issuing at the same time as the branch. We therefore
+ insert a nop before the branch in order to align its
+ delay slot. */
+ emit_insn_after (gen_nop (), last2);
+ aligned_p = false;
+ }
+ else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
+ {
+ /* SUBINSN is the delay slot of INSN, but INSN is
+ currently unaligned. Insert a nop between
+ LAST and INSN to align it. */
+ emit_insn_after (gen_nop (), last);
+ aligned_p = true;
+ }
+ }
+ mips_sim_issue_insn (&state, subinsn);
+ }
+ mips_sim_finish_insn (&state, insn);
+
+ /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
+ length = get_attr_length (insn);
+ if (length > 0)
+ {
+ /* If the instruction is an asm statement or multi-instruction
+ mips.md patern, the length is only an estimate. Insert an
+ 8 byte alignment after it so that the following instructions
+ can be handled correctly. */
+ if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
+ && (recog_memoized (insn) < 0 || length >= 8))
+ {
+ next = emit_insn_after (gen_align (GEN_INT (3)), insn);
+ next = NEXT_INSN (next);
+ mips_sim_next_cycle (&state);
+ aligned_p = true;
+ }
+ else if (length & 4)
+ aligned_p = !aligned_p;
+ last2 = last;
+ last = insn;
}
+
+ /* See whether INSN is an aligned label. */
+ if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
+ aligned_p = true;
}
- return false;
+ dfa_finish ();
}
+\f
+/* This structure records that the current function has a LO_SUM
+ involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
+ the largest offset applied to BASE by all such LO_SUMs. */
+struct mips_lo_sum_offset {
+ rtx base;
+ HOST_WIDE_INT offset;
+};
-/* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
- queue with at least two instructions. Swap the first two if
- vr4130_swap_insns_p says that it could be worthwhile. */
+/* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
-static void
-vr4130_reorder (rtx *ready, int nready)
+static hashval_t
+mips_hash_base (rtx base)
{
- if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
- mips_promote_ready (ready, nready - 2, nready - 1);
+ int do_not_record_p;
+
+ return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
}
-\f
-/* Remove the instruction at index LOWER from ready queue READY and
- reinsert it in front of the instruction at index HIGHER. LOWER must
- be <= HIGHER. */
-static void
-mips_promote_ready (rtx *ready, int lower, int higher)
+/* Hash-table callbacks for mips_lo_sum_offsets. */
+
+static hashval_t
+mips_lo_sum_offset_hash (const void *entry)
{
- rtx new_head;
- int i;
+ return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
+}
- new_head = ready[lower];
- for (i = lower; i < higher; i++)
- ready[i] = ready[i + 1];
- ready[i] = new_head;
+static int
+mips_lo_sum_offset_eq (const void *entry, const void *value)
+{
+ return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
+ (const_rtx) value);
}
-/* If the priority of the instruction at POS2 in the ready queue READY
- is within LIMIT units of that of the instruction at POS1, swap the
- instructions if POS2 is not already less than POS1. */
+/* Look up symbolic constant X in HTAB, which is a hash table of
+ mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
+ paired with a recorded LO_SUM, otherwise record X in the table. */
-static void
-mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
+static bool
+mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
{
- if (pos1 < pos2
- && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
+ rtx base, offset;
+ void **slot;
+ struct mips_lo_sum_offset *entry;
+
+ /* Split X into a base and offset. */
+ split_const (x, &base, &offset);
+ if (UNSPEC_ADDRESS_P (base))
+ base = UNSPEC_ADDRESS (base);
+
+ /* Look up the base in the hash table. */
+ slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
+ if (slot == NULL)
+ return false;
+
+ entry = (struct mips_lo_sum_offset *) *slot;
+ if (option == INSERT)
{
- rtx temp;
- temp = ready[pos1];
- ready[pos1] = ready[pos2];
- ready[pos2] = temp;
+ if (entry == NULL)
+ {
+ entry = XNEW (struct mips_lo_sum_offset);
+ entry->base = base;
+ entry->offset = INTVAL (offset);
+ *slot = entry;
+ }
+ else
+ {
+ if (INTVAL (offset) > entry->offset)
+ entry->offset = INTVAL (offset);
+ }
}
+ return INTVAL (offset) <= entry->offset;
}
-/* Record whether last 74k AGEN instruction was a load or store. */
+/* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
+ Record every LO_SUM in *LOC. */
-static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
+static int
+mips_record_lo_sum (rtx *loc, void *data)
+{
+ if (GET_CODE (*loc) == LO_SUM)
+ mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
+ return 0;
+}
-/* Initialize mips_last_74k_agen_insn from INSN. A null argument
- resets to TYPE_UNKNOWN state. */
+/* Return true if INSN is a SET of an orphaned high-part relocation.
+ HTAB is a hash table of mips_lo_sum_offsets that describes all the
+ LO_SUMs in the current function. */
-static void
-mips_74k_agen_init (rtx insn)
+static bool
+mips_orphaned_high_part_p (htab_t htab, rtx insn)
{
- if (!insn || !NONJUMP_INSN_P (insn))
- mips_last_74k_agen_insn = TYPE_UNKNOWN;
- else if (USEFUL_INSN_P (insn))
+ enum mips_symbol_type type;
+ rtx x, set;
+
+ set = single_set (insn);
+ if (set)
{
- enum attr_type type = get_attr_type (insn);
- if (type == TYPE_LOAD || type == TYPE_STORE)
- mips_last_74k_agen_insn = type;
+ /* Check for %his. */
+ x = SET_SRC (set);
+ if (GET_CODE (x) == HIGH
+ && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
+ return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
+
+ /* Check for local %gots (and %got_pages, which is redundant but OK). */
+ if (GET_CODE (x) == UNSPEC
+ && XINT (x, 1) == UNSPEC_LOAD_GOT
+ && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
+ SYMBOL_CONTEXT_LEA, &type)
+ && type == SYMBOL_GOTOFF_PAGE)
+ return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
}
+ return false;
}
-/* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
- loads to be grouped together, and multiple stores to be grouped
- together. Swap things around in the ready queue to make this happen. */
+/* Subroutine of mips_reorg_process_insns. If there is a hazard between
+ INSN and a previous instruction, avoid it by inserting nops after
+ instruction AFTER.
+
+ *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
+ this point. If *DELAYED_REG is non-null, INSN must wait a cycle
+ before using the value of that register. *HILO_DELAY counts the
+ number of instructions since the last hilo hazard (that is,
+ the number of instructions since the last MFLO or MFHI).
+
+ After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
+ for the next instruction.
+
+ LO_REG is an rtx for the LO register, used in dependence checking. */
static void
-mips_74k_agen_reorder (rtx *ready, int nready)
+mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
+ rtx *delayed_reg, rtx lo_reg)
{
- int i;
- int store_pos, load_pos;
+ rtx pattern, set;
+ int nops, ninsns;
- store_pos = -1;
- load_pos = -1;
+ pattern = PATTERN (insn);
- for (i = nready - 1; i >= 0; i--)
- {
- rtx insn = ready[i];
- if (USEFUL_INSN_P (insn))
- switch (get_attr_type (insn))
- {
- case TYPE_STORE:
- if (store_pos == -1)
- store_pos = i;
- break;
-
- case TYPE_LOAD:
- if (load_pos == -1)
- load_pos = i;
- break;
-
- default:
- break;
- }
- }
-
- if (load_pos == -1 || store_pos == -1)
+ /* Do not put the whole function in .set noreorder if it contains
+ an asm statement. We don't know whether there will be hazards
+ between the asm statement and the gcc-generated code. */
+ if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
+ cfun->machine->all_noreorder_p = false;
+
+ /* Ignore zero-length instructions (barriers and the like). */
+ ninsns = get_attr_length (insn) / 4;
+ if (ninsns == 0)
return;
-
- switch (mips_last_74k_agen_insn)
- {
- case TYPE_UNKNOWN:
- /* Prefer to schedule loads since they have a higher latency. */
- case TYPE_LOAD:
- /* Swap loads to the front of the queue. */
- mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
- break;
- case TYPE_STORE:
- /* Swap stores to the front of the queue. */
- mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
- break;
- default:
- break;
- }
+
+ /* Work out how many nops are needed. Note that we only care about
+ registers that are explicitly mentioned in the instruction's pattern.
+ It doesn't matter that calls use the argument registers or that they
+ clobber hi and lo. */
+ if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
+ nops = 2 - *hilo_delay;
+ else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
+ nops = 1;
+ else
+ nops = 0;
+
+ /* Insert the nops between this instruction and the previous one.
+ Each new nop takes us further from the last hilo hazard. */
+ *hilo_delay += nops;
+ while (nops-- > 0)
+ emit_insn_after (gen_hazard_nop (), after);
+
+ /* Set up the state for the next instruction. */
+ *hilo_delay += ninsns;
+ *delayed_reg = 0;
+ if (INSN_CODE (insn) >= 0)
+ switch (get_attr_hazard (insn))
+ {
+ case HAZARD_NONE:
+ break;
+
+ case HAZARD_HILO:
+ *hilo_delay = 0;
+ break;
+
+ case HAZARD_DELAY:
+ set = single_set (insn);
+ gcc_assert (set);
+ *delayed_reg = SET_DEST (set);
+ break;
+ }
}
-/* Implement TARGET_SCHED_INIT. */
+/* Go through the instruction stream and insert nops where necessary.
+ Also delete any high-part relocations whose partnering low parts
+ are now all dead. See if the whole function can then be put into
+ .set noreorder and .set nomacro. */
static void
-mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
- int max_ready ATTRIBUTE_UNUSED)
+mips_reorg_process_insns (void)
{
- mips_macc_chains_last_hilo = 0;
- vr4130_last_insn = 0;
- mips_74k_agen_init (NULL_RTX);
-}
+ rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
+ int hilo_delay;
+ htab_t htab;
-/* Implement TARGET_SCHED_REORDER and TARG_SCHED_REORDER2. */
+ /* Force all instructions to be split into their final form. */
+ split_all_insns_noflow ();
-static int
-mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
- rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
-{
- if (!reload_completed
- && TUNE_MACC_CHAINS
- && *nreadyp > 0)
- mips_macc_chains_reorder (ready, *nreadyp);
- if (reload_completed
- && TUNE_MIPS4130
- && !TARGET_VR4130_ALIGN
- && *nreadyp > 1)
- vr4130_reorder (ready, *nreadyp);
- if (TUNE_74K)
- mips_74k_agen_reorder (ready, *nreadyp);
- return mips_issue_rate ();
-}
+ /* Recalculate instruction lengths without taking nops into account. */
+ cfun->machine->ignore_hazard_length_p = true;
+ shorten_branches (get_insns ());
-/* Implement TARGET_SCHED_VARIABLE_ISSUE. */
+ cfun->machine->all_noreorder_p = true;
-static int
-mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
- rtx insn, int more)
-{
- if (TUNE_74K)
- mips_74k_agen_init (insn);
- switch (GET_CODE (PATTERN (insn)))
- {
- case USE:
- case CLOBBER:
- /* Don't count USEs and CLOBBERs against the issue rate. */
- break;
+ /* Code that doesn't use explicit relocs can't be ".set nomacro". */
+ if (!TARGET_EXPLICIT_RELOCS)
+ cfun->machine->all_noreorder_p = false;
- default:
- more--;
- if (!reload_completed && TUNE_MACC_CHAINS)
- mips_macc_chains_record (insn);
- vr4130_last_insn = insn;
- break;
+ /* Profiled functions can't be all noreorder because the profiler
+ support uses assembler macros. */
+ if (current_function_profile)
+ cfun->machine->all_noreorder_p = false;
+
+ /* Code compiled with -mfix-vr4120 can't be all noreorder because
+ we rely on the assembler to work around some errata. */
+ if (TARGET_FIX_VR4120)
+ cfun->machine->all_noreorder_p = false;
+
+ /* The same is true for -mfix-vr4130 if we might generate MFLO or
+ MFHI instructions. Note that we avoid using MFLO and MFHI if
+ the VR4130 MACC and DMACC instructions are available instead;
+ see the *mfhilo_{si,di}_macc patterns. */
+ if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
+ cfun->machine->all_noreorder_p = false;
+
+ htab = htab_create (37, mips_lo_sum_offset_hash,
+ mips_lo_sum_offset_eq, free);
+
+ /* Make a first pass over the instructions, recording all the LO_SUMs. */
+ for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
+ FOR_EACH_SUBINSN (subinsn, insn)
+ if (INSN_P (subinsn))
+ for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
+
+ last_insn = 0;
+ hilo_delay = 2;
+ delayed_reg = 0;
+ lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
+
+ /* Make a second pass over the instructions. Delete orphaned
+ high-part relocations or turn them into NOPs. Avoid hazards
+ by inserting NOPs. */
+ for (insn = get_insns (); insn != 0; insn = next_insn)
+ {
+ next_insn = NEXT_INSN (insn);
+ if (INSN_P (insn))
+ {
+ if (GET_CODE (PATTERN (insn)) == SEQUENCE)
+ {
+ /* If we find an orphaned high-part relocation in a delay
+ slot, it's easier to turn that instruction into a NOP than
+ to delete it. The delay slot will be a NOP either way. */
+ FOR_EACH_SUBINSN (subinsn, insn)
+ if (INSN_P (subinsn))
+ {
+ if (mips_orphaned_high_part_p (htab, subinsn))
+ {
+ PATTERN (subinsn) = gen_nop ();
+ INSN_CODE (subinsn) = CODE_FOR_nop;
+ }
+ mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
+ &delayed_reg, lo_reg);
+ }
+ last_insn = insn;
+ }
+ else
+ {
+ /* INSN is a single instruction. Delete it if it's an
+ orphaned high-part relocation. */
+ if (mips_orphaned_high_part_p (htab, insn))
+ delete_insn (insn);
+ else
+ {
+ mips_avoid_hazard (last_insn, insn, &hilo_delay,
+ &delayed_reg, lo_reg);
+ last_insn = insn;
+ }
+ }
+ }
}
- return more;
+
+ htab_delete (htab);
}
-\f
-/* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
- dependencies have no cost, except on the 20Kc where output-dependence
- is treated like input-dependence. */
-static int
-mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
- rtx dep ATTRIBUTE_UNUSED, int cost)
+/* Implement TARGET_MACHINE_DEPENDENT_REORG. */
+
+static void
+mips_reorg (void)
{
- if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
- && TUNE_20KC)
- return cost;
- if (REG_NOTE_KIND (link) != 0)
- return 0;
- return cost;
+ mips16_lay_out_constants ();
+ if (mips_base_delayed_branch)
+ dbr_schedule (get_insns ());
+ mips_reorg_process_insns ();
+ if (TARGET_EXPLICIT_RELOCS && TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
+ vr4130_align_insns ();
}
+\f
+/* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
+ in order to avoid duplicating too much logic from elsewhere. */
-/* Return the number of instructions that can be issued per cycle. */
-
-static int
-mips_issue_rate (void)
+static void
+mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+ HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
+ tree function)
{
- switch (mips_tune)
- {
- case PROCESSOR_74KC:
- case PROCESSOR_74KF2_1:
- case PROCESSOR_74KF1_1:
- case PROCESSOR_74KF3_2:
- /* The 74k is not strictly quad-issue cpu, but can be seen as one
- by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
- but in reality only a maximum of 3 insns can be issued as the
- floating point load/stores also require a slot in the AGEN pipe. */
- return 4;
+ rtx this, temp1, temp2, insn, fnaddr;
+ bool use_sibcall_p;
- case PROCESSOR_20KC:
- case PROCESSOR_R4130:
- case PROCESSOR_R5400:
- case PROCESSOR_R5500:
- case PROCESSOR_R7000:
- case PROCESSOR_R9000:
- return 2;
+ /* Pretend to be a post-reload pass while generating rtl. */
+ reload_completed = 1;
- case PROCESSOR_SB1:
- case PROCESSOR_SB1A:
- /* This is actually 4, but we get better performance if we claim 3.
- This is partly because of unwanted speculative code motion with the
- larger number, and partly because in most common cases we can't
- reach the theoretical max of 4. */
- return 3;
+ /* Mark the end of the (empty) prologue. */
+ emit_note (NOTE_INSN_PROLOGUE_END);
- default:
- return 1;
+ /* Determine if we can use a sibcall to call FUNCTION directly. */
+ fnaddr = XEXP (DECL_RTL (function), 0);
+ use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
+ && const_call_insn_operand (fnaddr, Pmode));
+
+ /* Determine if we need to load FNADDR from the GOT. */
+ if (!use_sibcall_p)
+ switch (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))
+ {
+ case SYMBOL_GOT_PAGE_OFST:
+ case SYMBOL_GOT_DISP:
+ /* Pick a global pointer. Use a call-clobbered register if
+ TARGET_CALL_SAVED_GP. */
+ cfun->machine->global_pointer =
+ TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
+ SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
+
+ /* Set up the global pointer for n32 or n64 abicalls. */
+ mips_emit_loadgp ();
+ break;
+
+ default:
+ break;
+ }
+
+ /* We need two temporary registers in some cases. */
+ temp1 = gen_rtx_REG (Pmode, 2);
+ temp2 = gen_rtx_REG (Pmode, 3);
+
+ /* Find out which register contains the "this" pointer. */
+ if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
+ this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
+ else
+ this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
+
+ /* Add DELTA to THIS. */
+ if (delta != 0)
+ {
+ rtx offset = GEN_INT (delta);
+ if (!SMALL_OPERAND (delta))
+ {
+ mips_emit_move (temp1, offset);
+ offset = temp1;
+ }
+ emit_insn (gen_add3_insn (this, this, offset));
}
-}
-/* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
- be as wide as the scheduling freedom in the DFA. */
+ /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
+ if (vcall_offset != 0)
+ {
+ rtx addr;
-static int
-mips_multipass_dfa_lookahead (void)
-{
- /* Can schedule up to 4 of the 6 function units in any one cycle. */
- if (TUNE_SB1)
- return 4;
+ /* Set TEMP1 to *THIS. */
+ mips_emit_move (temp1, gen_rtx_MEM (Pmode, this));
- return 0;
-}
+ /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
+ addr = mips_add_offset (temp2, temp1, vcall_offset);
-/* Implements a store data bypass check. We need this because the cprestore
- pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
- default routine to abort. We just return false for that case. */
-/* ??? Should try to give a better result here than assuming false. */
+ /* Load the offset and add it to THIS. */
+ mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
+ emit_insn (gen_add3_insn (this, this, temp1));
+ }
-int
-mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
-{
- if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
- return false;
+ /* Jump to the target function. Use a sibcall if direct jumps are
+ allowed, otherwise load the address into a register first. */
+ if (use_sibcall_p)
+ {
+ insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
+ SIBLING_CALL_P (insn) = 1;
+ }
+ else
+ {
+ /* This is messy. GAS treats "la $25,foo" as part of a call
+ sequence and may allow a global "foo" to be lazily bound.
+ The general move patterns therefore reject this combination.
- return ! store_data_bypass_p (out_insn, in_insn);
-}
-\f
-/* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
- return the first operand of the associated "pref" or "prefx" insn. */
+ In this context, lazy binding would actually be OK
+ for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
+ TARGET_CALL_SAVED_GP; see mips_load_call_address.
+ We must therefore load the address via a temporary
+ register if mips_dangerous_for_la25_p.
-rtx
-mips_prefetch_cookie (rtx write, rtx locality)
-{
- /* store_streamed / load_streamed. */
- if (INTVAL (locality) <= 0)
- return GEN_INT (INTVAL (write) + 4);
+ If we jump to the temporary register rather than $25, the assembler
+ can use the move insn to fill the jump's delay slot. */
+ if (TARGET_USE_PIC_FN_ADDR_REG
+ && !mips_dangerous_for_la25_p (fnaddr))
+ temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
+ mips_load_call_address (temp1, fnaddr, true);
- /* store / load. */
- if (INTVAL (locality) <= 2)
- return write;
+ if (TARGET_USE_PIC_FN_ADDR_REG
+ && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
+ mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
+ emit_jump_insn (gen_indirect_jump (temp1));
+ }
- /* store_retained / load_retained. */
- return GEN_INT (INTVAL (write) + 6);
+ /* Run just enough of rest_of_compilation. This sequence was
+ "borrowed" from alpha.c. */
+ insn = get_insns ();
+ insn_locators_alloc ();
+ split_all_insns_noflow ();
+ mips16_lay_out_constants ();
+ shorten_branches (insn);
+ final_start_function (insn, file, 1);
+ final (insn, file, 1);
+ final_end_function ();
+ free_after_compilation (cfun);
+
+ /* Clean up the vars set above. Note that final_end_function resets
+ the global pointer for us. */
+ reload_completed = 0;
}
\f
-/* MIPS builtin function support. */
-
-struct builtin_description
-{
- /* The code of the main .md file instruction. See mips_builtin_type
- for more information. */
- enum insn_code icode;
-
- /* The floating-point comparison code to use with ICODE, if any. */
- enum mips_fp_condition cond;
+/* The last argument passed to mips_set_mips16_mode, or negative if the
+ function hasn't been called yet. */
+static GTY(()) int was_mips16_p = -1;
- /* The name of the builtin function. */
- const char *name;
+/* Set up the target-dependent global state so that it matches the
+ current function's ISA mode. */
- /* Specifies how the function should be expanded. */
- enum mips_builtin_type builtin_type;
+static void
+mips_set_mips16_mode (int mips16_p)
+{
+ if (mips16_p == was_mips16_p)
+ return;
- /* The function's prototype. */
- enum mips_function_type function_type;
+ /* Restore base settings of various flags. */
+ target_flags = mips_base_target_flags;
+ flag_schedule_insns = mips_base_schedule_insns;
+ flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
+ flag_move_loop_invariants = mips_base_move_loop_invariants;
+ align_loops = mips_base_align_loops;
+ align_jumps = mips_base_align_jumps;
+ align_functions = mips_base_align_functions;
- /* The target flags required for this function. */
- int target_flags;
-};
+ if (mips16_p)
+ {
+ /* Switch to MIPS16 mode. */
+ target_flags |= MASK_MIPS16;
-/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
- FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
-#define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
- { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
- MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
+ /* Don't run the scheduler before reload, since it tends to
+ increase register pressure. */
+ flag_schedule_insns = 0;
-/* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
- TARGET_FLAGS. */
-#define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
- { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
- "__builtin_mips_" #INSN "_" #COND "_s", \
- MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
- { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
- "__builtin_mips_" #INSN "_" #COND "_d", \
- MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
+ /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
+ the whole function to be in a single section. */
+ flag_reorder_blocks_and_partition = 0;
-/* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
- The lower and upper forms require TARGET_FLAGS while the any and all
- forms require MASK_MIPS3D. */
-#define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
- { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
- "__builtin_mips_any_" #INSN "_" #COND "_ps", \
- MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
- { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
- "__builtin_mips_all_" #INSN "_" #COND "_ps", \
- MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
- { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
- "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
- MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
- { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
- "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
- MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
+ /* Don't move loop invariants, because it tends to increase
+ register pressure. It also introduces an extra move in cases
+ where the constant is the first operand in a two-operand binary
+ instruction, or when it forms a register argument to a functon
+ call. */
+ flag_move_loop_invariants = 0;
-/* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
- require MASK_MIPS3D. */
-#define CMP_4S_BUILTINS(INSN, COND) \
- { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
- "__builtin_mips_any_" #INSN "_" #COND "_4s", \
- MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
- MASK_MIPS3D }, \
- { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
- "__builtin_mips_all_" #INSN "_" #COND "_4s", \
- MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
- MASK_MIPS3D }
+ /* Silently disable -mexplicit-relocs since it doesn't apply
+ to MIPS16 code. Even so, it would overly pedantic to warn
+ about "-mips16 -mexplicit-relocs", especially given that
+ we use a %gprel() operator. */
+ target_flags &= ~MASK_EXPLICIT_RELOCS;
-/* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
- instruction requires TARGET_FLAGS. */
-#define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
- { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
- "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
- MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
- TARGET_FLAGS }, \
- { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
- "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
- MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
- TARGET_FLAGS }
+ /* Experiments suggest we get the best overall section-anchor
+ results from using the range of an unextended LW or SW. Code
+ that makes heavy use of byte or short accesses can do better
+ with ranges of 0...31 and 0...63 respectively, but most code is
+ sensitive to the range of LW and SW instead. */
+ targetm.min_anchor_offset = 0;
+ targetm.max_anchor_offset = 127;
-/* Define all the builtins related to c.cond.fmt condition COND. */
-#define CMP_BUILTINS(COND) \
- MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
- MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
- CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
- CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
- CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
- CMP_4S_BUILTINS (c, COND), \
- CMP_4S_BUILTINS (cabs, COND)
+ if (flag_pic || TARGET_ABICALLS)
+ sorry ("MIPS16 PIC");
-static const struct builtin_description mips_bdesc[] =
-{
- DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
- DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
- DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
- DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
- DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
- DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
- DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
- DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
+ if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
+ sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
+ }
+ else
+ {
+ /* Switch to normal (non-MIPS16) mode. */
+ target_flags &= ~MASK_MIPS16;
- DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
- MASK_PAIRED_SINGLE_FLOAT),
- DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
- DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
- DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
- DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
+ /* Provide default values for align_* for 64-bit targets. */
+ if (TARGET_64BIT)
+ {
+ if (align_loops == 0)
+ align_loops = 8;
+ if (align_jumps == 0)
+ align_jumps = 8;
+ if (align_functions == 0)
+ align_functions = 8;
+ }
- DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
- DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
- DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
- DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
- DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
- DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
+ targetm.min_anchor_offset = -32768;
+ targetm.max_anchor_offset = 32767;
+ }
- DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
- DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
- DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
- DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
- DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
- DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
+ /* (Re)initialize MIPS target internals for new ISA. */
+ mips_init_relocs ();
- MIPS_FP_CONDITIONS (CMP_BUILTINS)
-};
+ if (was_mips16_p >= 0)
+ /* Reinitialize target-dependent state. */
+ target_reinit ();
-/* Builtin functions for the SB-1 processor. */
+ was_mips16_p = mips16_p;
+}
-#define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
+/* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
+ function should use the MIPS16 ISA and switch modes accordingly. */
-static const struct builtin_description sb1_bdesc[] =
+static void
+mips_set_current_function (tree fndecl)
{
- DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
-};
+ mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
+}
+\f
+/* Allocate a chunk of memory for per-function machine-dependent data. */
-/* Builtin functions for DSP ASE. */
+static struct machine_function *
+mips_init_machine_status (void)
+{
+ return ((struct machine_function *)
+ ggc_alloc_cleared (sizeof (struct machine_function)));
+}
-#define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
-#define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
-#define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
-#define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
-#define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
+/* Return the processor associated with the given ISA level, or null
+ if the ISA isn't valid. */
-/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
- CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
- builtin_description fields. */
-#define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
- { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
- MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
+static const struct mips_cpu_info *
+mips_cpu_info_from_isa (int isa)
+{
+ unsigned int i;
-/* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
- branch instruction. TARGET_FLAGS is a builtin_description field. */
-#define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
- { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
- MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
+ for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
+ if (mips_cpu_info_table[i].isa == isa)
+ return mips_cpu_info_table + i;
-static const struct builtin_description dsp_bdesc[] =
-{
- DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
- DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
- DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
- DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
- DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
- DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
- DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
- DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
- DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
- DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
- DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
- DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
- DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
- DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
- DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
- DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
- DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
- DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
- DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
- DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
- DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
- DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
- DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
- DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
- DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
- DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
- DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
- DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
- DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
- DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
- DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
- DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
- DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
- DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
- DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
- DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
- DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
- DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
- DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
- DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
- DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
- DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
- DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
- DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
- DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
- DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
- DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
- DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
- DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
- DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
- DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
- BPOSGE_BUILTIN (32, MASK_DSP),
+ return NULL;
+}
- /* The following are for the MIPS DSP ASE REV 2. */
- DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, MASK_DSPR2),
- DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
- DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
- DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
- DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
- DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
- DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
- DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
- DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
- DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
- DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
- DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
- DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
- DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
- DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
- DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSPR2),
- DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
- DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
- DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
- DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
- DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
- DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2)
-};
+/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
+ with a final "000" replaced by "k". Ignore case.
+
+ Note: this function is shared between GCC and GAS. */
-static const struct builtin_description dsp_32only_bdesc[] =
+static bool
+mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
{
- DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
- DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
- DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
- DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
- DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
- DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
- DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
- DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
- DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
- DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
- DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
- DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
- DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
- DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
- DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
+ while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
+ given++, canonical++;
- /* The following are for the MIPS DSP ASE REV 2. */
- DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
- DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
- DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
- DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
- DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, MASK_DSPR2),
- DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, MASK_DSPR2),
- DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
- DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2)
-};
+ return ((*given == 0 && *canonical == 0)
+ || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
+}
+
+/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
+ CPU name. We've traditionally allowed a lot of variation here.
-/* This helps provide a mapping from builtin function codes to bdesc
- arrays. */
+ Note: this function is shared between GCC and GAS. */
-struct bdesc_map
+static bool
+mips_matching_cpu_name_p (const char *canonical, const char *given)
{
- /* The builtin function table that this entry describes. */
- const struct builtin_description *bdesc;
+ /* First see if the name matches exactly, or with a final "000"
+ turned into "k". */
+ if (mips_strict_matching_cpu_name_p (canonical, given))
+ return true;
- /* The number of entries in the builtin function table. */
- unsigned int size;
+ /* If not, try comparing based on numerical designation alone.
+ See if GIVEN is an unadorned number, or 'r' followed by a number. */
+ if (TOLOWER (*given) == 'r')
+ given++;
+ if (!ISDIGIT (*given))
+ return false;
- /* The target processor that supports these builtin functions.
- PROCESSOR_MAX means we enable them for all processors. */
- enum processor_type proc;
+ /* Skip over some well-known prefixes in the canonical name,
+ hoping to find a number there too. */
+ if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
+ canonical += 2;
+ else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
+ canonical += 2;
+ else if (TOLOWER (canonical[0]) == 'r')
+ canonical += 1;
- /* If the target has these flags, this builtin function table
- will not be supported. */
- int unsupported_target_flags;
-};
+ return mips_strict_matching_cpu_name_p (canonical, given);
+}
-static const struct bdesc_map bdesc_arrays[] =
-{
- { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX, 0 },
- { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1, 0 },
- { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX, 0 },
- { dsp_32only_bdesc, ARRAY_SIZE (dsp_32only_bdesc), PROCESSOR_MAX,
- MASK_64BIT }
-};
+/* Return the mips_cpu_info entry for the processor or ISA given
+ by CPU_STRING. Return null if the string isn't recognized.
-/* Take the argument ARGNUM of the arglist of EXP and convert it into a form
- suitable for input operand OP of instruction ICODE. Return the value. */
+ A similar function exists in GAS. */
-static rtx
-mips_prepare_builtin_arg (enum insn_code icode,
- unsigned int op, tree exp, unsigned int argnum)
+static const struct mips_cpu_info *
+mips_parse_cpu (const char *cpu_string)
{
- rtx value;
- enum machine_mode mode;
+ unsigned int i;
+ const char *s;
- value = expand_normal (CALL_EXPR_ARG (exp, argnum));
- mode = insn_data[icode].operand[op].mode;
- if (!insn_data[icode].operand[op].predicate (value, mode))
+ /* In the past, we allowed upper-case CPU names, but it doesn't
+ work well with the multilib machinery. */
+ for (s = cpu_string; *s != 0; s++)
+ if (ISUPPER (*s))
+ {
+ warning (0, "CPU names must be lower case");
+ break;
+ }
+
+ /* 'from-abi' selects the most compatible architecture for the given
+ ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
+ EABIs, we have to decide whether we're using the 32-bit or 64-bit
+ version. */
+ if (strcasecmp (cpu_string, "from-abi") == 0)
+ return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
+ : ABI_NEEDS_64BIT_REGS ? 3
+ : (TARGET_64BIT ? 3 : 1));
+
+ /* 'default' has traditionally been a no-op. Probably not very useful. */
+ if (strcasecmp (cpu_string, "default") == 0)
+ return NULL;
+
+ for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
+ if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
+ return mips_cpu_info_table + i;
+
+ return NULL;
+}
+
+/* Set up globals to generate code for the ISA or processor
+ described by INFO. */
+
+static void
+mips_set_architecture (const struct mips_cpu_info *info)
+{
+ if (info != 0)
{
- value = copy_to_mode_reg (mode, value);
- /* Check the predicate again. */
- if (!insn_data[icode].operand[op].predicate (value, mode))
- {
- error ("invalid argument to builtin function");
- return const0_rtx;
- }
+ mips_arch_info = info;
+ mips_arch = info->cpu;
+ mips_isa = info->isa;
}
+}
- return value;
+/* Likewise for tuning. */
+
+static void
+mips_set_tune (const struct mips_cpu_info *info)
+{
+ if (info != 0)
+ {
+ mips_tune_info = info;
+ mips_tune = info->cpu;
+ }
}
-/* Return an rtx suitable for output operand OP of instruction ICODE.
- If TARGET is non-null, try to use it where possible. */
+/* Implement TARGET_HANDLE_OPTION. */
-static rtx
-mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
+static bool
+mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
{
- enum machine_mode mode;
+ switch (code)
+ {
+ case OPT_mabi_:
+ if (strcmp (arg, "32") == 0)
+ mips_abi = ABI_32;
+ else if (strcmp (arg, "o64") == 0)
+ mips_abi = ABI_O64;
+ else if (strcmp (arg, "n32") == 0)
+ mips_abi = ABI_N32;
+ else if (strcmp (arg, "64") == 0)
+ mips_abi = ABI_64;
+ else if (strcmp (arg, "eabi") == 0)
+ mips_abi = ABI_EABI;
+ else
+ return false;
+ return true;
- mode = insn_data[icode].operand[op].mode;
- if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
- target = gen_reg_rtx (mode);
+ case OPT_march_:
+ case OPT_mtune_:
+ return mips_parse_cpu (arg) != 0;
- return target;
+ case OPT_mips:
+ mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
+ return mips_isa_option_info != 0;
+
+ case OPT_mno_flush_func:
+ mips_cache_flush_func = NULL;
+ return true;
+
+ case OPT_mcode_readable_:
+ if (strcmp (arg, "yes") == 0)
+ mips_code_readable = CODE_READABLE_YES;
+ else if (strcmp (arg, "pcrel") == 0)
+ mips_code_readable = CODE_READABLE_PCREL;
+ else if (strcmp (arg, "no") == 0)
+ mips_code_readable = CODE_READABLE_NO;
+ else
+ return false;
+ return true;
+
+ default:
+ return true;
+ }
}
-/* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
+/* Implement OVERRIDE_OPTIONS. */
-rtx
-mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
- enum machine_mode mode ATTRIBUTE_UNUSED,
- int ignore ATTRIBUTE_UNUSED)
+void
+mips_override_options (void)
{
- enum insn_code icode;
- enum mips_builtin_type type;
- tree fndecl;
- unsigned int fcode;
- const struct builtin_description *bdesc;
- const struct bdesc_map *m;
+ int i, start, regno, mode;
- fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
- fcode = DECL_FUNCTION_CODE (fndecl);
+#ifdef SUBTARGET_OVERRIDE_OPTIONS
+ SUBTARGET_OVERRIDE_OPTIONS;
+#endif
- if (TARGET_MIPS16)
+ /* Set the small data limit. */
+ mips_small_data_threshold = (g_switch_set
+ ? g_switch_value
+ : MIPS_DEFAULT_GVALUE);
+
+ /* The following code determines the architecture and register size.
+ Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
+ The GAS and GCC code should be kept in sync as much as possible. */
+
+ if (mips_arch_string != 0)
+ mips_set_architecture (mips_parse_cpu (mips_arch_string));
+
+ if (mips_isa_option_info != 0)
{
- error ("built-in function %qs not supported for MIPS16",
- IDENTIFIER_POINTER (DECL_NAME (fndecl)));
- return const0_rtx;
+ if (mips_arch_info == 0)
+ mips_set_architecture (mips_isa_option_info);
+ else if (mips_arch_info->isa != mips_isa_option_info->isa)
+ error ("%<-%s%> conflicts with the other architecture options, "
+ "which specify a %s processor",
+ mips_isa_option_info->name,
+ mips_cpu_info_from_isa (mips_arch_info->isa)->name);
}
- bdesc = NULL;
- for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
+ if (mips_arch_info == 0)
{
- if (fcode < m->size)
+#ifdef MIPS_CPU_STRING_DEFAULT
+ mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
+#else
+ mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
+#endif
+ }
+
+ if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
+ error ("%<-march=%s%> is not compatible with the selected ABI",
+ mips_arch_info->name);
+
+ /* Optimize for mips_arch, unless -mtune selects a different processor. */
+ if (mips_tune_string != 0)
+ mips_set_tune (mips_parse_cpu (mips_tune_string));
+
+ if (mips_tune_info == 0)
+ mips_set_tune (mips_arch_info);
+
+ if ((target_flags_explicit & MASK_64BIT) != 0)
+ {
+ /* The user specified the size of the integer registers. Make sure
+ it agrees with the ABI and ISA. */
+ if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
+ error ("%<-mgp64%> used with a 32-bit processor");
+ else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
+ error ("%<-mgp32%> used with a 64-bit ABI");
+ else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
+ error ("%<-mgp64%> used with a 32-bit ABI");
+ }
+ else
+ {
+ /* Infer the integer register size from the ABI and processor.
+ Restrict ourselves to 32-bit registers if that's all the
+ processor has, or if the ABI cannot handle 64-bit registers. */
+ if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
+ target_flags &= ~MASK_64BIT;
+ else
+ target_flags |= MASK_64BIT;
+ }
+
+ if ((target_flags_explicit & MASK_FLOAT64) != 0)
+ {
+ if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
+ error ("unsupported combination: %s", "-mfp64 -msingle-float");
+ else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
+ error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
+ else if (!TARGET_64BIT && TARGET_FLOAT64)
{
- bdesc = m->bdesc;
- icode = bdesc[fcode].icode;
- type = bdesc[fcode].builtin_type;
- break;
+ if (!ISA_HAS_MXHC1)
+ error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
+ " the target supports the mfhc1 and mthc1 instructions");
+ else if (mips_abi != ABI_32)
+ error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
+ " the o32 ABI");
}
- fcode -= m->size;
}
- if (bdesc == NULL)
- return 0;
+ else
+ {
+ /* -msingle-float selects 32-bit float registers. Otherwise the
+ float registers should be the same size as the integer ones. */
+ if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
+ target_flags |= MASK_FLOAT64;
+ else
+ target_flags &= ~MASK_FLOAT64;
+ }
- switch (type)
+ /* End of code shared with GAS. */
+
+ /* If no -mlong* option was given, infer it from the other options. */
+ if ((target_flags_explicit & MASK_LONG64) == 0)
{
- case MIPS_BUILTIN_DIRECT:
- return mips_expand_builtin_direct (icode, target, exp, true);
+ if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
+ target_flags |= MASK_LONG64;
+ else
+ target_flags &= ~MASK_LONG64;
+ }
- case MIPS_BUILTIN_DIRECT_NO_TARGET:
- return mips_expand_builtin_direct (icode, target, exp, false);
+ if (!TARGET_OLDABI)
+ flag_pcc_struct_return = 0;
- case MIPS_BUILTIN_MOVT:
- case MIPS_BUILTIN_MOVF:
- return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
- target, exp);
+ /* Decide which rtx_costs structure to use. */
+ if (optimize_size)
+ mips_cost = &mips_rtx_cost_optimize_size;
+ else
+ mips_cost = &mips_rtx_cost_data[mips_tune];
- case MIPS_BUILTIN_CMP_ANY:
- case MIPS_BUILTIN_CMP_ALL:
- case MIPS_BUILTIN_CMP_UPPER:
- case MIPS_BUILTIN_CMP_LOWER:
- case MIPS_BUILTIN_CMP_SINGLE:
- return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
- target, exp);
+ /* If the user hasn't specified a branch cost, use the processor's
+ default. */
+ if (mips_branch_cost == 0)
+ mips_branch_cost = mips_cost->branch_cost;
- case MIPS_BUILTIN_BPOSGE32:
- return mips_expand_builtin_bposge (type, target);
+ /* If neither -mbranch-likely nor -mno-branch-likely was given
+ on the command line, set MASK_BRANCHLIKELY based on the target
+ architecture and tuning flags. Annulled delay slots are a
+ size win, so we only consider the processor-specific tuning
+ for !optimize_size. */
+ if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
+ {
+ if (ISA_HAS_BRANCHLIKELY
+ && (optimize_size
+ || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
+ target_flags |= MASK_BRANCHLIKELY;
+ else
+ target_flags &= ~MASK_BRANCHLIKELY;
+ }
+ else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
+ warning (0, "the %qs architecture does not support branch-likely"
+ " instructions", mips_arch_info->name);
- default:
- return 0;
+ /* The effect of -mabicalls isn't defined for the EABI. */
+ if (mips_abi == ABI_EABI && TARGET_ABICALLS)
+ {
+ error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
+ target_flags &= ~MASK_ABICALLS;
}
-}
-/* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
+ /* MIPS16 cannot generate PIC yet. */
+ if (TARGET_MIPS16 && (flag_pic || TARGET_ABICALLS))
+ {
+ sorry ("MIPS16 PIC");
+ target_flags &= ~MASK_ABICALLS;
+ flag_pic = flag_pie = flag_shlib = 0;
+ }
-void
-mips_init_builtins (void)
-{
- const struct builtin_description *d;
- const struct bdesc_map *m;
- tree types[(int) MIPS_MAX_FTYPE_MAX];
- tree V2SF_type_node;
- tree V2HI_type_node;
- tree V4QI_type_node;
- unsigned int offset;
+ if (TARGET_ABICALLS)
+ /* We need to set flag_pic for executables as well as DSOs
+ because we may reference symbols that are not defined in
+ the final executable. (MIPS does not use things like
+ copy relocs, for example.)
- /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
- if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
- return;
+ Also, there is a body of code that uses __PIC__ to distinguish
+ between -mabicalls and -mno-abicalls code. */
+ flag_pic = 1;
- if (TARGET_PAIRED_SINGLE_FLOAT)
- {
- V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
+ /* -mvr4130-align is a "speed over size" optimization: it usually produces
+ faster code, but at the expense of more nops. Enable it at -O3 and
+ above. */
+ if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
+ target_flags |= MASK_VR4130_ALIGN;
- types[MIPS_V2SF_FTYPE_V2SF]
- = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
+ /* Prefer a call to memcpy over inline code when optimizing for size,
+ though see MOVE_RATIO in mips.h. */
+ if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
+ target_flags |= MASK_MEMCPY;
- types[MIPS_V2SF_FTYPE_V2SF_V2SF]
- = build_function_type_list (V2SF_type_node,
- V2SF_type_node, V2SF_type_node, NULL_TREE);
+ /* If we have a nonzero small-data limit, check that the -mgpopt
+ setting is consistent with the other target flags. */
+ if (mips_small_data_threshold > 0)
+ {
+ if (!TARGET_GPOPT)
+ {
+ if (!TARGET_MIPS16 && !TARGET_EXPLICIT_RELOCS)
+ error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
- types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
- = build_function_type_list (V2SF_type_node,
- V2SF_type_node, V2SF_type_node,
- integer_type_node, NULL_TREE);
+ TARGET_LOCAL_SDATA = false;
+ TARGET_EXTERN_SDATA = false;
+ }
+ else
+ {
+ if (TARGET_VXWORKS_RTP)
+ warning (0, "cannot use small-data accesses for %qs", "-mrtp");
- types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
- = build_function_type_list (V2SF_type_node,
- V2SF_type_node, V2SF_type_node,
- V2SF_type_node, V2SF_type_node, NULL_TREE);
+ if (TARGET_ABICALLS)
+ warning (0, "cannot use small-data accesses for %qs",
+ "-mabicalls");
+ }
+ }
- types[MIPS_V2SF_FTYPE_SF_SF]
- = build_function_type_list (V2SF_type_node,
- float_type_node, float_type_node, NULL_TREE);
+#ifdef MIPS_TFMODE_FORMAT
+ REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
+#endif
- types[MIPS_INT_FTYPE_V2SF_V2SF]
- = build_function_type_list (integer_type_node,
- V2SF_type_node, V2SF_type_node, NULL_TREE);
+ /* Make sure that the user didn't turn off paired single support when
+ MIPS-3D support is requested. */
+ if (TARGET_MIPS3D
+ && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
+ && !TARGET_PAIRED_SINGLE_FLOAT)
+ error ("%<-mips3d%> requires %<-mpaired-single%>");
- types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
- = build_function_type_list (integer_type_node,
- V2SF_type_node, V2SF_type_node,
- V2SF_type_node, V2SF_type_node, NULL_TREE);
+ /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
+ if (TARGET_MIPS3D)
+ target_flags |= MASK_PAIRED_SINGLE_FLOAT;
- types[MIPS_INT_FTYPE_SF_SF]
- = build_function_type_list (integer_type_node,
- float_type_node, float_type_node, NULL_TREE);
+ /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
+ and TARGET_HARD_FLOAT_ABI are both true. */
+ if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
+ error ("%qs must be used with %qs",
+ TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
+ TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
- types[MIPS_INT_FTYPE_DF_DF]
- = build_function_type_list (integer_type_node,
- double_type_node, double_type_node, NULL_TREE);
+ /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
+ enabled. */
+ if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
+ warning (0, "the %qs architecture does not support paired-single"
+ " instructions", mips_arch_info->name);
- types[MIPS_SF_FTYPE_V2SF]
- = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
-
- types[MIPS_SF_FTYPE_SF]
- = build_function_type_list (float_type_node,
- float_type_node, NULL_TREE);
-
- types[MIPS_SF_FTYPE_SF_SF]
- = build_function_type_list (float_type_node,
- float_type_node, float_type_node, NULL_TREE);
-
- types[MIPS_DF_FTYPE_DF]
- = build_function_type_list (double_type_node,
- double_type_node, NULL_TREE);
-
- types[MIPS_DF_FTYPE_DF_DF]
- = build_function_type_list (double_type_node,
- double_type_node, double_type_node, NULL_TREE);
- }
-
- if (TARGET_DSP)
- {
- V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
- V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode);
-
- types[MIPS_V2HI_FTYPE_V2HI_V2HI]
- = build_function_type_list (V2HI_type_node,
- V2HI_type_node, V2HI_type_node,
- NULL_TREE);
-
- types[MIPS_SI_FTYPE_SI_SI]
- = build_function_type_list (intSI_type_node,
- intSI_type_node, intSI_type_node,
- NULL_TREE);
-
- types[MIPS_V4QI_FTYPE_V4QI_V4QI]
- = build_function_type_list (V4QI_type_node,
- V4QI_type_node, V4QI_type_node,
- NULL_TREE);
-
- types[MIPS_SI_FTYPE_V4QI]
- = build_function_type_list (intSI_type_node,
- V4QI_type_node,
- NULL_TREE);
-
- types[MIPS_V2HI_FTYPE_V2HI]
- = build_function_type_list (V2HI_type_node,
- V2HI_type_node,
- NULL_TREE);
-
- types[MIPS_SI_FTYPE_SI]
- = build_function_type_list (intSI_type_node,
- intSI_type_node,
- NULL_TREE);
-
- types[MIPS_V4QI_FTYPE_V2HI_V2HI]
- = build_function_type_list (V4QI_type_node,
- V2HI_type_node, V2HI_type_node,
- NULL_TREE);
-
- types[MIPS_V2HI_FTYPE_SI_SI]
- = build_function_type_list (V2HI_type_node,
- intSI_type_node, intSI_type_node,
- NULL_TREE);
-
- types[MIPS_SI_FTYPE_V2HI]
- = build_function_type_list (intSI_type_node,
- V2HI_type_node,
- NULL_TREE);
-
- types[MIPS_V2HI_FTYPE_V4QI]
- = build_function_type_list (V2HI_type_node,
- V4QI_type_node,
- NULL_TREE);
-
- types[MIPS_V4QI_FTYPE_V4QI_SI]
- = build_function_type_list (V4QI_type_node,
- V4QI_type_node, intSI_type_node,
- NULL_TREE);
-
- types[MIPS_V2HI_FTYPE_V2HI_SI]
- = build_function_type_list (V2HI_type_node,
- V2HI_type_node, intSI_type_node,
- NULL_TREE);
-
- types[MIPS_V2HI_FTYPE_V4QI_V2HI]
- = build_function_type_list (V2HI_type_node,
- V4QI_type_node, V2HI_type_node,
- NULL_TREE);
-
- types[MIPS_SI_FTYPE_V2HI_V2HI]
- = build_function_type_list (intSI_type_node,
- V2HI_type_node, V2HI_type_node,
- NULL_TREE);
-
- types[MIPS_DI_FTYPE_DI_V4QI_V4QI]
- = build_function_type_list (intDI_type_node,
- intDI_type_node, V4QI_type_node, V4QI_type_node,
- NULL_TREE);
-
- types[MIPS_DI_FTYPE_DI_V2HI_V2HI]
- = build_function_type_list (intDI_type_node,
- intDI_type_node, V2HI_type_node, V2HI_type_node,
- NULL_TREE);
-
- types[MIPS_DI_FTYPE_DI_SI_SI]
- = build_function_type_list (intDI_type_node,
- intDI_type_node, intSI_type_node, intSI_type_node,
- NULL_TREE);
-
- types[MIPS_V4QI_FTYPE_SI]
- = build_function_type_list (V4QI_type_node,
- intSI_type_node,
- NULL_TREE);
-
- types[MIPS_V2HI_FTYPE_SI]
- = build_function_type_list (V2HI_type_node,
- intSI_type_node,
- NULL_TREE);
-
- types[MIPS_VOID_FTYPE_V4QI_V4QI]
- = build_function_type_list (void_type_node,
- V4QI_type_node, V4QI_type_node,
- NULL_TREE);
-
- types[MIPS_SI_FTYPE_V4QI_V4QI]
- = build_function_type_list (intSI_type_node,
- V4QI_type_node, V4QI_type_node,
- NULL_TREE);
-
- types[MIPS_VOID_FTYPE_V2HI_V2HI]
- = build_function_type_list (void_type_node,
- V2HI_type_node, V2HI_type_node,
- NULL_TREE);
-
- types[MIPS_SI_FTYPE_DI_SI]
- = build_function_type_list (intSI_type_node,
- intDI_type_node, intSI_type_node,
- NULL_TREE);
-
- types[MIPS_DI_FTYPE_DI_SI]
- = build_function_type_list (intDI_type_node,
- intDI_type_node, intSI_type_node,
- NULL_TREE);
-
- types[MIPS_VOID_FTYPE_SI_SI]
- = build_function_type_list (void_type_node,
- intSI_type_node, intSI_type_node,
- NULL_TREE);
-
- types[MIPS_SI_FTYPE_PTR_SI]
- = build_function_type_list (intSI_type_node,
- ptr_type_node, intSI_type_node,
- NULL_TREE);
-
- types[MIPS_SI_FTYPE_VOID]
- = build_function_type (intSI_type_node, void_list_node);
-
- if (TARGET_DSPR2)
- {
- types[MIPS_V4QI_FTYPE_V4QI]
- = build_function_type_list (V4QI_type_node,
- V4QI_type_node,
- NULL_TREE);
-
- types[MIPS_SI_FTYPE_SI_SI_SI]
- = build_function_type_list (intSI_type_node,
- intSI_type_node, intSI_type_node,
- intSI_type_node, NULL_TREE);
-
- types[MIPS_DI_FTYPE_DI_USI_USI]
- = build_function_type_list (intDI_type_node,
- intDI_type_node,
- unsigned_intSI_type_node,
- unsigned_intSI_type_node, NULL_TREE);
-
- types[MIPS_DI_FTYPE_SI_SI]
- = build_function_type_list (intDI_type_node,
- intSI_type_node, intSI_type_node,
- NULL_TREE);
-
- types[MIPS_DI_FTYPE_USI_USI]
- = build_function_type_list (intDI_type_node,
- unsigned_intSI_type_node,
- unsigned_intSI_type_node, NULL_TREE);
-
- types[MIPS_V2HI_FTYPE_SI_SI_SI]
- = build_function_type_list (V2HI_type_node,
- intSI_type_node, intSI_type_node,
- intSI_type_node, NULL_TREE);
+ /* If TARGET_DSPR2, enable MASK_DSP. */
+ if (TARGET_DSPR2)
+ target_flags |= MASK_DSP;
- }
- }
+ mips_init_print_operand_punct ();
- /* Iterate through all of the bdesc arrays, initializing all of the
- builtin functions. */
+ /* Set up array to map GCC register number to debug register number.
+ Ignore the special purpose register numbers. */
- offset = 0;
- for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
+ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
- if ((m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
- && (m->unsupported_target_flags & target_flags) == 0)
- for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
- if ((d->target_flags & target_flags) == d->target_flags)
- add_builtin_function (d->name, types[d->function_type],
- d - m->bdesc + offset,
- BUILT_IN_MD, NULL, NULL);
- offset += m->size;
+ mips_dbx_regno[i] = INVALID_REGNUM;
+ if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
+ mips_dwarf_regno[i] = i;
+ else
+ mips_dwarf_regno[i] = INVALID_REGNUM;
}
-}
-/* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
- .md pattern and CALL is the function expr with arguments. TARGET,
- if nonnull, suggests a good place to put the result.
- HAS_TARGET indicates the function must return something. */
+ start = GP_DBX_FIRST - GP_REG_FIRST;
+ for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
+ mips_dbx_regno[i] = i + start;
-static rtx
-mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
- bool has_target)
-{
- rtx ops[MAX_RECOG_OPERANDS];
- int i = 0;
- int j = 0;
+ start = FP_DBX_FIRST - FP_REG_FIRST;
+ for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
+ mips_dbx_regno[i] = i + start;
- if (has_target)
+ /* Accumulator debug registers use big-endian ordering. */
+ mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
+ mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
+ mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
+ mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
+ for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
{
- /* We save target to ops[0]. */
- ops[0] = mips_prepare_builtin_target (icode, 0, target);
- i = 1;
+ mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
+ mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
}
- /* We need to test if the arglist is not zero. Some instructions have extra
- clobber registers. */
- for (; i < insn_data[icode].n_operands && i <= call_expr_nargs (exp); i++, j++)
- ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
+ /* Set up mips_hard_regno_mode_ok. */
+ for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
+ for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
+ mips_hard_regno_mode_ok[(int)mode][regno]
+ = mips_hard_regno_mode_ok_p (regno, mode);
- switch (i)
- {
- case 2:
- emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
- break;
+ /* Function to allocate machine-dependent function status. */
+ init_machine_status = &mips_init_machine_status;
- case 3:
- emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
- break;
+ /* Default to working around R4000 errata only if the processor
+ was selected explicitly. */
+ if ((target_flags_explicit & MASK_FIX_R4000) == 0
+ && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
+ target_flags |= MASK_FIX_R4000;
- case 4:
- emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
- break;
+ /* Default to working around R4400 errata only if the processor
+ was selected explicitly. */
+ if ((target_flags_explicit & MASK_FIX_R4400) == 0
+ && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
+ target_flags |= MASK_FIX_R4400;
- default:
- gcc_unreachable ();
- }
- return target;
+ /* Save base state of options. */
+ mips_base_mips16 = TARGET_MIPS16;
+ mips_base_target_flags = target_flags;
+ mips_base_delayed_branch = flag_delayed_branch;
+ mips_base_schedule_insns = flag_schedule_insns;
+ mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
+ mips_base_move_loop_invariants = flag_move_loop_invariants;
+ mips_base_align_loops = align_loops;
+ mips_base_align_jumps = align_jumps;
+ mips_base_align_functions = align_functions;
+
+ /* Now select the ISA mode. */
+ mips_set_mips16_mode (mips_base_mips16);
+
+ /* We call dbr_schedule from within mips_reorg. */
+ flag_delayed_branch = 0;
}
-/* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
- function (TYPE says which). EXP is the tree for the function
- function, ICODE is the instruction that should be used to compare
- the first two arguments, and COND is the condition it should test.
- TARGET, if nonnull, suggests a good place to put the result. */
+/* Swap the register information for registers I and I + 1, which
+ currently have the wrong endianness. Note that the registers'
+ fixedness and call-clobberedness might have been set on the
+ command line. */
-static rtx
-mips_expand_builtin_movtf (enum mips_builtin_type type,
- enum insn_code icode, enum mips_fp_condition cond,
- rtx target, tree exp)
+static void
+mips_swap_registers (unsigned int i)
{
- rtx cmp_result, op0, op1;
+ int tmpi;
+ const char *tmps;
- cmp_result = mips_prepare_builtin_target (icode, 0, 0);
- op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
- op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
- emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
+#define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
+#define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
- icode = CODE_FOR_mips_cond_move_tf_ps;
- target = mips_prepare_builtin_target (icode, 0, target);
- if (type == MIPS_BUILTIN_MOVT)
- {
- op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
- op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
- }
- else
- {
- op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
- op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
- }
- emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
- return target;
+ SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
+ SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
+ SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
+ SWAP_STRING (reg_names[i], reg_names[i + 1]);
+
+#undef SWAP_STRING
+#undef SWAP_INT
}
-/* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
- into TARGET otherwise. Return TARGET. */
+/* Implement CONDITIONAL_REGISTER_USAGE. */
-static rtx
-mips_builtin_branch_and_move (rtx condition, rtx target,
- rtx value_if_true, rtx value_if_false)
+void
+mips_conditional_register_usage (void)
{
- rtx true_label, done_label;
-
- true_label = gen_label_rtx ();
- done_label = gen_label_rtx ();
+ if (!ISA_HAS_DSP)
+ {
+ int regno;
- /* First assume that CONDITION is false. */
- mips_emit_move (target, value_if_false);
+ for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
+ fixed_regs[regno] = call_used_regs[regno] = 1;
+ }
+ if (!TARGET_HARD_FLOAT)
+ {
+ int regno;
- /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
- emit_jump_insn (gen_condjump (condition, true_label));
- emit_jump_insn (gen_jump (done_label));
- emit_barrier ();
+ for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
+ fixed_regs[regno] = call_used_regs[regno] = 1;
+ for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
+ fixed_regs[regno] = call_used_regs[regno] = 1;
+ }
+ else if (! ISA_HAS_8CC)
+ {
+ int regno;
- /* Fix TARGET if CONDITION is true. */
- emit_label (true_label);
- mips_emit_move (target, value_if_true);
+ /* We only have a single condition-code register. We implement
+ this by fixing all the condition-code registers and generating
+ RTL that refers directly to ST_REG_FIRST. */
+ for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
+ fixed_regs[regno] = call_used_regs[regno] = 1;
+ }
+ /* In MIPS16 mode, we permit the $t temporary registers to be used
+ for reload. We prohibit the unused $s registers, since they
+ are call-saved, and saving them via a MIPS16 register would
+ probably waste more time than just reloading the value. */
+ if (TARGET_MIPS16)
+ {
+ fixed_regs[18] = call_used_regs[18] = 1;
+ fixed_regs[19] = call_used_regs[19] = 1;
+ fixed_regs[20] = call_used_regs[20] = 1;
+ fixed_regs[21] = call_used_regs[21] = 1;
+ fixed_regs[22] = call_used_regs[22] = 1;
+ fixed_regs[23] = call_used_regs[23] = 1;
+ fixed_regs[26] = call_used_regs[26] = 1;
+ fixed_regs[27] = call_used_regs[27] = 1;
+ fixed_regs[30] = call_used_regs[30] = 1;
+ }
+ /* $f20-$f23 are call-clobbered for n64. */
+ if (mips_abi == ABI_64)
+ {
+ int regno;
+ for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
+ call_really_used_regs[regno] = call_used_regs[regno] = 1;
+ }
+ /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
+ for n32. */
+ if (mips_abi == ABI_N32)
+ {
+ int regno;
+ for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
+ call_really_used_regs[regno] = call_used_regs[regno] = 1;
+ }
+ /* Make sure that double-register accumulator values are correctly
+ ordered for the current endianness. */
+ if (TARGET_LITTLE_ENDIAN)
+ {
+ unsigned int regno;
- emit_label (done_label);
- return target;
+ mips_swap_registers (MD_REG_FIRST);
+ for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
+ mips_swap_registers (regno);
+ }
}
-/* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
- of the comparison instruction and COND is the condition it should test.
- EXP is the function call and arguments and TARGET, if nonnull,
- suggests a good place to put the boolean result. */
+/* When generating MIPS16 code, we want to allocate $24 (T_REG) before
+ other registers for instructions for which it is possible. This
+ encourages the compiler to use CMP in cases where an XOR would
+ require some register shuffling. */
-static rtx
-mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
- enum insn_code icode, enum mips_fp_condition cond,
- rtx target, tree exp)
+void
+mips_order_regs_for_local_alloc (void)
{
- rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
int i;
- int j = 0;
-
- if (target == 0 || GET_MODE (target) != SImode)
- target = gen_reg_rtx (SImode);
- /* Prepare the operands to the comparison. */
- cmp_result = mips_prepare_builtin_target (icode, 0, 0);
- for (i = 1; i < insn_data[icode].n_operands - 1; i++, j++)
- ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
+ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+ reg_alloc_order[i] = i;
- switch (insn_data[icode].n_operands)
+ if (TARGET_MIPS16)
{
- case 4:
- emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
- break;
-
- case 6:
- emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
- ops[3], ops[4], GEN_INT (cond)));
- break;
-
- default:
- gcc_unreachable ();
+ /* It really doesn't matter where we put register 0, since it is
+ a fixed register anyhow. */
+ reg_alloc_order[0] = 24;
+ reg_alloc_order[24] = 0;
}
+}
+\f
+/* Initialize the GCC target structure. */
+#undef TARGET_ASM_ALIGNED_HI_OP
+#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
+#undef TARGET_ASM_ALIGNED_SI_OP
+#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
+#undef TARGET_ASM_ALIGNED_DI_OP
+#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
- /* If the comparison sets more than one register, we define the result
- to be 0 if all registers are false and -1 if all registers are true.
- The value of the complete result is indeterminate otherwise. */
- switch (builtin_type)
- {
- case MIPS_BUILTIN_CMP_ALL:
- condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
- return mips_builtin_branch_and_move (condition, target,
- const0_rtx, const1_rtx);
+#undef TARGET_ASM_FUNCTION_PROLOGUE
+#define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
+#undef TARGET_ASM_FUNCTION_EPILOGUE
+#define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
+#undef TARGET_ASM_SELECT_RTX_SECTION
+#define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
+#undef TARGET_ASM_FUNCTION_RODATA_SECTION
+#define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
- case MIPS_BUILTIN_CMP_UPPER:
- case MIPS_BUILTIN_CMP_LOWER:
- offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
- condition = gen_single_cc (cmp_result, offset);
- return mips_builtin_branch_and_move (condition, target,
- const1_rtx, const0_rtx);
+#undef TARGET_SCHED_INIT
+#define TARGET_SCHED_INIT mips_sched_init
+#undef TARGET_SCHED_REORDER
+#define TARGET_SCHED_REORDER mips_sched_reorder
+#undef TARGET_SCHED_REORDER2
+#define TARGET_SCHED_REORDER2 mips_sched_reorder
+#undef TARGET_SCHED_VARIABLE_ISSUE
+#define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
+#undef TARGET_SCHED_ADJUST_COST
+#define TARGET_SCHED_ADJUST_COST mips_adjust_cost
+#undef TARGET_SCHED_ISSUE_RATE
+#define TARGET_SCHED_ISSUE_RATE mips_issue_rate
+#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
+#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
+ mips_multipass_dfa_lookahead
- default:
- condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
- return mips_builtin_branch_and_move (condition, target,
- const1_rtx, const0_rtx);
- }
-}
+#undef TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS \
+ (TARGET_DEFAULT \
+ | TARGET_CPU_DEFAULT \
+ | TARGET_ENDIAN_DEFAULT \
+ | TARGET_FP_EXCEPTIONS_DEFAULT \
+ | MASK_CHECK_ZERO_DIV \
+ | MASK_FUSED_MADD)
+#undef TARGET_HANDLE_OPTION
+#define TARGET_HANDLE_OPTION mips_handle_option
-/* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
- suggests a good place to put the boolean result. */
+#undef TARGET_FUNCTION_OK_FOR_SIBCALL
+#define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
-static rtx
-mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
-{
- rtx condition, cmp_result;
- int cmp_value;
+#undef TARGET_INSERT_ATTRIBUTES
+#define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
+#undef TARGET_MERGE_DECL_ATTRIBUTES
+#define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
+#undef TARGET_SET_CURRENT_FUNCTION
+#define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
- if (target == 0 || GET_MODE (target) != SImode)
- target = gen_reg_rtx (SImode);
+#undef TARGET_VALID_POINTER_MODE
+#define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
+#undef TARGET_RTX_COSTS
+#define TARGET_RTX_COSTS mips_rtx_costs
+#undef TARGET_ADDRESS_COST
+#define TARGET_ADDRESS_COST mips_address_cost
- cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
+#undef TARGET_IN_SMALL_DATA_P
+#define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
- if (builtin_type == MIPS_BUILTIN_BPOSGE32)
- cmp_value = 32;
- else
- gcc_assert (0);
+#undef TARGET_MACHINE_DEPENDENT_REORG
+#define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
- condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
- return mips_builtin_branch_and_move (condition, target,
- const1_rtx, const0_rtx);
-}
-\f
-/* Return true if we should force MIPS16 mode for the function named by
- the SYMBOL_REF SYMBOL, which belongs to DECL and has type TYPE.
- FIRST is true if this is the first time handling this decl. */
+#undef TARGET_ASM_FILE_START
+#define TARGET_ASM_FILE_START mips_file_start
+#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
+#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
-static bool
-mips_use_mips16_mode_p (rtx symbol, tree decl, int first, tree type)
-{
- tree parent;
+#undef TARGET_INIT_LIBFUNCS
+#define TARGET_INIT_LIBFUNCS mips_init_libfuncs
- /* Explicit function attributes take precedence. */
- if (mips_mips16_type_p (type))
- return true;
- if (mips_nomips16_type_p (type))
- return false;
+#undef TARGET_BUILD_BUILTIN_VA_LIST
+#define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
+#undef TARGET_EXPAND_BUILTIN_VA_START
+#define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
+#undef TARGET_GIMPLIFY_VA_ARG_EXPR
+#define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
- /* A nested function should inherit the MIPS16 setting from its parent. */
- parent = decl_function_context (decl);
- if (parent)
- return SYMBOL_REF_MIPS16_FUNC_P (XEXP (DECL_RTL (parent), 0));
+#undef TARGET_PROMOTE_FUNCTION_ARGS
+#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
+#undef TARGET_PROMOTE_FUNCTION_RETURN
+#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
+#undef TARGET_PROMOTE_PROTOTYPES
+#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
- /* Handle -mflip-mips16. */
- if (TARGET_FLIP_MIPS16
- && !DECL_BUILT_IN (decl)
- && !DECL_ARTIFICIAL (decl))
- {
- if (!first)
- /* Use the setting we picked first time around. */
- return SYMBOL_REF_MIPS16_FUNC_P (symbol);
+#undef TARGET_RETURN_IN_MEMORY
+#define TARGET_RETURN_IN_MEMORY mips_return_in_memory
+#undef TARGET_RETURN_IN_MSB
+#define TARGET_RETURN_IN_MSB mips_return_in_msb
- mips16_flipper = !mips16_flipper;
- if (mips16_flipper)
- return !mips_base_mips16;
- }
+#undef TARGET_ASM_OUTPUT_MI_THUNK
+#define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
+#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
+#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
- return mips_base_mips16;
-}
+#undef TARGET_SETUP_INCOMING_VARARGS
+#define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
+#undef TARGET_STRICT_ARGUMENT_NAMING
+#define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
+#undef TARGET_MUST_PASS_IN_STACK
+#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
+#undef TARGET_PASS_BY_REFERENCE
+#define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
+#undef TARGET_CALLEE_COPIES
+#define TARGET_CALLEE_COPIES mips_callee_copies
+#undef TARGET_ARG_PARTIAL_BYTES
+#define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
-/* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
- FIRST is true if this is the first time handling this decl. */
+#undef TARGET_MODE_REP_EXTENDED
+#define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
-static void
-mips_encode_section_info (tree decl, rtx rtl, int first)
-{
- default_encode_section_info (decl, rtl, first);
+#undef TARGET_VECTOR_MODE_SUPPORTED_P
+#define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
- if (TREE_CODE (decl) == FUNCTION_DECL)
- {
- rtx symbol = XEXP (rtl, 0);
- tree type = TREE_TYPE (decl);
+#undef TARGET_SCALAR_MODE_SUPPORTED_P
+#define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
- if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
- || mips_far_type_p (type))
- SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
+#undef TARGET_INIT_BUILTINS
+#define TARGET_INIT_BUILTINS mips_init_builtins
+#undef TARGET_EXPAND_BUILTIN
+#define TARGET_EXPAND_BUILTIN mips_expand_builtin
- if (mips_use_mips16_mode_p (symbol, decl, first, type))
- {
- if (flag_pic || TARGET_ABICALLS)
- sorry ("MIPS16 PIC");
- else
- SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_MIPS16_FUNC;
- }
- }
-}
+#undef TARGET_HAVE_TLS
+#define TARGET_HAVE_TLS HAVE_AS_TLS
-/* Implement TARGET_EXTRA_LIVE_ON_ENTRY. Some code models use the incoming
- value of PIC_FUNCTION_ADDR_REGNUM to set up the global pointer. */
+#undef TARGET_CANNOT_FORCE_CONST_MEM
+#define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
-static void
-mips_extra_live_on_entry (bitmap regs)
-{
- if (TARGET_USE_GOT && !TARGET_ABSOLUTE_ABICALLS)
- bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
-}
+#undef TARGET_ENCODE_SECTION_INFO
+#define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
-/* SImode values are represented as sign-extended to DImode. */
+#undef TARGET_ATTRIBUTE_TABLE
+#define TARGET_ATTRIBUTE_TABLE mips_attribute_table
+/* All our function attributes are related to how out-of-line copies should
+ be compiled or called. They don't in themselves prevent inlining. */
+#undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
+#define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
-int
-mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
-{
- if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
- return SIGN_EXTEND;
+#undef TARGET_EXTRA_LIVE_ON_ENTRY
+#define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
- return UNKNOWN;
-}
-\f
-/* MIPS implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
+#undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
+#define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
+#undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
+#define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
-static void
-mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
-{
- switch (size)
- {
- case 4:
- fputs ("\t.dtprelword\t", file);
- break;
+#undef TARGET_COMP_TYPE_ATTRIBUTES
+#define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
- case 8:
- fputs ("\t.dtpreldword\t", file);
- break;
+#ifdef HAVE_AS_DTPRELWORD
+#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
+#define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
+#endif
+#undef TARGET_DWARF_REGISTER_SPAN
+#define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
- default:
- gcc_unreachable ();
- }
- output_addr_const (file, x);
- fputs ("+0x8000", file);
-}
+struct gcc_target targetm = TARGET_INITIALIZER;
\f
#include "gt-mips.h"
OSDN Git Service
