;;- Machine description for GNU compiler, Motorola 68000 Version
-;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001
+;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003
;; Free Software Foundation, Inc.
;; This file is part of GNU CC.
;;- 'd' one of the data registers can be used.
;;- 'f' one of the m68881 registers can be used
;;- 'r' either a data or an address register can be used.
-;;- 'x' if one of the Sun FPA registers
-;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
;;- Immediate Floating point operator constraints
;;- 'G' a floating point constant that is *NOT* one of the standard
;; 68881 constant values (to force calling output_move_const_double
;; to get it from rom if it is a 68881 constant).
-;;- 'H' one of the standard FPA constant values
;;
;; See the functions standard_XXX_constant_p in output-m68k.c for more
;; info.
;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
-;; UNSPEC usage:
-;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
-;; operand 1 is the argument for `sin'.
-;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
-;; operand 1 is the argument for `cos'.
-
;;- Information about 68040 port.
;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
-;;- FPA port explanation:
-
-;;- Usage of the Sun FPA and the 68881 together
-
-;;- The current port of gcc to the sun fpa disallows use of the m68881
-;;- instructions completely if code is targeted for the fpa. This is
-;;- for the following reasons:
-
-;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
-;;- can, the 68881 otherwise, and data registers only if you are
-;;- forced to it) is a bitch with the current constraint scheme,
-;;- especially since it would have to work for any combination of
-;;- -mfpa, -m68881.
-
-;;- 2) There are no instructions to move between the two types of
-;;- registers; the stack must be used as an intermediary.
-
-;;- It could indeed be done; I think the best way would be to have
-;;- separate patterns for TARGET_FPA (which implies a 68881),
-;;- TARGET_68881, and no floating point co-processor. Use
-;;- define_expands for all of the named instruction patterns, and
-;;- include code in the FPA instruction to deal with the 68881 with
-;;- preferences specifically set to favor the fpa. Some of this has
-;;- already been done:
-;;-
-;;- 1) Separation of most of the patterns out into a TARGET_FPA
-;;- case and a TARGET_68881 case (the exceptions are the patterns
-;;- which would need one define_expand and three define_insn's under
-;;- it (with a lot of duplicate code between them) to replace the
-;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
-;;- first two patterns in the md.
-;;-
-;;- Some would still have to be done:
-;;-
-;;- 1) Add code to the fpa patterns which correspond to 68881
-;;- patterns to deal with the 68881 case (including preferences!).
-;;- What you might actually do here is combine the fpa and 68881 code
-;;- back together into one pattern for those instructions where it's
-;;- absolutely necessary and save yourself some duplicate code. I'm
-;;- not completely sure as to whether you could get away with doing
-;;- this only for the mov* insns, or if you'd have to do it for all
-;;- named insns.
-;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
-;;- moving between fpa regs and 68881 regs.
-
-;;- Since the fpa is more powerful than the 68881 and also has more
-;;- registers, and since I think the resultant md would be medium ugly
-;;- (lot's of duplicate code, ugly constraint strings), I elected not
-;;- to do this change.
-
-;;- Another reason why someone *might* want to do the change is to
-;;- control which register classes are accessed in a slightly cleaner
-;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
-;;- the internals manual.
-
-;;- Yet another reason why someone might want to do this change is to
-;;- allow use of some of the 68881 insns which have no equivalent on
-;;- the fpa. The sqrt instruction comes fairly quickly to mind.
-
-;;- If this is ever done, don't forget to change sun3.h so that
-;;- it *will* define __HAVE_68881__ when the FPA is in use.
-
-;;- Condition code hack
-
-;;- When a floating point compare is done in the fpa, the resulting
-;;- condition codes are left in the fpastatus register. The values in
-;;- this register must be moved into the 68000 cc register before any
-;;- jump is executed. Once this has been done, regular jump
-;;- instructions are fine (ie. floating point jumps are not necessary.
-;;- They are only done if the cc is in the 68881).
-
-;;- The instructions that move the fpastatus register to the 68000
-;;- register clobber a data register (the move cannot be done direct).
-;;- These instructions might be bundled either with the compare
-;;- instruction, or the branch instruction. If we were using both the
-;;- fpa and the 68881 together, we would wish to only mark the
-;;- register clobbered if we were doing the compare in the fpa, but I
-;;- think that that decision (whether to clobber the register or not)
-;;- must be done before register allocation (makes sense) and hence we
-;;- can't know if the floating point compare will be done in the fpa
-;;- or the fp. So whenever we are asked for code that uses the fpa,
-;;- we will mark a data register as clobbered. This is reasonable, as
-;;- almost all floating point compare operations done with fpa code
-;;- enabled will be done in the fpa. It's even more reasonable since
-;;- we decided to make the 68881 and the fpa mutually exclusive.
-
-;;- We place to code to move the fpastatus register inside of a
-;;- define_expand so that we can do it conditionally based on whether
-;;- we are targeting an fpa or not.
-
-;;- This still leaves us with the question of where we wish to put the
-;;- code to move the fpastatus reg. If we put it in the compare
-;;- instruction, we can restrict the clobbering of the register to
-;;- floating point compares, but we can't take advantage of floating
-;;- point subtracts & etc. that alter the fpastatus register. If we
-;;- put it in the branch instruction, all branches compiled with fpa
-;;- code enabled will clobber a data register, but we will be able to
-;;- take advantage of fpa subtracts. This balance favors putting the
-;;- code in with the compare instruction.
-
-;;- Note that if some enterprising hacker should decide to switch
-;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
-
-;;- Usage of the top 16 fpa registers
-
-;;- The only locations which we may transfer fpa registers 16-31 from
-;;- or to are the fpa registers 0-15. (68000 registers and memory
-;;- locations are impossible). This causes problems in gcc, which
-;;- assumes that mov?? instructions require no additional registers
-;;- (see section 11.7) and since floating point moves *must* be
-;;- supported into general registers (see section 12.3 under
-;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
-
-;;- My solution was to reserve fpa0 for moves into or out of these top
-;;- 16 registers and to disparage the choice to reload into or out of
-;;- these registers as much as I could. That alternative is always
-;;- last in the list, so it will not be used unless all else fails. I
-;;- will note that according to my current information, sun's compiler
-;;- doesn't use these top 16 registers at all.
-
-;;- There is another possible way to do it. I *believe* that if you
-;;- make absolutely sure that the code will not be executed in the
-;;- reload pass, you can support the mov?? names with define_expands
-;;- which require new registers. This may be possible by the
-;;- appropriate juggling of constraints. I may come back to this later.
-
-;;- Usage of constant RAM
-
-;;- This has been handled correctly (I believe) but the way I've done
-;;- it could use a little explanation. The constant RAM can only be
-;;- accessed when the instruction is in "command register" mode.
-;;- "command register" mode means that no accessing of memory or the
-;;- 68000 registers is being done. This can be expressed easily in
-;;- constraints, so generally the mode of the instruction is
-;;- determined by a branch off of which_alternative. In outputting
-;;- instructions, a 'w' means to output an access to the constant ram
-;;- (if the arg is CONST_DOUBLE and is one of the available
-;;- constants), and 'x' means to output a register pair (if the arg is
-;;- a 68000 register) and a 'y' is the combination of the above two
-;;- processes. You use a 'y' in two operand DF instructions where you
-;;- *know* the other operand is an fpa register, you use an 'x' in DF
-;;- instructions where the arg might be a 68000 register and the
-;;- instruction is *not* in "command register" mode, and you use a 'w'
-;;- in two situations: 1) The instruction *is* in command register
-;;- mode (and hence won't be accessing 68000 registers), or 2) The
-;;- instruction is a two operand SF instruction where you know the
-;;- other operand is an fpa register.
-
-;;- Optimization issues
-
-;;- I actually think that I've included all of the fpa instructions
-;;- that should be included. Note that if someone is interested in
-;;- doing serious floating point work on the sun fpa, I would advise
-;;- the use of the "asm" instruction in gcc to allow you to use the
-;;- sin, cos, and exponential functions on the fpa board.
-
-;;- END FPA Explanation Section.
-
-
;;- Some of these insn's are composites of several m68000 op codes.
;;- The assembler (or final @@??) insures that the appropriate one is
;;- selected.
+
+;; UNSPEC usage:
+
+(define_constants
+ [(UNSPEC_SIN 1)
+ (UNSPEC_COS 2)
+ ])
+
+;; UNSPEC_VOLATILE usage:
+
+(define_constants
+ [(UNSPECV_BLOCKAGE 0)
+ ])
\f
(define_insn ""
[(set (match_operand:DF 0 "push_operand" "=m")
{
if (FP_REG_P (operands[1]))
return \"fmove%.d %f1,%0\";
- if (FPA_REG_P (operands[1]))
- return \"fpmove%.d %1, %x0\";
return output_move_double (operands);
}")
""
"*
{
-#ifdef ISI_OV
- /* ISI's assembler fails to handle tstl a0. */
- if (! ADDRESS_REG_P (operands[0]))
-#else
if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
-#endif
return \"tst%.l %0\";
/* If you think that the 68020 does not support tstl a0,
reread page B-167 of the 68020 manual more carefully. */
(define_expand "tstsf"
[(set (cc0)
(match_operand:SF 0 "general_operand" ""))]
- "TARGET_68881 || TARGET_FPA"
+ "TARGET_68881"
"
{
m68k_last_compare_had_fp_operands = 1;
- if (TARGET_FPA)
- {
- emit_insn (gen_tstsf_fpa (operands[0]));
- DONE;
- }
}")
-(define_insn "tstsf_fpa"
- [(set (cc0)
- (match_operand:SF 0 "general_operand" "xmdF"))
- (clobber (match_scratch:SI 1 "=d"))]
- "TARGET_FPA"
- "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
-
(define_insn ""
[(set (cc0)
(match_operand:SF 0 "general_operand" "fdm"))]
(define_expand "tstdf"
[(set (cc0)
(match_operand:DF 0 "general_operand" ""))]
- "TARGET_68881 || TARGET_FPA"
+ "TARGET_68881"
"
{
m68k_last_compare_had_fp_operands = 1;
- if (TARGET_FPA)
- {
- emit_insn (gen_tstsf_fpa (operands[0]));
- DONE;
- }
}")
-(define_insn "tstdf_fpa"
- [(set (cc0)
- (match_operand:DF 0 "general_operand" "xrmF"))
- (clobber (match_scratch:SI 1 "=d"))]
- "TARGET_FPA"
- "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
-
(define_insn ""
[(set (cc0)
(match_operand:DF 0 "general_operand" "fm"))]
[(set (cc0)
(compare (match_operand:DF 0 "general_operand" "")
(match_operand:DF 1 "general_operand" "")))]
- "TARGET_68881 || TARGET_FPA"
+ "TARGET_68881"
"
{
m68k_last_compare_had_fp_operands = 1;
- if (TARGET_FPA)
- {
- emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
- DONE;
- }
}")
-(define_insn "cmpdf_fpa"
- [(set (cc0)
- (compare (match_operand:DF 0 "general_operand" "x,y")
- (match_operand:DF 1 "general_operand" "xH,rmF")))
- (clobber (match_scratch:SI 2 "=d,d"))]
- "TARGET_FPA"
- "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
-
(define_insn ""
[(set (cc0)
(compare (match_operand:DF 0 "general_operand" "f,mG")
[(set (cc0)
(compare (match_operand:SF 0 "general_operand" "")
(match_operand:SF 1 "general_operand" "")))]
- "TARGET_68881 || TARGET_FPA"
+ "TARGET_68881"
"
{
m68k_last_compare_had_fp_operands = 1;
- if (TARGET_FPA)
- {
- emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
- DONE;
- }
}")
-(define_insn "cmpsf_fpa"
- [(set (cc0)
- (compare (match_operand:SF 0 "general_operand" "x,y")
- (match_operand:SF 1 "general_operand" "xH,rmF")))
- (clobber (match_scratch:SI 2 "=d,d"))]
- "TARGET_FPA"
- "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
-
(define_insn ""
[(set (cc0)
(compare (match_operand:SF 0 "general_operand" "f,mdG")
}
/* moveq is faster on the 68000. */
if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
-#if defined(MOTOROLA) && !defined(CRDS)
- return \"moveq%.l %#0,%0\";
-#else
return \"moveq %#0,%0\";
-#endif
return \"clr%.l %0\";
}")
(define_insn ""
;; Notes: make sure no alternative allows g vs g.
;; We don't allow f-regs since fixed point cannot go in them.
- ;; We do allow y and x regs since fixed point is allowed in them.
- [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<,y,!*x*r*m")
- (match_operand:SI 1 "general_src_operand" "daymSKT,n,i,g,*x*r*m"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
+ (match_operand:SI 1 "general_src_operand" "daymSKT,n,i"))]
"!TARGET_5200"
"*
{
- if (which_alternative == 4)
- return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
- if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
- return \"fpmove%.l %x1,%x0\";
return output_move_simode (operands);
}")
"")
(define_insn ""
- [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf,x,y,rm,!x,!rm")
- (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
-; [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
-; (match_operand:SF 1 "general_operand" "rmfF"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
+ (match_operand:SF 1 "general_operand" "rmfF"))]
"!TARGET_5200"
"*
{
- if (which_alternative >= 4)
- return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
- if (FPA_REG_P (operands[0]))
- {
- if (FPA_REG_P (operands[1]))
- return \"fpmove%.s %x1,%x0\";
- else if (GET_CODE (operands[1]) == CONST_DOUBLE)
- return output_move_const_single (operands);
- else if (FP_REG_P (operands[1]))
- return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
- return \"fpmove%.s %x1,%x0\";
- }
- if (FPA_REG_P (operands[1]))
- {
- if (FP_REG_P (operands[0]))
- return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
- else
- return \"fpmove%.s %x1,%x0\";
- }
if (FP_REG_P (operands[0]))
{
if (FP_REG_P (operands[1]))
/* moveq is faster on the 68000. */
if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
{
-#if defined(MOTOROLA) && !defined(CRDS)
- return \"moveq%.l %#0,%0\";
-#else
return \"moveq %#0,%0\";
-#endif
}
return \"clr%.l %0\";
}
"")
(define_insn ""
- [(set (match_operand:DF 0 "nonimmediate_operand"
- "=*rm,*rf,*rf,&*rof<>,y,*rm,x,!x,!*rm")
- (match_operand:DF 1 "general_operand"
- "*rf,m,0,*rofE<>,*rmE,y,xH,*rm,x"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,rf,rf,&rof<>")
+ (match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))]
; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
"!TARGET_5200"
"*
{
- if (which_alternative == 7)
- return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
- if (FPA_REG_P (operands[0]))
- {
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
- return output_move_const_double (operands);
- if (FP_REG_P (operands[1]))
- return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
- return \"fpmove%.d %x1,%x0\";
- }
- else if (FPA_REG_P (operands[1]))
- {
- if (FP_REG_P(operands[0]))
- return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
- else
- return \"fpmove%.d %x1,%x0\";
- }
if (FP_REG_P (operands[0]))
{
if (FP_REG_P (operands[1]))
"TARGET_5200"
"* return output_move_double (operands);")
+;; ??? The XFmode patterns are schizophrenic about whether constants are
+;; allowed. Most but not all have predicates and constraint that disallow
+;; constants. Most but not all have output templates that handle constants.
+;; See also LEGITIMATE_CONSTANT_P.
+
(define_expand "movxf"
[(set (match_operand:XF 0 "nonimmediate_operand" "")
(match_operand:XF 1 "general_operand" ""))]
""
"
{
- if (CONSTANT_P (operands[1]))
- {
- operands[1] = force_const_mem (XFmode, operands[1]);
- if (! memory_address_p (XFmode, XEXP (operands[1], 0))
- && ! reload_in_progress)
- operands[1] = adjust_address (operands[1], XFmode, 0);
- }
- if (flag_pic && TARGET_PCREL && ! reload_in_progress)
+ /* We can't rewrite operands during reload. */
+ if (! reload_in_progress)
{
- /* Don't allow writes to memory except via a register;
- the m68k doesn't consider PC-relative addresses to be writable. */
- if (GET_CODE (operands[0]) == MEM
- && symbolic_operand (XEXP (operands[0], 0), SImode))
- operands[0] = gen_rtx (MEM, XFmode,
- force_reg (SImode, XEXP (operands[0], 0)));
+ if (CONSTANT_P (operands[1]))
+ {
+ operands[1] = force_const_mem (XFmode, operands[1]);
+ if (! memory_address_p (XFmode, XEXP (operands[1], 0)))
+ operands[1] = adjust_address (operands[1], XFmode, 0);
+ }
+ if (flag_pic && TARGET_PCREL)
+ {
+ /* Don't allow writes to memory except via a register; the
+ m68k doesn't consider PC-relative addresses to be writable. */
+ if (GET_CODE (operands[0]) == MEM
+ && symbolic_operand (XEXP (operands[0], 0), SImode))
+ operands[0] = gen_rtx (MEM, XFmode,
+ force_reg (SImode, XEXP (operands[0], 0)));
+ }
}
}")
;; movdi can apply to fp regs in some cases
(define_insn ""
;; Let's see if it really still needs to handle fp regs, and, if so, why.
- [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
- (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
-; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
-; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r,&ro<>")
+ (match_operand:DI 1 "general_operand" "rF,m,roi<>F"))]
+; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&r,&ro<>,!&rm,!&f")
+; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF"))]
; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f")
; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
"!TARGET_5200"
"*
{
- if (which_alternative == 8)
- return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
- if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
- return \"fpmove%.d %x1,%x0\";
if (FP_REG_P (operands[0]))
{
if (FP_REG_P (operands[1]))
"")
(define_insn "*zero_extendsidi2_cf"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
- (zero_extend:DI (match_operand:SI 1 "general_operand" "ro,r")))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,m")
+ (zero_extend:DI (match_operand:SI 1 "general_operand" "rm,r")))]
"TARGET_5200"
"*
{
}")
(define_insn "*zero_extendsidi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
- (zero_extend:DI (match_operand:SI 1 "general_operand" "ro")))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
+ (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
"!TARGET_5200"
"*
{
"
{
operands[1] = make_safe_from (operands[1], operands[0]);
- operands[2] = gen_lowpart (HImode, operands[0]);
+ operands[2] = gen_lowpart_SUBREG (HImode, operands[0]);
}")
(define_expand "zero_extendqihi2"
"
{
operands[1] = make_safe_from (operands[1], operands[0]);
- operands[2] = gen_lowpart (QImode, operands[0]);
+ operands[2] = gen_lowpart_SUBREG (QImode, operands[0]);
}")
(define_expand "zero_extendqisi2"
"
{
operands[1] = make_safe_from (operands[1], operands[0]);
- operands[2] = gen_lowpart (QImode, operands[0]);
+ operands[2] = gen_lowpart_SUBREG (QImode, operands[0]);
}")
\f
;; Patterns to recognize zero-extend insns produced by the combiner.
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(float_extend:DF
(match_operand:SF 1 "general_operand" "")))]
- "TARGET_68881 || TARGET_FPA"
+ "TARGET_68881"
"")
(define_insn ""
- [(set (match_operand:DF 0 "nonimmediate_operand" "=x,y")
- (float_extend:DF
- (match_operand:SF 1 "general_operand" "xH,rmF")))]
- "TARGET_FPA"
- "fpstod %w1,%0")
-
-(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=*fdm,f")
(float_extend:DF
(match_operand:SF 1 "general_operand" "f,dmF")))]
;; This cannot output into an f-reg because there is no way to be
;; sure of truncating in that case.
-;; But on the Sun FPA, we can be sure.
(define_expand "truncdfsf2"
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(float_truncate:SF
(match_operand:DF 1 "general_operand" "")))]
- "TARGET_68881 || TARGET_FPA"
+ "TARGET_68881"
"")
-(define_insn ""
- [(set (match_operand:SF 0 "nonimmediate_operand" "=x,y")
- (float_truncate:SF
- (match_operand:DF 1 "general_operand" "xH,rmF")))]
- "TARGET_FPA"
- "fpdtos %y1,%0")
-
;; On the '040 we can truncate in a register accurately and easily.
(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(float:SF (match_operand:SI 1 "general_operand" "")))]
- "TARGET_68881 || TARGET_FPA"
+ "TARGET_68881"
"")
(define_insn ""
- [(set (match_operand:SF 0 "nonimmediate_operand" "=y,x")
- (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
- "TARGET_FPA"
- "fpltos %1,%0")
-
-(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
(float:SF (match_operand:SI 1 "general_operand" "dmi")))]
"TARGET_68881"
(define_expand "floatsidf2"
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(float:DF (match_operand:SI 1 "general_operand" "")))]
- "TARGET_68881 || TARGET_FPA"
+ "TARGET_68881"
"")
(define_insn ""
- [(set (match_operand:DF 0 "nonimmediate_operand" "=y,x")
- (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
- "TARGET_FPA"
- "fpltod %1,%0")
-
-(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(float:DF (match_operand:SI 1 "general_operand" "dmi")))]
"TARGET_68881"
(fix:SI (match_operand:DF 1 "general_operand" "f")))]
"TARGET_68881"
"fmove%.l %1,%0")
-
-;; Convert a float to an integer.
-;; On the Sun FPA, this is done in one step.
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=x,y")
- (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
- "TARGET_FPA"
- "fpstol %w1,%0")
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=x,y")
- (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
- "TARGET_FPA"
- "fpdtol %y1,%0")
\f
;; add instructions
if (GET_CODE (operands[1]) == CONST_INT)
{
if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
- {
-#ifdef NO_ADDSUB_Q
- return \"add%.l %1,%R0\;addx%.l %3,%0\";
-#else
- return \"addq%.l %1,%R0\;addx%.l %3,%0\";
-#endif
- }
+ return \"addq%.l %1,%R0\;addx%.l %3,%0\";
else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
{
operands[1] = GEN_INT (-INTVAL (operands[1]));
-#ifdef NO_ADDSUB_Q
- return \"sub%.l %1,%R0\;subx%.l %3,%0\";
-#else
return \"subq%.l %1,%R0\;subx%.l %3,%0\";
-#endif
}
}
return \"add%.l %1,%R0\;addx%.l %3,%0\";
#else
output_asm_insn (\"jpl %l3\", operands);
#endif
-#ifndef NO_ADDSUB_Q
output_asm_insn (\"addq%.l %#1,%2\", operands);
-#else
- output_asm_insn (\"add%.l %#1,%2\", operands);
-#endif
- ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
+ (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
CODE_LABEL_NUMBER (operands[3]));
return \"\";
}")
{
if (GET_CODE (operands[2]) == CONST_INT)
{
-#ifndef NO_ADDSUB_Q
/* If the constant would be a negative number when interpreted as
HImode, make it negative. This is usually, but not always, done
elsewhere in the compiler. First check for constants out of range,
return \"subq%.w %#8,%0\;subq%.w %2,%0\";
}
}
-#endif
if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
#ifdef MOTOROLA
return \"lea (%c2,%0),%0\";
{
if (GET_CODE (operands[1]) == CONST_INT)
{
-#ifndef NO_ADDSUB_Q
/* If the constant would be a negative number when interpreted as
HImode, make it negative. This is usually, but not always, done
elsewhere in the compiler. First check for constants out of range,
return \"subq%.w %#8,%0\;subq%.w %1,%0\";
}
}
-#endif
if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
#ifdef MOTOROLA
return \"lea (%c1,%0),%0\";
{
if (GET_CODE (operands[1]) == CONST_INT)
{
-#ifndef NO_ADDSUB_Q
/* If the constant would be a negative number when interpreted as
HImode, make it negative. This is usually, but not always, done
elsewhere in the compiler. First check for constants out of range,
return \"subq%.w %#8,%0\;subq%.w %1,%0\";
}
}
-#endif
if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
#ifdef MOTOROLA
return \"lea (%c1,%0),%0\";
"!TARGET_5200"
"*
{
-#ifndef NO_ADDSUB_Q
if (GET_CODE (operands[2]) == CONST_INT)
{
if (INTVAL (operands[2]) >= 128)
return \"subq%.b %2,%0\";
}
}
-#endif
return \"add%.b %2,%0\";
}")
"!TARGET_5200"
"*
{
-#ifndef NO_ADDSUB_Q
if (GET_CODE (operands[1]) == CONST_INT)
{
if (INTVAL (operands[1]) >= 128)
return \"subq%.b %1,%0\";
}
}
-#endif
return \"add%.b %1,%0\";
}")
"!TARGET_5200"
"*
{
-#ifndef NO_ADDSUB_Q
if (GET_CODE (operands[1]) == CONST_INT)
{
if (INTVAL (operands[1]) >= 128)
return \"subq%.b %1,%0\";
}
}
-#endif
return \"add%.b %1,%0\";
}")
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(plus:DF (match_operand:DF 1 "general_operand" "")
(match_operand:DF 2 "general_operand" "")))]
- "TARGET_68881 || TARGET_FPA"
+ "TARGET_68881"
"")
(define_insn ""
- [(set (match_operand:DF 0 "nonimmediate_operand" "=x,y")
- (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
- (match_operand:DF 2 "general_operand" "xH,dmF")))]
- "TARGET_FPA"
- "*
-{
- if (rtx_equal_p (operands[0], operands[1]))
- return \"fpadd%.d %y2,%0\";
- if (rtx_equal_p (operands[0], operands[2]))
- return \"fpadd%.d %y1,%0\";
- if (which_alternative == 0)
- return \"fpadd3%.d %w2,%w1,%0\";
- return \"fpadd3%.d %x2,%x1,%0\";
-}")
-
-(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
(match_operand:DF 1 "general_operand" "0")))]
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(plus:SF (match_operand:SF 1 "general_operand" "")
(match_operand:SF 2 "general_operand" "")))]
- "TARGET_68881 || TARGET_FPA"
+ "TARGET_68881"
"")
(define_insn ""
- [(set (match_operand:SF 0 "nonimmediate_operand" "=x,y")
- (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
- (match_operand:SF 2 "general_operand" "xH,rmF")))]
- "TARGET_FPA"
- "*
-{
- if (rtx_equal_p (operands[0], operands[1]))
- return \"fpadd%.s %w2,%0\";
- if (rtx_equal_p (operands[0], operands[2]))
- return \"fpadd%.s %w1,%0\";
- if (which_alternative == 0)
- return \"fpadd3%.s %w2,%w1,%0\";
- return \"fpadd3%.s %2,%1,%0\";
-}")
-
-(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
(plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
(match_operand:SF 1 "general_operand" "0")))]
if (GET_CODE (operands[1]) == CONST_INT)
{
if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
- {
-#ifdef NO_ADDSUB_Q
- return \"sub%.l %1,%R0\;subx%.l %3,%0\";
-#else
- return \"subq%.l %1,%R0\;subx%.l %3,%0\";
-#endif
- }
+ return \"subq%.l %1,%R0\;subx%.l %3,%0\";
else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
{
operands[1] = GEN_INT (-INTVAL (operands[1]));
-#ifdef NO_ADDSUB_Q
- return \"add%.l %1,%R0\;addx%.l %3,%0\";
-#else
return \"addq%.l %1,%R0\;addx%.l %3,%0\";
-#endif
}
}
return \"sub%.l %1,%R0\;subx%.l %3,%0\";
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(minus:DF (match_operand:DF 1 "general_operand" "")
(match_operand:DF 2 "general_operand" "")))]
- "TARGET_68881 || TARGET_FPA"
+ "TARGET_68881"
"")
(define_insn ""
- [(set (match_operand:DF 0 "nonimmediate_operand" "=x,y,y")
- (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
- (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
- "TARGET_FPA"
- "*
-{
- if (rtx_equal_p (operands[0], operands[2]))
- return \"fprsub%.d %y1,%0\";
- if (rtx_equal_p (operands[0], operands[1]))
- return \"fpsub%.d %y2,%0\";
- if (which_alternative == 0)
- return \"fpsub3%.d %w2,%w1,%0\";
- return \"fpsub3%.d %x2,%x1,%0\";
-}")
-
-(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(minus:DF (match_operand:DF 1 "general_operand" "0")
(float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(minus:SF (match_operand:SF 1 "general_operand" "")
(match_operand:SF 2 "general_operand" "")))]
- "TARGET_68881 || TARGET_FPA"
+ "TARGET_68881"
"")
(define_insn ""
- [(set (match_operand:SF 0 "nonimmediate_operand" "=x,y,y")
- (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
- (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
- "TARGET_FPA"
- "*
-{
- if (rtx_equal_p (operands[0], operands[2]))
- return \"fprsub%.s %w1,%0\";
- if (rtx_equal_p (operands[0], operands[1]))
- return \"fpsub%.s %w2,%0\";
- if (which_alternative == 0)
- return \"fpsub3%.s %w2,%w1,%0\";
- return \"fpsub3%.s %2,%1,%0\";
-}")
-
-(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
(minus:SF (match_operand:SF 1 "general_operand" "0")
(float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
""
"*
{
-#if defined(MOTOROLA) && !defined(CRDS)
+#if defined(MOTOROLA)
return \"muls%.w %2,%0\";
#else
return \"muls %2,%0\";
""
"*
{
-#if defined(MOTOROLA) && !defined(CRDS)
+#if defined(MOTOROLA)
return \"muls%.w %2,%0\";
#else
return \"muls %2,%0\";
"INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
"*
{
-#if defined(MOTOROLA) && !defined(CRDS)
+#if defined(MOTOROLA)
return \"muls%.w %2,%0\";
#else
return \"muls %2,%0\";
""
"*
{
-#if defined(MOTOROLA) && !defined(CRDS)
+#if defined(MOTOROLA)
return \"mulu%.w %2,%0\";
#else
return \"mulu %2,%0\";
"INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
"*
{
-#if defined(MOTOROLA) && !defined(CRDS)
+#if defined(MOTOROLA)
return \"mulu%.w %2,%0\";
#else
return \"mulu %2,%0\";
[(parallel
[(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
(mult:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "nonimmediate_operand" "")))
+ (match_operand:SI 2 "register_operand" "")))
(set (subreg:SI (match_dup 0) 0)
(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
(zero_extend:DI (match_dup 2)))
[(parallel
[(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
(mult:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "nonimmediate_operand" "")))
+ (match_operand:SI 2 "register_operand" "")))
(set (subreg:SI (match_dup 0) 0)
(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
(sign_extend:DI (match_dup 2)))
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(mult:DF (match_operand:DF 1 "general_operand" "")
(match_operand:DF 2 "general_operand" "")))]
- "TARGET_68881 || TARGET_FPA"
+ "TARGET_68881"
"")
(define_insn ""
- [(set (match_operand:DF 0 "nonimmediate_operand" "=x,y")
- (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
- (match_operand:DF 2 "general_operand" "xH,rmF")))]
- "TARGET_FPA"
- "*
-{
- if (rtx_equal_p (operands[1], operands[2]))
- return \"fpsqr%.d %y1,%0\";
- if (rtx_equal_p (operands[0], operands[1]))
- return \"fpmul%.d %y2,%0\";
- if (rtx_equal_p (operands[0], operands[2]))
- return \"fpmul%.d %y1,%0\";
- if (which_alternative == 0)
- return \"fpmul3%.d %w2,%w1,%0\";
- return \"fpmul3%.d %x2,%x1,%0\";
-}")
-
-(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
(match_operand:DF 1 "general_operand" "0")))]
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(mult:SF (match_operand:SF 1 "general_operand" "")
(match_operand:SF 2 "general_operand" "")))]
- "TARGET_68881 || TARGET_FPA"
+ "TARGET_68881"
"")
(define_insn ""
- [(set (match_operand:SF 0 "nonimmediate_operand" "=x,y")
- (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
- (match_operand:SF 2 "general_operand" "xH,rmF")))]
- "TARGET_FPA"
- "*
-{
- if (rtx_equal_p (operands[1], operands[2]))
- return \"fpsqr%.s %w1,%0\";
- if (rtx_equal_p (operands[0], operands[1]))
- return \"fpmul%.s %w2,%0\";
- if (rtx_equal_p (operands[0], operands[2]))
- return \"fpmul%.s %w1,%0\";
- if (which_alternative == 0)
- return \"fpmul3%.s %w2,%w1,%0\";
- return \"fpmul3%.s %2,%1,%0\";
-}")
-
-(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
(mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
(match_operand:SF 1 "general_operand" "0")))]
"TARGET_68881"
"*
{
-#ifdef FSGLMUL_USE_S
- if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
- return (TARGET_68040_ONLY
- ? \"fsmul%.s %2,%0\"
- : \"fsglmul%.s %2,%0\");
-#else
if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
return (TARGET_68040_ONLY
? \"fsmul%.x %2,%0\"
: \"fsglmul%.x %2,%0\");
-#endif
return (TARGET_68040_ONLY
? \"fsmul%.s %f2,%0\"
: \"fsglmul%.s %f2,%0\");
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(div:DF (match_operand:DF 1 "general_operand" "")
(match_operand:DF 2 "general_operand" "")))]
- "TARGET_68881 || TARGET_FPA"
+ "TARGET_68881"
"")
(define_insn ""
- [(set (match_operand:DF 0 "nonimmediate_operand" "=x,y,y")
- (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
- (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
- "TARGET_FPA"
- "*
-{
- if (rtx_equal_p (operands[0], operands[2]))
- return \"fprdiv%.d %y1,%0\";
- if (rtx_equal_p (operands[0], operands[1]))
- return \"fpdiv%.d %y2,%0\";
- if (which_alternative == 0)
- return \"fpdiv3%.d %w2,%w1,%0\";
- return \"fpdiv3%.d %x2,%x1,%x0\";
-}")
-
-(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(div:DF (match_operand:DF 1 "general_operand" "0")
(float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(div:SF (match_operand:SF 1 "general_operand" "")
(match_operand:SF 2 "general_operand" "")))]
- "TARGET_68881 || TARGET_FPA"
+ "TARGET_68881"
"")
(define_insn ""
- [(set (match_operand:SF 0 "nonimmediate_operand" "=x,y,y")
- (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
- (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
- "TARGET_FPA"
- "*
-{
- if (rtx_equal_p (operands[0], operands[1]))
- return \"fpdiv%.s %w2,%0\";
- if (rtx_equal_p (operands[0], operands[2]))
- return \"fprdiv%.s %w1,%0\";
- if (which_alternative == 0)
- return \"fpdiv3%.s %w2,%w1,%0\";
- return \"fpdiv3%.s %2,%1,%0\";
-}")
-
-(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
(div:SF (match_operand:SF 1 "general_operand" "0")
(float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
"TARGET_68881"
"*
{
-#ifdef FSGLDIV_USE_S
- if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
- return (TARGET_68040_ONLY
- ? \"fsdiv%.s %2,%0\"
- : \"fsgldiv%.s %2,%0\");
-#else
if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
return (TARGET_68040_ONLY
? \"fsdiv%.x %2,%0\"
: \"fsgldiv%.x %2,%0\");
-#endif
return (TARGET_68040_ONLY
? \"fsdiv%.s %f2,%0\"
: \"fsgldiv%.s %f2,%0\");
case -1 :
/* FIXME : a scratch register would be welcome here if operand[0]
is not a register */
- output_asm_insn (\"move%.l %#-1,%R0\", operands);
+ output_asm_insn (\"move%.l %#-1,%0\", operands);
break;
default :
{
""
"
{
- if (!TARGET_FPA && !TARGET_68881)
+ if (!TARGET_68881)
{
rtx result;
rtx target;
}")
(define_insn ""
- [(set (match_operand:SF 0 "nonimmediate_operand" "=x,y")
- (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
- "TARGET_FPA"
- "fpneg%.s %w1,%0")
-
-(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,d")
(neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
"TARGET_68881"
""
"
{
- if (!TARGET_FPA && !TARGET_68881)
+ if (!TARGET_68881)
{
rtx result;
rtx target;
}")
(define_insn ""
- [(set (match_operand:DF 0 "nonimmediate_operand" "=x,y")
- (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
- "TARGET_FPA"
- "fpneg%.d %y1, %0")
-
-(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,d")
(neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
"TARGET_68881"
""
"
{
- if (!TARGET_FPA && !TARGET_68881)
+ if (!TARGET_68881)
{
rtx result;
rtx target;
}")
(define_insn ""
- [(set (match_operand:SF 0 "nonimmediate_operand" "=x,y")
- (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
- "TARGET_FPA"
- "fpabs%.s %y1,%0")
-
-(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
(abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
"TARGET_68881"
""
"
{
- if (!TARGET_FPA && !TARGET_68881)
+ if (!TARGET_68881)
{
rtx result;
rtx target;
}")
(define_insn ""
- [(set (match_operand:DF 0 "nonimmediate_operand" "=x,y")
- (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
- "TARGET_FPA"
- "fpabs%.d %y1,%0")
-
-(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
"TARGET_68881"
output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
#endif
}
- ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
+ (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
CODE_LABEL_NUMBER (operands[4]));
return \"\";
} ")
#ifdef SGS
#ifdef ASM_OUTPUT_CASE_LABEL
if (TARGET_5200)
- return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
+ {
+ if (ADDRESS_REG_P (operands[0]))
+ return \"jmp 6(%%pc,%0.l)\";
+ else
+ return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
+ }
else
return \"jmp 6(%%pc,%0.w)\";
#else
if (TARGET_5200)
{
-#ifdef CRDS
- return \"ext%.l %0\;jmp 2(pc,%0.l)\";
-#else
- return \"extl %0\;jmp 2(%%pc,%0.l)\";
-#endif /* end !CRDS */
+ if (ADDRESS_REG_P (operands[0]))
+ return \"jmp 2(%%pc,%0.l)\";
+ else
+ return \"extl %0\;jmp 2(%%pc,%0.l)\";
}
else
- {
-#ifdef CRDS
- return \"jmp 2(pc,%0.w)\";
-#else
- return \"jmp 2(%%pc,%0.w)\";
-#endif /* end !CRDS */
- }
+ return \"jmp 2(%%pc,%0.w)\";
#endif
#else /* not SGS */
if (TARGET_5200)
{
+ if (ADDRESS_REG_P (operands[0]))
+ {
#ifdef MOTOROLA
- return \"ext%.l %0\;jmp (2,pc,%0.l)\";
+ return \"jmp (2,pc,%0.l)\";
#else
- return \"extl %0\;jmp pc@(2,%0:l)\";
+ return \"jmp pc@(2,%0:l)\";
#endif
+ }
+ else
+ {
+#ifdef MOTOROLA
+ return \"ext%.l %0\;jmp (2,pc,%0.l)\";
+#else
+ return \"extl %0\;jmp pc@(2,%0:l)\";
+#endif
+ }
}
else
{
if (GET_CODE (operands[0]) == MEM)
{
#ifdef MOTOROLA
-#ifdef NO_ADDSUB_Q
- return \"sub%.w %#1,%0\;jbcc %l1\";
-#else
return \"subq%.w %#1,%0\;jbcc %l1\";
-#endif
#else /* not MOTOROLA */
return \"subqw %#1,%0\;jcc %l1\";
#endif
}
#ifdef MOTOROLA
#ifdef SGS_CMP_ORDER
-#ifdef NO_ADDSUB_Q
- return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
-#else
return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
-#endif
#else /* not SGS_CMP_ORDER */
return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
#endif
{
CC_STATUS_INIT;
#ifdef MOTOROLA
-#ifdef NO_ADDSUB_Q
- if (DATA_REG_P (operands[0]))
- return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
- if (GET_CODE (operands[0]) == MEM)
- return \"sub%.l %#1,%0\;jbcc %l1\";
-#else
if (DATA_REG_P (operands[0]))
return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
if (GET_CODE (operands[0]) == MEM)
return \"subq%.l %#1,%0\;jbcc %l1\";
-#endif /* NO_ADDSUB_Q */
#ifdef SGS_CMP_ORDER
-#ifdef NO_ADDSUB_Q
- return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
-#else
return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
-#endif
#else /* not SGS_CMP_ORDER */
return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
#endif /* not SGS_CMP_ORDER */
{
CC_STATUS_INIT;
#ifdef MOTOROLA
-#ifdef NO_ADDSUB_Q
- if (DATA_REG_P (operands[0]))
- return \"dbra %0,%l1\";
- if (GET_CODE (operands[0]) == MEM)
- return \"sub%.w %#1,%0\;jbcc %l1\";
-#else
if (DATA_REG_P (operands[0]))
return \"dbra %0,%l1\";
if (GET_CODE (operands[0]) == MEM)
return \"subq%.w %#1,%0\;jbcc %l1\";
-#endif
#ifdef SGS_CMP_ORDER
-#ifdef NO_ADDSUB_Q
- return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
-#else
return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
-#endif
#else /* not SGS_CMP_ORDER */
return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
#endif /* not SGS_CMP_ORDER */
{
CC_STATUS_INIT;
#ifdef MOTOROLA
-#ifdef NO_ADDSUB_Q
- if (DATA_REG_P (operands[0]))
- return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
- if (GET_CODE (operands[0]) == MEM)
- return \"sub%.l %#1,%0\;jbcc %l1\";
-#else
if (DATA_REG_P (operands[0]))
return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
if (GET_CODE (operands[0]) == MEM)
return \"subq%.l %#1,%0\;jbcc %l1\";
-#endif
#ifdef SGS_CMP_ORDER
-#ifdef NO_ADDSUB_Q
- return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
-#else
return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
-#endif
#else /* not SGS_CMP_ORDER */
return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
#endif /* not SGS_CMP_ORDER */
"! flag_pic"
"*
#if defined (MOTOROLA) && !defined (USE_GAS)
-#ifdef MOTOROLA_BSR
- if (GET_CODE (operands[0]) == MEM
- && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
- return \"bsr %0\";
-#endif
return \"jsr %0\";
#else
return \"jbsr %0\";
"! flag_pic"
"*
#if defined (MOTOROLA) && !defined (USE_GAS)
-#ifdef MOTOROLA_BSR
- if (GET_CODE (operands[1]) == MEM
- && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
- return \"bsr %1\";
-#endif
return \"jsr %1\";
#else
return \"jbsr %1\";
;; all of memory. This blocks insns from being moved across this point.
(define_insn "blockage"
- [(unspec_volatile [(const_int 0)] 0)]
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
""
"")
""
"nop")
-(define_insn "probe"
- [(reg:SI 15)]
- "NEED_PROBE"
- "*
-{
- operands[0] = plus_constant (stack_pointer_rtx, NEED_PROBE);
- return \"tstl %a0\";
-}")
-
;; Used for frameless functions which save no regs and allocate no locals.
(define_insn "return"
[(return)]
""
"*
{
-#ifndef SGS_NO_LI
/* Recognize an insn that refers to a table of offsets. Such an insn will
need to refer to a label on the insn. So output one. Use the
label-number of the table of offsets to generate this label. This code,
CODE_LABEL_NUMBER (XEXP (labelref, 0)));
#endif /* not SGS */
#else /* SGS_SWITCH_TABLES or not MOTOROLA */
- ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
+ (*targetm.asm_out.internal_label) (asm_out_file, \"LI\",
CODE_LABEL_NUMBER (XEXP (labelref, 0)));
#ifdef SGS_SWITCH_TABLES
/* Set flag saying we need to define the symbol
#endif /* SGS_SWITCH_TABLES */
#endif /* SGS_SWITCH_TABLES or not MOTOROLA */
}
-#endif /* SGS_NO_LI */
return \"lea %a1,%0\";
}")
rtx xoperands[2];
xoperands[0] = stack_pointer_rtx;
xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
-#ifndef NO_ADDSUB_Q
if (INTVAL (xoperands[1]) <= 8)
{
if (!TARGET_5200)
xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
}
- else
-#endif
- if (INTVAL (xoperands[1]) <= 0x7FFF)
+ else if (INTVAL (xoperands[1]) <= 0x7FFF)
{
if (TARGET_68040)
output_asm_insn (\"add%.w %1,%0\", xoperands);
rtx xoperands[2];
xoperands[0] = stack_pointer_rtx;
xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
-#ifndef NO_ADDSUB_Q
if (INTVAL (xoperands[1]) <= 8)
{
if (!TARGET_5200)
xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
}
- else
-#endif
- if (INTVAL (xoperands[1]) <= 0x7FFF)
+ else if (INTVAL (xoperands[1]) <= 0x7FFF)
{
if (TARGET_68040)
output_asm_insn (\"add%.w %1,%0\", xoperands);
}")
\f
-;; FPA multiply and add.
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=x,y,y")
- (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
- (match_operand:DF 2 "general_operand" "xH,y,y"))
- (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
- "TARGET_FPA"
- "@
- fpma%.d %1,%w2,%w3,%0
- fpma%.d %x1,%x2,%x3,%0
- fpma%.d %x1,%x2,%x3,%0")
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=x,y,y")
- (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
- (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
- (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
- "TARGET_FPA"
- "@
- fpma%.s %1,%w2,%w3,%0
- fpma%.s %1,%2,%3,%0
- fpma%.s %1,%2,%3,%0")
-
-;; FPA Multiply and subtract
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=x,y,y")
- (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
- (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
- (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
- "TARGET_FPA"
- "@
- fpms%.d %3,%w2,%w1,%0
- fpms%.d %x3,%2,%x1,%0
- fpms%.d %x3,%2,%x1,%0")
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=x,y,y")
- (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
- (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
- (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
- "TARGET_FPA"
- "@
- fpms%.s %3,%w2,%w1,%0
- fpms%.s %3,%2,%1,%0
- fpms%.s %3,%2,%1,%0")
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=x,y,y")
- (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
- (match_operand:DF 2 "general_operand" "x,y,rmF"))
- (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
- "TARGET_FPA"
- "@
- fpmr%.d %2,%w1,%w3,%0
- fpmr%.d %x2,%1,%x3,%0
- fpmr%.d %x2,%1,%x3,%0")
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=x,y,y")
- (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
- (match_operand:SF 2 "general_operand" "x,y,yrmF"))
- (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
- "TARGET_FPA"
- "@
- fpmr%.s %2,%w1,%w3,%0
- fpmr%.s %x2,%1,%x3,%0
- fpmr%.s %x2,%1,%x3,%0")
-
-;; FPA Add and multiply
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=x,y,y")
- (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
- (match_operand:DF 2 "general_operand" "x,y,rmF"))
- (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
- "TARGET_FPA"
- "@
- fpam%.d %2,%w1,%w3,%0
- fpam%.d %x2,%1,%x3,%0
- fpam%.d %x2,%1,%x3,%0")
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=x,y,y")
- (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
- (match_operand:SF 2 "general_operand" "x,y,yrmF"))
- (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
- "TARGET_FPA"
- "@
- fpam%.s %2,%w1,%w3,%0
- fpam%.s %x2,%1,%x3,%0
- fpam%.s %x2,%1,%x3,%0")
-
-;;FPA Subtract and multiply
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=x,y,y")
- (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
- (match_operand:DF 2 "general_operand" "x,y,rmF"))
- (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
- "TARGET_FPA"
- "@
- fpsm%.d %2,%w1,%w3,%0
- fpsm%.d %x2,%1,%x3,%0
- fpsm%.d %x2,%1,%x3,%0")
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=x,y,y")
- (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
- (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
- (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
- "TARGET_FPA"
- "@
- fpsm%.d %3,%w2,%w1,%0
- fpsm%.d %x3,%2,%x1,%0
- fpsm%.d %x3,%2,%x1,%0")
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=x,y,y")
- (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
- (match_operand:SF 2 "general_operand" "x,y,yrmF"))
- (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
- "TARGET_FPA"
- "@
- fpsm%.s %2,%w1,%w3,%0
- fpsm%.s %x2,%1,%x3,%0
- fpsm%.s %x2,%1,%x3,%0")
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=x,y,y")
- (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
- (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
- (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
- "TARGET_FPA"
- "@
- fpsm%.s %3,%w2,%w1,%0
- fpsm%.s %x3,%2,%x1,%0
- fpsm%.s %x3,%2,%x1,%0")
-
(define_expand "tstxf"
[(set (cc0)
(match_operand:XF 0 "nonimmediate_operand" ""))]
""
"
{
- /* ??? There isn't an FPA define_insn so we could handle it here too.
- For now we don't (paranoia). */
if (!TARGET_68881)
{
rtx result;
""
"
{
- /* ??? There isn't an FPA define_insn so we could handle it here too.
- For now we don't (paranoia). */
if (!TARGET_68881)
{
rtx result;
(define_insn "sinsf2"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
- (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
+ (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] UNSPEC_SIN))]
"TARGET_68881 && flag_unsafe_math_optimizations"
"*
{
(define_insn "sindf2"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
- (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
+ (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] UNSPEC_SIN))]
"TARGET_68881 && flag_unsafe_math_optimizations"
"*
{
(define_insn "sinxf2"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f")
- (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
+ (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] UNSPEC_SIN))]
"TARGET_68881 && flag_unsafe_math_optimizations"
"fsin%.x %1,%0")
(define_insn "cossf2"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
- (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
+ (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] UNSPEC_COS))]
"TARGET_68881 && flag_unsafe_math_optimizations"
"*
{
(define_insn "cosdf2"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
- (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
+ (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] UNSPEC_COS))]
"TARGET_68881 && flag_unsafe_math_optimizations"
"*
{
(define_insn "cosxf2"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f")
- (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
+ (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] UNSPEC_COS))]
"TARGET_68881 && flag_unsafe_math_optimizations"
"fcos%.x %1,%0")
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