;;- The MCF5200 "ColdFire" architecture is a reduced version of the
;;- 68k ISA. Differences include reduced support for byte and word
;;- operands and the removal of BCD, bitfield, rotate, and integer
-;;- divide instructions. The TARGET_5200 flag turns the use of the
+;;- divide instructions. The TARGET_COLDFIRE flag turns the use of the
;;- removed opcodes and addressing modes off.
;;-
""
"*
{
- if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
+ if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
return \"tst%.l %0\";
/* If you think that the 68020 does not support tstl a0,
reread page B-167 of the 68020 manual more carefully. */
[(set (cc0)
(compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
(match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
[(set (cc0)
(compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
(match_operand:SI 1 "general_operand" "r,mrKs")))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"*
{
if (REG_P (operands[1])
[(set (cc0)
(compare (match_operand:HI 0 "nonimmediate_src_operand" "")
(match_operand:HI 1 "general_src_operand" "")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"m68k_last_compare_had_fp_operands = 0;")
(define_insn ""
[(set (cc0)
(compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
(match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
[(set (cc0)
(compare (match_operand:QI 0 "nonimmediate_src_operand" "")
(match_operand:QI 1 "general_src_operand" "")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"m68k_last_compare_had_fp_operands = 0;")
(define_insn ""
[(set (cc0)
(compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
(match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
(const_int 1)
(minus:SI (const_int 7)
(match_operand:SI 1 "general_operand" "di"))))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
;; This is the same as the above pattern except for the constraints. The 'i'
(const_int 1)
(minus:SI (const_int 7)
(match_operand:SI 1 "general_operand" "d"))))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
(define_insn ""
[(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
(const_int 1)
(match_operand:SI 1 "const_int_operand" "n")))]
- "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
+ "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE"
"*
{
operands[1] = GEN_INT (7 - INTVAL (operands[1]));
[(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
(const_int 1)
(match_operand:SI 1 "const_int_operand" "n")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (GET_CODE (operands[0]) == MEM)
[(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
(const_int 1)
(match_operand:SI 1 "const_int_operand" "n")))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"*
{
if (GET_CODE (operands[0]) == MEM)
(const_int 0))]
;; clr insns on 68000 read before writing.
;; This isn't so on the 68010, but we have no TARGET_68010.
- "((TARGET_68020 || TARGET_5200)
+ "((TARGET_68020 || TARGET_COLDFIRE)
|| !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
"*
{
}
}
/* moveq is faster on the 68000. */
- if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
+ if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_COLDFIRE))
return \"moveq %#0,%0\";
return \"clr%.l %0\";
}")
[(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
(match_operand:SI 1 "general_src_operand" "daymSKT,n,i"))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
return output_move_simode (operands);
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g")
(match_operand:SI 1 "general_operand" "g,r<Q>"))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"* return output_move_simode (operands);")
;; Special case of fullword move, where we need to get a non-GOT PIC
(define_insn ""
[(set (match_operand:HI 0 "nonimmediate_operand" "=g")
(match_operand:HI 1 "general_src_operand" "gS"))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"* return output_move_himode (operands);")
(define_insn ""
[(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g")
(match_operand:HI 1 "general_operand" "g,r<Q>"))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"* return output_move_himode (operands);")
(define_expand "movstricthi"
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
(match_operand:HI 1 "general_src_operand" "rmSn"))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"* return output_move_stricthi (operands);")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m"))
(match_operand:HI 1 "general_src_operand" "rmn,r"))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"* return output_move_stricthi (operands);")
(define_expand "movqi"
(define_insn ""
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m")
(match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"* return output_move_qimode (operands);")
(define_insn ""
[(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,d*a")
(match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"* return output_move_qimode (operands);")
(define_expand "movstrictqi"
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
(match_operand:QI 1 "general_src_operand" "dmSn"))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"* return output_move_strictqi (operands);")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d,m"))
(match_operand:QI 1 "general_src_operand" "dmn,d"))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"* return output_move_strictqi (operands);")
(define_expand "pushqi1"
[(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int -2)))
(set (mem:QI (plus:SI (reg:SI 15) (const_int 1)))
(match_operand:QI 0 "general_operand" ""))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"")
(define_expand "movsf"
(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
(match_operand:SF 1 "general_operand" "rmfF"))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (FP_REG_P (operands[0]))
if (operands[1] == CONST0_RTX (SFmode)
/* clr insns on 68000 read before writing.
This isn't so on the 68010, but we have no TARGET_68010. */
- && ((TARGET_68020 || TARGET_5200)
+ && ((TARGET_68020 || TARGET_COLDFIRE)
|| !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
{
if (ADDRESS_REG_P (operands[0]))
}
}
/* moveq is faster on the 68000. */
- if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
+ if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_COLDFIRE))
{
return \"moveq %#0,%0\";
}
(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=r,g")
(match_operand:SF 1 "general_operand" "g,r"))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"* return \"move%.l %1,%0\";")
(define_expand "movdf"
(match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))]
; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (FP_REG_P (operands[0]))
(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,g")
(match_operand:DF 1 "general_operand" "g,r"))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"* return output_move_double (operands);")
;; ??? The XFmode patterns are schizophrenic about whether constants are
(define_insn ""
[(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
(match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
- "! TARGET_68881 && ! TARGET_5200"
+ "! TARGET_68881 && ! TARGET_COLDFIRE"
"*
{
if (FP_REG_P (operands[0]))
(define_insn ""
[(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
(match_operand:XF 1 "nonimmediate_operand" "g,r"))]
- "! TARGET_68881 && TARGET_5200"
+ "! TARGET_68881 && TARGET_COLDFIRE"
"* return output_move_double (operands);")
(define_expand "movdi"
; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF"))]
; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f")
; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (FP_REG_P (operands[0]))
(define_insn ""
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,g")
(match_operand:DI 1 "general_operand" "g,r"))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"* return output_move_double (operands);")
;; Thus goes after the move instructions
(define_insn "*zero_extendsidi2_cf"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,m")
(zero_extend:DI (match_operand:SI 1 "general_operand" "rm,r")))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"*
{
CC_STATUS_INIT;
(define_insn "*zero_extendsidi2"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
CC_STATUS_INIT;
{
if (GET_CODE (operands[1]) == REG
&& REGNO (operands[0]) == REGNO (operands[1]))
- return (!TARGET_5200 ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
+ return (!TARGET_COLDFIRE ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
if (reg_mentioned_p (operands[0], operands[1]))
- return (!TARGET_5200 ? \"move%.b %1,%0\;and%.w %#0xFF,%0\"
+ return (!TARGET_COLDFIRE ? \"move%.b %1,%0\;and%.w %#0xFF,%0\"
: \"move%.b %1,%0\;and%.l %#0xFF,%0\");
return \"clr%.w %0\;move%.b %1,%0\";
}
{
CC_STATUS_INIT;
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- if (TARGET_68020 || TARGET_5200)
+ if (TARGET_68020 || TARGET_COLDFIRE)
return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
else
return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
{
CC_STATUS_INIT;
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- if (TARGET_68020 || TARGET_5200)
+ if (TARGET_68020 || TARGET_COLDFIRE)
return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
else
return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
{
CC_STATUS_INIT;
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- if (TARGET_68020 || TARGET_5200)
+ if (TARGET_68020 || TARGET_COLDFIRE)
return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
else
return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
output_asm_insn (\"add%.l %2,%3\", operands);
else
output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
- if (TARGET_68020 || TARGET_5200)
+ if (TARGET_68020 || TARGET_COLDFIRE)
return \"smi %0\;extb%.l %0\";
else
return \"smi %0\;ext%.w %0\;ext%.l %0\";
(define_insn "extendqisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
- "TARGET_68020 || TARGET_5200"
+ "TARGET_68020 || TARGET_COLDFIRE"
"extb%.l %0")
\f
;; Conversions between float and double.
&& GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
output_asm_insn (\"move%.l %4,%3\", operands);
output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
- if (TARGET_68020 || TARGET_5200)
+ if (TARGET_68020 || TARGET_COLDFIRE)
output_asm_insn (\"extb%.l %2\", operands);
else
output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
(const_int 32))
(match_operand:DI 2 "general_operand" "0,0,0,0")))
(clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
CC_STATUS_INIT;
(match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
- "! TARGET_5200"
+ "! TARGET_COLDFIRE"
"* return output_addsi3 (operands);")
(define_insn "*addsi3_5200"
[(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,r")
(plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
(match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"* return output_addsi3 (operands);")
(define_insn ""
(plus:SI (match_operand:SI 1 "general_operand" "0")
(sign_extend:SI
(match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"add%.w %2,%0")
(define_insn "addhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
(plus:HI (match_operand:HI 1 "general_operand" "%0,0")
(match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (GET_CODE (operands[2]) == CONST_INT)
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
(plus:HI (match_dup 0)
(match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (GET_CODE (operands[1]) == CONST_INT)
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
(plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
(match_dup 0)))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (GET_CODE (operands[1]) == CONST_INT)
[(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
(plus:QI (match_operand:QI 1 "general_operand" "%0,0")
(match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (GET_CODE (operands[2]) == CONST_INT)
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
(plus:QI (match_dup 0)
(match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (GET_CODE (operands[1]) == CONST_INT)
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
(plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
(match_dup 0)))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (GET_CODE (operands[1]) == CONST_INT)
(ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
(const_int 32))))
(clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
CC_STATUS_INIT;
(minus:SI (match_operand:SI 1 "general_operand" "0")
(sign_extend:SI
(match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"sub%.w %2,%0")
(define_insn "subhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
(minus:HI (match_operand:HI 1 "general_operand" "0,0")
(match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"sub%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
(minus:HI (match_dup 0)
(match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"sub%.w %1,%0")
(define_insn "subqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
(minus:QI (match_operand:QI 1 "general_operand" "0,0")
(match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"sub%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
(minus:QI (match_dup 0)
(match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"sub%.b %1,%0")
(define_expand "subdf3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(mult:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
- "TARGET_68020 || TARGET_5200"
+ "TARGET_68020 || TARGET_COLDFIRE"
"")
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(mult:SI (match_operand:SI 1 "general_operand" "%0")
(match_operand:SI 2 "general_operand" "d<Q>")))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"muls%.l %2,%0")
(define_insn "umulhisi3"
(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
(zero_extend:DI (match_dup 2)))
(const_int 32))))])]
- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
"")
(define_insn ""
(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
(zero_extend:DI (match_dup 2)))
(const_int 32))))]
- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
"mulu%.l %2,%3:%0")
; Match immediate case. For 2.4 only match things < 2^31.
(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
(match_dup 2))
(const_int 32))))]
- "TARGET_68020 && !TARGET_68060 && !TARGET_5200
+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE
&& (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
"mulu%.l %2,%3:%0")
(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
(sign_extend:DI (match_dup 2)))
(const_int 32))))])]
- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
"")
(define_insn ""
(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
(sign_extend:DI (match_dup 2)))
(const_int 32))))]
- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
"muls%.l %2,%3:%0")
(define_insn ""
(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
(match_dup 2))
(const_int 32))))]
- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
"muls%.l %2,%3:%0")
(define_expand "umulsi3_highpart"
(zero_extend:DI (match_operand:SI 2 "general_operand" "")))
(const_int 32))))
(clobber (match_dup 3))])]
- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
"
{
operands[3] = gen_reg_rtx (SImode);
(zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
"mulu%.l %3,%0:%1")
(define_insn "const_umulsi3_highpart"
(match_operand:DI 3 "const_uint32_operand" "n"))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
"mulu%.l %3,%0:%1")
(define_expand "smulsi3_highpart"
(sign_extend:DI (match_operand:SI 2 "general_operand" "")))
(const_int 32))))
(clobber (match_dup 3))])]
- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
"
{
operands[3] = gen_reg_rtx (SImode);
(sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
"muls%.l %3,%0:%1")
(define_insn "const_smulsi3_highpart"
(match_operand:DI 3 "const_sint32_operand" "n"))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
"muls%.l %3,%0:%1")
(define_expand "muldf3"
\f
;; Remainder instructions.
-(define_insn "divmodsi4"
+(define_expand "divmodsi4"
+ [(parallel
+ [(set (match_operand:SI 0 "nonimmediate_operand" "")
+ (div:SI (match_operand:SI 1 "general_operand" "")
+ (match_operand:SI 2 "general_src_operand" "")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "")
+ (mod:SI (match_dup 1) (match_dup 2)))])]
+ "TARGET_68020 || TARGET_CF_HWDIV"
+ "")
+
+(define_insn ""
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
+ (div:SI (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_src_operand" "d<Q>U")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
+ (mod:SI (match_dup 1) (match_dup 2)))]
+ "TARGET_CF_HWDIV"
+ "*
+{
+ if (find_reg_note (insn, REG_UNUSED, operands[3]))
+ return \"divs%.l %2,%0\";
+ else if (find_reg_note (insn, REG_UNUSED, operands[0]))
+ return \"rems%.l %2,%3:%0\";
+ else
+ return \"rems%.l %2,%3:%0\;divs%.l %2,%0\";
+}")
+
+(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(div:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_src_operand" "dmSTK")))
(set (match_operand:SI 3 "nonimmediate_operand" "=d")
(mod:SI (match_dup 1) (match_dup 2)))]
- "TARGET_68020 && !TARGET_5200"
+ "TARGET_68020"
"*
{
if (find_reg_note (insn, REG_UNUSED, operands[3]))
return \"divsl%.l %2,%3:%0\";
}")
-(define_insn "udivmodsi4"
+(define_expand "udivmodsi4"
+ [(parallel
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
+ (udiv:SI (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_src_operand" "dmSTK")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=d")
+ (umod:SI (match_dup 1) (match_dup 2)))])]
+ "TARGET_68020 || TARGET_CF_HWDIV"
+ "")
+
+(define_insn ""
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
+ (udiv:SI (match_operand:SI 1 "general_operand" "0")
+ (match_operand:SI 2 "general_src_operand" "d<Q>U")))
+ (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
+ (umod:SI (match_dup 1) (match_dup 2)))]
+ "TARGET_CF_HWDIV"
+ "*
+{
+ if (find_reg_note (insn, REG_UNUSED, operands[3]))
+ return \"divu%.l %2,%0\";
+ else if (find_reg_note (insn, REG_UNUSED, operands[0]))
+ return \"remu%.l %2,%3:%0\";
+ else
+ return \"remu%.l %2,%3:%0\;divu%.l %2,%0\";
+}")
+
+(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(udiv:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_src_operand" "dmSTK")))
(set (match_operand:SI 3 "nonimmediate_operand" "=d")
(umod:SI (match_dup 1) (match_dup 2)))]
- "TARGET_68020 && !TARGET_5200"
+ "TARGET_68020 && !TARGET_COLDFIRE"
"*
{
if (find_reg_note (insn, REG_UNUSED, operands[3]))
(match_operand:HI 2 "general_src_operand" "dmSKT")))
(set (match_operand:HI 3 "nonimmediate_operand" "=d")
(mod:HI (match_dup 1) (match_dup 2)))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
"*
{
#ifdef MOTOROLA
(match_operand:HI 2 "general_src_operand" "dmSKT")))
(set (match_operand:HI 3 "nonimmediate_operand" "=d")
(umod:HI (match_dup 1) (match_dup 2)))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
"*
{
#ifdef MOTOROLA
[(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
(and:DI (match_operand:DI 1 "general_operand" "%0,0")
(match_operand:DI 2 "general_operand" "dn,don")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
CC_STATUS_INIT;
[(set (match_operand:SI 0 "not_sp_operand" "=m,d")
(and:SI (match_operand:SI 1 "general_operand" "%0,0")
(match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
return output_andsi3 (operands);
[(set (match_operand:SI 0 "not_sp_operand" "=m,d")
(and:SI (match_operand:SI 1 "general_operand" "%0,0")
(match_operand:SI 2 "general_src_operand" "d,dmsK")))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"and%.l %2,%0")
(define_insn "andhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
(and:HI (match_operand:HI 1 "general_operand" "%0,0")
(match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"and%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
(and:HI (match_dup 0)
(match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"and%.w %1,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
(and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
(match_dup 0)))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"and%.w %1,%0")
(define_insn "andqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
(and:QI (match_operand:QI 1 "general_operand" "%0,0")
(match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"and%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
(and:QI (match_dup 0)
(match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"and%.b %1,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
(and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
(match_dup 0)))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"and%.b %1,%0")
\f
;; inclusive-or instructions
[(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
(ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
(match_operand:DI 2 "general_operand" "0,0")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
int byte_mode;
[(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
(ior:DI (match_operand:DI 1 "general_operand" "%0,0")
(match_operand:DI 2 "general_operand" "dn,don")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
CC_STATUS_INIT;
[(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
(match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
- "! TARGET_5200"
+ "! TARGET_COLDFIRE"
"*
{
return output_iorsi3 (operands);
[(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
(match_operand:SI 2 "general_src_operand" "d,dmsK")))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"or%.l %2,%0")
(define_insn "iorhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
(ior:HI (match_operand:HI 1 "general_operand" "%0,0")
(match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"or%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
(ior:HI (match_dup 0)
(match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"or%.w %1,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
(ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
(match_dup 0)))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"or%.w %1,%0")
(define_insn "iorqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
(ior:QI (match_operand:QI 1 "general_operand" "%0,0")
(match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"or%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
(ior:QI (match_dup 0)
(match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"or%.b %1,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
(ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
(match_dup 0)))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"or%.b %1,%0")
;; On all 68k models, this makes faster code in a special case.
[(set (match_operand:SI 0 "nonimmediate_operand" "=o,d")
(ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
(match_operand:SI 2 "general_operand" "0,0")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
int byte_mode;
[(set (match_operand:DI 0 "nonimmediate_operand" "=od")
(xor:DI (match_operand:DI 1 "general_operand" "%0")
(match_operand:DI 2 "general_operand" "dn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
CC_STATUS_INIT;
(xor:SI (match_operand:SI 1 "general_operand" "%0,0")
(match_operand:SI 2 "general_operand" "di,dKT")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
return output_xorsi3 (operands);
[(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d")
(xor:SI (match_operand:SI 1 "general_operand" "%0,0")
(match_operand:SI 2 "general_operand" "d,Ks")))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"eor%.l %2,%0")
(define_insn "xorhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
(xor:HI (match_operand:HI 1 "general_operand" "%0")
(match_operand:HI 2 "general_operand" "dn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"eor%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
(xor:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"eor%.w %1,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
(xor:HI (match_operand:HI 1 "general_operand" "dn")
(match_dup 0)))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"eor%.w %1,%0")
(define_insn "xorqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
(xor:QI (match_operand:QI 1 "general_operand" "%0")
(match_operand:QI 2 "general_operand" "dn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"eor%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
(xor:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dn")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"eor%.b %1,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
(xor:QI (match_operand:QI 1 "general_operand" "dn")
(match_dup 0)))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"eor%.b %1,%0")
\f
;; negation instructions
""
"
{
- if (TARGET_5200)
+ if (TARGET_COLDFIRE)
emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
else
emit_insn (gen_negdi2_internal (operands[0], operands[1]));
(define_insn "negdi2_internal"
[(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
(neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (which_alternative == 0)
(define_insn "negdi2_5200"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d")
(neg:DI (match_operand:DI 1 "general_operand" "0")))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"*
{
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
""
"
{
- if (TARGET_5200)
+ if (TARGET_COLDFIRE)
emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
else
emit_insn (gen_negsi2_internal (operands[0], operands[1]));
(define_insn "negsi2_internal"
[(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
(neg:SI (match_operand:SI 1 "general_operand" "0")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"neg%.l %0")
(define_insn "negsi2_5200"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(neg:SI (match_operand:SI 1 "general_operand" "0")))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"neg%.l %0")
(define_insn "neghi2"
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
(neg:HI (match_operand:HI 1 "general_operand" "0")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"neg%.w %0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
(neg:HI (match_dup 0)))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"neg%.w %0")
(define_insn "negqi2"
[(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
(neg:QI (match_operand:QI 1 "general_operand" "0")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"neg%.b %0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
(neg:QI (match_dup 0)))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"neg%.b %0")
;; If using software floating point, just flip the sign bit.
(define_insn "one_cmpldi2"
[(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
(not:DI (match_operand:DI 1 "general_operand" "0")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
CC_STATUS_INIT;
""
"
{
- if (TARGET_5200)
+ if (TARGET_COLDFIRE)
emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
else
emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
(define_insn "one_cmplsi2_internal"
[(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
(not:SI (match_operand:SI 1 "general_operand" "0")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"not%.l %0")
(define_insn "one_cmplsi2_5200"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(not:SI (match_operand:SI 1 "general_operand" "0")))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"not%.l %0")
(define_insn "one_cmplhi2"
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
(not:HI (match_operand:HI 1 "general_operand" "0")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"not%.w %0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
(not:HI (match_dup 0)))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"not%.w %0")
(define_insn "one_cmplqi2"
[(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
(not:QI (match_operand:QI 1 "general_operand" "0")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"not%.b %0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
(not:QI (match_dup 0)))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"not%.b %0")
\f
;; arithmetic shift instructions
[(set (match_operand:DI 0 "nonimmediate_operand" "=d")
(ashift:DI (match_operand:DI 1 "general_operand" "0")
(match_operand 2 "const_int_operand" "n")))]
- "(!TARGET_5200
+ "(!TARGET_COLDFIRE
&& ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
|| INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
|| (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(ashift:DI (match_operand:DI 1 "general_operand" "")
(match_operand 2 "const_int_operand" "")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"
{
/* ??? This is a named pattern like this is not allowed to FAIL based
[(set (match_operand:SI 0 "register_operand" "=d")
(ashift:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "const_int_operand" "n")))]
- "(! TARGET_68020 && !TARGET_5200
+ "(! TARGET_68020 && !TARGET_COLDFIRE
&& INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
"*
{
[(set (match_operand:HI 0 "register_operand" "=d")
(ashift:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"lsl%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(ashift:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"lsl%.w %1,%0")
(define_insn "ashlqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(ashift:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"lsl%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(ashift:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"lsl%.b %1,%0")
;; On most 68k models, this makes faster code in a special case.
[(set (match_operand:SI 0 "register_operand" "=d")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "const_int_operand" "n")))]
- "(! TARGET_68020 && !TARGET_5200
+ "(! TARGET_68020 && !TARGET_COLDFIRE
&& INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
"*
{
[(set (match_operand:DI 0 "nonimmediate_operand" "=d")
(ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
(match_operand 2 "const_int_operand" "n")))]
- "(!TARGET_5200
+ "(!TARGET_COLDFIRE
&& ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
|| INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
|| INTVAL (operands[2]) == 31
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(ashiftrt:DI (match_operand:DI 1 "general_operand" "")
(match_operand 2 "const_int_operand" "")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"
{
/* ??? This is a named pattern like this is not allowed to FAIL based
[(set (match_operand:HI 0 "register_operand" "=d")
(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"asr%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(ashiftrt:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"asr%.w %1,%0")
(define_insn "ashrqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"asr%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(ashiftrt:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"asr%.b %1,%0")
\f
;; logical shift instructions
[(set (match_operand:DI 0 "nonimmediate_operand" "=d")
(lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
(match_operand 2 "const_int_operand" "n")))]
- "(!TARGET_5200
+ "(!TARGET_COLDFIRE
&& ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
|| INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
|| (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(lshiftrt:DI (match_operand:DI 1 "general_operand" "")
(match_operand 2 "const_int_operand" "")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"
{
/* ??? This is a named pattern like this is not allowed to FAIL based
[(set (match_operand:SI 0 "register_operand" "=d")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "const_int_operand" "n")))]
- "(! TARGET_68020 && !TARGET_5200
+ "(! TARGET_68020 && !TARGET_COLDFIRE
&& INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
"*
{
[(set (match_operand:HI 0 "register_operand" "=d")
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"lsr%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(lshiftrt:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"lsr%.w %1,%0")
(define_insn "lshrqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"lsr%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(lshiftrt:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"lsr%.b %1,%0")
\f
;; rotate instructions
[(set (match_operand:SI 0 "register_operand" "=d")
(rotate:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "general_operand" "dINO")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
[(set (match_operand:HI 0 "register_operand" "=d")
(rotate:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "general_operand" "dIP")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(rotate:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dIP")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
[(set (match_operand:QI 0 "register_operand" "=d")
(rotate:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(rotate:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
[(set (match_operand:SI 0 "register_operand" "=d")
(rotatert:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"ror%.l %2,%0")
(define_insn "rotrhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(rotatert:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"ror%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(rotatert:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"ror%.w %1,%0")
(define_insn "rotrqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(rotatert:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"ror%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(rotatert:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dI")))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"ror%.b %1,%0")
\f
[(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
(match_operator 1 "valid_dbcc_comparison_p"
[(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
- "! TARGET_5200"
+ "! TARGET_COLDFIRE"
"*
{
return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
[(set (match_operand:QI 0 "nonimmediate_operand" "=d")
(match_operator 1 "valid_dbcc_comparison_p"
[(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"*
{
return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
(match_operator 1 "valid_dbcc_comparison_p"
[(match_operand:DI 2 "general_operand" "ro,r")
(match_operand:DI 3 "general_operand" "r,ro")]))]
- "! TARGET_5200"
+ "! TARGET_COLDFIRE"
"*
{
return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
(match_operator 1 "valid_dbcc_comparison_p"
[(match_operand:DI 2 "general_operand" "ro,r")
(match_operand:DI 3 "general_operand" "r,ro")]))]
- "TARGET_5200"
+ "TARGET_COLDFIRE"
"*
{
return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
#endif
}
operands[4] = gen_label_rtx();
- if (TARGET_68020 || TARGET_5200)
+ if (TARGET_68020 || TARGET_COLDFIRE)
{
#ifdef MOTOROLA
output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
#endif
}
- if (TARGET_68020 || TARGET_5200)
+ if (TARGET_68020 || TARGET_COLDFIRE)
{
#ifdef MOTOROLA
return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
}
}
CC_STATUS_INIT;
- if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
+ if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
output_asm_insn(\"tst%.l %0\", operands);
else
{
}
}
CC_STATUS_INIT;
- if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
+ if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
output_asm_insn(\"tst%.l %0\", operands);
else
{
#else
#ifdef SGS
#ifdef ASM_OUTPUT_CASE_LABEL
- if (TARGET_5200)
+ if (TARGET_COLDFIRE)
{
if (ADDRESS_REG_P (operands[0]))
return \"jmp 6(%%pc,%0.l)\";
else
return \"jmp 6(%%pc,%0.w)\";
#else
- if (TARGET_5200)
+ if (TARGET_COLDFIRE)
{
if (ADDRESS_REG_P (operands[0]))
return \"jmp 2(%%pc,%0.l)\";
return \"jmp 2(%%pc,%0.w)\";
#endif
#else /* not SGS */
- if (TARGET_5200)
+ if (TARGET_COLDFIRE)
{
if (ADDRESS_REG_P (operands[0]))
{
(set (match_dup 0)
(plus:HI (match_dup 0)
(const_int -1)))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
CC_STATUS_INIT;
(set (match_dup 0)
(plus:SI (match_dup 0)
(const_int -1)))]
- "!TARGET_5200"
+ "!TARGET_COLDFIRE"
"*
{
CC_STATUS_INIT;
(set (match_dup 0)
(plus:HI (match_dup 0)
(const_int -1)))]
- "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
+ "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
CC_STATUS_INIT;
(set (match_dup 0)
(plus:SI (match_dup 0)
(const_int -1)))]
- "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
+ "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
CC_STATUS_INIT;
xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
if (INTVAL (xoperands[1]) <= 8)
{
- if (!TARGET_5200)
+ if (!TARGET_COLDFIRE)
output_asm_insn (\"addq%.w %1,%0\", xoperands);
else
output_asm_insn (\"addq%.l %1,%0\", xoperands);
xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
if (INTVAL (xoperands[1]) <= 8)
{
- if (!TARGET_5200)
+ if (!TARGET_COLDFIRE)
output_asm_insn (\"addq%.w %1,%0\", xoperands);
else
output_asm_insn (\"addq%.l %1,%0\", xoperands);
xoperands[2]
= gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3));
xoperands[3] = stack_pointer_rtx;
- if (!TARGET_5200)
+ if (!TARGET_COLDFIRE)
output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
else
output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
|| GET_CODE (operands[0]) == MEM)
/* clr insns on 68000 read before writing.
This isn't so on the 68010, but we have no TARGET_68010. */
- && ((TARGET_68020 || TARGET_5200)
+ && ((TARGET_68020 || TARGET_COLDFIRE)
|| !(GET_CODE (operands[0]) == MEM
&& MEM_VOLATILE_P (operands[0]))))
return \"clr%.w %0\";
(set (match_dup 0)
(plus:HI (match_dup 0)
(const_int -1)))])]
- "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
+ "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
"*
{
CC_STATUS_INIT;
(set (match_dup 0)
(plus:SI (match_dup 0)
(const_int -1)))])]
- "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
+ "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
"*
{
CC_STATUS_INIT;
(set (match_dup 0)
(plus:HI (match_dup 0)
(const_int -1)))])]
- "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
+ "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
"*
{
CC_STATUS_INIT;
(set (match_dup 0)
(plus:SI (match_dup 0)
(const_int -1)))])]
- "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
+ "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
"*
{
CC_STATUS_INIT;
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