;;- Machine description for GNU compiler, Motorola 68000 Version
;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001,
-;; 2002, 2003, 2004, 2005, 2006
+;; 2002, 2003, 2004, 2005, 2006, 2007, 2008
;; Free Software Foundation, Inc.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
+;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;; GCC is distributed in the hope that it will be useful,
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
-;; Boston, MA 02110-1301, USA.
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
;;- Information about MCF5200 port.
;; UNSPEC usage:
(define_constants
- [(UNSPEC_SIN 1)
- (UNSPEC_COS 2)
+ [(UNSPEC_SIN 1)
+ (UNSPEC_COS 2)
+ (UNSPEC_GOT 3)
+ (UNSPEC_IB 4)
+ (UNSPEC_TIE 5)
+ (UNSPEC_RELOC16 6)
+ (UNSPEC_RELOC32 7)
])
;; UNSPEC_VOLATILE usage:
(define_constants
[(D0_REG 0)
(A0_REG 8)
+ (A1_REG 9)
+ (PIC_REG 13)
+ (A6_REG 14)
(SP_REG 15)
+ (FP0_REG 16)
])
(include "predicates.md")
+(include "constraints.md")
+\f
+;; ::::::::::::::::::::
+;; ::
+;; :: Attributes
+;; ::
+;; ::::::::::::::::::::
+
+;; Processor type.
+(define_attr "cpu" "cfv1, cfv2, cfv3, cfv4, unknown"
+ (const (symbol_ref "m68k_sched_cpu")))
+
+;; MAC type.
+(define_attr "mac" "no, cf_mac, cf_emac"
+ (const (symbol_ref "m68k_sched_mac")))
+
+;; Instruction type for use in scheduling description.
+;; _l and _w suffixes indicate size of the operands of instruction.
+;; alu - usual arithmetic or logic instruction.
+;; aluq - arithmetic or logic instruction which has a quick immediate (the one
+;; that is encoded in the instruction word) for its Y operand.
+;; alux - Arithmetic instruction that uses carry bit (e.g., addx and subx).
+;; bcc - conditional branch.
+;; bitr - bit operation that only updates flags.
+;; bitrw - bit operation that updates flags and output operand.
+;; bra, bsr, clr, cmp, div, ext - corresponding instruction.
+;; falu, fbcc, fcmp, fdiv, fmove, fmul, fneg, fsqrt, ftst - corresponding
+;; instruction.
+;; ib - fake instruction to subscribe slots in ColdFire V1,V2,V3 instruction
+;; buffer.
+;; ignore - fake instruction.
+;; jmp, jsr, lea, link, mov3q, move, moveq, mul - corresponding instruction.
+;; mvsz - mvs or mvz instruction.
+;; neg, nop, pea, rts, scc - corresponding instruction.
+;; shift - arithmetic or logical shift instruction.
+;; trap, tst, unlk - corresponding instruction.
+(define_attr "type"
+ "alu_l,aluq_l,alux_l,bcc,bitr,bitrw,bra,bsr,clr,clr_l,cmp,cmp_l,
+ div_w,div_l,ext,
+ falu,fbcc,fcmp,fdiv,fmove,fmul,fneg,fsqrt,ftst,
+ ib,ignore,
+ jmp,jsr,lea,link,mov3q_l,move,move_l,moveq_l,mul_w,mul_l,mvsz,neg_l,nop,
+ pea,rts,scc,shift,
+ trap,tst,tst_l,unlk,
+ unknown"
+ (const_string "unknown"))
+
+;; Index of the X or Y operand in recog_data.operand[].
+;; Should be used only within opx_type and opy_type.
+(define_attr "opx" "" (const_int 0))
+(define_attr "opy" "" (const_int 1))
+
+;; Type of the Y operand.
+;; See m68k.c: enum attr_op_type.
+(define_attr "opy_type"
+ "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l"
+ (cond [(eq_attr "type" "ext,fbcc,ftst,neg_l,bcc,bra,bsr,clr,clr_l,ib,ignore,
+ jmp,jsr,nop,rts,scc,trap,tst,tst_l,
+ unlk,unknown") (const_string "none")
+ (eq_attr "type" "lea,pea")
+ (symbol_ref "m68k_sched_attr_opy_type (insn, 1)")]
+ (symbol_ref "m68k_sched_attr_opy_type (insn, 0)")))
+
+;; Type of the X operand.
+;; See m68k.c: enum attr_op_type.
+(define_attr "opx_type"
+ "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l"
+ (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk,
+ unknown") (const_string "none")
+ (eq_attr "type" "pea") (const_string "mem1")
+ (eq_attr "type" "jmp,jsr")
+ (symbol_ref "m68k_sched_attr_opx_type (insn, 1)")]
+ (symbol_ref "m68k_sched_attr_opx_type (insn, 0)")))
+
+;; Access to the X operand: none, read, write, read/write, unknown.
+;; Access to the Y operand is either none (if opy_type is none)
+;; or read otherwise.
+(define_attr "opx_access" "none, r, w, rw"
+ (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk,
+ unknown") (const_string "none")
+ (eq_attr "type" "bcc,bra,bsr,bitr,cmp,cmp_l,fbcc,fcmp,ftst,
+ jmp,jsr,tst,tst_l") (const_string "r")
+ (eq_attr "type" "clr,clr_l,fneg,fmove,lea,
+ mov3q_l,move,move_l,moveq_l,mvsz,
+ pea,scc") (const_string "w")
+ (eq_attr "type" "alu_l,aluq_l,alux_l,bitrw,div_w,div_l,ext,
+ falu,fdiv,fmul,fsqrt,link,mul_w,mul_l,
+ neg_l,shift") (const_string "rw")]
+ ;; Should never be used.
+ (symbol_ref "(gcc_unreachable (), OPX_ACCESS_NONE)")))
+
+;; Memory accesses of the insn.
+;; 00 - no memory references
+;; 10 - memory is read
+;; i0 - indexed memory is read
+;; 01 - memory is written
+;; 0i - indexed memory is written
+;; 11 - memory is read, memory is written
+;; i1 - indexed memory is read, memory is written
+;; 1i - memory is read, indexed memory is written
+(define_attr "op_mem" "00, 10, i0, 01, 0i, 11, i1, 1i"
+ (symbol_ref "m68k_sched_attr_op_mem (insn)"))
+
+;; Instruction size in words.
+(define_attr "size" "1,2,3"
+ (symbol_ref "m68k_sched_attr_size (insn)"))
+
+;; Alternative is OK for ColdFire.
+(define_attr "ok_for_coldfire" "yes,no" (const_string "yes"))
+
+;; Define 'enabled' attribute.
+(define_attr "enabled" ""
+ (cond [(and (ne (symbol_ref "TARGET_COLDFIRE") (const_int 0))
+ (eq_attr "ok_for_coldfire" "no"))
+ (const_int 0)]
+ (const_int 1)))
\f
;; Mode macros for floating point operations.
;; Valid floating point modes
-(define_mode_macro FP [SF DF (XF "TARGET_68881")])
+(define_mode_iterator FP [SF DF (XF "TARGET_68881")])
;; Mnemonic infix to round result
(define_mode_attr round [(SF "%$") (DF "%&") (XF "")])
;; Mnemonic infix to round result for mul or div instruction
;; Allowable 68881 constant constraints
(define_mode_attr const [(SF "F") (DF "G") (XF "")])
\f
-(define_insn ""
- [(set (match_operand:DF 0 "push_operand" "=m")
- (match_operand:DF 1 "general_operand" "ro<>fyE"))]
+
+(define_insn_and_split "*movdf_internal"
+ [(set (match_operand:DF 0 "push_operand" "=m, m")
+ (match_operand:DF 1 "general_operand" "f, ro<>E"))]
""
+ "@
+ fmove%.d %f1,%0
+ #"
+ "&& reload_completed && (extract_constrain_insn_cached (insn), which_alternative == 1)"
+ [(const_int 0)]
{
- if (FP_REG_P (operands[1]))
- return "fmove%.d %f1,%0";
- return output_move_double (operands);
-})
+ m68k_emit_move_double (operands);
+ DONE;
+}
+ [(set_attr "type" "fmove,*")])
-(define_insn "pushdi"
+(define_insn_and_split "pushdi"
[(set (match_operand:DI 0 "push_operand" "=m")
- (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
+ (match_operand:DI 1 "general_operand" "ro<>Fi"))]
""
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
{
- return output_move_double (operands);
+ m68k_emit_move_double (operands);
+ DONE;
})
\f
;; We don't want to allow a constant operand for test insns because
;; (set (cc0) (const_int foo)) has no mode information. Such insns will
;; be folded while optimizing anyway.
-(define_expand "tstdi"
- [(parallel [(set (cc0)
- (match_operand:DI 0 "nonimmediate_operand" ""))
- (clobber (match_scratch:SI 1 ""))
- (clobber (match_scratch:DI 2 ""))])]
- ""
- "m68k_last_compare_had_fp_operands = 0;")
-
-(define_insn ""
+(define_insn "tstdi"
[(set (cc0)
- (match_operand:DI 0 "nonimmediate_operand" "am,d"))
+ (compare (match_operand:DI 0 "nonimmediate_operand" "am,d")
+ (const_int 0)))
(clobber (match_scratch:SI 1 "=X,d"))
(clobber (match_scratch:DI 2 "=d,X"))]
""
xoperands[0] = operands[2];
xoperands[1] = operands[0];
output_move_double (xoperands);
- cc_status.flags |= CC_REVERSED;
+ cc_status.flags |= CC_REVERSED; /*|*/
return "neg%.l %R2\;negx%.l %2";
}
if (find_reg_note (insn, REG_DEAD, operands[0]))
{
- cc_status.flags |= CC_REVERSED;
+ cc_status.flags |= CC_REVERSED; /*|*/
return "neg%.l %R0\;negx%.l %0";
}
else
return "sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0";
})
-(define_expand "tstsi"
+;; If you think that the 68020 does not support tstl a0,
+;; reread page B-167 of the 68020 manual more carefully.
+(define_insn "*tstsi_internal_68020_cf"
[(set (cc0)
- (match_operand:SI 0 "nonimmediate_operand" ""))]
- ""
- "m68k_last_compare_had_fp_operands = 0;")
+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm")
+ (const_int 0)))]
+ "TARGET_68020 || TARGET_COLDFIRE"
+ "tst%.l %0"
+ [(set_attr "type" "tst_l")])
-(define_insn ""
+;; On an address reg, cmpw may replace cmpl.
+(define_insn "*tstsi_internal"
[(set (cc0)
- (match_operand:SI 0 "nonimmediate_operand" "rm"))]
- ""
-{
- if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
- return "tst%.l %0";
- /* If you think that the 68020 does not support tstl a0,
- reread page B-167 of the 68020 manual more carefully. */
- /* On an address reg, cmpw may replace cmpl. */
- return "cmp%.w #0,%0";
-})
+ (compare (match_operand:SI 0 "nonimmediate_operand" "dm,r")
+ (const_int 0)))]
+ "!(TARGET_68020 || TARGET_COLDFIRE)"
+ "@
+ tst%.l %0
+ cmp%.w #0,%0"
+ [(set_attr "type" "tst_l,cmp")])
;; This can't use an address register, because comparisons
;; with address registers as second operand always test the whole word.
-(define_expand "tsthi"
+(define_insn "*tsthi_internal"
[(set (cc0)
- (match_operand:HI 0 "nonimmediate_operand" ""))]
+ (compare (match_operand:HI 0 "nonimmediate_operand" "dm")
+ (const_int 0)))]
""
- "m68k_last_compare_had_fp_operands = 0;")
+ "tst%.w %0"
+ [(set_attr "type" "tst")])
-(define_insn ""
- [(set (cc0)
- (match_operand:HI 0 "nonimmediate_operand" "dm"))]
- ""
- "tst%.w %0")
-
-(define_expand "tstqi"
- [(set (cc0)
- (match_operand:QI 0 "nonimmediate_operand" ""))]
- ""
- "m68k_last_compare_had_fp_operands = 0;")
-
-(define_insn ""
+(define_insn "*tstqi_internal"
[(set (cc0)
- (match_operand:QI 0 "nonimmediate_operand" "dm"))]
+ (compare (match_operand:QI 0 "nonimmediate_operand" "dm")
+ (const_int 0)))]
""
- "tst%.b %0")
-
-(define_expand "tst<mode>"
- [(set (cc0)
- (match_operand:FP 0 "general_operand" ""))]
- "TARGET_HARD_FLOAT"
-{
- m68k_last_compare_had_fp_operands = 1;
-})
+ "tst%.b %0"
+ [(set_attr "type" "tst")])
(define_insn "tst<mode>_68881"
[(set (cc0)
- (match_operand:FP 0 "general_operand" "f<FP:dreg>m"))]
+ (compare (match_operand:FP 0 "general_operand" "f<FP:dreg>m")
+ (match_operand:FP 1 "const0_operand" "H")))]
"TARGET_68881"
{
cc_status.flags = CC_IN_68881;
if (FP_REG_P (operands[0]))
return "ftst%.x %0";
return "ftst%.<FP:prec> %0";
-})
+}
+ [(set_attr "type" "ftst")])
(define_insn "tst<mode>_cf"
[(set (cc0)
- (match_operand:FP 0 "general_operand" "f<FP:dreg><Q>U"))]
+ (compare (match_operand:FP 0 "general_operand" "f<FP:dreg><Q>U")
+ (match_operand:FP 1 "const0_operand" "H")))]
"TARGET_COLDFIRE_FPU"
{
cc_status.flags = CC_IN_68881;
if (FP_REG_P (operands[0]))
return "ftst%.d %0";
return "ftst%.<FP:prec> %0";
-})
+}
+ [(set_attr "type" "ftst")])
\f
;; compare instructions.
-(define_expand "cmpdi"
- [(parallel
- [(set (cc0)
- (compare (match_operand:DI 0 "nonimmediate_operand" "")
- (match_operand:DI 1 "general_operand" "")))
- (clobber (match_dup 2))])]
- ""
- "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
-
-(define_insn ""
- [(set (cc0)
- (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
- (match_operand:DI 2 "general_operand" "d,0")))
- (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
+(define_insn "*cmpdi_internal"
+ [(set (cc0)
+ (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
+ (match_operand:DI 2 "general_operand" "d,0")))
+ (clobber (match_scratch:DI 0 "=d,d"))]
""
{
if (rtx_equal_p (operands[0], operands[1]))
return "sub%.l %R2,%R0\;subx%.l %2,%0";
else
{
- cc_status.flags |= CC_REVERSED;
+ cc_status.flags |= CC_REVERSED; /*|*/
return "sub%.l %R1,%R0\;subx%.l %1,%0";
}
})
-(define_expand "cmpsi"
- [(set (cc0)
- (compare (match_operand:SI 0 "nonimmediate_operand" "")
- (match_operand:SI 1 "general_operand" "")))]
+(define_insn "cmpdi"
+ [(set (cc0)
+ (compare (match_operand:DI 0 "nonimmediate_operand")
+ (match_operand:DI 1 "general_operand")))
+ (clobber (match_scratch:DI 2))]
+ ""
+ "")
+
+
+(define_expand "cbranchdi4"
+ [(set (pc)
+ (if_then_else (match_operator 0 "ordered_comparison_operator"
+ [(match_operand:DI 1 "nonimmediate_operand")
+ (match_operand:DI 2 "general_operand")])
+ (label_ref (match_operand 3 ""))
+ (pc)))]
+ ""
+{
+ if (operands[2] == const0_rtx)
+ emit_insn (gen_tstdi (operands[1]));
+ else
+ emit_insn (gen_cmpdi (operands[1], operands[2]));
+ operands[1] = cc0_rtx;
+ operands[2] = const0_rtx;
+})
+
+(define_expand "cstoredi4"
+ [(set (match_operand:QI 0 "register_operand")
+ (match_operator:QI 1 "ordered_comparison_operator"
+ [(match_operand:DI 2 "nonimmediate_operand")
+ (match_operand:DI 3 "general_operand")]))]
""
{
- m68k_last_compare_had_fp_operands = 0;
+ if (operands[3] == const0_rtx)
+ emit_insn (gen_tstdi (operands[2]));
+ else
+ emit_insn (gen_cmpdi (operands[2], operands[3]));
+ operands[2] = cc0_rtx;
+ operands[3] = const0_rtx;
})
+
+(define_expand "cbranchsi4"
+ [(set (cc0)
+ (compare (match_operand:SI 1 "nonimmediate_operand" "")
+ (match_operand:SI 2 "general_operand" "")))
+ (set (pc)
+ (if_then_else (match_operator 0 "ordered_comparison_operator"
+ [(cc0) (const_int 0)])
+ (label_ref (match_operand 3 ""))
+ (pc)))]
+ ""
+ "")
+
+(define_expand "cstoresi4"
+ [(set (cc0)
+ (compare (match_operand:SI 2 "nonimmediate_operand" "")
+ (match_operand:SI 3 "general_operand" "")))
+ (set (match_operand:QI 0 "register_operand")
+ (match_operator:QI 1 "ordered_comparison_operator"
+ [(cc0) (const_int 0)]))]
+ ""
+ "")
+
+
;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
(define_insn ""
[(set (cc0)
if (REG_P (operands[1])
|| (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
{
- cc_status.flags |= CC_REVERSED;
+ cc_status.flags |= CC_REVERSED; /*|*/
return "cmp%.l %d0,%d1";
}
if (ADDRESS_REG_P (operands[0])
return "cmp%.l %d1,%d0";
})
-(define_insn ""
+(define_insn "*cmpsi_cf"
[(set (cc0)
(compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
(match_operand:SI 1 "general_operand" "r,mrKs")))]
if (REG_P (operands[1])
|| (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
{
- cc_status.flags |= CC_REVERSED;
+ cc_status.flags |= CC_REVERSED; /*|*/
return "cmp%.l %d0,%d1";
}
return "cmp%.l %d1,%d0";
-})
+}
+ [(set_attr "type" "cmp_l")])
-(define_expand "cmphi"
+(define_expand "cbranchhi4"
[(set (cc0)
- (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
- (match_operand:HI 1 "general_src_operand" "")))]
- "!TARGET_COLDFIRE"
- "m68k_last_compare_had_fp_operands = 0;")
+ (compare (match_operand:HI 1 "nonimmediate_src_operand" "")
+ (match_operand:HI 2 "m68k_subword_comparison_operand" "")))
+ (set (pc)
+ (if_then_else (match_operator 0 "ordered_comparison_operator"
+ [(cc0) (const_int 0)])
+ (label_ref (match_operand 3 ""))
+ (pc)))]
+ ""
+ "")
+
+(define_expand "cstorehi4"
+ [(set (cc0)
+ (compare (match_operand:HI 2 "nonimmediate_operand" "")
+ (match_operand:HI 3 "m68k_subword_comparison_operand" "")))
+ (set (match_operand:QI 0 "register_operand")
+ (match_operator:QI 1 "ordered_comparison_operator"
+ [(cc0) (const_int 0)]))]
+ ""
+ "")
(define_insn ""
[(set (cc0)
if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
|| (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
{
- cc_status.flags |= CC_REVERSED;
+ cc_status.flags |= CC_REVERSED; /*|*/
return "cmp%.w %d0,%d1";
}
return "cmp%.w %d1,%d0";
})
-(define_expand "cmpqi"
+(define_expand "cbranchqi4"
[(set (cc0)
- (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
- (match_operand:QI 1 "general_src_operand" "")))]
- "!TARGET_COLDFIRE"
- "m68k_last_compare_had_fp_operands = 0;")
+ (compare (match_operand:QI 1 "nonimmediate_src_operand" "")
+ (match_operand:QI 2 "m68k_subword_comparison_operand" "")))
+ (set (pc)
+ (if_then_else (match_operator 0 "ordered_comparison_operator"
+ [(cc0) (const_int 0)])
+ (label_ref (match_operand 3 ""))
+ (pc)))]
+ ""
+ "")
+
+(define_expand "cstoreqi4"
+ [(set (cc0)
+ (compare (match_operand:QI 2 "nonimmediate_src_operand" "")
+ (match_operand:QI 3 "m68k_subword_comparison_operand" "")))
+ (set (match_operand:QI 0 "register_operand")
+ (match_operator:QI 1 "ordered_comparison_operator"
+ [(cc0) (const_int 0)]))]
+ ""
+ "")
(define_insn ""
[(set (cc0)
if (REG_P (operands[1])
|| (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
{
- cc_status.flags |= CC_REVERSED;
+ cc_status.flags |= CC_REVERSED; /*|*/
return "cmp%.b %d0,%d1";
}
return "cmp%.b %d1,%d0";
})
-(define_expand "cmp<mode>"
+(define_expand "cbranch<mode>4"
[(set (cc0)
- (compare (match_operand:FP 0 "general_operand" "")
- (match_operand:FP 1 "general_operand" "")))]
+ (compare (match_operand:FP 1 "register_operand" "")
+ (match_operand:FP 2 "fp_src_operand" "")))
+ (set (pc)
+ (if_then_else (match_operator 0 "comparison_operator"
+ [(cc0) (const_int 0)])
+ (label_ref (match_operand 3 ""))
+ (pc)))]
"TARGET_HARD_FLOAT"
-{
- m68k_last_compare_had_fp_operands = 1;
- if (TARGET_COLDFIRE && !reload_completed)
- operands[1] = force_reg (<MODE>mode, operands[1]);
-})
+ "")
-(define_insn "cmp<mode>_68881"
+(define_expand "cstore<mode>4"
[(set (cc0)
- (compare (match_operand:FP 0 "general_operand" "f,m<FP:const>")
- (match_operand:FP 1 "general_operand" "f<FP:dreg>m<FP:const>,f")))]
- "TARGET_68881"
-{
- cc_status.flags = CC_IN_68881;
- if (FP_REG_P (operands[0]))
- {
- if (FP_REG_P (operands[1]))
- return "fcmp%.x %1,%0";
- else
- return "fcmp%.<FP:prec> %f1,%0";
- }
- cc_status.flags |= CC_REVERSED;
- return "fcmp%.<FP:prec> %f0,%1";
-})
+ (compare (match_operand:FP 2 "register_operand" "")
+ (match_operand:FP 3 "fp_src_operand" "")))
+ (set (match_operand:QI 0 "register_operand")
+ (match_operator:QI 1 "m68k_cstore_comparison_operator"
+ [(cc0) (const_int 0)]))]
+ "TARGET_HARD_FLOAT && !(TUNE_68060 || TARGET_COLDFIRE_FPU)"
+ "if (TARGET_COLDFIRE && operands[2] != const0_rtx)
+ FAIL;")
+
+(define_insn "*cmp<mode>_68881"
+ [(set (cc0)
+ (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg>mF")
+ (match_operand:FP 1 "fp_src_operand" "f,<FP:dreg>mF,f")))]
+ "TARGET_68881
+ && (register_operand (operands[0], <MODE>mode)
+ || register_operand (operands[1], <MODE>mode))"
+ "@
+ fcmp%.x %1,%0
+ fcmp%.<FP:prec> %f1,%0
+ fcmp%.<FP:prec> %0,%f1"
+ [(set_attr "type" "fcmp")])
-(define_insn "cmp<mode>_cf"
+(define_insn "*cmp<mode>_cf"
[(set (cc0)
- (compare (match_operand:FP 0 "general_operand" "f,<FP:dreg><Q>U")
- (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,f")))]
- "TARGET_COLDFIRE_FPU"
-{
- cc_status.flags = CC_IN_68881;
- if (FP_REG_P (operands[0]))
- {
- if (FP_REG_P (operands[1]))
- return "fcmp%.d %1,%0";
- else
- return "fcmp%.<FP:prec> %f1,%0";
- }
- cc_status.flags |= CC_REVERSED;
- return "fcmp%.<FP:prec> %f0,%1";
-})
+ (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg><Q>U")
+ (match_operand:FP 1 "fp_src_operand" "f,<FP:dreg><Q>U,f")))]
+ "TARGET_COLDFIRE_FPU
+ && (register_operand (operands[0], <MODE>mode)
+ || register_operand (operands[1], <MODE>mode))"
+ "@
+ fcmp%.d %1,%0
+ fcmp%.<FP:prec> %f1,%0
+ fcmp%.<FP:prec> %0,%f1"
+ [(set_attr "type" "fcmp")])
\f
;; Recognizers for btst instructions.
;; from a MEM at a constant bit position if we can't use this as a constraint.
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS")
- (const_int 1)
- (minus:SI (const_int 7)
- (match_operand:SI 1 "general_operand" "di"))))]
+ [(set
+ (cc0)
+ (compare (zero_extract:SI (match_operand:QI 0 "memory_src_operand" "oS")
+ (const_int 1)
+ (minus:SI (const_int 7)
+ (match_operand:SI 1 "general_operand" "di")))
+ (const_int 0)))]
"!TARGET_COLDFIRE"
{
return output_btst (operands, operands[1], operands[0], insn, 7);
;; has been deleted.
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
- (const_int 1)
- (minus:SI (const_int 7)
- (match_operand:SI 1 "general_operand" "d"))))]
+ [(set
+ (cc0)
+ (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
+ (const_int 1)
+ (minus:SI (const_int 7)
+ (match_operand:SI 1 "general_operand" "d")))
+ (const_int 0)))]
"TARGET_COLDFIRE"
{
return output_btst (operands, operands[1], operands[0], insn, 7);
})
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
- (const_int 1)
- (minus:SI (const_int 31)
- (match_operand:SI 1 "general_operand" "di"))))]
+ [(set
+ (cc0)
+ (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
+ (const_int 1)
+ (minus:SI (const_int 31)
+ (match_operand:SI 1 "general_operand" "di")))
+ (const_int 0)))]
""
{
return output_btst (operands, operands[1], operands[0], insn, 31);
;; are automatically masked to 3 or 5 bits.
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
- (const_int 1)
- (minus:SI (const_int 7)
- (and:SI
- (match_operand:SI 1 "register_operand" "d")
- (const_int 7)))))]
+ [(set
+ (cc0)
+ (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
+ (const_int 1)
+ (minus:SI (const_int 7)
+ (and:SI
+ (match_operand:SI 1 "register_operand" "d")
+ (const_int 7))))
+ (const_int 0)))]
""
{
return output_btst (operands, operands[1], operands[0], insn, 7);
})
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
- (const_int 1)
- (minus:SI (const_int 31)
- (and:SI
- (match_operand:SI 1 "register_operand" "d")
- (const_int 31)))))]
+ [(set
+ (cc0)
+ (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
+ (const_int 1)
+ (minus:SI (const_int 31)
+ (and:SI
+ (match_operand:SI 1 "register_operand" "d")
+ (const_int 31))))
+ (const_int 0)))]
""
{
return output_btst (operands, operands[1], operands[0], insn, 31);
;; Nonoffsettable mem refs are ok in this one pattern
;; since we don't try to adjust them.
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
- (const_int 1)
- (match_operand:SI 1 "const_int_operand" "n")))]
+ [(set
+ (cc0)
+ (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
+ (const_int 1)
+ (match_operand:SI 1 "const_int_operand" "n"))
+ (const_int 0)))]
"(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE"
{
operands[1] = GEN_INT (7 - INTVAL (operands[1]));
})
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
- (const_int 1)
- (match_operand:SI 1 "const_int_operand" "n")))]
+ [(set
+ (cc0)
+ (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "do")
+ (const_int 1)
+ (match_operand:SI 1 "const_int_operand" "n"))
+ (const_int 0)))]
"!TARGET_COLDFIRE"
{
if (GET_CODE (operands[0]) == MEM)
;; The 'o' has been replaced with 'Q'.
(define_insn ""
- [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
- (const_int 1)
- (match_operand:SI 1 "const_int_operand" "n")))]
+ [(set
+ (cc0)
+ (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "dQ")
+ (const_int 1)
+ (match_operand:SI 1 "const_int_operand" "n"))
+ (const_int 0)))]
"TARGET_COLDFIRE"
{
if (GET_CODE (operands[0]) == MEM)
;; A special case in which it is not desirable
;; to reload the constant into a data register.
(define_insn "pushexthisi_const"
- [(set (match_operand:SI 0 "push_operand" "=m")
- (match_operand:SI 1 "const_int_operand" "J"))]
+ [(set (match_operand:SI 0 "push_operand" "=m,m,m")
+ (match_operand:SI 1 "const_int_operand" "C0,R,J"))]
"INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
-{
- if (operands[1] == const0_rtx)
- return "clr%.l %0";
- if (valid_mov3q_const (INTVAL (operands[1])))
- return "mov3q%.l %1,%-";
- return "pea %a1";
-})
+ "@
+ clr%.l %0
+ mov3q%.l %1,%-
+ pea %a1"
+ [(set_attr "type" "clr_l,mov3q_l,pea")])
;This is never used.
;(define_insn "swapsi"
; ""
; "exg %1,%0")
-;; Special case of fullword move when source is zero.
-;; The reason this is special is to avoid loading a zero
-;; into a data reg with moveq in order to store it elsewhere.
-
-(define_insn "movsi_const0"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
+;; Special case of fullword move when source is zero for 68000_10.
+;; moveq is faster on the 68000.
+(define_insn "*movsi_const0_68000_10"
+ [(set (match_operand:SI 0 "movsi_const0_operand" "=d,a,g")
+ (const_int 0))]
+ "TUNE_68000_10"
+ "@
+ moveq #0,%0
+ sub%.l %0,%0
+ clr%.l %0"
+ [(set_attr "type" "moveq_l,alu_l,clr_l")
+ (set_attr "opy" "*,0,*")])
+
+;; Special case of fullword move when source is zero for 68040_60.
+;; On the '040, 'subl an,an' takes 2 clocks while lea takes only 1
+(define_insn "*movsi_const0_68040_60"
+ [(set (match_operand:SI 0 "movsi_const0_operand" "=a,g")
(const_int 0))]
- ;; clr insns on 68000 read before writing.
- "((TARGET_68010 || TARGET_COLDFIRE)
- || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
+ "TUNE_68040_60"
{
- if (ADDRESS_REG_P (operands[0]))
+ if (which_alternative == 0)
+ return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0";
+ else if (which_alternative == 1)
+ return "clr%.l %0";
+ else
{
- /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
- if (TUNE_68040_60)
- return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0";
- else
- return "sub%.l %0,%0";
+ gcc_unreachable ();
+ return "";
}
- /* moveq is faster on the 68000. */
- if (DATA_REG_P (operands[0]) && TUNE_68000_10)
- return "moveq #0,%0";
- return "clr%.l %0";
-})
+}
+ [(set_attr "type" "lea,clr_l")])
+
+;; Special case of fullword move when source is zero.
+(define_insn "*movsi_const0"
+ [(set (match_operand:SI 0 "movsi_const0_operand" "=a,g")
+ (const_int 0))]
+ "!(TUNE_68000_10 || TUNE_68040_60)"
+ "@
+ sub%.l %0,%0
+ clr%.l %0"
+ [(set_attr "type" "alu_l,clr_l")
+ (set_attr "opy" "0,*")])
;; General case of fullword move.
;;
;; In both the PIC and non-PIC cases the patterns generated will
;; matched by the next define_insn.
(define_expand "movsi"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (match_operand:SI 1 "general_operand" ""))]
+ [(set (match_operand:SI 0 "" "")
+ (match_operand:SI 1 "" ""))]
""
{
- if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
+ rtx tmp, base, offset;
+
+ /* Recognize the case where operand[1] is a reference to thread-local
+ data and load its address to a register. */
+ if (!TARGET_PCREL && m68k_tls_reference_p (operands[1], false))
+ {
+ rtx tmp = operands[1];
+ rtx addend = NULL;
+
+ if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
+ {
+ addend = XEXP (XEXP (tmp, 0), 1);
+ tmp = XEXP (XEXP (tmp, 0), 0);
+ }
+
+ gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_TLS_MODEL (tmp) != 0);
+
+ tmp = m68k_legitimize_tls_address (tmp);
+
+ if (addend)
+ {
+ if (!REG_P (tmp))
+ {
+ rtx reg;
+
+ reg = gen_reg_rtx (Pmode);
+ emit_move_insn (reg, tmp);
+ tmp = reg;
+ }
+
+ tmp = gen_rtx_PLUS (SImode, tmp, addend);
+ }
+
+ operands[1] = tmp;
+ }
+ else if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
{
/* The source is an address which requires PIC relocation.
Call legitimize_pic_address with the source, mode, and a relocation
operands[0] = gen_rtx_MEM (SImode,
force_reg (SImode, XEXP (operands[0], 0)));
}
+ if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
+ {
+ split_const (operands[1], &base, &offset);
+ if (GET_CODE (base) == SYMBOL_REF
+ && !offset_within_block_p (base, INTVAL (offset)))
+ {
+ tmp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (SImode);
+ emit_move_insn (tmp, base);
+ emit_insn (gen_addsi3 (operands[0], tmp, offset));
+ DONE;
+ }
+ }
})
-;; General case of fullword move. The register constraints
-;; force integer constants in range for a moveq to be reloaded
-;; if they are headed for memory.
-(define_insn ""
+;; General case of fullword move.
+(define_insn "*movsi_m68k"
;; Notes: make sure no alternative allows g vs g.
;; We don't allow f-regs since fixed point cannot go in them.
[(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
- (match_operand:SI 1 "general_src_operand" "daymSKT,n,i"))]
+ (match_operand:SI 1 "general_src_operand" "damSnT,n,i"))]
+ "!TARGET_COLDFIRE && reload_completed"
+{
+ return output_move_simode (operands);
+})
+
+;; Before reload is completed the register constraints
+;; force integer constants in range for a moveq to be reloaded
+;; if they are headed for memory.
+(define_insn "*movsi_m68k2"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
+ (match_operand:SI 1 "general_src_operand" "damSKT,n,i"))]
"!TARGET_COLDFIRE"
{
;; ColdFire move instructions can have at most one operand of mode >= 6.
(define_insn "*movsi_cf"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g,U")
- (match_operand:SI 1 "general_operand" "g,Rr<Q>,U"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d, d, d, d, d, a,Ap, a, r<Q>,g, U")
+ (match_operand:SI 1 "general_operand" " R,CQ,CW,CZ,CS,Ci,J,J Cs,Cs, g, Rr<Q>,U"))]
"TARGET_COLDFIRE"
- "* return output_move_simode (operands);")
+{
+ switch (which_alternative)
+ {
+ case 0:
+ return "mov3q%.l %1,%0";
+
+ case 1:
+ return "moveq %1,%0";
+
+ case 2:
+ {
+ unsigned u = INTVAL (operands[1]);
+
+ operands[1] = GEN_INT ((u << 16) | (u >> 16)); /*|*/
+ return "moveq %1,%0\n\tswap %0";
+ }
+
+ case 3:
+ return "mvz%.w %1,%0";
+
+ case 4:
+ return "mvs%.w %1,%0";
+
+ case 5:
+ return "move%.l %1,%0";
+
+ case 6:
+ return "move%.w %1,%0";
+
+ case 7:
+ return "pea %a1";
+
+ case 8:
+ return "lea %a1,%0";
+
+ case 9:
+ case 10:
+ case 11:
+ return "move%.l %1,%0";
+
+ default:
+ gcc_unreachable ();
+ return "";
+ }
+}
+ [(set_attr "type" "mov3q_l,moveq_l,*,mvsz,mvsz,move_l,move,pea,lea,move_l,move_l,move_l")])
;; Special case of fullword move, where we need to get a non-GOT PIC
;; reference into an address register.
"!TARGET_COLDFIRE"
"* return output_move_strictqi (operands);")
-(define_insn ""
- [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d,m"))
- (match_operand:QI 1 "general_src_operand" "dmn,d"))]
+(define_insn "*movstrictqi_cf"
+ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d, Ac, d,m"))
+ (match_operand:QI 1 "general_src_operand" "C0,C0, dmn,d"))]
"TARGET_COLDFIRE"
- "* return output_move_strictqi (operands);")
+ "@
+ clr%.b %0
+ clr%.b %0
+ move%.b %1,%0
+ move%.b %1,%0"
+ [(set_attr "type" "clr,clr,move,move")])
(define_expand "pushqi1"
[(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2)))
})
(define_insn "movsf_cf_soft"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g")
- (match_operand:SF 1 "general_operand" "g,r"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>,g,U")
+ (match_operand:SF 1 "general_operand" "g,r<Q>,U"))]
"TARGET_COLDFIRE && !TARGET_COLDFIRE_FPU"
-{
- return "move%.l %1,%0";
-})
+ "move%.l %1,%0"
+ [(set_attr "type" "move_l")])
+;; SFmode MEMs are restricted to modes 2-4 if TARGET_COLDFIRE_FPU.
+;; The move instructions can handle all combinations.
(define_insn "movsf_cf_hard"
[(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>U, f, f,mr,f,r<Q>,f
,m")
return output_move_double (operands);
})
-(define_insn "movdf_cf_soft"
+(define_insn_and_split "movdf_cf_soft"
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,g")
(match_operand:DF 1 "general_operand" "g,r"))]
"TARGET_COLDFIRE && !TARGET_COLDFIRE_FPU"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
{
- return output_move_double (operands);
+ m68k_emit_move_double (operands);
+ DONE;
})
(define_insn "movdf_cf_hard"
[(set (match_operand:SI 0 "push_operand" "=m")
(match_operand:SI 1 "address_operand" "p"))]
""
- "pea %a1")
+ "pea %a1"
+ [(set_attr "type" "pea")])
\f
;; truncation instructions
(define_insn "truncsiqi2"
(define_insn "*zero_extendhisi2_cf"
[(set (match_operand:SI 0 "register_operand" "=d")
(zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
- "TARGET_ISAB"
- "mvz%.w %1,%0")
+ "ISA_HAS_MVS_MVZ"
+ "mvz%.w %1,%0"
+ [(set_attr "type" "mvsz")])
(define_insn "zero_extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=d")
(define_insn "*zero_extendqisi2_cfv4"
[(set (match_operand:SI 0 "register_operand" "=d")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
- "TARGET_ISAB"
- "mvz%.b %1,%0")
+ "ISA_HAS_MVS_MVZ"
+ "mvz%.b %1,%0"
+ [(set_attr "type" "mvsz")])
(define_insn "zero_extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=d")
(define_split
[(set (match_operand 0 "register_operand" "")
(zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
- "!TARGET_ISAB
+ "!ISA_HAS_MVS_MVZ
&& reload_completed
&& reg_mentioned_p (operands[0], operands[1])"
[(set (strict_low_part (match_dup 2))
(define_split
[(set (match_operand 0 "register_operand" "")
(zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
- "!TARGET_ISAB && reload_completed"
+ "!ISA_HAS_MVS_MVZ && reload_completed"
[(set (match_dup 0)
(const_int 0))
(set (strict_low_part (match_dup 2))
{
CC_STATUS_INIT;
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- if (TARGET_ISAB)
+ if (ISA_HAS_MVS_MVZ)
return "mvs%.b %1,%2\;smi %0\;extb%.l %0";
if (TARGET_68020 || TARGET_COLDFIRE)
{
{
CC_STATUS_INIT;
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- if (TARGET_ISAB)
+ if (ISA_HAS_MVS_MVZ)
return "mvs%.w %1,%2\;smi %0\;extb%.l %0";
if (TARGET_68020 || TARGET_COLDFIRE)
return "move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0";
})
(define_insn "extendsidi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o,o,<")
(sign_extend:DI
- (match_operand:SI 1 "general_operand" "rm")))]
+ (match_operand:SI 1 "nonimmediate_src_operand" "rm,rm,r<Q>,rm")))
+ (clobber (match_scratch:SI 2 "=X,d,d,d"))]
""
{
CC_STATUS_INIT;
- operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
+
+ if (which_alternative == 0)
+ /* Handle alternative 0. */
+ {
+ if (TARGET_68020 || TARGET_COLDFIRE)
+ return "move%.l %1,%R0\;smi %0\;extb%.l %0";
+ else
+ return "move%.l %1,%R0\;smi %0\;ext%.w %0\;ext%.l %0";
+ }
+
+ /* Handle alternatives 1, 2 and 3. We don't need to adjust address by 4
+ in alternative 3 because autodecrement will do that for us. */
+ operands[3] = adjust_address (operands[0], SImode,
+ which_alternative == 3 ? 0 : 4);
+ operands[0] = adjust_address (operands[0], SImode, 0);
+
if (TARGET_68020 || TARGET_COLDFIRE)
- return "move%.l %1,%2\;smi %0\;extb%.l %0";
+ return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0";
else
- return "move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0";
-})
+ return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0";
+}
+ [(set_attr "ok_for_coldfire" "yes,no,yes,yes")])
;; Special case when one can avoid register clobbering, copy and test
;; Maybe there is a way to make that the general case, by forcing the
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extend:SI
(match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
- "TARGET_ISAB"
- "mvs%.w %1,%0")
+ "ISA_HAS_MVS_MVZ"
+ "mvs%.w %1,%0"
+ [(set_attr "type" "mvsz")])
(define_insn "*68k_extendhisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
(sign_extend:SI
(match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
- "!TARGET_ISAB"
-{
- if (ADDRESS_REG_P (operands[0]))
- return "move%.w %1,%0";
- return "ext%.l %0";
-})
+ "!ISA_HAS_MVS_MVZ"
+ "@
+ ext%.l %0
+ move%.w %1,%0"
+ [(set_attr "type" "ext,move")])
(define_insn "extendqihi2"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d")
(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
""
- "ext%.w %0")
+ "ext%.w %0"
+ [(set_attr "type" "ext")])
(define_expand "extendqisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(define_insn "*cfv4_extendqisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))]
- "TARGET_ISAB"
- "mvs%.b %1,%0")
+ "ISA_HAS_MVS_MVZ"
+ "mvs%.b %1,%0"
+ [(set_attr "type" "mvsz")])
(define_insn "*68k_extendqisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
- "TARGET_68020 || (TARGET_COLDFIRE && !TARGET_ISAB)"
- "extb%.l %0")
+ "TARGET_68020 || (TARGET_COLDFIRE && !ISA_HAS_MVS_MVZ)"
+ "extb%.l %0"
+ [(set_attr "type" "ext")])
\f
;; Conversions between float and double.
"TARGET_COLDFIRE_FPU"
"@
fsmove%.d %1,%0
- fmove%.s %1,%0")
+ fmove%.s %1,%0"
+ [(set_attr "type" "fmove")])
-(define_insn ""
+(define_insn "*truncdfsf2_68881"
[(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
(float_truncate:SF
(match_operand:DF 1 "general_operand" "f")))]
"TARGET_68881"
- "fmove%.s %f1,%0")
+ "fmove%.s %f1,%0"
+ [(set_attr "type" "fmove")])
\f
;; Conversion between fixed point and floating point.
;; Note that among the fix-to-float insns
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(float:FP (match_operand:SI 1 "general_operand" "dmi")))]
"TARGET_68881"
- "f<FP:round>move%.l %1,%0")
+ "f<FP:round>move%.l %1,%0"
+ [(set_attr "type" "fmove")])
(define_insn "floatsi<mode>2_cf"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(float:FP (match_operand:SI 1 "general_operand" "d<Q>U")))]
"TARGET_COLDFIRE_FPU"
- "f<FP:prec>move%.l %1,%0")
+ "f<FP:prec>move%.l %1,%0"
+ [(set_attr "type" "fmove")])
(define_expand "floathi<mode>2"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(float:FP (match_operand:HI 1 "general_operand" "dmn")))]
"TARGET_68881"
- "fmove%.w %1,%0")
+ "fmove%.w %1,%0"
+ [(set_attr "type" "fmove")])
(define_insn "floathi<mode>2_cf"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(float:FP (match_operand:HI 1 "general_operand" "d<Q>U")))]
"TARGET_COLDFIRE_FPU"
- "fmove%.w %1,%0")
+ "fmove%.w %1,%0"
+ [(set_attr "type" "fmove")])
(define_expand "floatqi<mode>2"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(float:FP (match_operand:QI 1 "general_operand" "dmn")))]
"TARGET_68881"
- "fmove%.b %1,%0")
+ "fmove%.b %1,%0"
+ [(set_attr "type" "fmove")])
(define_insn "floatqi<mode>2_cf"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(float:FP (match_operand:QI 1 "general_operand" "d<Q>U")))]
"TARGET_COLDFIRE_FPU"
- "fmove%.b %1,%0")
+ "fmove%.b %1,%0"
+ [(set_attr "type" "fmove")])
;; New routines to convert floating-point values to integers
if (FP_REG_P (operands[1]))
return "fintrz%.x %f1,%0";
return "fintrz%.<FP:prec> %f1,%0";
-})
+}
+ [(set_attr "type" "falu")])
(define_insn "ftrunc<mode>2_cf"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
if (FP_REG_P (operands[1]))
return "fintrz%.d %f1,%0";
return "fintrz%.<FP:prec> %f1,%0";
-})
+}
+ [(set_attr "type" "falu")])
;; Convert a float whose value is an integer
;; to an actual integer. Second stage of converting float to integer type.
[(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
(fix:QI (match_operand:FP 1 "general_operand" "f")))]
"TARGET_68881"
- "fmove%.b %1,%0")
+ "fmove%.b %1,%0"
+ [(set_attr "type" "fmove")])
(define_insn "fix<mode>qi2_cf"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>U")
(fix:QI (match_operand:FP 1 "general_operand" "f")))]
"TARGET_COLDFIRE_FPU"
- "fmove%.b %1,%0")
+ "fmove%.b %1,%0"
+ [(set_attr "type" "fmove")])
(define_expand "fix<mode>hi2"
[(set (match_operand:HI 0 "nonimmediate_operand" "")
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
(fix:HI (match_operand:FP 1 "general_operand" "f")))]
"TARGET_68881"
- "fmove%.w %1,%0")
+ "fmove%.w %1,%0"
+ [(set_attr "type" "fmove")])
(define_insn "fix<mode>hi2_cf"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d<Q>U")
(fix:HI (match_operand:FP 1 "general_operand" "f")))]
"TARGET_COLDFIRE_FPU"
- "fmove%.w %1,%0")
+ "fmove%.w %1,%0"
+ [(set_attr "type" "fmove")])
(define_expand "fix<mode>si2"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
[(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
(fix:SI (match_operand:FP 1 "general_operand" "f")))]
"TARGET_68881"
- "fmove%.l %1,%0")
+ "fmove%.l %1,%0"
+ [(set_attr "type" "fmove")])
(define_insn "fix<mode>si2_cf"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d<Q>U")
(fix:SI (match_operand:FP 1 "general_operand" "f")))]
"TARGET_COLDFIRE_FPU"
- "fmove%.l %1,%0")
+ "fmove%.l %1,%0"
+ [(set_attr "type" "fmove")])
\f
;; add instructions
return "move%.w %1,%3\;ext%.l %3\;add%.l %3,%0";
})
-(define_insn "adddi_dilshr32"
+(define_insn "*adddi_dilshr32"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,o")
-;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
-;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
-;; (const_int 32))))]
- (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,d")
- (const_int 32))
- (match_operand:DI 2 "general_operand" "0,0")))]
- ""
+ (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,d")
+ (const_int 32))
+ (match_operand:DI 2 "general_operand" "0,0")))]
+ "!TARGET_COLDFIRE"
{
CC_STATUS_INIT;
if (GET_CODE (operands[0]) == REG)
return "add%.l %1,%2\;negx%.l %0\;neg%.l %0";
})
+(define_insn "*adddi_dilshr32_cf"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (plus:DI (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "ro")
+ (const_int 32))
+ (match_operand:DI 2 "register_operand" "0")))]
+ "TARGET_COLDFIRE"
+{
+ CC_STATUS_INIT;
+ return "add%.l %1,%R0\;negx%.l %0\;neg%.l %0";
+})
+
(define_insn "adddi_dishl32"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
else
operands[1] = adjust_address (operands[1], SImode, 4);
return "add%.l %1,%0";
-})
+}
+ [(set_attr "type" "alu_l")])
(define_insn "adddi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
- (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
- (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
- (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d")
+ (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0")
+ (match_operand:DI 2 "general_operand" "d,no>,d,a")))
+ (clobber (match_scratch:SI 3 "=&d,&d,X,&d"))]
""
{
if (DATA_REG_P (operands[0]))
else
{
gcc_assert (GET_CODE (operands[0]) == MEM);
- if (GET_CODE (operands[2]) == MEM
- && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
- return "add%.l %2,%0\;addx%.l %2,%0";
CC_STATUS_INIT;
if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
{
})
(define_insn "addsi_lshrsi_31"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
- (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,dm,d<Q>")
+ (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm,r<Q>,rm")
(const_int 31))
(match_dup 1)))]
""
operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
}
output_asm_insn ("move%.l %1,%0", operands);
- output_asm_insn (MOTOROLA ? "jbpl %l3" : "jpl %l3", operands);
+ output_asm_insn ("jpl %l3", operands);
output_asm_insn ("addq%.l #1,%2", operands);
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (operands[3]));
return "";
-})
+}
+ [(set_attr "ok_for_coldfire" "no,yes,yes")])
(define_expand "addsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
"! TARGET_COLDFIRE"
"* return output_addsi3 (operands);")
-(define_insn "*addsi3_5200"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,r")
- (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
- (match_operand:SI 2 "general_src_operand" "dIL,rJK,a,mrIKLi")))]
+(define_insn_and_split "*addsi3_5200"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mr,mr,a, m,r, ?a, ?a,?a,?a")
+ (plus:SI (match_operand:SI 1 "general_operand" "%0, 0, 0, 0,0, a, a, r, a")
+ (match_operand:SI 2 "general_src_operand" " I, L, JCu,d,mrKi,Cj, r, a, JCu")))]
"TARGET_COLDFIRE"
- "* return output_addsi3 (operands);")
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
- (plus:SI (match_operand:SI 1 "general_operand" "0")
- (sign_extend:SI
- (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
- "!TARGET_COLDFIRE"
- "add%.w %2,%0")
-
-(define_insn "addhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
- (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
- (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
- "!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ switch (which_alternative)
{
- /* If the constant would be a negative number when interpreted as
- HImode, make it negative. This is usually, but not always, done
- elsewhere in the compiler. First check for constants out of range,
+ case 0:
+ return "addq%.l %2,%0";
+
+ case 1:
+ operands[2] = GEN_INT (- INTVAL (operands[2]));
+ return "subq%.l %2,%0";
+
+ case 3:
+ case 4:
+ return "add%.l %2,%0";
+
+ case 5:
+ /* move%.l %2,%0\n\tadd%.l %1,%0 */
+ return "#";
+
+ case 6:
+ return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
+
+ case 7:
+ return MOTOROLA ? "lea (%2,%1.l),%0" : "lea %2@(0,%1:l),%0";
+
+ case 2:
+ case 8:
+ return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
+
+ default:
+ gcc_unreachable ();
+ return "";
+ }
+}
+ "&& reload_completed && (extract_constrain_insn_cached (insn), which_alternative == 5) && !operands_match_p (operands[0], operands[1])"
+ [(set (match_dup 0)
+ (match_dup 2))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_dup 1)))]
+ ""
+ [(set_attr "type" "aluq_l,aluq_l,lea, alu_l,alu_l,*,lea, lea, lea")
+ (set_attr "opy" "2, 2, *, 2, 2, *,*, *, *")
+ (set_attr "opy_type" "*, *, mem5,*, *, *,mem6,mem6,mem5")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
+ (plus:SI (match_operand:SI 1 "general_operand" "0")
+ (sign_extend:SI
+ (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
+ "!TARGET_COLDFIRE"
+ "add%.w %2,%0")
+
+(define_insn "addhi3"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
+ (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
+ (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
+ "!TARGET_COLDFIRE"
+{
+ if (GET_CODE (operands[2]) == CONST_INT)
+ {
+ /* If the constant would be a negative number when interpreted as
+ HImode, make it negative. This is usually, but not always, done
+ elsewhere in the compiler. First check for constants out of range,
which could confuse us. */
if (INTVAL (operands[2]) >= 32768)
(plus:FP (float:FP (match_operand:SI 2 "general_operand" "dmi"))
(match_operand:FP 1 "general_operand" "0")))]
"TARGET_68881"
- "f<FP:round>add%.l %2,%0")
+ "f<FP:round>add%.l %2,%0"
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
(define_insn "add<mode>3_floathi_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(plus:FP (float:FP (match_operand:HI 2 "general_operand" "dmn"))
(match_operand:FP 1 "general_operand" "0")))]
"TARGET_68881"
- "f<FP:round>add%.w %2,%0")
+ "f<FP:round>add%.w %2,%0"
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
(define_insn "add<mode>3_floatqi_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(plus:FP (float:FP (match_operand:QI 2 "general_operand" "dmn"))
(match_operand:FP 1 "general_operand" "0")))]
"TARGET_68881"
- "f<FP:round>add%.b %2,%0")
+ "f<FP:round>add%.b %2,%0"
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
(define_insn "add<mode>3_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
if (FP_REG_P (operands[2]))
return "f<FP:round>add%.x %2,%0";
return "f<FP:round>add%.<FP:prec> %f2,%0";
-})
+}
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
(define_insn "add<mode>3_cf"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
if (FP_REG_P (operands[2]))
return "f<FP:prec>add%.d %2,%0";
return "f<FP:prec>add%.<FP:prec> %2,%0";
-})
+}
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
\f
;; subtract instructions
else
operands[1] = adjust_address (operands[1], SImode, 4);
return "sub%.l %1,%0";
-})
+}
+ [(set_attr "type" "alu_l")])
(define_insn "subdi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
- (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
- (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
- (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d")
+ (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
+ (match_operand:DI 2 "general_operand" "d,no>,d,a")))
+ (clobber (match_scratch:SI 3 "=&d,&d,X,&d"))]
""
{
if (DATA_REG_P (operands[0]))
else
{
gcc_assert (GET_CODE (operands[0]) == MEM);
- if (GET_CODE (operands[2]) == MEM
- && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
- return "sub%.l %2,%0\;subx%.l %2,%0";
CC_STATUS_INIT;
if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
{
})
(define_insn "subsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d,a")
- (minus:SI (match_operand:SI 1 "general_operand" "0,0,0")
- (match_operand:SI 2 "general_src_operand" "dT,mSrT,mSrs")))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=mda,m,d,a")
+ (minus:SI (match_operand:SI 1 "general_operand" "0,0,0,0")
+ (match_operand:SI 2 "general_src_operand" "I,dT,mSrT,mSrs")))]
""
- "sub%.l %2,%0")
+ "@
+ subq%.l %2, %0
+ sub%.l %2,%0
+ sub%.l %2,%0
+ sub%.l %2,%0"
+ [(set_attr "type" "aluq_l,alu_l,alu_l,alu_l")
+ (set_attr "opy" "2")])
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=a")
(minus:FP (match_operand:FP 1 "general_operand" "0")
(float:FP (match_operand:SI 2 "general_operand" "dmi"))))]
"TARGET_68881"
- "f<FP:round>sub%.l %2,%0")
+ "f<FP:round>sub%.l %2,%0"
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
(define_insn "sub<mode>3_floathi_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(minus:FP (match_operand:FP 1 "general_operand" "0")
(float:FP (match_operand:HI 2 "general_operand" "dmn"))))]
"TARGET_68881"
- "f<FP:round>sub%.w %2,%0")
+ "f<FP:round>sub%.w %2,%0"
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
(define_insn "sub<mode>3_floatqi_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(minus:FP (match_operand:FP 1 "general_operand" "0")
(float:FP (match_operand:QI 2 "general_operand" "dmn"))))]
"TARGET_68881"
- "f<FP:round>sub%.b %2,%0")
+ "f<FP:round>sub%.b %2,%0"
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
(define_insn "sub<mode>3_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
if (FP_REG_P (operands[2]))
return "f<FP:round>sub%.x %2,%0";
return "f<FP:round>sub%.<FP:prec> %f2,%0";
-})
+}
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
(define_insn "sub<mode>3_cf"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
if (FP_REG_P (operands[2]))
return "f<FP:prec>sub%.d %2,%0";
return "f<FP:prec>sub%.<FP:prec> %2,%0";
-})
+}
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
\f
;; multiply instructions
""
{
return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
-})
+}
+ [(set_attr "type" "mul_w")
+ (set_attr "opy" "2")])
(define_insn "mulhisi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
""
{
return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
-})
+}
+ [(set_attr "type" "mul_w")
+ (set_attr "opy" "2")])
-(define_insn ""
+(define_insn "*mulhisisi3_s"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(mult:SI (sign_extend:SI
(match_operand:HI 1 "nonimmediate_operand" "%0"))
"INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
{
return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
-})
+}
+ [(set_attr "type" "mul_w")
+ (set_attr "opy" "2")])
(define_expand "mulsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
"TARGET_68020 || TARGET_COLDFIRE"
"")
-(define_insn ""
+(define_insn "*mulsi3_68020"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(mult:SI (match_operand:SI 1 "general_operand" "%0")
(match_operand:SI 2 "general_src_operand" "dmSTK")))]
"TARGET_68020"
- "muls%.l %2,%0")
+ "muls%.l %2,%0"
+ [(set_attr "type" "mul_l")
+ (set_attr "opy" "2")])
-(define_insn ""
+(define_insn "*mulsi3_cf"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(mult:SI (match_operand:SI 1 "general_operand" "%0")
(match_operand:SI 2 "general_operand" "d<Q>")))]
"TARGET_COLDFIRE"
- "muls%.l %2,%0")
+ "muls%.l %2,%0"
+ [(set_attr "type" "mul_l")
+ (set_attr "opy" "2")])
(define_insn "umulhisi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
""
{
return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
-})
+}
+ [(set_attr "type" "mul_w")
+ (set_attr "opy" "2")])
-(define_insn ""
+(define_insn "*mulhisisi3_z"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(mult:SI (zero_extend:SI
(match_operand:HI 1 "nonimmediate_operand" "%0"))
"INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
{
return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
-})
+}
+ [(set_attr "type" "mul_w")
+ (set_attr "opy" "2")])
;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
;; proper matching constraint. This is because the matching is between
return TARGET_68040
? "f<FP:round>mul%.l %2,%0"
: "f<FP:round_mul>mul%.l %2,%0";
-})
+}
+ [(set_attr "type" "fmul")
+ (set_attr "opy" "2")])
(define_insn "mul<mode>3_floathi_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
return TARGET_68040
? "f<FP:round>mul%.w %2,%0"
: "f<FP:round_mul>mul%.w %2,%0";
-})
+}
+ [(set_attr "type" "fmul")
+ (set_attr "opy" "2")])
(define_insn "mul<mode>3_floatqi_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
return TARGET_68040
? "f<FP:round>mul%.b %2,%0"
: "f<FP:round_mul>mul%.b %2,%0";
-})
+}
+ [(set_attr "type" "fmul")
+ (set_attr "opy" "2")])
(define_insn "muldf_68881"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
if (FP_REG_P (operands[2]))
return "f<FP:prec>mul%.d %2,%0";
return "f<FP:prec>mul%.<FP:prec> %2,%0";
-})
+}
+ [(set_attr "type" "fmul")
+ (set_attr "opy" "2")])
\f
;; divide instructions
if (FP_REG_P (operands[2]))
return "f<FP:prec>div%.d %2,%0";
return "f<FP:prec>div%.<FP:prec> %2,%0";
-})
+}
+ [(set_attr "type" "fdiv")
+ (set_attr "opy" "2")])
\f
;; Remainder instructions.
return "rems%.l %2,%3:%0";
else
return "rems%.l %2,%3:%0\;divs%.l %2,%0";
-})
+}
+ [(set_attr "type" "div_l")
+ (set_attr "opy" "2")])
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
return "remu%.l %2,%3:%0";
else
return "remu%.l %2,%3:%0\;divu%.l %2,%0";
-})
+}
+ [(set_attr "type" "div_l")
+ (set_attr "opy" "2")])
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(umod:HI (match_dup 1) (match_dup 2)))]
"!TARGET_COLDFIRE || TARGET_CF_HWDIV"
{
- if (TARGET_ISAB)
+ if (ISA_HAS_MVS_MVZ)
output_asm_insn (MOTOROLA ?
"mvz%.w %0,%0\;divu%.w %2,%0" :
"mvz%.w %0,%0\;divu %2,%0",
(match_operand:SI 2 "general_src_operand" "d,dmsK")))]
"TARGET_COLDFIRE"
{
- if (TARGET_ISAB
+ if (ISA_HAS_MVS_MVZ
&& DATA_REG_P (operands[0])
&& GET_CODE (operands[2]) == CONST_INT)
{
[(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
(neg:SI (match_operand:SI 1 "general_operand" "0")))]
"!TARGET_COLDFIRE"
- "neg%.l %0")
+ "neg%.l %0"
+ [(set_attr "type" "neg_l")])
(define_insn "negsi2_5200"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(neg:SI (match_operand:SI 1 "general_operand" "0")))]
"TARGET_COLDFIRE"
- "neg%.l %0")
+ "neg%.l %0"
+ [(set_attr "type" "neg_l")])
(define_insn "neghi2"
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
insns = get_insns ();
end_sequence ();
- emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
+ emit_insn (insns);
DONE;
}
})
insns = get_insns ();
end_sequence ();
- emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
+ emit_insn (insns);
DONE;
}
})
if (FP_REG_P (operands[1]))
return "f<FP:round>sqrt%.x %1,%0";
return "f<FP:round>sqrt%.<FP:prec> %1,%0";
-})
+}
+ [(set_attr "type" "fsqrt")])
(define_insn "sqrt<mode>2_cf"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
if (FP_REG_P (operands[1]))
return "f<FP:prec>sqrt%.d %1,%0";
return "f<FP:prec>sqrt%.<FP:prec> %1,%0";
-})
+}
+ [(set_attr "type" "fsqrt")])
;; Absolute value instructions
;; If using software floating point, just zero the sign bit.
insns = get_insns ();
end_sequence ();
- emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
+ emit_insn (insns);
DONE;
}
})
insns = get_insns ();
end_sequence ();
- emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
+ emit_insn (insns);
DONE;
}
})
if (FP_REG_P (operands[1]))
return "f<FP:prec>abs%.d %1,%0";
return "f<FP:prec>abs%.<FP:prec> %1,%0";
-})
+}
+ [(set_attr "type" "bitrw,fneg")])
\f
;; bit indexing instructions
(define_insn "clzsi2"
[(set (match_operand:SI 0 "register_operand" "=d")
(clz:SI (match_operand:SI 1 "register_operand" "0")))]
- "TARGET_ISAAPLUS || TARGET_ISAC"
- "ff1 %0")
+ "ISA_HAS_FF1"
+ "ff1 %0"
+ [(set_attr "type" "ext")])
\f
;; one complement instructions
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(not:SI (match_operand:SI 1 "general_operand" "0")))]
"TARGET_COLDFIRE"
- "not%.l %0")
+ "not%.l %0"
+ [(set_attr "type" "neg_l")])
(define_insn "one_cmplhi2"
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
return "move%.w %1,%0\;sub%.l %R0,%R0";
})
-(define_insn "ashldi_const32"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
- (ashift:DI (match_operand:DI 1 "general_operand" "ro")
- (const_int 32)))]
+(define_insn "*ashldi3_const1"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (ashift:DI (match_operand:DI 1 "register_operand" "0")
+ (const_int 1)))]
+ "!TARGET_COLDFIRE"
+ "add%.l %R0,%R0\;addx%.l %0,%0")
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ashift:DI (match_operand:DI 1 "register_operand" "")
+ (const_int 2)))]
+ "reload_completed && !TARGET_COLDFIRE"
+ [(set (match_dup 0)
+ (ashift:DI (match_dup 1) (const_int 1)))
+ (set (match_dup 0)
+ (ashift:DI (match_dup 0) (const_int 1)))]
+ "")
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ashift:DI (match_operand:DI 1 "register_operand" "")
+ (const_int 3)))]
+ "reload_completed && !TARGET_COLDFIRE"
+ [(set (match_dup 0)
+ (ashift:DI (match_dup 1) (const_int 2)))
+ (set (match_dup 0)
+ (ashift:DI (match_dup 0) (const_int 1)))]
+ "")
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ashift:DI (match_operand:DI 1 "register_operand" "")
+ (const_int 8)))]
+ "reload_completed && !TARGET_COLDFIRE"
+ [(set (match_dup 2)
+ (rotate:SI (match_dup 2) (const_int 8)))
+ (set (match_dup 3)
+ (rotate:SI (match_dup 3) (const_int 8)))
+ (set (strict_low_part (subreg:QI (match_dup 0) 3))
+ (subreg:QI (match_dup 0) 7))
+ (set (strict_low_part (subreg:QI (match_dup 0) 7))
+ (const_int 0))]
+{
+ operands[2] = gen_highpart (SImode, operands[0]);
+ operands[3] = gen_lowpart (SImode, operands[0]);
+})
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ashift:DI (match_operand:DI 1 "register_operand" "")
+ (const_int 16)))]
+ "reload_completed && !TARGET_COLDFIRE"
+ [(set (match_dup 2)
+ (rotate:SI (match_dup 2) (const_int 16)))
+ (set (match_dup 3)
+ (rotate:SI (match_dup 3) (const_int 16)))
+ (set (strict_low_part (subreg:HI (match_dup 0) 2))
+ (subreg:HI (match_dup 0) 6))
+ (set (strict_low_part (subreg:HI (match_dup 0) 6))
+ (const_int 0))]
+{
+ operands[2] = gen_highpart (SImode, operands[0]);
+ operands[3] = gen_lowpart (SImode, operands[0]);
+})
+
+(define_split
+ [(set (match_operand:DI 0 "pre_dec_operand" "")
+ (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "")
+ (const_int 32)))]
+ "reload_completed"
+ [(set (match_dup 0) (const_int 0))
+ (set (match_dup 0) (match_dup 1))]
+{
+ operands[0] = adjust_address(operands[0], SImode, 0);
+ operands[1] = gen_lowpart(SImode, operands[1]);
+})
+
+(define_split
+ [(set (match_operand:DI 0 "post_inc_operand" "")
+ (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "")
+ (const_int 32)))]
+ "reload_completed"
+ [(set (match_dup 0) (match_dup 1))
+ (set (match_dup 0) (const_int 0))]
+{
+ operands[0] = adjust_address(operands[0], SImode, 0);
+ operands[1] = gen_lowpart(SImode, operands[1]);
+})
+
+(define_insn_and_split "*ashldi3_const32"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=ro<>")
+ (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "ro")
+ (const_int 32)))]
""
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 4) (match_dup 3))
+ (set (match_dup 2) (const_int 0))]
+ "split_di(operands, 2, operands + 2, operands + 4);")
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ashift:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand 2 "const_int_operand" "")))]
+ "reload_completed && !TARGET_COLDFIRE
+ && INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 40"
+ [(set (match_dup 4) (ashift:SI (match_dup 4) (match_dup 2)))
+ (set (match_dup 3) (match_dup 4))
+ (set (match_dup 4) (const_int 0))]
+{
+ operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
+ operands[3] = gen_highpart (SImode, operands[0]);
+ operands[4] = gen_lowpart (SImode, operands[0]);
+})
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ashift:DI (match_operand:DI 1 "register_operand" "")
+ (const_int 48)))]
+ "reload_completed && !TARGET_COLDFIRE"
+ [(set (match_dup 2) (match_dup 3))
+ (set (match_dup 2)
+ (rotate:SI (match_dup 2) (const_int 16)))
+ (set (match_dup 3) (const_int 0))
+ (set (strict_low_part (subreg:HI (match_dup 0) 2))
+ (const_int 0))]
{
- CC_STATUS_INIT;
- if (GET_CODE (operands[1]) == REG)
- operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
- else
- operands[3] = adjust_address (operands[1], SImode, 4);
- if (GET_CODE (operands[0]) == REG)
- operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
- return "clr%.l %0\;move%.l %3,%0";
- else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
- return "move%.l %3,%0\;clr%.l %0";
- else
- operands[2] = adjust_address (operands[0], SImode, 4);
- if (ADDRESS_REG_P (operands[2]))
- return "move%.l %3,%0\;sub%.l %2,%2";
- else
- return "move%.l %3,%0\;clr%.l %2";
+ operands[2] = gen_highpart (SImode, operands[0]);
+ operands[3] = gen_lowpart (SImode, operands[0]);
})
-;; The predicate below must be general_operand, because ashldi3 allows that
-(define_insn "ashldi_const"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
- (ashift:DI (match_operand:DI 1 "general_operand" "0")
- (match_operand 2 "const_int_operand" "n")))]
- "(!TARGET_COLDFIRE
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ashift:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand 2 "const_int_operand" "")))]
+ "reload_completed && !TARGET_COLDFIRE
+ && INTVAL (operands[2]) > 40 && INTVAL (operands[2]) <= 63"
+ [(set (match_dup 3) (match_dup 2))
+ (set (match_dup 4) (ashift:SI (match_dup 4) (match_dup 3)))
+ (set (match_dup 3) (match_dup 4))
+ (set (match_dup 4) (const_int 0))]
+{
+ operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
+ operands[3] = gen_highpart (SImode, operands[0]);
+ operands[4] = gen_lowpart (SImode, operands[0]);
+})
+
+(define_insn "*ashldi3"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (ashift:DI (match_operand:DI 1 "register_operand" "0")
+ (match_operand 2 "const_int_operand" "n")))]
+ "!TARGET_COLDFIRE
&& ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
|| INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
- || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
-{
- operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- if (INTVAL (operands[2]) == 1)
- return "add%.l %1,%1\;addx%.l %0,%0";
- else if (INTVAL (operands[2]) == 8)
- return "rol%.l #8,%1\;rol%.l #8,%0\;move%.b %1,%0\;clr%.b %1";
- else if (INTVAL (operands[2]) == 16)
- return "swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1";
- else if (INTVAL (operands[2]) == 48)
- return "mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0";
- else if (INTVAL (operands[2]) == 2)
- return "add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0";
- else if (INTVAL (operands[2]) == 3)
- return "add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0";
- else /* 32 < INTVAL (operands[2]) <= 63 */
- {
- operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
- output_asm_insn (INTVAL (operands[2]) <= 8 ? "asl%.l %2,%1" :
- "moveq %2,%0\;asl%.l %0,%1", operands);
- return "mov%.l %1,%0\;moveq #0,%1";
- }
-})
+ || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
+ "#")
(define_expand "ashldi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (ashift:DI (match_operand:DI 1 "general_operand" "")
- (match_operand 2 "const_int_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ashift:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand 2 "const_int_operand" "")))]
"!TARGET_COLDFIRE"
- "
{
/* ??? This is a named pattern like this is not allowed to FAIL based
on its operands. */
&& INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
&& (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
FAIL;
-} ")
+})
;; On most 68k models, this makes faster code in a special case.
if (GET_CODE (operands[1]) != REG)
operands[1] = adjust_address (operands[1], HImode, 2);
return "move%.w %1,%0";
-})
+}
+ [(set_attr "type" "move")])
(define_insn "subregsi1ashrdi_const32"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
""
{
return "move%.l %1,%0";
+}
+ [(set_attr "type" "move_l")])
+
+(define_insn "*ashrdi3_const1"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
+ (const_int 1)))]
+ "!TARGET_COLDFIRE"
+{
+ operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
+ return "asr%.l #1,%0\;roxr%.l #1,%1";
+})
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
+ (const_int 2)))]
+ "reload_completed && !TARGET_COLDFIRE"
+ [(set (match_dup 0)
+ (ashiftrt:DI (match_dup 1) (const_int 1)))
+ (set (match_dup 0)
+ (ashiftrt:DI (match_dup 0) (const_int 1)))]
+ "")
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
+ (const_int 3)))]
+ "reload_completed && !TARGET_COLDFIRE"
+ [(set (match_dup 0)
+ (ashiftrt:DI (match_dup 1) (const_int 2)))
+ (set (match_dup 0)
+ (ashiftrt:DI (match_dup 0) (const_int 1)))]
+ "")
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
+ (const_int 8)))]
+ "reload_completed && !TARGET_COLDFIRE"
+ [(set (strict_low_part (subreg:QI (match_dup 0) 7))
+ (subreg:QI (match_dup 0) 3))
+ (set (match_dup 2)
+ (ashiftrt:SI (match_dup 2) (const_int 8)))
+ (set (match_dup 3)
+ (rotatert:SI (match_dup 3) (const_int 8)))]
+{
+ operands[2] = gen_highpart (SImode, operands[0]);
+ operands[3] = gen_lowpart (SImode, operands[0]);
+})
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
+ (const_int 16)))]
+ "reload_completed && !TARGET_COLDFIRE"
+ [(set (strict_low_part (subreg:HI (match_dup 0) 6))
+ (subreg:HI (match_dup 0) 2))
+ (set (match_dup 2)
+ (rotate:SI (match_dup 2) (const_int 16)))
+ (set (match_dup 3)
+ (rotate:SI (match_dup 3) (const_int 16)))
+ (set (match_dup 2)
+ (sign_extend:SI (subreg:HI (match_dup 2) 2)))]
+{
+ operands[2] = gen_highpart (SImode, operands[0]);
+ operands[3] = gen_lowpart (SImode, operands[0]);
+})
+
+(define_insn "*ashrdi_const32"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (ashiftrt:DI (match_operand:DI 1 "nonimmediate_src_operand" "ro")
+ (const_int 32)))]
+ ""
+{
+ CC_STATUS_INIT;
+ if (TARGET_68020)
+ return "move%.l %1,%R0\;smi %0\;extb%.l %0";
+ else
+ return "move%.l %1,%R0\;smi %0\;ext%.w %0\;ext%.l %0";
})
-(define_insn "ashrdi_const32"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o,<")
- (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
+(define_insn "*ashrdi_const32_mem"
+ [(set (match_operand:DI 0 "memory_operand" "=o,<")
+ (ashiftrt:DI (match_operand:DI 1 "nonimmediate_src_operand" "ro,ro")
(const_int 32)))
- (clobber (match_scratch:SI 2 "=X,d,d"))]
+ (clobber (match_scratch:SI 2 "=d,d"))]
""
{
CC_STATUS_INIT;
- if (which_alternative == 0)
- {
- operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- if (TARGET_68020)
- return "move%.l %1,%2\;smi %0\;extb%.l %0";
- else
- return "move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0";
- }
+ operands[3] = adjust_address (operands[0], SImode,
+ which_alternative == 0 ? 4 : 0);
+ operands[0] = adjust_address (operands[0], SImode, 0);
+ if (TARGET_68020 || TARGET_COLDFIRE)
+ return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0";
else
- {
- if (which_alternative == 2)
- operands[3] = operands[0];
- else if (which_alternative == 1)
- operands[3] = adjust_address (operands[0], SImode, 4);
- if (TARGET_68020)
- return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0";
- else
- return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0";
- }
+ return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0";
})
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
+ (const_int 63)))]
+ "reload_completed && !TARGET_COLDFIRE"
+ [(set (match_dup 3)
+ (ashiftrt:SI (match_dup 3) (const_int 31)))
+ (set (match_dup 2)
+ (match_dup 3))]
+ "split_di(operands, 1, operands + 2, operands + 3);")
+
;; The predicate below must be general_operand, because ashrdi3 allows that
(define_insn "ashrdi_const"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
- (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
- (match_operand 2 "const_int_operand" "n")))
- (clobber (match_scratch:SI 3 "=X"))]
- "(!TARGET_COLDFIRE
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
+ (match_operand 2 "const_int_operand" "n")))]
+ "!TARGET_COLDFIRE
&& ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
|| INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
|| INTVAL (operands[2]) == 31
- || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
+ || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
{
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- if (INTVAL (operands[2]) == 63)
- return "add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1";
CC_STATUS_INIT;
- if (INTVAL (operands[2]) == 1)
- return "asr%.l #1,%0\;roxr%.l #1,%1";
- else if (INTVAL (operands[2]) == 8)
- return "move%.b %0,%1\;asr%.l #8,%0\;ror%.l #8,%1";
- else if (INTVAL (operands[2]) == 16)
- return "move%.w %0,%1\;swap %0\;ext%.l %0\;swap %1";
- else if (INTVAL (operands[2]) == 48)
+ if (INTVAL (operands[2]) == 48)
return "swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0";
- else if (INTVAL (operands[2]) == 31)
+ if (INTVAL (operands[2]) == 31)
return "add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0";
- else if (INTVAL (operands[2]) == 2)
- return "asr%.l #1,%0\;roxr%.l #1,%1\;asr%.l #1,%0\;roxr%.l #1,%1";
- else if (INTVAL (operands[2]) == 3)
- return "asr%.l #1,%0\;roxr%.l #1,%1\;asr%.l #1,%0\;roxr%.l #1,%1\;asr%.l #1,%0\;roxr%.l #1,%1";
- else /* 32 < INTVAL (operands[2]) <= 63 */
+ if (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)
{
operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
output_asm_insn (INTVAL (operands[2]) <= 8 ? "asr%.l %2,%0" :
return INTVAL (operands[2]) >= 15 ? "ext%.w %d0" :
TARGET_68020 ? "extb%.l %0" : "ext%.w %0\;ext%.l %0";
}
+ return "#";
})
(define_expand "ashrdi3"
- [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
- (match_operand 2 "const_int_operand" "")))
- (clobber (match_scratch:SI 3 ""))])]
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand 2 "const_int_operand" "")))]
"!TARGET_COLDFIRE"
- "
{
/* ??? This is a named pattern like this is not allowed to FAIL based
on its operands. */
&& INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
&& (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
FAIL;
- operands[3] = gen_rtx_SCRATCH (SImode);
-} ")
+})
;; On all 68k models, this makes faster code in a special case.
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "general_operand" "dI")))]
""
- "asr%.l %2,%0")
+ "asr%.l %2,%0"
+ [(set_attr "type" "shift")
+ (set_attr "opy" "2")])
(define_insn "ashrhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
(const_int 32)) 4))]
""
+ "move%.l %1,%0"
+ [(set_attr "type" "move_l")])
+
+(define_insn "*lshrdi3_const1"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
+ (const_int 1)))]
+ "!TARGET_COLDFIRE"
+ "lsr%.l #1,%0\;roxr%.l #1,%R0")
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
+ (const_int 2)))]
+ "reload_completed && !TARGET_COLDFIRE"
+ [(set (match_dup 0)
+ (lshiftrt:DI (match_dup 1) (const_int 1)))
+ (set (match_dup 0)
+ (lshiftrt:DI (match_dup 0) (const_int 1)))]
+ "")
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
+ (const_int 3)))]
+ "reload_completed && !TARGET_COLDFIRE"
+ [(set (match_dup 0)
+ (lshiftrt:DI (match_dup 1) (const_int 2)))
+ (set (match_dup 0)
+ (lshiftrt:DI (match_dup 0) (const_int 1)))]
+ "")
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
+ (const_int 8)))]
+ "reload_completed && !TARGET_COLDFIRE"
+ [(set (strict_low_part (subreg:QI (match_dup 0) 7))
+ (subreg:QI (match_dup 0) 3))
+ (set (match_dup 2)
+ (lshiftrt:SI (match_dup 2) (const_int 8)))
+ (set (match_dup 3)
+ (rotatert:SI (match_dup 3) (const_int 8)))]
{
- return "move%.l %1,%0";
+ operands[2] = gen_highpart (SImode, operands[0]);
+ operands[3] = gen_lowpart (SImode, operands[0]);
})
-(define_insn "lshrdi_const32"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=ro,<,>")
- (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
- (const_int 32)))]
- ""
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
+ (const_int 16)))]
+ "reload_completed && !TARGET_COLDFIRE"
+ [(set (strict_low_part (subreg:HI (match_dup 0) 6))
+ (subreg:HI (match_dup 0) 2))
+ (set (strict_low_part (subreg:HI (match_dup 0) 2))
+ (const_int 0))
+ (set (match_dup 3)
+ (rotate:SI (match_dup 3) (const_int 16)))
+ (set (match_dup 2)
+ (rotate:SI (match_dup 2) (const_int 16)))]
{
- CC_STATUS_INIT;
- if (which_alternative == 1)
- return "move%.l %1,%0\;clr%.l %0";
- if (which_alternative == 2)
- return "clr%.l %0\;move%.l %1,%0";
- if (GET_CODE (operands[0]) == REG)
- operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- else
- operands[2] = adjust_address (operands[0], SImode, 4);
- if (GET_CODE (operands[1]) == REG)
- operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
- else
- operands[3] = adjust_address (operands[1], SImode, 4);
- if (ADDRESS_REG_P (operands[0]))
- return "move%.l %1,%2\;sub%.l %0,%0";
- else
- return "move%.l %1,%2\;clr%.l %0";
+ operands[2] = gen_highpart (SImode, operands[0]);
+ operands[3] = gen_lowpart (SImode, operands[0]);
})
-;; The predicate below must be general_operand, because lshrdi3 allows that
-(define_insn "lshrdi_const"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
+(define_split
+ [(set (match_operand:DI 0 "pre_dec_operand" "")
+ (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
+ (const_int 32)))]
+ "reload_completed"
+ [(set (match_dup 0) (match_dup 1))
+ (set (match_dup 0) (const_int 0))]
+{
+ operands[0] = adjust_address(operands[0], SImode, 0);
+ operands[1] = gen_highpart(SImode, operands[1]);
+})
+
+(define_split
+ [(set (match_operand:DI 0 "post_inc_operand" "")
+ (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
+ (const_int 32)))]
+ "reload_completed"
+ [(set (match_dup 0) (const_int 0))
+ (set (match_dup 0) (match_dup 1))]
+{
+ operands[0] = adjust_address(operands[0], SImode, 0);
+ operands[1] = gen_highpart(SImode, operands[1]);
+})
+
+(define_split
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
+ (const_int 32)))]
+ "reload_completed"
+ [(set (match_dup 2) (match_dup 5))
+ (set (match_dup 4) (const_int 0))]
+ "split_di(operands, 2, operands + 2, operands + 4);")
+
+(define_insn "*lshrdi_const32"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=ro<>")
+ (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
+ (const_int 32)))]
+ ""
+ "#")
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand 2 "const_int_operand" "")))]
+ "reload_completed && !TARGET_COLDFIRE
+ && INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 40"
+ [(set (match_dup 3) (lshiftrt:SI (match_dup 3) (match_dup 2)))
+ (set (match_dup 4) (match_dup 3))
+ (set (match_dup 3) (const_int 0))]
+{
+ operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
+ operands[3] = gen_highpart (SImode, operands[0]);
+ operands[4] = gen_lowpart (SImode, operands[0]);
+})
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
+ (const_int 48)))]
+ "reload_completed"
+ [(set (match_dup 3) (match_dup 2))
+ (set (strict_low_part (subreg:HI (match_dup 0) 6))
+ (const_int 0))
+ (set (match_dup 2) (const_int 0))
+ (set (match_dup 3)
+ (rotate:SI (match_dup 3) (const_int 16)))]
+{
+ operands[2] = gen_highpart (SImode, operands[0]);
+ operands[3] = gen_lowpart (SImode, operands[0]);
+})
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand 2 "const_int_operand" "")))]
+ "reload_completed && !TARGET_COLDFIRE
+ && INTVAL (operands[2]) > 40 && INTVAL (operands[2]) <= 62"
+ [(set (match_dup 4) (match_dup 2))
+ (set (match_dup 3) (lshiftrt:SI (match_dup 3) (match_dup 4)))
+ (set (match_dup 4) (match_dup 3))
+ (set (match_dup 3) (const_int 0))]
+{
+ operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
+ operands[3] = gen_highpart (SImode, operands[0]);
+ operands[4] = gen_lowpart (SImode, operands[0]);
+})
+
+(define_insn "*lshrdi_const63"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
+ (const_int 63)))]
+ ""
+ "add%.l %0,%0\;clr%.l %0\;clr%.l %R1\;addx%.l %R1,%R1")
+
+(define_insn "*lshrdi3_const"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand 2 "const_int_operand" "n")))]
"(!TARGET_COLDFIRE
- && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
+ && ((INTVAL (operands[2]) >= 2 && INTVAL (operands[2]) <= 3)
|| INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
|| (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
-{
- operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- if (INTVAL (operands[2]) == 63)
- return "add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1";
- CC_STATUS_INIT;
- if (INTVAL (operands[2]) == 1)
- return "lsr%.l #1,%0\;roxr%.l #1,%1";
- else if (INTVAL (operands[2]) == 8)
- return "move%.b %0,%1\;lsr%.l #8,%0\;ror%.l #8,%1";
- else if (INTVAL (operands[2]) == 16)
- return "move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0";
- else if (INTVAL (operands[2]) == 48)
- return "move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1";
- else if (INTVAL (operands[2]) == 2)
- return "lsr%.l #1,%0\;roxr%.l #1,%1\;lsr%.l #1,%0\;roxr%.l #1,%1";
- else if (INTVAL (operands[2]) == 3)
- return "lsr%.l #1,%0\;roxr%.l #1,%1\;lsr%.l #1,%0\;roxr%.l #1,%1\;lsr%.l #1,%0\;roxr%.l #1,%1";
- else /* 32 < INTVAL (operands[2]) <= 63 */
- {
- operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
- output_asm_insn (INTVAL (operands[2]) <= 8 ? "lsr%.l %2,%0" :
- "moveq %2,%1\;lsr%.l %1,%0", operands);
- return "mov%.l %0,%1\;moveq #0,%0";
- }
-})
+ "#")
(define_expand "lshrdi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
+ [(set (match_operand:DI 0 "register_operand" "")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")))]
"!TARGET_COLDFIRE"
{
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "general_operand" "dI")))]
""
- "lsr%.l %2,%0")
+ "lsr%.l %2,%0"
+ [(set_attr "type" "shift")
+ (set_attr "opy" "2")])
(define_insn "lshrhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
{
CC_STATUS_INIT;
return "bset %1,%0";
-})
+}
+ [(set_attr "type" "bitrw")])
;; set bit, bit number is (sign/zero)_extended from HImode/QImode
-(define_insn ""
+(define_insn "*bsetmemqi_ext"
[(set (match_operand:QI 0 "memory_operand" "+m")
(ior:QI (subreg:QI (ashift:SI (const_int 1)
(match_operator:SI 2 "extend_operator"
{
CC_STATUS_INIT;
return "bset %1,%0";
-})
+}
+ [(set_attr "type" "bitrw")])
;; clear bit, bit number is int
(define_insn "bclrmemqi"
{
CC_STATUS_INIT;
return "bclr %1,%0";
-})
+}
+ [(set_attr "type" "bitrw")])
;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
-(define_insn ""
+(define_insn "*bclrmemqi_ext"
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
(const_int 1)
(minus:SI (const_int 7)
{
CC_STATUS_INIT;
return "bclr %1,%0";
-})
+}
+ [(set_attr "type" "bitrw")])
;; Special cases of bit-field insns which we should
;; recognize in preference to the general case.
;; so that its address is reloaded.
(define_expand "extv"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
+ [(set (match_operand:SI 0 "register_operand" "")
(sign_extract:SI (match_operand:SI 1 "general_operand" "")
- (match_operand:SI 2 "general_operand" "")
- (match_operand:SI 3 "general_operand" "")))]
+ (match_operand:SI 2 "const_int_operand" "")
+ (match_operand:SI 3 "const_int_operand" "")))]
"TARGET_68020 && TARGET_BITFIELD"
"")
(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
+ [(set (match_operand:SI 0 "register_operand" "=d")
(sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
- (match_operand:SI 2 "general_operand" "dn")
- (match_operand:SI 3 "general_operand" "dn")))]
+ (match_operand:SI 2 "nonmemory_operand" "dn")
+ (match_operand:SI 3 "nonmemory_operand" "dn")))]
"TARGET_68020 && TARGET_BITFIELD"
"bfexts %1{%b3:%b2},%0")
(define_expand "extzv"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
+ [(set (match_operand:SI 0 "register_operand" "")
(zero_extract:SI (match_operand:SI 1 "general_operand" "")
- (match_operand:SI 2 "general_operand" "")
- (match_operand:SI 3 "general_operand" "")))]
+ (match_operand:SI 2 "const_int_operand" "")
+ (match_operand:SI 3 "const_int_operand" "")))]
"TARGET_68020 && TARGET_BITFIELD"
"")
(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d")
- (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
- (match_operand:SI 2 "general_operand" "dn,dn")
- (match_operand:SI 3 "general_operand" "dn,dn")))]
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
+ (match_operand:SI 2 "nonmemory_operand" "dn")
+ (match_operand:SI 3 "nonmemory_operand" "dn")))]
"TARGET_68020 && TARGET_BITFIELD"
{
if (GET_CODE (operands[2]) == CONST_INT)
(define_insn ""
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
- (match_operand:SI 1 "general_operand" "dn")
- (match_operand:SI 2 "general_operand" "dn"))
+ (match_operand:SI 1 "nonmemory_operand" "dn")
+ (match_operand:SI 2 "nonmemory_operand" "dn"))
(xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
(match_operand 3 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD
(define_insn ""
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
- (match_operand:SI 1 "general_operand" "dn")
- (match_operand:SI 2 "general_operand" "dn"))
+ (match_operand:SI 1 "nonmemory_operand" "dn")
+ (match_operand:SI 2 "nonmemory_operand" "dn"))
(const_int 0))]
"TARGET_68020 && TARGET_BITFIELD"
{
(define_expand "insv"
[(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "")
- (match_operand:SI 1 "general_operand" "")
- (match_operand:SI 2 "general_operand" ""))
+ (match_operand:SI 1 "const_int_operand" "")
+ (match_operand:SI 2 "const_int_operand" ""))
(match_operand:SI 3 "register_operand" ""))]
"TARGET_68020 && TARGET_BITFIELD"
"")
(define_insn ""
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
- (match_operand:SI 1 "general_operand" "dn")
- (match_operand:SI 2 "general_operand" "dn"))
+ (match_operand:SI 1 "nonmemory_operand" "dn")
+ (match_operand:SI 2 "nonmemory_operand" "dn"))
(match_operand:SI 3 "register_operand" "d"))]
"TARGET_68020 && TARGET_BITFIELD"
"bfins %3,%0{%b2:%b1}")
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extract:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "general_operand" "dn")
- (match_operand:SI 3 "general_operand" "dn")))]
+ (match_operand:SI 2 "const_int_operand" "n")
+ (match_operand:SI 3 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD"
"bfexts %1{%b3:%b2},%0")
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(zero_extract:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "general_operand" "dn")
- (match_operand:SI 3 "general_operand" "dn")))]
+ (match_operand:SI 2 "const_int_operand" "n")
+ (match_operand:SI 3 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD"
{
if (GET_CODE (operands[2]) == CONST_INT)
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
- (match_operand:SI 1 "general_operand" "dn")
- (match_operand:SI 2 "general_operand" "dn"))
+ (match_operand:SI 1 "const_int_operand" "n")
+ (match_operand:SI 2 "const_int_operand" "n"))
(const_int 0))]
"TARGET_68020 && TARGET_BITFIELD"
{
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
- (match_operand:SI 1 "general_operand" "dn")
- (match_operand:SI 2 "general_operand" "dn"))
+ (match_operand:SI 1 "const_int_operand" "n")
+ (match_operand:SI 2 "const_int_operand" "n"))
(const_int -1))]
"TARGET_68020 && TARGET_BITFIELD"
{
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
- (match_operand:SI 1 "general_operand" "dn")
- (match_operand:SI 2 "general_operand" "dn"))
+ (match_operand:SI 1 "const_int_operand" "n")
+ (match_operand:SI 2 "const_int_operand" "n"))
(match_operand:SI 3 "register_operand" "d"))]
"TARGET_68020 && TARGET_BITFIELD"
{
(define_insn ""
[(set (cc0)
- (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
- (match_operand:SI 1 "const_int_operand" "n")
- (match_operand:SI 2 "general_operand" "dn")))]
+ (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
+ (match_operand:SI 1 "const_int_operand" "n")
+ (match_operand:SI 2 "general_operand" "dn"))
+ (const_int 0)))]
"TARGET_68020 && TARGET_BITFIELD"
{
if (operands[1] == const1_rtx
;;; now handle the register cases
(define_insn ""
[(set (cc0)
- (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
- (match_operand:SI 1 "const_int_operand" "n")
- (match_operand:SI 2 "general_operand" "dn")))]
+ (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
+ (match_operand:SI 1 "const_int_operand" "n")
+ (match_operand:SI 2 "general_operand" "dn"))
+ (const_int 0)))]
"TARGET_68020 && TARGET_BITFIELD"
{
if (operands[1] == const1_rtx
\f
(define_insn "scc0_di"
[(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
- (match_operator 1 "valid_dbcc_comparison_p"
+ (match_operator 1 "ordered_comparison_operator"
[(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
"! TARGET_COLDFIRE"
{
(define_insn "scc0_di_5200"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d")
- (match_operator 1 "valid_dbcc_comparison_p"
+ (match_operator 1 "ordered_comparison_operator"
[(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
"TARGET_COLDFIRE"
{
(define_insn "scc_di"
[(set (match_operand:QI 0 "nonimmediate_operand" "=dm,dm")
- (match_operator 1 "valid_dbcc_comparison_p"
+ (match_operator 1 "ordered_comparison_operator"
[(match_operand:DI 2 "general_operand" "ro,r")
(match_operand:DI 3 "general_operand" "r,ro")]))]
"! TARGET_COLDFIRE"
(define_insn "scc_di_5200"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d")
- (match_operator 1 "valid_dbcc_comparison_p"
+ (match_operator 1 "ordered_comparison_operator"
[(match_operand:DI 2 "general_operand" "ro,r")
(match_operand:DI 3 "general_operand" "r,ro")]))]
"TARGET_COLDFIRE"
;; memory, but we cannot allow it to be in memory in case the address
;; needs to be reloaded.
-(define_expand "seq"
- [(set (match_operand:QI 0 "register_operand" "")
- (eq:QI (cc0) (const_int 0)))]
- ""
-{
- if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
- && m68k_last_compare_had_fp_operands)
- {
- m68k_last_compare_had_fp_operands = 0;
- FAIL;
- }
-})
-
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=d")
(eq:QI (cc0) (const_int 0)))]
OUTPUT_JUMP ("seq %0", "fseq %0", "seq %0");
})
-(define_expand "sne"
- [(set (match_operand:QI 0 "register_operand" "")
- (ne:QI (cc0) (const_int 0)))]
- ""
-{
- if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
- && m68k_last_compare_had_fp_operands)
- {
- m68k_last_compare_had_fp_operands = 0;
- FAIL;
- }
-})
-
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=d")
(ne:QI (cc0) (const_int 0)))]
OUTPUT_JUMP ("sne %0", "fsne %0", "sne %0");
})
-(define_expand "sgt"
- [(set (match_operand:QI 0 "register_operand" "")
- (gt:QI (cc0) (const_int 0)))]
- ""
-{
- if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
- && m68k_last_compare_had_fp_operands)
- {
- m68k_last_compare_had_fp_operands = 0;
- FAIL;
- }
-})
-
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=d")
(gt:QI (cc0) (const_int 0)))]
OUTPUT_JUMP ("sgt %0", "fsgt %0", 0);
})
-(define_expand "sgtu"
- [(set (match_operand:QI 0 "register_operand" "")
- (gtu:QI (cc0) (const_int 0)))]
- ""
- "")
-
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=d")
(gtu:QI (cc0) (const_int 0)))]
return "shi %0";
})
-(define_expand "slt"
- [(set (match_operand:QI 0 "register_operand" "")
- (lt:QI (cc0) (const_int 0)))]
- ""
-{
- if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
- && m68k_last_compare_had_fp_operands)
- {
- m68k_last_compare_had_fp_operands = 0;
- FAIL;
- }
-})
-
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=d")
(lt:QI (cc0) (const_int 0)))]
OUTPUT_JUMP ("slt %0", "fslt %0", "smi %0");
})
-(define_expand "sltu"
- [(set (match_operand:QI 0 "register_operand" "")
- (ltu:QI (cc0) (const_int 0)))]
- ""
- "")
-
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=d")
(ltu:QI (cc0) (const_int 0)))]
return "scs %0";
})
-(define_expand "sge"
- [(set (match_operand:QI 0 "register_operand" "")
- (ge:QI (cc0) (const_int 0)))]
- ""
-{
- if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
- && m68k_last_compare_had_fp_operands)
- {
- m68k_last_compare_had_fp_operands = 0;
- FAIL;
- }
-})
-
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=d")
(ge:QI (cc0) (const_int 0)))]
OUTPUT_JUMP ("sge %0", "fsge %0", "spl %0");
})
-(define_expand "sgeu"
- [(set (match_operand:QI 0 "register_operand" "")
- (geu:QI (cc0) (const_int 0)))]
- ""
- "")
-
-(define_insn ""
+(define_insn "*scc"
[(set (match_operand:QI 0 "register_operand" "=d")
(geu:QI (cc0) (const_int 0)))]
""
{
cc_status = cc_prev_status;
return "scc %0";
-})
-
-(define_expand "sle"
- [(set (match_operand:QI 0 "register_operand" "")
- (le:QI (cc0) (const_int 0)))]
- ""
-{
- if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
- && m68k_last_compare_had_fp_operands)
- {
- m68k_last_compare_had_fp_operands = 0;
- FAIL;
- }
-})
+}
+ [(set_attr "type" "scc")])
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=d")
OUTPUT_JUMP ("sle %0", "fsle %0", 0);
})
-(define_expand "sleu"
- [(set (match_operand:QI 0 "register_operand" "")
- (leu:QI (cc0) (const_int 0)))]
- ""
- "")
-
-(define_insn ""
+(define_insn "*sls"
[(set (match_operand:QI 0 "register_operand" "=d")
(leu:QI (cc0) (const_int 0)))]
""
{
cc_status = cc_prev_status;
return "sls %0";
-})
-
-(define_expand "sordered"
- [(set (match_operand:QI 0 "register_operand" "")
- (ordered:QI (cc0) (const_int 0)))]
- "TARGET_68881 && !TUNE_68060"
-{
- gcc_assert (m68k_last_compare_had_fp_operands);
- m68k_last_compare_had_fp_operands = 0;
-})
+}
+ [(set_attr "type" "scc")])
(define_insn "*sordered_1"
[(set (match_operand:QI 0 "register_operand" "=d")
return "fsor %0";
})
-(define_expand "sunordered"
- [(set (match_operand:QI 0 "register_operand" "")
- (unordered:QI (cc0) (const_int 0)))]
- "TARGET_68881 && !TUNE_68060"
-{
- gcc_assert (m68k_last_compare_had_fp_operands);
- m68k_last_compare_had_fp_operands = 0;
-})
-
(define_insn "*sunordered_1"
[(set (match_operand:QI 0 "register_operand" "=d")
(unordered:QI (cc0) (const_int 0)))]
return "fsun %0";
})
-(define_expand "suneq"
- [(set (match_operand:QI 0 "register_operand" "")
- (uneq:QI (cc0) (const_int 0)))]
- "TARGET_68881 && !TUNE_68060"
-{
- gcc_assert (m68k_last_compare_had_fp_operands);
- m68k_last_compare_had_fp_operands = 0;
-})
-
(define_insn "*suneq_1"
[(set (match_operand:QI 0 "register_operand" "=d")
(uneq:QI (cc0) (const_int 0)))]
return "fsueq %0";
})
-(define_expand "sunge"
- [(set (match_operand:QI 0 "register_operand" "")
- (unge:QI (cc0) (const_int 0)))]
- "TARGET_68881 && !TUNE_68060"
-{
- gcc_assert (m68k_last_compare_had_fp_operands);
- m68k_last_compare_had_fp_operands = 0;
-})
-
(define_insn "*sunge_1"
[(set (match_operand:QI 0 "register_operand" "=d")
(unge:QI (cc0) (const_int 0)))]
return "fsuge %0";
})
-(define_expand "sungt"
- [(set (match_operand:QI 0 "register_operand" "")
- (ungt:QI (cc0) (const_int 0)))]
- "TARGET_68881 && !TUNE_68060"
-{
- gcc_assert (m68k_last_compare_had_fp_operands);
- m68k_last_compare_had_fp_operands = 0;
-})
-
(define_insn "*sungt_1"
[(set (match_operand:QI 0 "register_operand" "=d")
(ungt:QI (cc0) (const_int 0)))]
return "fsugt %0";
})
-(define_expand "sunle"
- [(set (match_operand:QI 0 "register_operand" "")
- (unle:QI (cc0) (const_int 0)))]
- "TARGET_68881 && !TUNE_68060"
-{
- gcc_assert (m68k_last_compare_had_fp_operands);
- m68k_last_compare_had_fp_operands = 0;
-})
-
(define_insn "*sunle_1"
[(set (match_operand:QI 0 "register_operand" "=d")
(unle:QI (cc0) (const_int 0)))]
return "fsule %0";
})
-(define_expand "sunlt"
- [(set (match_operand:QI 0 "register_operand" "")
- (unlt:QI (cc0) (const_int 0)))]
- "TARGET_68881 && !TUNE_68060"
-{
- gcc_assert (m68k_last_compare_had_fp_operands);
- m68k_last_compare_had_fp_operands = 0;
-})
-
(define_insn "*sunlt_1"
[(set (match_operand:QI 0 "register_operand" "=d")
(unlt:QI (cc0) (const_int 0)))]
return "fsult %0";
})
-(define_expand "sltgt"
- [(set (match_operand:QI 0 "register_operand" "")
- (ltgt:QI (cc0) (const_int 0)))]
- "TARGET_68881 && !TUNE_68060"
-{
- gcc_assert (m68k_last_compare_had_fp_operands);
- m68k_last_compare_had_fp_operands = 0;
-})
-
(define_insn "*sltgt_1"
[(set (match_operand:QI 0 "register_operand" "=d")
(ltgt:QI (cc0) (const_int 0)))]
{
CC_STATUS_INIT;
if (which_alternative == 1)
- {
- if (MOTOROLA)
- return "move%.l %0,%2\;or%.l %0,%2\;jbeq %l1";
- else
- return "move%.l %0,%2\;or%.l %0,%2\;jeq %l1";
- }
+ return "move%.l %0,%2\;or%.l %0,%2\;jeq %l1";
if ((cc_prev_status.value1
&& rtx_equal_p (cc_prev_status.value1, operands[0]))
|| (cc_prev_status.value2
&& rtx_equal_p (cc_prev_status.value2, operands[0])))
{
cc_status = cc_prev_status;
- return MOTOROLA ? "jbeq %l1" : "jeq %l1";
+ return "jeq %l1";
}
if (GET_CODE (operands[0]) == REG)
operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
if (reg_overlap_mentioned_p (operands[2], operands[0]))
{
if (reg_overlap_mentioned_p (operands[2], operands[3]))
- {
- if (MOTOROLA)
- return "or%.l %0,%2\;jbeq %l1";
- else
- return "or%.l %0,%2\;jeq %l1";
- }
+ return "or%.l %0,%2\;jeq %l1";
else
- {
- if (MOTOROLA)
- return "or%.l %3,%2\;jbeq %l1";
- else
- return "or%.l %3,%2\;jeq %l1";
- }
+ return "or%.l %3,%2\;jeq %l1";
}
- if (MOTOROLA)
- return "move%.l %0,%2\;or%.l %3,%2\;jbeq %l1";
- else
- return "move%.l %0,%2\;or%.l %3,%2\;jeq %l1";
+ return "move%.l %0,%2\;or%.l %3,%2\;jeq %l1";
}
operands[4] = gen_label_rtx();
if (TARGET_68020 || TARGET_COLDFIRE)
- {
- if (MOTOROLA)
- output_asm_insn ("tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1", operands);
- else
- output_asm_insn ("tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1", operands);
- }
+ output_asm_insn ("tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1", operands);
else
- {
- if (MOTOROLA)
- output_asm_insn ("cmp%.w #0,%0\;jbne %l4\;cmp%.w #0,%3\;jbeq %l1", operands);
- else
- output_asm_insn ("cmp%.w #0,%0\;jne %l4\;cmp%.w #0,%3\;jeq %l1", operands);
- }
+ output_asm_insn ("cmp%.w #0,%0\;jne %l4\;cmp%.w #0,%3\;jeq %l1", operands);
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (operands[4]));
return "";
&& rtx_equal_p (cc_prev_status.value2, operands[0])))
{
cc_status = cc_prev_status;
- return MOTOROLA ? "jbne %l1" : "jne %l1";
+ return "jne %l1";
}
CC_STATUS_INIT;
if (GET_CODE (operands[0]) == REG)
if (reg_overlap_mentioned_p (operands[2], operands[0]))
{
if (reg_overlap_mentioned_p (operands[2], operands[3]))
- {
- if (MOTOROLA)
- return "or%.l %0,%2\;jbne %l1";
- else
- return "or%.l %0,%2\;jne %l1";
- }
+ return "or%.l %0,%2\;jne %l1";
else
- {
- if (MOTOROLA)
- return "or%.l %3,%2\;jbne %l1";
- else
- return "or%.l %3,%2\;jne %l1";
- }
+ return "or%.l %3,%2\;jne %l1";
}
- if (MOTOROLA)
- return "move%.l %0,%2\;or%.l %3,%2\;jbne %l1";
- else
- return "move%.l %0,%2\;or%.l %3,%2\;jne %l1";
+ return "move%.l %0,%2\;or%.l %3,%2\;jne %l1";
}
if (TARGET_68020 || TARGET_COLDFIRE)
- {
- if (MOTOROLA)
- return "tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1";
- else
- return "tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1";
- }
+ return "tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1";
else
- {
- if (MOTOROLA)
- return "cmp%.w #0,%0\;jbne %l1\;cmp%.w #0,%3\;jbne %l1";
- else
- return "cmp%.w #0,%0\;jne %l1\;cmp%.w #0,%3\;jne %l1";
- }
+ return "cmp%.w #0,%0\;jne %l1\;cmp%.w #0,%3\;jne %l1";
})
(define_insn "bge0_di"
&& rtx_equal_p (cc_prev_status.value2, operands[0])))
{
cc_status = cc_prev_status;
- if (cc_status.flags & CC_REVERSED)
- {
- return MOTOROLA ? "jble %l1" : "jle %l1";
- }
- else
- {
- return MOTOROLA ? "jbpl %l1" : "jpl %l1";
- }
+ return cc_status.flags & CC_REVERSED ? "jle %l1" : "jpl %l1";
}
CC_STATUS_INIT;
if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
/* On an address reg, cmpw may replace cmpl. */
output_asm_insn("cmp%.w #0,%0", operands);
}
- return MOTOROLA ? "jbpl %l1" : "jpl %l1";
+ return "jpl %l1";
})
(define_insn "blt0_di"
&& rtx_equal_p (cc_prev_status.value2, operands[0])))
{
cc_status = cc_prev_status;
- if (cc_status.flags & CC_REVERSED)
- {
- return MOTOROLA ? "jbgt %l1" : "jgt %l1";
- }
- else
- {
- return MOTOROLA ? "jbmi %l1" : "jmi %l1";
- }
+ return cc_status.flags & CC_REVERSED ? "jgt %l1" : "jmi %l1";
}
CC_STATUS_INIT;
if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
/* On an address reg, cmpw may replace cmpl. */
output_asm_insn("cmp%.w #0,%0", operands);
}
-
- return MOTOROLA ? "jbmi %l1" : "jmi %l1";
+ return "jmi %l1";
})
(define_insn "beq"
(pc)))]
""
{
- if (MOTOROLA)
- OUTPUT_JUMP ("jbeq %l0", "fbeq %l0", "jbeq %l0");
- else
- OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
-})
+ OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
+}
+ [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
(define_insn "bne"
[(set (pc)
(pc)))]
""
{
- if (MOTOROLA)
- OUTPUT_JUMP ("jbne %l0", "fbne %l0", "jbne %l0");
- else
- OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
-})
+ OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
+}
+ [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
(define_insn "bgt"
[(set (pc)
(pc)))]
""
{
- if (MOTOROLA)
- OUTPUT_JUMP ("jbgt %l0", "fbgt %l0", 0);
- else
- OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0);
-})
+ if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
+ {
+ cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
+ return 0;
+ }
+
+ OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0);
+}
+ [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
(define_insn "bgtu"
[(set (pc)
(pc)))]
""
{
- return MOTOROLA ? "jbhi %l0" : "jhi %l0";
-})
+ if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
+ {
+ cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
+ return 0;
+ }
+
+ return "jhi %l0";
+}
+ [(set_attr "type" "bcc")])
(define_insn "blt"
[(set (pc)
(pc)))]
""
{
- if (MOTOROLA)
- OUTPUT_JUMP ("jblt %l0", "fblt %l0", "jbmi %l0");
- else
- OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0");
-})
+ if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
+ {
+ cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
+ return 0;
+ }
+
+ OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0");
+}
+ [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
(define_insn "bltu"
[(set (pc)
(pc)))]
""
{
- return MOTOROLA ? "jbcs %l0" : "jcs %l0";
-})
+ if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
+ {
+ cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
+ return 0;
+ }
+
+ return "jcs %l0";
+}
+ [(set_attr "type" "bcc")])
(define_insn "bge"
[(set (pc)
(pc)))]
""
{
- if (MOTOROLA)
- OUTPUT_JUMP ("jbge %l0", "fbge %l0", "jbpl %l0");
- else
- OUTPUT_JUMP ("jge %l0", "fjge %l0", "jpl %l0");
+ if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
+ {
+ cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
+ return 0;
+ }
+
+ OUTPUT_JUMP ("jge %l0", "fjge %l0", "jpl %l0");
})
(define_insn "bgeu"
(pc)))]
""
{
- return MOTOROLA ? "jbcc %l0" : "jcc %l0";
-})
+ if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
+ {
+ cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
+ return 0;
+ }
+
+ return "jcc %l0";
+}
+ [(set_attr "type" "bcc")])
(define_insn "ble"
[(set (pc)
(pc)))]
""
{
- if (MOTOROLA)
- OUTPUT_JUMP ("jble %l0", "fble %l0", 0);
- else
- OUTPUT_JUMP ("jle %l0", "fjle %l0", 0);
-})
+ if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
+ {
+ cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
+ return 0;
+ }
+
+ OUTPUT_JUMP ("jle %l0", "fjle %l0", 0);
+}
+ [(set_attr "type" "bcc")])
(define_insn "bleu"
[(set (pc)
(pc)))]
""
{
- return MOTOROLA ? "jbls %l0" : "jls %l0";
-})
+ if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
+ {
+ cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
+ return 0;
+ }
+
+ return "jls %l0";
+}
+ [(set_attr "type" "bcc")])
(define_insn "bordered"
[(set (pc)
"TARGET_HARD_FLOAT"
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return MOTOROLA ? "fbor %l0" : "fjor %l0";
-})
+ return "fjor %l0";
+}
+ [(set_attr "type" "fbcc")])
(define_insn "bunordered"
[(set (pc)
"TARGET_HARD_FLOAT"
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return MOTOROLA ? "fbun %l0" : "fjun %l0";
-})
+ return "fjun %l0";
+}
+ [(set_attr "type" "fbcc")])
(define_insn "buneq"
[(set (pc)
"TARGET_HARD_FLOAT"
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return MOTOROLA ? "fbueq %l0" : "fjueq %l0";
-})
+ return "fjueq %l0";
+}
+ [(set_attr "type" "fbcc")])
(define_insn "bunge"
[(set (pc)
"TARGET_HARD_FLOAT"
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return MOTOROLA ? "fbuge %l0" : "fjuge %l0";
-})
+ return "fjuge %l0";
+}
+ [(set_attr "type" "fbcc")])
(define_insn "bungt"
[(set (pc)
"TARGET_HARD_FLOAT"
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return MOTOROLA ? "fbugt %l0" : "fjugt %l0";
-})
+ return "fjugt %l0";
+}
+ [(set_attr "type" "fbcc")])
(define_insn "bunle"
[(set (pc)
"TARGET_HARD_FLOAT"
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return MOTOROLA ? "fbule %l0" : "fjule %l0";
-})
+ return "fjule %l0";
+}
+ [(set_attr "type" "fbcc")])
(define_insn "bunlt"
[(set (pc)
"TARGET_HARD_FLOAT"
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return MOTOROLA ? "fbult %l0" : "fjult %l0";
-})
+ return "fjult %l0";
+}
+ [(set_attr "type" "fbcc")])
(define_insn "bltgt"
[(set (pc)
"TARGET_HARD_FLOAT"
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return MOTOROLA ? "fbogl %l0" : "fjogl %l0";
-})
+ return "fjogl %l0";
+}
+ [(set_attr "type" "fbcc")])
\f
;; Negated conditional jump instructions.
-(define_insn ""
+(define_insn "*beq_rev"
[(set (pc)
(if_then_else (eq (cc0)
(const_int 0))
(label_ref (match_operand 0 "" ""))))]
""
{
- if (MOTOROLA)
- OUTPUT_JUMP ("jbne %l0", "fbne %l0", "jbne %l0");
- else
- OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
-})
+ OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
+}
+ [(set_attr "type" "bcc")])
-(define_insn ""
+(define_insn "*bne_rev"
[(set (pc)
(if_then_else (ne (cc0)
(const_int 0))
(label_ref (match_operand 0 "" ""))))]
""
{
- if (MOTOROLA)
- OUTPUT_JUMP ("jbeq %l0", "fbeq %l0", "jbeq %l0");
- else
- OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
-})
+ OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
+}
+ [(set_attr "type" "bcc")])
-(define_insn ""
+(define_insn "*bgt_rev"
[(set (pc)
(if_then_else (gt (cc0)
(const_int 0))
(label_ref (match_operand 0 "" ""))))]
""
{
- if (MOTOROLA)
- OUTPUT_JUMP ("jble %l0", "fbngt %l0", 0);
- else
- OUTPUT_JUMP ("jle %l0", "fjngt %l0", 0);
-})
+ if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
+ {
+ cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
+ return 0;
+ }
-(define_insn ""
+ OUTPUT_JUMP ("jle %l0", "fjngt %l0", 0);
+}
+ [(set_attr "type" "bcc")])
+
+(define_insn "*bgtu_rev"
[(set (pc)
(if_then_else (gtu (cc0)
(const_int 0))
(label_ref (match_operand 0 "" ""))))]
""
{
- return MOTOROLA ? "jbls %l0" : "jls %l0";
-})
+ if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
+ {
+ cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
+ return 0;
+ }
-(define_insn ""
+ return "jls %l0";
+}
+ [(set_attr "type" "bcc")])
+
+(define_insn "*blt_rev"
[(set (pc)
(if_then_else (lt (cc0)
(const_int 0))
(label_ref (match_operand 0 "" ""))))]
""
{
- if (MOTOROLA)
- OUTPUT_JUMP ("jbge %l0", "fbnlt %l0", "jbpl %l0");
- else
- OUTPUT_JUMP ("jge %l0", "fjnlt %l0", "jpl %l0");
-})
+ if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
+ {
+ cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
+ return 0;
+ }
-(define_insn ""
+ OUTPUT_JUMP ("jge %l0", "fjnlt %l0", "jpl %l0");
+}
+ [(set_attr "type" "bcc")])
+
+(define_insn "*bltu_rev"
[(set (pc)
(if_then_else (ltu (cc0)
(const_int 0))
(label_ref (match_operand 0 "" ""))))]
""
{
- return MOTOROLA ? "jbcc %l0" : "jcc %l0";
-})
+ if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
+ {
+ cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
+ return 0;
+ }
-(define_insn ""
+ return "jcc %l0";
+}
+ [(set_attr "type" "bcc")])
+
+(define_insn "*bge_rev"
[(set (pc)
(if_then_else (ge (cc0)
(const_int 0))
(label_ref (match_operand 0 "" ""))))]
""
{
- if (MOTOROLA)
- OUTPUT_JUMP ("jblt %l0", "fbnge %l0", "jbmi %l0");
- else
- OUTPUT_JUMP ("jlt %l0", "fjnge %l0", "jmi %l0");
-})
+ if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
+ {
+ cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
+ return 0;
+ }
-(define_insn ""
+ OUTPUT_JUMP ("jlt %l0", "fjnge %l0", "jmi %l0");
+}
+ [(set_attr "type" "bcc")])
+
+(define_insn "*bgeu_rev"
[(set (pc)
(if_then_else (geu (cc0)
(const_int 0))
(label_ref (match_operand 0 "" ""))))]
""
{
- return MOTOROLA ? "jbcs %l0" : "jcs %l0";
-})
+ if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
+ {
+ cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
+ return 0;
+ }
-(define_insn ""
+ return "jcs %l0";
+}
+ [(set_attr "type" "bcc")])
+
+(define_insn "*ble_rev"
[(set (pc)
(if_then_else (le (cc0)
(const_int 0))
(label_ref (match_operand 0 "" ""))))]
""
{
- if (MOTOROLA)
- OUTPUT_JUMP ("jbgt %l0", "fbnle %l0", 0);
- else
- OUTPUT_JUMP ("jgt %l0", "fjnle %l0", 0);
-})
+ if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
+ {
+ cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
+ return 0;
+ }
-(define_insn ""
+ OUTPUT_JUMP ("jgt %l0", "fjnle %l0", 0);
+}
+ [(set_attr "type" "bcc")])
+
+(define_insn "*bleu_rev"
[(set (pc)
(if_then_else (leu (cc0)
(const_int 0))
(label_ref (match_operand 0 "" ""))))]
""
{
- return MOTOROLA ? "jbhi %l0" : "jhi %l0";
-})
+ if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
+ {
+ cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
+ return 0;
+ }
+
+ return "jhi %l0";
+}
+ [(set_attr "type" "bcc")])
(define_insn "*bordered_rev"
[(set (pc)
"TARGET_HARD_FLOAT"
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return MOTOROLA ? "fbun %l0" : "fjun %l0";
-})
+ return "fjun %l0";
+}
+ [(set_attr "type" "fbcc")])
(define_insn "*bunordered_rev"
[(set (pc)
"TARGET_HARD_FLOAT"
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return MOTOROLA ? "fbor %l0" : "fjor %l0";
-})
+ return "fjor %l0";
+}
+ [(set_attr "type" "fbcc")])
(define_insn "*buneq_rev"
[(set (pc)
"TARGET_HARD_FLOAT"
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return MOTOROLA ? "fbogl %l0" : "fjogl %l0";
-})
+ return "fjogl %l0";
+}
+ [(set_attr "type" "fbcc")])
(define_insn "*bunge_rev"
[(set (pc)
"TARGET_HARD_FLOAT"
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return MOTOROLA ? "fbolt %l0" : "fjolt %l0";
-})
+ return "fjolt %l0";
+}
+ [(set_attr "type" "fbcc")])
(define_insn "*bungt_rev"
[(set (pc)
"TARGET_HARD_FLOAT"
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return MOTOROLA ? "fbole %l0" : "fjole %l0";
-})
+ return "fjole %l0";
+}
+ [(set_attr "type" "fbcc")])
(define_insn "*bunle_rev"
[(set (pc)
"TARGET_HARD_FLOAT"
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return MOTOROLA ? "fbogt %l0" : "fjogt %l0";
-})
+ return "fjogt %l0";
+}
+ [(set_attr "type" "fbcc")])
(define_insn "*bunlt_rev"
[(set (pc)
"TARGET_HARD_FLOAT"
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return MOTOROLA ? "fboge %l0" : "fjoge %l0";
-})
+ return "fjoge %l0";
+}
+ [(set_attr "type" "fbcc")])
(define_insn "*bltgt_rev"
[(set (pc)
"TARGET_HARD_FLOAT"
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return MOTOROLA ? "fbueq %l0" : "fjueq %l0";
-})
+ return "fjueq %l0";
+}
+ [(set_attr "type" "fbcc")])
\f
;; Unconditional and other jump instructions
(define_insn "jump"
[(set (pc)
(label_ref (match_operand 0 "" "")))]
""
-{
- return MOTOROLA ? "jbra %l0" : "jra %l0";
-})
+ "jra %l0"
+ [(set_attr "type" "bra")])
(define_expand "tablejump"
[(parallel [(set (pc) (match_operand 0 "" ""))
})
;; Jump to variable address from dispatch table of absolute addresses.
-(define_insn ""
+(define_insn "*tablejump_internal"
[(set (pc) (match_operand:SI 0 "register_operand" "a"))
(use (label_ref (match_operand 1 "" "")))]
""
{
return MOTOROLA ? "jmp (%0)" : "jmp %0@";
-})
+}
+ [(set_attr "type" "jmp")])
;; Jump to variable address from dispatch table of relative addresses.
(define_insn ""
})
;; Decrement-and-branch insns.
-(define_insn ""
+(define_insn "*dbne_hi"
[(set (pc)
(if_then_else
(ne (match_operand:HI 0 "nonimmediate_operand" "+d*g")
if (DATA_REG_P (operands[0]))
return "dbra %0,%l1";
if (GET_CODE (operands[0]) == MEM)
- return MOTOROLA ?
- "subq%.w #1,%0\;jbcc %l1" :
- "subqw #1,%0\;jcc %l1";
- return MOTOROLA ?
- "subq%.w #1,%0\;cmp%.w #-1,%0\;jbne %l1" :
- "subqw #1,%0\;cmpw #-1,%0\;jne %l1";
+ return "subq%.w #1,%0\;jcc %l1";
+ return "subq%.w #1,%0\;cmp%.w #-1,%0\;jne %l1";
})
-(define_insn ""
+(define_insn "*dbne_si"
[(set (pc)
(if_then_else
(ne (match_operand:SI 0 "nonimmediate_operand" "+d*g")
{
CC_STATUS_INIT;
if (DATA_REG_P (operands[0]))
- return MOTOROLA ?
- "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jbcc %l1" :
- "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1";
+ return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1";
if (GET_CODE (operands[0]) == MEM)
- return MOTOROLA ?
- "subq%.l #1,%0\;jbcc %l1" :
- "subq%.l #1,%0\;jcc %l1";
- return MOTOROLA ?
- "subq.l #1,%0\;cmp.l #-1,%0\;jbne %l1" :
- "subql #1,%0\;cmpl #-1,%0\;jne %l1";
+ return "subq%.l #1,%0\;jcc %l1";
+ return "subq%.l #1,%0\;cmp%.l #-1,%0\;jne %l1";
})
;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
-(define_insn ""
+(define_insn "*dbge_hi"
[(set (pc)
(if_then_else
(ge (plus:HI (match_operand:HI 0 "nonimmediate_operand" "+d*am")
if (DATA_REG_P (operands[0]))
return "dbra %0,%l1";
if (GET_CODE (operands[0]) == MEM)
- return MOTOROLA ?
- "subq%.w #1,%0\;jbcc %l1" :
- "subq%.w #1,%0\;jcc %l1";
- return MOTOROLA ?
- "subq.w #1,%0\;cmp.w #-1,%0\;jbne %l1" :
- "subqw #1,%0\;cmpw #-1,%0\;jne %l1";
+ return "subq%.w #1,%0\;jcc %l1";
+ return "subq%.w #1,%0\;cmp%.w #-1,%0\;jne %l1";
})
(define_expand "decrement_and_branch_until_zero"
""
"")
-(define_insn ""
+(define_insn "*dbge_si"
[(set (pc)
(if_then_else
(ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+d*am")
{
CC_STATUS_INIT;
if (DATA_REG_P (operands[0]))
- return MOTOROLA ?
- "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jbcc %l1" :
- "dbra %0,%l1\;clr%.w %0\;subql #1,%0\;jcc %l1";
+ return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1";
if (GET_CODE (operands[0]) == MEM)
- return MOTOROLA ?
- "subq%.l #1,%0\;jbcc %l1" :
- "subql #1,%0\;jcc %l1";
- return MOTOROLA ?
- "subq.l #1,%0\;cmp.l #-1,%0\;jbne %l1" :
- "subql #1,%0\;cmpl #-1,%0\;jne %l1";
+ return "subq%.l #1,%0\;jcc %l1";
+ return "subq%.l #1,%0\;cmp%.l #-1,%0\;jne %l1";
+})
+
+(define_expand "sibcall"
+ [(call (match_operand:QI 0 "memory_operand" "")
+ (match_operand:SI 1 "general_operand" ""))]
+ ""
+{
+ operands[0] = m68k_legitimize_sibcall_address (operands[0]);
+})
+
+(define_insn "*sibcall"
+ [(call (mem:QI (match_operand:SI 0 "sibcall_operand" ""))
+ (match_operand:SI 1 "general_operand" ""))]
+ "SIBLING_CALL_P (insn)"
+{
+ return output_sibcall (operands[0]);
+})
+
+(define_expand "sibcall_value"
+ [(set (match_operand 0 "" "")
+ (call (match_operand:QI 1 "memory_operand" "")
+ (match_operand:SI 2 "general_operand" "")))]
+ ""
+{
+ operands[1] = m68k_legitimize_sibcall_address (operands[1]);
+})
+
+(define_insn "*sibcall_value"
+ [(set (match_operand 0 "" "=rf,rf")
+ (call (mem:QI (match_operand:SI 1 "sibcall_operand" ""))
+ (match_operand:SI 2 "general_operand" "")))]
+ "SIBLING_CALL_P (insn)"
+{
+ operands[0] = operands[1];
+ return output_sibcall (operands[0]);
})
;; Call subroutine with no return value.
[(call (mem:QI (match_operand:SI 0 "call_operand" "a,W"))
(match_operand:SI 1 "general_operand" "g,g"))]
;; Operand 1 not really used on the m68000.
- ""
+ "!SIBLING_CALL_P (insn)"
{
return output_call (operands[0]);
-})
+}
+ [(set_attr "type" "jsr")])
;; Call subroutine, returning value in operand 0
;; (which must be a hard register).
operands[1] = m68k_legitimize_call_address (operands[1]);
})
-(define_insn "*call_value"
+(define_insn "*non_symbolic_call_value"
[(set (match_operand 0 "" "=rf,rf")
- (call (mem:QI (match_operand:SI 1 "call_operand" "a,W"))
+ (call (mem:QI (match_operand:SI 1 "non_symbolic_call_operand" "a,W"))
(match_operand:SI 2 "general_operand" "g,g")))]
;; Operand 2 not really used on the m68000.
- ""
+ "!SIBLING_CALL_P (insn)"
+ "jsr %a1"
+ [(set_attr "type" "jsr")
+ (set_attr "opx" "1")])
+
+(define_insn "*symbolic_call_value_jsr"
+ [(set (match_operand 0 "" "=rf,rf")
+ (call (mem:QI (match_operand:SI 1 "symbolic_operand" "a,W"))
+ (match_operand:SI 2 "general_operand" "g,g")))]
+ ;; Operand 2 not really used on the m68000.
+ "!SIBLING_CALL_P (insn) && m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_JSR"
{
operands[0] = operands[1];
- return output_call (operands[0]);
-})
+ return m68k_symbolic_call;
+}
+ [(set_attr "type" "jsr")
+ (set_attr "opx" "1")])
+
+(define_insn "*symbolic_call_value_bsr"
+ [(set (match_operand 0 "" "=rf,rf")
+ (call (mem:QI (match_operand:SI 1 "symbolic_operand" "a,W"))
+ (match_operand:SI 2 "general_operand" "g,g")))]
+ ;; Operand 2 not really used on the m68000.
+ "!SIBLING_CALL_P (insn)
+ && (m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_BSR_C
+ || m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_BSR_P)"
+{
+ operands[0] = operands[1];
+ return m68k_symbolic_call;
+}
+ [(set_attr "type" "bsr")
+ (set_attr "opx" "1")])
;; Call subroutine returning any type.
(define_insn "nop"
[(const_int 0)]
""
- "nop")
+ "nop"
+ [(set_attr "type" "nop")])
+
+(define_expand "prologue"
+ [(const_int 0)]
+ ""
+{
+ m68k_expand_prologue ();
+ DONE;
+})
+
+(define_expand "epilogue"
+ [(return)]
+ ""
+{
+ m68k_expand_epilogue (false);
+ DONE;
+})
+
+(define_expand "sibcall_epilogue"
+ [(return)]
+ ""
+{
+ m68k_expand_epilogue (true);
+ DONE;
+})
;; Used for frameless functions which save no regs and allocate no locals.
-(define_insn "return"
+(define_expand "return"
[(return)]
"m68k_use_return_insn ()"
+ "")
+
+(define_insn "*return"
+ [(return)]
+ ""
+{
+ switch (m68k_get_function_kind (current_function_decl))
+ {
+ case m68k_fk_interrupt_handler:
+ return "rte";
+
+ case m68k_fk_interrupt_thread:
+ return "sleep";
+
+ default:
+ if (crtl->args.pops_args)
+ {
+ operands[0] = GEN_INT (crtl->args.pops_args);
+ return "rtd %0";
+ }
+ else
+ return "rts";
+ }
+}
+ [(set_attr "type" "rts")])
+
+(define_insn "*m68k_store_multiple"
+ [(match_parallel 0 "" [(match_operand 1 "")])]
+ "m68k_movem_pattern_p (operands[0], NULL, 0, true)"
{
- if (current_function_pops_args == 0)
- return "rts";
- operands[0] = GEN_INT (current_function_pops_args);
- return "rtd %0";
+ return m68k_output_movem (operands, operands[0], 0, true);
+})
+
+(define_insn "*m68k_store_multiple_automod"
+ [(match_parallel 0 ""
+ [(set (match_operand:SI 1 "register_operand" "=a")
+ (plus:SI (match_operand:SI 2 "register_operand" "1")
+ (match_operand:SI 3 "const_int_operand")))])]
+ "m68k_movem_pattern_p (operands[0], operands[1], INTVAL (operands[3]), true)"
+{
+ return m68k_output_movem (operands, operands[0], INTVAL (operands[3]), true);
+})
+
+(define_insn "*m68k_load_multiple"
+ [(match_parallel 0 "" [(match_operand 1 "")])]
+ "m68k_movem_pattern_p (operands[0], NULL, 0, false)"
+{
+ return m68k_output_movem (operands, operands[0], 0, false);
+})
+
+(define_insn "*m68k_load_multiple_automod"
+ [(match_parallel 0 ""
+ [(set (match_operand:SI 1 "register_operand" "=a")
+ (plus:SI (match_operand:SI 2 "register_operand" "1")
+ (match_operand:SI 3 "const_int_operand")))])]
+ "m68k_movem_pattern_p (operands[0], operands[1],
+ INTVAL (operands[3]), false)"
+{
+ return m68k_output_movem (operands, operands[0],
+ INTVAL (operands[3]), false);
+})
+
+(define_expand "link"
+ [(parallel
+ [(set (match_operand:SI 0 "register_operand")
+ (plus:SI (reg:SI SP_REG) (const_int -4)))
+ (set (match_dup 2)
+ (match_dup 0))
+ (set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 1 "const_int_operand")))])]
+ "TARGET_68020 || INTVAL (operands[1]) >= -0x8004"
+{
+ operands[2] = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, -4));
+})
+
+(define_insn "*link"
+ [(set (match_operand:SI 0 "register_operand" "+r")
+ (plus:SI (reg:SI SP_REG) (const_int -4)))
+ (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
+ (match_dup 0))
+ (set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 1 "const_int_operand")))]
+ "TARGET_68020 || INTVAL (operands[1]) >= -0x8004"
+{
+ operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
+ if (!MOTOROLA)
+ return "link %0,%1";
+ else if (INTVAL (operands[1]) >= -0x8000)
+ return "link.w %0,%1";
+ else
+ return "link.l %0,%1";
+}
+ [(set_attr "type" "link")])
+
+(define_expand "unlink"
+ [(parallel
+ [(set (match_operand:SI 0 "register_operand")
+ (match_dup 1))
+ (set (reg:SI SP_REG)
+ (plus:SI (match_dup 0)
+ (const_int 4)))])]
+ ""
+{
+ operands[1] = gen_frame_mem (SImode, copy_rtx (operands[0]));
+})
+
+(define_insn "*unlink"
+ [(set (match_operand:SI 0 "register_operand" "+r")
+ (mem:SI (match_dup 0)))
+ (set (reg:SI SP_REG)
+ (plus:SI (match_dup 0)
+ (const_int 4)))]
+ ""
+ "unlk %0"
+ [(set_attr "type" "unlk")])
+
+(define_insn "load_got"
+ [(set (match_operand:SI 0 "register_operand" "=a")
+ (unspec:SI [(const_int 0)] UNSPEC_GOT))]
+ ""
+{
+ if (TARGET_ID_SHARED_LIBRARY)
+ {
+ operands[1] = gen_rtx_REG (Pmode, PIC_REG);
+ return MOTOROLA ? "move.l %?(%1),%0" : "movel %1@(%?), %0";
+ }
+ else if (MOTOROLA)
+ {
+ if (TARGET_COLDFIRE)
+ /* Load the full 32-bit PC-relative offset of
+ _GLOBAL_OFFSET_TABLE_ into the PIC register, then use it to
+ calculate the absolute value. The offset and "lea"
+ operation word together occupy 6 bytes. */
+ return ("move.l #_GLOBAL_OFFSET_TABLE_@GOTPC, %0\n\t"
+ "lea (-6, %%pc, %0), %0");
+ else
+ return "lea (%%pc, _GLOBAL_OFFSET_TABLE_@GOTPC), %0";
+ }
+ else
+ return ("movel #_GLOBAL_OFFSET_TABLE_, %0\n\t"
+ "lea %%pc@(0,%0:l),%0");
})
(define_insn "indirect_jump"
[(set (pc) (match_operand:SI 0 "address_operand" "p"))]
""
- "jmp %a0")
+ "jmp %a0"
+ [(set_attr "type" "jmp")])
\f
;; This should not be used unless the add/sub insns can't be.
-(define_insn ""
+(define_insn "*lea"
[(set (match_operand:SI 0 "nonimmediate_operand" "=a")
(match_operand:QI 1 "address_operand" "p"))]
""
-{
- /* Recognize an insn that refers to a table of offsets. Such an insn will
- need to refer to a label on the insn. So output one. Use the
- label-number of the table of offsets to generate this label. This code,
- and similar code above, assumes that there will be at most one reference
- to each table. */
- if (GET_CODE (operands[1]) == PLUS
- && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
- && GET_CODE (XEXP (operands[1], 0)) != PLUS)
- {
- rtx labelref = XEXP (operands[1], 1);
- if (MOTOROLA)
- asm_fprintf (asm_out_file, "\\t.set %LLI%d,.+2\\n",
- CODE_LABEL_NUMBER (XEXP (labelref, 0)));
- else
- (*targetm.asm_out.internal_label) (asm_out_file, "LI",
- CODE_LABEL_NUMBER (XEXP (labelref, 0)));
- }
- return "lea %a1,%0";
-})
+ "lea %a1,%0")
\f
;; This is the first machine-dependent peephole optimization.
;; It is useful when a floating value is returned from a function call
;; and then is moved into an FP register.
;; But it is mainly intended to test the support for these optimizations.
-(define_peephole
+(define_peephole2
[(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
- (set (match_operand:DF 0 "register_operand" "=f")
- (match_operand:DF 1 "register_operand" "ad"))]
- "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
-{
- rtx xoperands[2];
- xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
- output_asm_insn ("move%.l %1,%@", xoperands);
- output_asm_insn ("move%.l %1,%-", operands);
- return "fmove%.d %+,%0";
-})
+ (set (match_operand:DF 0 "register_operand" "")
+ (match_operand:DF 1 "register_operand" ""))]
+ "FP_REG_P (operands[0]) && !FP_REG_P (operands[1])"
+ [(set (mem:SI (reg:SI SP_REG)) (match_dup 1))
+ (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 2))
+ (set (match_dup 0) (mem:DF (post_inc:SI (reg:SI SP_REG))))]
+ "split_di(operands + 1, 1, operands + 1, operands + 2);")
;; Optimize a stack-adjust followed by a push of an argument.
;; This is said to happen frequently with -msoft-float
;; when there are consecutive library calls.
-(define_peephole
+(define_peephole2
+ [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
+ (set (match_operand:SF 0 "push_operand" "")
+ (match_operand:SF 1 "general_operand" ""))]
+ "!reg_mentioned_p (stack_pointer_rtx, operands[0])"
+ [(set (match_dup 0) (match_dup 1))]
+ "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);")
+
+(define_peephole2
[(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
- (match_operand:SI 0 "const_int_operand" "n")))
- (set (match_operand:SF 1 "push_operand" "=m")
- (match_operand:SF 2 "general_operand" "rmfF"))]
- "INTVAL (operands[0]) >= 4
- && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
+ (match_operand:SI 0 "const_int_operand" "")))
+ (set (match_operand:SF 1 "push_operand" "")
+ (match_operand:SF 2 "general_operand" ""))]
+ "INTVAL (operands[0]) > 4
+ && !reg_mentioned_p (stack_pointer_rtx, operands[2])"
+ [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 0)))
+ (set (match_dup 1) (match_dup 2))]
{
- if (INTVAL (operands[0]) > 4)
- {
- rtx xoperands[2];
- xoperands[0] = stack_pointer_rtx;
- xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
- if (INTVAL (xoperands[1]) <= 8)
- {
- if (!TARGET_COLDFIRE)
- output_asm_insn ("addq%.w %1,%0", xoperands);
- else
- output_asm_insn ("addq%.l %1,%0", xoperands);
- }
- else if (TUNE_CPU32 && INTVAL (xoperands[1]) <= 16)
- {
- xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
- output_asm_insn ("addq%.w #8,%0\;addq%.w %1,%0", xoperands);
- }
- else if (INTVAL (xoperands[1]) <= 0x7FFF)
- {
- if (TUNE_68040)
- output_asm_insn ("add%.w %1,%0", xoperands);
- else if (MOTOROLA)
- output_asm_insn ("lea (%c1,%0),%0", xoperands);
- else
- output_asm_insn ("lea %0@(%c1),%0", xoperands);
- }
- else
- output_asm_insn ("add%.l %1,%0", xoperands);
- }
- if (FP_REG_P (operands[2]))
- return "fmove%.s %2,%@";
- return "move%.l %2,%@";
+ operands[0] = GEN_INT (INTVAL (operands[0]) - 4);
+ operands[1] = replace_equiv_address (operands[1], stack_pointer_rtx);
})
;; Speed up stack adjust followed by a fullword fixedpoint push.
+;; Constant operands need special care, as replacing a "pea X.w" with
+;; "move.l #X,(%sp)" is often not a win.
-(define_peephole
+;; Already done by the previous csa pass, left as reference.
+(define_peephole2
+ [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
+ (set (match_operand:SI 0 "push_operand" "")
+ (match_operand:SI 1 "general_operand" ""))]
+ "!reg_mentioned_p (stack_pointer_rtx, operands[1])"
+ [(set (match_dup 0) (match_dup 1))]
+ "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);")
+
+;; Try to use moveq, after stack push has been changed into a simple move.
+(define_peephole2
+ [(match_scratch:SI 2 "d")
+ (set (match_operand:SI 0 "memory_operand" "")
+ (match_operand:SI 1 "const_int_operand" ""))]
+ "GET_CODE (XEXP (operands[0], 0)) != PRE_DEC
+ && INTVAL (operands[1]) != 0
+ && IN_RANGE (INTVAL (operands[1]), -0x80, 0x7f)
+ && !valid_mov3q_const (INTVAL (operands[1]))"
+ [(set (match_dup 2) (match_dup 1))
+ (set (match_dup 0) (match_dup 2))])
+
+;; This sequence adds an instruction, but is two bytes shorter.
+(define_peephole2
+ [(match_scratch:SI 2 "d")
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 12)))
+ (set (match_operand:SI 0 "push_operand" "")
+ (match_operand:SI 1 "const_int_operand" ""))]
+ "INTVAL (operands[1]) != 0
+ && IN_RANGE (INTVAL (operands[1]), -0x80, 0x7f)
+ && !valid_mov3q_const (INTVAL (operands[1]))"
+ [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
+ (set (match_dup 2) (match_dup 1))
+ (set (match_dup 0) (match_dup 2))]
+ "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);")
+
+;; Changing pea X.w into a move.l is no real win here.
+(define_peephole2
[(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
- (match_operand:SI 0 "const_int_operand" "n")))
- (set (match_operand:SI 1 "push_operand" "=m")
- (match_operand:SI 2 "general_operand" "g"))]
- "INTVAL (operands[0]) >= 4
- && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
-{
- if (INTVAL (operands[0]) > 4)
- {
- rtx xoperands[2];
- xoperands[0] = stack_pointer_rtx;
- xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
- if (INTVAL (xoperands[1]) <= 8)
- {
- if (!TARGET_COLDFIRE)
- output_asm_insn ("addq%.w %1,%0", xoperands);
- else
- output_asm_insn ("addq%.l %1,%0", xoperands);
- }
- else if (TUNE_CPU32 && INTVAL (xoperands[1]) <= 16)
- {
- xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
- output_asm_insn ("addq%.w #8,%0\;addq%.w %1,%0", xoperands);
- }
- else if (INTVAL (xoperands[1]) <= 0x7FFF)
- {
- if (TUNE_68040)
- output_asm_insn ("add%.w %1,%0", xoperands);
- else if (MOTOROLA)
- output_asm_insn ("lea (%c1,%0),%0", xoperands);
- else
- output_asm_insn ("lea %0@(%c1),%0", xoperands);
- }
- else
- output_asm_insn ("add%.l %1,%0", xoperands);
- }
- if (operands[2] == const0_rtx)
- return "clr%.l %@";
- return "move%.l %2,%@";
-})
-
-;; Speed up pushing a single byte but leaving four bytes of space.
-
-(define_peephole
- [(set (mem:QI (pre_dec:SI (reg:SI SP_REG)))
- (match_operand:QI 1 "general_operand" "dami"))
- (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (const_int 2)))]
- "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
-{
- rtx xoperands[4];
-
- if (GET_CODE (operands[1]) == REG)
- return "move%.l %1,%-";
-
- xoperands[1] = operands[1];
- xoperands[2]
- = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3));
- xoperands[3] = stack_pointer_rtx;
- if (!TARGET_COLDFIRE)
- output_asm_insn ("subq%.w #4,%3\;move%.b %1,%2", xoperands);
- else
- output_asm_insn ("subq%.l #4,%3\;move%.b %1,%2", xoperands);
- return "";
-})
+ (match_operand:SI 0 "const_int_operand" "")))
+ (set (match_operand:SI 1 "push_operand" "")
+ (match_operand:SI 2 "general_operand" ""))]
+ "INTVAL (operands[0]) > 4
+ && !reg_mentioned_p (stack_pointer_rtx, operands[2])
+ && !(CONST_INT_P (operands[2]) && INTVAL (operands[2]) != 0
+ && IN_RANGE (INTVAL (operands[2]), -0x8000, 0x7fff)
+ && !valid_mov3q_const (INTVAL (operands[2])))"
+ [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 0)))
+ (set (match_dup 1) (match_dup 2))]
+{
+ operands[0] = GEN_INT (INTVAL (operands[0]) - 4);
+ operands[1] = replace_equiv_address (operands[1], stack_pointer_rtx);
+})
+
+;; Speed up pushing a single byte/two bytes but leaving four bytes of space
+;; (which differs slightly between m680x0 and ColdFire).
+
+(define_peephole2
+ [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
+ (set (match_operand:QI 0 "memory_operand" "")
+ (match_operand:QI 1 "register_operand" ""))]
+ "!reg_mentioned_p (stack_pointer_rtx, operands[1])
+ && GET_CODE (XEXP (operands[0], 0)) == PLUS
+ && rtx_equal_p (XEXP (XEXP (operands[0], 0), 0), stack_pointer_rtx)
+ && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1))
+ && INTVAL (XEXP (XEXP (operands[0], 0), 1)) == 3"
+ [(set (match_dup 0) (match_dup 1))]
+{
+ rtx addr = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx);
+ operands[0] = adjust_automodify_address (operands[0], SImode, addr, -3);
+ operands[1] = simplify_gen_subreg (SImode, operands[1], QImode, 0);
+})
+
+(define_peephole2
+ [(set (match_operand:QI 0 "push_operand" "")
+ (match_operand:QI 1 "register_operand" ""))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -3)))]
+ "!reg_mentioned_p (stack_pointer_rtx, operands[1])"
+ [(set (match_dup 0) (match_dup 1))]
+{
+ operands[0] = adjust_automodify_address (operands[0], SImode,
+ XEXP (operands[0], 0), -3);
+ operands[1] = simplify_gen_subreg (SImode, operands[1], QImode, 0);
+})
+
+(define_peephole2
+ [(set (match_operand:HI 0 "push_operand" "")
+ (match_operand:HI 1 "register_operand" ""))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2)))]
+ "!reg_mentioned_p (stack_pointer_rtx, operands[1])"
+ [(set (match_dup 0) (match_dup 1))]
+{
+ operands[0] = adjust_automodify_address (operands[0], SImode,
+ XEXP (operands[0], 0), -2);
+ operands[1] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
+})
+
+;; Optimize a series of strict_low_part assignments
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand" "")
+ (const_int 0))
+ (set (strict_low_part (match_operand:HI 1 "register_operand" ""))
+ (match_operand:HI 2 "general_operand" ""))]
+ "REGNO (operands[0]) == REGNO (operands[1])
+ && strict_low_part_peephole_ok (HImode, insn, operands[0])"
+ [(set (strict_low_part (match_dup 1)) (match_dup 2))]
+ "")
-(define_peephole
- [(set (match_operand:SI 0 "register_operand" "=d")
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand" "")
(const_int 0))
- (set (strict_low_part (subreg:HI (match_dup 0) 2))
- (match_operand:HI 1 "general_operand" "rmn"))]
- "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
-{
- if (GET_CODE (operands[1]) == CONST_INT)
- {
- if (operands[1] == const0_rtx
- && (DATA_REG_P (operands[0])
- || GET_CODE (operands[0]) == MEM)
- /* clr insns on 68000 read before writing. */
- && ((TARGET_68010 || TARGET_COLDFIRE)
- || !(GET_CODE (operands[0]) == MEM
- && MEM_VOLATILE_P (operands[0]))))
- return "clr%.w %0";
- }
- return "move%.w %1,%0";
-})
+ (set (strict_low_part (match_operand:QI 1 "register_operand" ""))
+ (match_operand:QI 2 "general_operand" ""))]
+ "REGNO (operands[0]) == REGNO (operands[1])
+ && strict_low_part_peephole_ok (QImode, insn, operands[0])"
+ [(set (strict_low_part (match_dup 1)) (match_dup 2))]
+ "")
;; dbCC peepholes
;;
return "fcos%.<FP:prec> %1,%0";
})
+;; Unconditional traps are assumed to have (const_int 1) for the condition.
(define_insn "trap"
- [(trap_if (const_int -1) (const_int 7))]
+ [(trap_if (const_int 1) (const_int 7))]
""
- "trap #7")
+ "trap #7"
+ [(set_attr "type" "trap")])
+
+(define_expand "ctrapdi4"
+ [(trap_if (match_operator 0 "ordered_comparison_operator"
+ [(cc0) (const_int 0)])
+ (match_operand:SI 3 "const1_operand" ""))]
+ "TARGET_68020"
+{
+ if (operands[2] == const0_rtx)
+ emit_insn (gen_tstdi (operands[1]));
+ else
+ emit_insn (gen_cmpdi (operands[1], operands[2]));
+ operands[1] = cc0_rtx;
+ operands[2] = const0_rtx;
+})
+
+(define_expand "ctrapsi4"
+ [(set (cc0)
+ (compare (match_operand:SI 1 "nonimmediate_operand" "")
+ (match_operand:SI 2 "general_operand" "")))
+ (trap_if (match_operator 0 "ordered_comparison_operator"
+ [(cc0) (const_int 0)])
+ (match_operand:SI 3 "const1_operand" ""))]
+ "TARGET_68020"
+ "")
-(define_insn "conditional_trap"
- [(trap_if (match_operator 0 "valid_dbcc_comparison_p"
+(define_expand "ctraphi4"
+ [(set (cc0)
+ (compare (match_operand:HI 1 "nonimmediate_src_operand" "")
+ (match_operand:HI 2 "general_src_operand" "")))
+ (trap_if (match_operator 0 "ordered_comparison_operator"
[(cc0) (const_int 0)])
- (match_operand:SI 1 "const_int_operand" "I"))]
+ (match_operand:SI 3 "const1_operand" ""))]
+ "TARGET_68020"
+ "")
+
+(define_expand "ctrapqi4"
+ [(set (cc0)
+ (compare (match_operand:QI 1 "nonimmediate_src_operand" "")
+ (match_operand:QI 2 "general_src_operand" "")))
+ (trap_if (match_operator 0 "ordered_comparison_operator"
+ [(cc0) (const_int 0)])
+ (match_operand:SI 3 "const1_operand" ""))]
+ "TARGET_68020"
+ "")
+
+(define_insn "*conditional_trap"
+ [(trap_if (match_operator 0 "ordered_comparison_operator"
+ [(cc0) (const_int 0)])
+ (match_operand:SI 1 "const1_operand" "I"))]
"TARGET_68020 && ! flags_in_68881 ()"
{
switch (GET_CODE (operands[0]))
default: gcc_unreachable ();
}
})
+
+;; These are to prevent the scheduler from moving stores to the frame
+;; before the stack adjustment.
+(define_insn "stack_tie"
+ [(set (mem:BLK (scratch))
+ (unspec:BLK [(match_operand:SI 0 "register_operand" "r")
+ (match_operand:SI 1 "register_operand" "r")]
+ UNSPEC_TIE))]
+ ""
+ ""
+ [(set_attr "type" "ignore")])
+
+;; Instruction that subscribes one word in ColdFire instruction buffer.
+;; This instruction is used within scheduler only and should not appear
+;; in the instruction stream.
+(define_insn "ib"
+ [(unspec [(const_int 0)] UNSPEC_IB)]
+ ""
+ "#"
+ [(set_attr "type" "ib")])
+
+(include "cf.md")
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