#define TARGET_CPU_CPP_BUILTINS() \
do \
{ \
- builtin_define ("__mc68000__"); \
- builtin_define ("__mc68020__"); \
builtin_define ("__m68k__"); \
+ builtin_define_std ("mc68000"); \
+ if (TARGET_68060) \
+ builtin_define_std ("mc68060"); \
+ else if (TARGET_68040) \
+ builtin_define_std ("mc68040"); \
+ else if (TARGET_68020) \
+ builtin_define_std ("mc68020"); \
+ if (TARGET_68881) \
+ builtin_define ("__HAVE_68881__"); \
+ if (TARGET_CPU32) \
+ { \
+ builtin_define_std ("mc68332"); \
+ builtin_define_std ("mcpu32"); \
+ } \
+ if (TARGET_COLDFIRE) \
+ builtin_define ("__mcoldfire__"); \
+ if (TARGET_5200) \
+ builtin_define ("__mcf5200__"); \
+ if (TARGET_528x) \
+ { \
+ builtin_define ("__mcf528x__"); \
+ builtin_define ("__mcf5200__"); \
+ } \
+ if (TARGET_CFV3) \
+ { \
+ builtin_define ("__mcf5300__"); \
+ builtin_define ("__mcf5307__"); \
+ } \
+ if (TARGET_CFV4) \
+ { \
+ builtin_define ("__mcf5400__"); \
+ builtin_define ("__mcf5407__"); \
+ } \
+ if (TARGET_CF_HWDIV) \
+ builtin_define ("__mcfhwdiv__"); \
+ if (flag_pic) \
+ builtin_define ("__pic__"); \
+ if (flag_pic > 1) \
+ builtin_define ("__PIC__"); \
builtin_assert ("cpu=m68k"); \
builtin_assert ("machine=m68k"); \
} \
#define MASK_NO_STRICT_ALIGNMENT 16384
#define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT)
+/* Build for ColdFire v3 */
+#define MASK_CFV3 0x8000
+#define TARGET_CFV3 (target_flags & MASK_CFV3)
+
+/* Build for ColdFire v4 */
+#define MASK_CFV4 0x10000
+#define TARGET_CFV4 (target_flags & MASK_CFV4)
+
+/* Divide support for ColdFire */
+#define MASK_CF_HWDIV 0x40000
+#define TARGET_CF_HWDIV (target_flags & MASK_CF_HWDIV)
+
+/* Compile for mcf528x */
+#define MASK_528x 0x80000
+#define TARGET_528x (target_flags & MASK_528x)
+
+
+/* Is the target a coldfire */
+#define MASK_COLDFIRE (MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4)
+#define TARGET_COLDFIRE (target_flags & MASK_COLDFIRE)
+
+/* Which bits can be set by specifying a coldfire */
+#define MASK_ALL_CF_BITS (MASK_COLDFIRE|MASK_CF_HWDIV)
+
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE }
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
- { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
+ { { "68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
N_("Generate code for a 68020") }, \
- { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
+ { "c68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
N_("Generate code for a 68020") }, \
{ "68020", (MASK_68020|MASK_BITFIELD), "" }, \
{ "c68020", (MASK_68020|MASK_BITFIELD), "" }, \
- { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
+ { "68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
|MASK_68020|MASK_BITFIELD|MASK_68881), \
N_("Generate code for a 68000") }, \
- { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
+ { "c68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
|MASK_68020|MASK_BITFIELD|MASK_68881), \
N_("Generate code for a 68000") }, \
{ "bitfield", MASK_BITFIELD, \
{ "68881", MASK_68881, "" }, \
{ "soft-float", - (MASK_68040_ONLY|MASK_68881), \
N_("Generate code with library calls for floating point") }, \
- { "68020-40", -(MASK_5200|MASK_68060|MASK_68040_ONLY), \
+ { "68020-40", -(MASK_ALL_CF_BITS|MASK_68060|MASK_68040_ONLY), \
N_("Generate code for a 68040, without any new instructions") }, \
{ "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\
- { "68020-60", -(MASK_5200|MASK_68040_ONLY), \
+ { "68020-60", -(MASK_ALL_CF_BITS|MASK_68040_ONLY), \
N_("Generate code for a 68060, without any new instructions") }, \
{ "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \
|MASK_68060), "" }, \
- { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
+ { "68030", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
N_("Generate code for a 68030") }, \
{ "68030", (MASK_68020|MASK_BITFIELD), "" }, \
- { "68040", - (MASK_5200|MASK_68060), \
+ { "68040", - (MASK_ALL_CF_BITS|MASK_68060), \
N_("Generate code for a 68040") }, \
{ "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
|MASK_68040_ONLY|MASK_68040), "" }, \
- { "68060", - (MASK_5200|MASK_68040), \
+ { "68060", - (MASK_ALL_CF_BITS|MASK_68040), \
N_("Generate code for a 68060") }, \
{ "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
|MASK_68040_ONLY|MASK_68060), "" }, \
- { "5200", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
+ { "5200", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
|MASK_BITFIELD|MASK_68881), \
N_("Generate code for a 520X") }, \
{ "5200", (MASK_5200), "" }, \
+ { "5206e", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
+ |MASK_BITFIELD|MASK_68881), \
+ N_("Generate code for a 5206e") }, \
+ { "5206e", (MASK_5200|MASK_CF_HWDIV), "" }, \
+ { "528x", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
+ |MASK_BITFIELD|MASK_68881), \
+ N_("Generate code for a 528x") }, \
+ { "528x", (MASK_528x|MASK_CF_HWDIV), "" }, \
+ { "5307", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
+ |MASK_BITFIELD|MASK_68881), \
+ N_("Generate code for a 5307") }, \
+ { "5307", (MASK_CFV3|MASK_CF_HWDIV), "" }, \
+ { "5407", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
+ |MASK_BITFIELD|MASK_68881), \
+ N_("Generate code for a 5407") }, \
+ { "5407", (MASK_CFV4|MASK_CF_HWDIV), "" }, \
{ "68851", 0, \
N_("Generate code for a 68851") }, \
{ "no-68851", 0, \
N_("Do no generate code for a 68851") }, \
- { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
+ { "68302", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
|MASK_68020|MASK_BITFIELD|MASK_68881), \
N_("Generate code for a 68302") }, \
- { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
+ { "68332", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
|MASK_BITFIELD|MASK_68881), \
N_("Generate code for a 68332") }, \
{ "68332", MASK_68020, "" }, \
- { "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
+ { "cpu32", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
|MASK_BITFIELD|MASK_68881), \
N_("Generate code for a cpu32") }, \
{ "cpu32", MASK_68020, "" }, \
For the 68000, we give the data registers numbers 0-7,
the address registers numbers 010-017,
and the 68881 floating point registers numbers 020-027. */
-#define FIRST_PSEUDO_REGISTER 24
+#define FIRST_PSEUDO_REGISTER 25
/* This defines the register which is used to hold the offset table for PIC. */
#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
This is computed in `reload', in reload1.c. */
#define FRAME_POINTER_REQUIRED 0
-/* Base register for access to arguments of the function. */
-#define ARG_POINTER_REGNUM 14
+/* Base register for access to arguments of the function.
+ * This isn't a hardware register. It will be eliminated to the
+ * stack pointer or frame pointer.
+ */
+#define ARG_POINTER_REGNUM 24
/* Register in which static-chain is passed to a function. */
#define STATIC_CHAIN_REGNUM 8
makes the stack pointer a smaller address. */
#define STACK_GROWS_DOWNWARD
-/* Nonzero if we need to generate stack-probe insns.
- On most systems they are not needed.
- When they are needed, define this as the stack offset to probe at. */
-#define NEED_PROBE 0
-
/* Define this if the nominal address of the stack frame
is at the high-address end of the local variables;
that is, each additional local variable allocated
this says how many the stack pointer really advances by.
On the 68000, sp@- in a byte insn really pushes a word.
On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */
-#define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1)
+#define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
/* We want to avoid trying to push bytes. */
#define MOVE_BY_PIECES_P(SIZE, ALIGN) \
(move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \
- && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_5200)))
+ && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_COLDFIRE)))
/* Offset of first parameter from the argument pointer register value. */
#define FIRST_PARM_OFFSET(FNDECL) 8
You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
#define USE_RETURN_INSN use_return_insn ()
-/* Store in the variable DEPTH the initial difference between the
- frame pointer reg contents and the stack pointer reg contents,
- as of the start of the function body. This depends on the layout
- of the fixed parts of the stack frame and on how registers are saved.
-
- On the 68k, if we have a frame, we must add one word to its length
- to allow for the place that a6 is stored when we do have a frame pointer.
- Otherwise, we would need to compute the offset from the frame pointer
- of a local variable as a function of frame_pointer_needed, which
- is hard. */
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
-{ int regno; \
- int offset = -4; \
- for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \
- if (regs_ever_live[regno] && ! call_used_regs[regno]) \
- offset += 12; \
- for (regno = 0; regno < 16; regno++) \
- if (regs_ever_live[regno] && ! call_used_regs[regno]) \
- offset += 4; \
- if (flag_pic && current_function_uses_pic_offset_table) \
- offset += 4; \
- (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \
- + (get_frame_size () == 0 ? 0 : 4)); \
-}
-
/* Output assembler code for a block containing the constant parts
of a trampoline, leaving space for the variable parts. */
asm ("rts":); \
}
\f
+/* Definitions for register eliminations.
+
+ This is an array of structures. Each structure initializes one pair
+ of eliminable registers. The "from" register number is given first,
+ followed by "to". Eliminations of the same "from" register are listed
+ in order of preference.
+
+ There are two registers that can always be eliminated on the m68k.
+ The frame pointer and the arg pointer can be replaced by either the
+ hard frame pointer or to the stack pointer, depending upon the
+ circumstances. The hard frame pointer is not used before reload and
+ so it is not eligible for elimination. */
+
+#define ELIMINABLE_REGS \
+{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
+ { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
+ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
+
+/* Given FROM and TO register numbers, say whether this elimination is
+ allowed. Frame pointer elimination is automatically handled.
+
+ All other eliminations are valid. */
+
+#define CAN_ELIMINATE(FROM, TO) \
+ ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
+
+/* Define the offset between two registers, one to be eliminated, and the other
+ its replacement, at the start of a routine. */
+
+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
+ (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
+\f
/* Addressing modes, and classification of registers for them. */
#define HAVE_POST_INCREMENT 1
/* Nonzero if the constant value X is a legitimate general operand.
It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
-#define LEGITIMATE_CONSTANT_P(X) 1
+#define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode)
/* Nonzero if the constant value X is a legitimate general operand
when generating PIC code. It is given that flag_pic is on and
#endif
#define LEGITIMATE_PIC_OPERAND_P(X) \
- ((! symbolic_operand (X, VOIDmode) \
- && ! (GET_CODE (X) == CONST_DOUBLE && mem_for_const_double (X) != 0 \
- && GET_CODE (mem_for_const_double (X)) == MEM \
- && symbolic_operand (XEXP (mem_for_const_double (X), 0), \
- VOIDmode))) \
- || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
+ (! symbolic_operand (X, VOIDmode) \
+ || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
|| PCREL_GENERAL_OPERAND_OK)
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
/* coldfire/5200 does not allow HImode index registers. */
#define LEGITIMATE_INDEX_REG_P(X) \
((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
- || (! TARGET_5200 \
+ || (! TARGET_COLDFIRE \
&& GET_CODE (X) == SIGN_EXTEND \
&& GET_CODE (XEXP (X, 0)) == REG \
&& GET_MODE (XEXP (X, 0)) == HImode \
#define LEGITIMATE_INDEX_P(X) \
(LEGITIMATE_INDEX_REG_P (X) \
- || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \
+ || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
&& LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
&& GET_CODE (XEXP (X, 1)) == CONST_INT \
&& (INTVAL (XEXP (X, 1)) == 2 \
|| INTVAL (XEXP (X, 1)) == 4 \
- || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200))))
+ || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_COLDFIRE))))
/* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
\f
/* Control the assembler format that we output. */
-/* Output at beginning of assembler file. */
-
-#define ASM_FILE_START(FILE) \
- fprintf (FILE, "#NO_APP\n");
-
/* Output to assembler file text saying following lines
may contain character constants, extra white space, comments, etc. */
#define REGISTER_NAMES \
{"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
"a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
- "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
+ "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", "argptr" }
/* How to renumber registers for dbx and gdb.
On the Sun-3, the floating point registers have numbers
`assemble_name' uses this. */
#define ASM_OUTPUT_LABELREF(FILE,NAME) \
- asm_fprintf (FILE, "%0U%s", NAME)
+ asm_fprintf (FILE, "%U%s", NAME)
/* This is how to store into the string LABEL
the symbol_ref name of an internal numbered label where
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