/* Subroutines used for code generation on the Renesas M32R cpu.
Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
- 2005, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+ 2005, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
This file is part of GCC.
#include "function.h"
#include "recog.h"
#include "diagnostic-core.h"
-#include "toplev.h"
#include "ggc.h"
#include "integrate.h"
#include "df.h"
static void m32r_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
const_tree, bool);
static bool m32r_can_eliminate (const int, const int);
+static void m32r_conditional_register_usage (void);
static void m32r_trampoline_init (rtx, tree, rtx);
\f
/* M32R specific attributes. */
{ "model", 1, 1, true, false, false, m32r_handle_model_attribute },
{ NULL, 0, 0, false, false, false, NULL }
};
+
+static const struct default_options m32r_option_optimization_table[] =
+ {
+ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
+ { OPT_LEVELS_1_PLUS, OPT_fregmove, NULL, 1 },
+ { OPT_LEVELS_NONE, 0, NULL, 0 }
+ };
\f
/* Initialize the GCC target structure. */
#undef TARGET_ATTRIBUTE_TABLE
#define TARGET_HANDLE_OPTION m32r_handle_option
#undef TARGET_OPTION_OVERRIDE
#define TARGET_OPTION_OVERRIDE m32r_option_override
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
+#define TARGET_OPTION_OPTIMIZATION_TABLE m32r_option_optimization_table
#undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
#define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
-#undef TARGET_MEMORY_MOVE_COSTS
-#define TARGET_MEMORY_MOVE_COSTS m32r_memory_move_costs
+#undef TARGET_MEMORY_MOVE_COST
+#define TARGET_MEMORY_MOVE_COST m32r_memory_move_cost
#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS m32r_rtx_costs
#undef TARGET_ADDRESS_COST
#undef TARGET_CAN_ELIMINATE
#define TARGET_CAN_ELIMINATE m32r_can_eliminate
+#undef TARGET_CONDITIONAL_REGISTER_USAGE
+#define TARGET_CONDITIONAL_REGISTER_USAGE m32r_conditional_register_usage
+
#undef TARGET_TRAMPOLINE_INIT
#define TARGET_TRAMPOLINE_INIT m32r_trampoline_init
+#undef TARGET_EXCEPT_UNWIND_INFO
+#define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
+
struct gcc_target targetm = TARGET_INITIALIZER;
\f
/* Implement TARGET_HANDLE_OPTION. */
{
switch (code)
{
- case OPT_G:
- g_switch_value = value;
- g_switch_set = true;
- return true;
-
case OPT_m32r:
target_flags &= ~(MASK_M32R2 | MASK_M32RX);
return true;
m32r_punct_chars['@'] = 1; /* ??? no longer used */
/* Provide default value if not specified. */
- if (!g_switch_set)
+ if (!global_options_set.x_g_switch_value)
g_switch_value = SDATA_DEFAULT_SIZE;
}
{
int size = int_size_in_bytes (TREE_TYPE (decl));
- if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
+ if (size > 0 && size <= g_switch_value)
return true;
}
}
static rtx
m32r_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
- const_tree type, bool named ATTRIBUTE_UNUSED)
+ const_tree type ATTRIBUTE_UNUSED,
+ bool named ATTRIBUTE_UNUSED)
{
return (PASS_IN_REG_P (*cum, mode, type)
? gen_rtx_REG (mode, ROUND_ADVANCE_CUM (*cum, mode, type))
{
unsigned int regno;
unsigned int total_size, var_size, args_size, pretend_size, extra_size;
- unsigned int reg_size, frame_size;
+ unsigned int reg_size;
unsigned int gmask;
enum m32r_function_type fn_type;
int interrupt_p;
handler will do the right thing if this changes total_size. */
total_size = M32R_STACK_ALIGN (total_size);
- frame_size = total_size - (pretend_size + reg_size);
+ /* frame_size = total_size - (pretend_size + reg_size); */
/* Save computed information. */
current_frame_info.total_size = total_size;
if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
{
rtx pic_ref, address;
- rtx insn;
int subregs = 0;
if (reg == 0)
emit_insn (gen_addsi3 (address, address, pic_offset_table_rtx));
pic_ref = gen_const_mem (Pmode, address);
- insn = emit_move_insn (reg, pic_ref);
-#if 0
- /* Put a REG_EQUAL note on this insn, so that it can be optimized
- by loop. */
- set_unique_reg_note (insn, REG_EQUAL, orig);
-#endif
+ emit_move_insn (reg, pic_ref);
return reg;
}
else if (GET_CODE (orig) == CONST)
if (flag_verbose_asm)
fprintf (asm_out_file,
- "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED "\n",
+ "%s M32R/D special options: -G %d\n",
ASM_COMMENT_START, g_switch_value);
if (TARGET_LITTLE_ENDIAN)
gen_int_mode (TRAMPOLINE_SIZE, SImode), SImode,
GEN_INT (3), SImode);
}
+
+static void
+m32r_conditional_register_usage (void)
+{
+ if (flag_pic)
+ {
+ fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
+ call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
+ }
+}