(UNSPEC_RET_ADDR 26)
(UNSPEC_SETF_EXP 27)
(UNSPEC_FR_SQRT_RECIP_APPROX 28)
+ (UNSPEC_SHRP 29)
])
(define_constants
(UNSPECV_PSAC_NORMAL 6)
(UNSPECV_SETJMP_RECEIVER 7)
])
+
+(include "predicates.md")
\f
;; ::::::::::::::::::::
;; ::
(define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,
fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,
- chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,
- syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,nop_b,nop_f,
- nop_i,nop_m,nop_x,lfetch,pre_cycle"
+ chk_s,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,
+ st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,
+ nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle"
(const_string "unknown"))
;; chk_s has an I and an M form; use type A for convenience.
(eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M")
(eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M")
(eq_attr "itanium_class" "lfetch") (const_string "M")
- (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog") (const_string "A")
+ (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog,mmalua")
+ (const_string "A")
(eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F")
(eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F")
(eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I")
(define_attr "predicable" "no,yes" (const_string "yes"))
-\f
+;; Empty. True iff this insn does not generate any code.
+(define_attr "empty" "no,yes" (const_string "no"))
+
+\f
;; DFA descriptions of ia64 processors used for insn scheduling and
;; bundling.
(automata_option "w")
-;;(automata_option "no-minimization")
-
-
(include "itanium1.md")
(include "itanium2.md")
""
{
operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
- operands[3] = gen_rtx_MEM (DImode, operands[2]);
- RTX_UNCHANGING_P (operands[3]) = 1;
+ operands[3] = gen_const_mem (DImode, operands[2]);
})
(define_insn "*load_fptr_internal1"
(match_operand:XF 1 "general_operand" ""))]
""
{
- /* We must support XFmode loads into general registers for stdarg/vararg
- and unprototyped calls. We split them into DImode loads for convenience.
- We don't need XFmode stores from general regs, because a stdarg/vararg
- routine does a block store to memory of unnamed arguments. */
- if (GET_CODE (operands[0]) == REG
- && GR_REGNO_P (REGNO (operands[0])))
+ rtx op0 = operands[0];
+
+ if (GET_CODE (op0) == SUBREG)
+ op0 = SUBREG_REG (op0);
+
+ /* We must support XFmode loads into general registers for stdarg/vararg,
+ unprototyped calls, and a rare case where a long double is passed as
+ an argument after a float HFA fills the FP registers. We split them into
+ DImode loads for convenience. We also need to support XFmode stores
+ for the last case. This case does not happen for stdarg/vararg routines,
+ because we do a block store to memory of unnamed arguments. */
+
+ if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
{
/* We're hoping to transform everything that deals with XFmode
quantities and GR registers early in the compiler. */
|| (GET_CODE (operands[1]) == REG
&& GR_REGNO_P (REGNO (operands[1]))))
{
- emit_move_insn (gen_rtx_REG (TImode, REGNO (operands[0])),
- SUBREG_REG (operands[1]));
+ rtx op1 = operands[1];
+
+ if (GET_CODE (op1) == SUBREG)
+ op1 = SUBREG_REG (op1);
+ else
+ op1 = gen_rtx_REG (TImode, REGNO (op1));
+
+ emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1);
DONE;
}
if (GET_CODE (operands[1]) == CONST_DOUBLE)
{
- emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0])),
+ emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)),
operand_subword (operands[1], 0, 0, XFmode));
- emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0]) + 1),
+ emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1),
operand_subword (operands[1], 1, 0, XFmode));
DONE;
}
{
rtx out[2];
- out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0]));
- out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])+1);
+ out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (op0));
+ out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (op0) + 1);
emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
abort ();
}
+ if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1])))
+ {
+ /* We're hoping to transform everything that deals with XFmode
+ quantities and GR registers early in the compiler. */
+ if (no_new_pseudos)
+ abort ();
+
+ /* Op0 can't be a GR_REG here, as that case is handled above.
+ If op0 is a register, then we spill op1, so that we now have a
+ MEM operand. This requires creating an XFmode subreg of a TImode reg
+ to force the spill. */
+ if (register_operand (operands[0], XFmode))
+ {
+ rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1]));
+ op1 = gen_rtx_SUBREG (XFmode, op1, 0);
+ operands[1] = spill_xfmode_operand (op1, 0);
+ }
+
+ else if (GET_CODE (operands[0]) == MEM)
+ {
+ rtx in[2];
+
+ in[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[1]));
+ in[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
+
+ emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]);
+ emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]);
+ DONE;
+ }
+
+ else
+ abort ();
+ }
+
if (! reload_in_progress && ! reload_completed)
{
- operands[0] = spill_xfmode_operand (operands[0], 0);
operands[1] = spill_xfmode_operand (operands[1], 0);
+ if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG)
+ {
+ rtx memt, memx, in = operands[1];
+ if (CONSTANT_P (in))
+ in = validize_mem (force_const_mem (XFmode, in));
+ if (GET_CODE (in) == MEM)
+ memt = adjust_address (in, TImode, 0);
+ else
+ {
+ memt = assign_stack_temp (TImode, 16, 0);
+ memx = adjust_address (memt, XFmode, 0);
+ emit_move_insn (memx, in);
+ }
+ emit_move_insn (op0, memt);
+ DONE;
+ }
+
if (! ia64_move_ok (operands[0], operands[1]))
operands[1] = force_reg (XFmode, operands[1]);
}
;; ??? There's no easy way to mind volatile acquire/release semantics.
(define_insn "*movxf_internal"
- [(set (match_operand:XF 0 "destination_xfmode_operand" "=f,f, m")
- (match_operand:XF 1 "general_xfmode_operand" "fG,m,fG"))]
+ [(set (match_operand:XF 0 "destination_operand" "=f,f, m")
+ (match_operand:XF 1 "general_operand" "fG,m,fG"))]
"ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %F1
})
(define_insn_and_split "*movtf_internal"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=r,r,m")
+ [(set (match_operand:TF 0 "destination_operand" "=r,r,m")
(match_operand:TF 1 "general_operand" "ri,m,r"))]
"ia64_move_ok (operands[0], operands[1])"
"#"
(match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))]
""
"@
- zxt4 %0 = %1
+ addp4 %0 = %1, r0
ld4%O1 %0 = %1%P1
fmix.r %0 = f0, %1"
- [(set_attr "itanium_class" "xtd,ld,fmisc")])
+ [(set_attr "itanium_class" "ialu,ld,fmisc")])
;; Convert between floating point types of different sizes.
[(set_attr "itanium_class" "ishf")])
;; Combine doesn't like to create bit-field insertions into zero.
+(define_insn "*shladdp4_internal"
+ [(set (match_operand:DI 0 "gr_register_operand" "=r")
+ (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
+ (match_operand:DI 2 "shladd_log2_operand" "n"))
+ (match_operand:DI 3 "const_int_operand" "n")))]
+ "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL (operands[2]) == 32"
+ "shladdp4 %0 = %1, %2, r0"
+ [(set_attr "itanium_class" "ialu")])
+
(define_insn "*depz_internal"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
(match_operand:SI 2 "general_operand" "")))]
"TARGET_INLINE_INT_DIV"
{
- rtx op1_xf, op2_xf, op0_xf, op0_di, twon34;
- REAL_VALUE_TYPE twon34_r;
+ rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp;
op0_xf = gen_reg_rtx (XFmode);
op0_di = gen_reg_rtx (DImode);
expand_float (op2_xf, operands[2], 0);
/* 2^-34 */
- real_2expN (&twon34_r, -34);
- twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, XFmode);
- twon34 = force_reg (XFmode, twon34);
+ twon34_exp = gen_reg_rtx (DImode);
+ emit_move_insn (twon34_exp, GEN_INT (65501));
+ twon34 = gen_reg_rtx (XFmode);
+ emit_insn (gen_setf_exp_xf (twon34, twon34_exp));
emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34));
(match_operand:SI 2 "general_operand" "")))]
"TARGET_INLINE_INT_DIV"
{
- rtx op1_xf, op2_xf, op0_xf, op0_di, twon34;
- REAL_VALUE_TYPE twon34_r;
+ rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp;
op0_xf = gen_reg_rtx (XFmode);
op0_di = gen_reg_rtx (DImode);
expand_float (op2_xf, operands[2], 1);
/* 2^-34 */
- real_2expN (&twon34_r, -34);
- twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, XFmode);
- twon34 = force_reg (XFmode, twon34);
+ twon34_exp = gen_reg_rtx (DImode);
+ emit_move_insn (twon34_exp, GEN_INT (65501));
+ twon34 = gen_reg_rtx (XFmode);
+ emit_insn (gen_setf_exp_xf (twon34, twon34_exp));
emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34));
[(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "no")])
-(define_insn "*setf_exp_xf"
+(define_insn "setf_exp_xf"
[(set (match_operand:XF 0 "fr_register_operand" "=f")
(unspec:XF [(match_operand:DI 1 "register_operand" "r")]
UNSPEC_SETF_EXP))]
\f
;; ::::::::::::::::::::
;; ::
+;; :: 128 bit Integer Shifts and Rotates
+;; ::
+;; ::::::::::::::::::::
+
+(define_expand "ashlti3"
+ [(set (match_operand:TI 0 "gr_register_operand" "")
+ (ashift:TI (match_operand:TI 1 "gr_register_operand" "")
+ (match_operand:DI 2 "nonmemory_operand" "")))]
+ ""
+{
+ if (!dshift_count_operand (operands[2], DImode))
+ FAIL;
+})
+
+(define_insn_and_split "*ashlti3_internal"
+ [(set (match_operand:TI 0 "gr_register_operand" "=&r")
+ (ashift:TI (match_operand:TI 1 "gr_register_operand" "r")
+ (match_operand:DI 2 "dshift_count_operand" "n")))]
+ ""
+ "#"
+ "reload_completed"
+ [(const_int 0)]
+{
+ HOST_WIDE_INT shift = INTVAL (operands[2]);
+ rtx rl = gen_lowpart (DImode, operands[0]);
+ rtx rh = gen_highpart (DImode, operands[0]);
+ rtx lo = gen_lowpart (DImode, operands[1]);
+ rtx shiftlo = GEN_INT (shift & 63);
+
+ if (shift & 64)
+ {
+ emit_move_insn (rl, const0_rtx);
+ if (shift & 63)
+ emit_insn (gen_ashldi3 (rh, lo, shiftlo));
+ else
+ emit_move_insn (rh, lo);
+ }
+ else
+ {
+ rtx hi = gen_highpart (DImode, operands[1]);
+
+ emit_insn (gen_shrp (rh, hi, lo, GEN_INT (-shift & 63)));
+ emit_insn (gen_ashldi3 (rl, lo, shiftlo));
+ }
+ DONE;
+})
+
+(define_expand "ashrti3"
+ [(set (match_operand:TI 0 "gr_register_operand" "")
+ (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "")
+ (match_operand:DI 2 "nonmemory_operand" "")))]
+ ""
+{
+ if (!dshift_count_operand (operands[2], DImode))
+ FAIL;
+})
+
+(define_insn_and_split "*ashrti3_internal"
+ [(set (match_operand:TI 0 "gr_register_operand" "=&r")
+ (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r")
+ (match_operand:DI 2 "dshift_count_operand" "n")))]
+ ""
+ "#"
+ "reload_completed"
+ [(const_int 0)]
+{
+ HOST_WIDE_INT shift = INTVAL (operands[2]);
+ rtx rl = gen_lowpart (DImode, operands[0]);
+ rtx rh = gen_highpart (DImode, operands[0]);
+ rtx hi = gen_highpart (DImode, operands[1]);
+ rtx shiftlo = GEN_INT (shift & 63);
+
+ if (shift & 64)
+ {
+ if (shift & 63)
+ emit_insn (gen_ashrdi3 (rl, hi, shiftlo));
+ else
+ emit_move_insn (rl, hi);
+ emit_insn (gen_ashrdi3 (rh, hi, GEN_INT (63)));
+ }
+ else
+ {
+ rtx lo = gen_lowpart (DImode, operands[1]);
+
+ emit_insn (gen_shrp (rl, hi, lo, shiftlo));
+ emit_insn (gen_ashrdi3 (rh, hi, shiftlo));
+ }
+ DONE;
+})
+
+(define_expand "lshrti3"
+ [(set (match_operand:TI 0 "gr_register_operand" "")
+ (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "")
+ (match_operand:DI 2 "nonmemory_operand" "")))]
+ ""
+{
+ if (!dshift_count_operand (operands[2], DImode))
+ FAIL;
+})
+
+(define_insn_and_split "*lshrti3_internal"
+ [(set (match_operand:TI 0 "gr_register_operand" "=&r")
+ (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r")
+ (match_operand:DI 2 "dshift_count_operand" "n")))]
+ ""
+ "#"
+ "reload_completed"
+ [(const_int 0)]
+{
+ HOST_WIDE_INT shift = INTVAL (operands[2]);
+ rtx rl = gen_lowpart (DImode, operands[0]);
+ rtx rh = gen_highpart (DImode, operands[0]);
+ rtx hi = gen_highpart (DImode, operands[1]);
+ rtx shiftlo = GEN_INT (shift & 63);
+
+ if (shift & 64)
+ {
+ if (shift & 63)
+ emit_insn (gen_lshrdi3 (rl, hi, shiftlo));
+ else
+ emit_move_insn (rl, hi);
+ emit_move_insn (rh, const0_rtx);
+ }
+ else
+ {
+ rtx lo = gen_lowpart (DImode, operands[1]);
+
+ emit_insn (gen_shrp (rl, hi, lo, shiftlo));
+ emit_insn (gen_lshrdi3 (rh, hi, shiftlo));
+ }
+ DONE;
+})
+
+(define_insn "shrp"
+ [(set (match_operand:DI 0 "gr_register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")
+ (match_operand:DI 2 "gr_register_operand" "r")
+ (match_operand:DI 3 "shift_count_operand" "M")]
+ UNSPEC_SHRP))]
+ ""
+ "shrp %0 = %1, %2, %3"
+ [(set_attr "itanium_class" "ishf")])
+\f
+;; ::::::::::::::::::::
+;; ::
;; :: 32 bit Integer Logical operations
;; ::
;; ::::::::::::::::::::
[(set_attr "itanium_class" "br,scall")])
(define_insn "call_value_nogp"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0 "" "=X,X")
(call (mem:DI (match_operand:DI 1 "call_operand" "?b,i"))
(const_int 0)))
(clobber (match_operand:DI 2 "register_operand" "=b,b"))]
})
(define_insn "call_value_gp"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0 "" "=X,X")
(call (mem:DI (match_operand:DI 1 "call_operand" "?r,i"))
(const_int 1)))
(clobber (match_operand:DI 2 "register_operand" "=b,b"))
""
""
[(set_attr "itanium_class" "ignore")
- (set_attr "predicable" "no")])
+ (set_attr "predicable" "no")
+ (set_attr "empty" "yes")])
;; Allocate a new register frame.
[(const_int 5)]
""
""
- [(set_attr "itanium_class" "nop_x")])
+ [(set_attr "itanium_class" "nop_x")
+ (set_attr "empty" "yes")])
;; The following insn will be never generated. It is used only by
;; insn scheduler to change state before advancing cycle.
""
";;"
[(set_attr "itanium_class" "stop_bit")
- (set_attr "predicable" "no")])
+ (set_attr "predicable" "no")
+ (set_attr "empty" "yes")])
(define_expand "trap"
[(trap_if (const_int 1) (const_int 0))]
"addp4_optimize_ok (operands[1], operands[2])"
"addp4 %0 = %1, %2"
[(set_attr "itanium_class" "ialu")])
+
+;; Vector operations
+(include "vect.md")
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