patch to fix extraneous nop at function start, bug from David Mosberger

[pf3gnuchains/gcc-fork.git] / gcc / config / ia64 / ia64.md

diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 9331d90..365c0a8 100644 (file)
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -78,6 +78,7 @@
    (UNSPEC_SETF_EXP             27)
    (UNSPEC_FR_SQRT_RECIP_APPROX 28)
    (UNSPEC_SHRP                        29)
+   (UNSPEC_COPYSIGN            30)
   ])
 
 (define_constants
@@ -162,6 +163,11 @@
 
 (define_attr "empty" "no,yes" (const_string "no"))
 
+;; True iff this insn must be the first insn of an instruction group.
+;; This is true for the alloc instruction, and will also be true of others
+;; when we have full intrinsics support.
+
+(define_attr "first_insn" "no,yes" (const_string "no"))
 \f
 ;; DFA descriptions of ia64 processors used for insn scheduling and
 ;; bundling.
@@ -2586,7 +2592,25 @@
   "fnegabs %0 = %1"
   [(set_attr "itanium_class" "fmisc")])
 
-(define_insn "minsf3"
+(define_insn "copysignsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+       (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
+                   (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")]
+                  UNSPEC_COPYSIGN))]
+  ""
+  "fmerge.s %0 = %F2, %F1"
+  [(set_attr "itanium_class" "fmisc")])
+
+(define_insn "*ncopysignsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+       (neg:SF (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
+                           (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")]
+                          UNSPEC_COPYSIGN)))]
+  ""
+  "fmerge.ns %0 = %F2, %F1"
+  [(set_attr "itanium_class" "fmisc")])
+
+(define_insn "sminsf3"
   [(set (match_operand:SF 0 "fr_register_operand" "=f")
        (smin:SF (match_operand:SF 1 "fr_register_operand" "f")
                 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
@@ -2594,7 +2618,7 @@
   "fmin %0 = %1, %F2"
   [(set_attr "itanium_class" "fmisc")])
 
-(define_insn "maxsf3"
+(define_insn "smaxsf3"
   [(set (match_operand:SF 0 "fr_register_operand" "=f")
        (smax:SF (match_operand:SF 1 "fr_register_operand" "f")
                 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
@@ -3000,7 +3024,25 @@
   "fnegabs %0 = %1"
   [(set_attr "itanium_class" "fmisc")])
 
-(define_insn "mindf3"
+(define_insn "copysigndf3"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+       (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
+                   (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")]
+                  UNSPEC_COPYSIGN))]
+  ""
+  "fmerge.s %0 = %F2, %F1"
+  [(set_attr "itanium_class" "fmisc")])
+
+(define_insn "*ncopysigndf3"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+       (neg:DF (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
+                           (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")]
+                          UNSPEC_COPYSIGN)))]
+  ""
+  "fmerge.ns %0 = %F2, %F1"
+  [(set_attr "itanium_class" "fmisc")])
+
+(define_insn "smindf3"
   [(set (match_operand:DF 0 "fr_register_operand" "=f")
        (smin:DF (match_operand:DF 1 "fr_register_operand" "f")
                 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
@@ -3008,7 +3050,7 @@
   "fmin %0 = %1, %F2"
   [(set_attr "itanium_class" "fmisc")])
 
-(define_insn "maxdf3"
+(define_insn "smaxdf3"
   [(set (match_operand:DF 0 "fr_register_operand" "=f")
        (smax:DF (match_operand:DF 1 "fr_register_operand" "f")
                 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
@@ -3556,7 +3598,25 @@
   "fnegabs %0 = %F1"
   [(set_attr "itanium_class" "fmisc")])
 
-(define_insn "minxf3"
+(define_insn "copysignxf3"
+  [(set (match_operand:XF 0 "register_operand" "=f")
+       (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
+                   (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")]
+                  UNSPEC_COPYSIGN))]
+  ""
+  "fmerge.s %0 = %F2, %F1"
+  [(set_attr "itanium_class" "fmisc")])
+
+(define_insn "*ncopysignxf3"
+  [(set (match_operand:XF 0 "register_operand" "=f")
+       (neg:XF (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
+                           (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")]
+                          UNSPEC_COPYSIGN)))]
+  ""
+  "fmerge.ns %0 = %F2, %F1"
+  [(set_attr "itanium_class" "fmisc")])
+
+(define_insn "sminxf3"
   [(set (match_operand:XF 0 "fr_register_operand" "=f")
        (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
                 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
@@ -3564,7 +3624,7 @@
   "fmin %0 = %F1, %F2"
   [(set_attr "itanium_class" "fmisc")])
 
-(define_insn "maxxf3"
+(define_insn "smaxxf3"
   [(set (match_operand:XF 0 "fr_register_operand" "=f")
        (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
                 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
@@ -5648,7 +5708,8 @@
   ""
   "alloc %0 = ar.pfs, %1, %2, %3, %4"
   [(set_attr "itanium_class" "syst_m0")
-   (set_attr "predicable" "no")])
+   (set_attr "predicable" "no")
+   (set_attr "first_insn" "yes")])
 
 ;; Modifies ar.unat
 (define_expand "gr_spill"