;; IA-64 Machine description template
-;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004
+;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
;; Free Software Foundation, Inc.
;; Contributed by James E. Wilson <wilson@cygnus.com> and
;; David Mosberger <davidm@hpl.hp.com>.
(UNSPEC_SETF_EXP 27)
(UNSPEC_FR_SQRT_RECIP_APPROX 28)
(UNSPEC_SHRP 29)
+ (UNSPEC_COPYSIGN 30)
])
(define_constants
(UNSPECV_PSAC_NORMAL 6)
(UNSPECV_SETJMP_RECEIVER 7)
])
-\f
-;; ::::::::::::::::::::
-;; ::
-;; :: Predicates
-;; ::
-;; ::::::::::::::::::::
-
-;; True if OP is a valid operand for the MEM of a CALL insn.
-(define_predicate "call_operand"
- (ior (match_code "symbol_ref")
- (match_operand 0 "register_operand")))
-
-;; True if OP refers to any kind of symbol.
-;; For roughly the same reasons that pmode_register_operand exists, this
-;; predicate ignores its mode argument.
-(define_special_predicate "symbolic_operand"
- (match_code "symbol_ref,const,label_ref"))
-
-;; True if OP is a SYMBOL_REF which refers to a function.
-(define_predicate "function_operand"
- (and (match_code "symbol_ref")
- (match_test "SYMBOL_REF_FUNCTION_P (op)")))
-
-;; True if OP refers to a symbol, and is appropriate for a GOT load.
-(define_predicate "got_symbolic_operand"
- (match_operand 0 "symbolic_operand" "")
-{
- switch (GET_CODE (op))
- {
- case LABEL_REF:
- return true;
-
- case SYMBOL_REF:
- /* This sort of load should not be used for things in sdata. */
- return !SYMBOL_REF_SMALL_ADDR_P (op);
-
- case CONST:
- /* Accept only (plus (symbol_ref) (const_int)). */
- op = XEXP (op, 0);
- if (GET_CODE (op) != PLUS
- || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
- || GET_CODE (XEXP (op, 1)) != CONST_INT)
- return false;
-
- /* Ok if we're not using GOT entries at all. */
- if (TARGET_NO_PIC || TARGET_AUTO_PIC)
- return true;
-
- /* The low 14 bits of the constant have been forced to zero
- by ia64_expand_load_address, so that we do not use up so
- many GOT entries. Prevent cse from undoing this. */
- op = XEXP (op, 1);
- return (INTVAL (op) & 0x3fff) == 0;
-
- default:
- abort ();
- }
-})
-
-;; True if OP refers to a symbol in the sdata section.
-(define_predicate "sdata_symbolic_operand"
- (match_code "symbol_ref,const")
-{
- switch (GET_CODE (op))
- {
- case CONST:
- op = XEXP (op, 0);
- if (GET_CODE (op) != PLUS
- || GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
- return false;
- op = XEXP (op, 0);
- /* FALLTHRU */
-
- case SYMBOL_REF:
- if (CONSTANT_POOL_ADDRESS_P (op))
- return GET_MODE_SIZE (get_pool_mode (op)) <= ia64_section_threshold;
- else
- return SYMBOL_REF_LOCAL_P (op) && SYMBOL_REF_SMALL_P (op);
-
- default:
- abort ();
- }
-})
-
-;; Like nonimmediate_operand, but don't allow MEMs that try to use a
-;; POST_MODIFY with a REG as displacement.
-(define_predicate "destination_operand"
- (and (match_operand 0 "nonimmediate_operand")
- (match_test "GET_CODE (op) != MEM
- || GET_CODE (XEXP (op, 0)) != POST_MODIFY
- || GET_CODE (XEXP (XEXP (XEXP (op, 0), 1), 1)) != REG")))
-
-;; Like memory_operand, but don't allow post-increments.
-(define_predicate "not_postinc_memory_operand"
- (and (match_operand 0 "memory_operand")
- (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
-
-;; True if OP is a general operand, excluding tls symbolic operands.
-(define_predicate "move_operand"
- (and (match_operand 0 "general_operand")
- (not (match_test
- "GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (op)"))))
-
-;; True if OP is a register operand that is (or could be) a GR reg.
-(define_predicate "gr_register_operand"
- (match_operand 0 "register_operand")
-{
- unsigned int regno;
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- regno = REGNO (op);
- return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
-})
-
-;; True if OP is a register operand that is (or could be) an FR reg.
-(define_predicate "fr_register_operand"
- (match_operand 0 "register_operand")
-{
- unsigned int regno;
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- regno = REGNO (op);
- return (regno >= FIRST_PSEUDO_REGISTER || FR_REGNO_P (regno));
-})
-
-;; True if OP is a register operand that is (or could be) a GR/FR reg.
-(define_predicate "grfr_register_operand"
- (match_operand 0 "register_operand")
-{
- unsigned int regno;
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- regno = REGNO (op);
- return (regno >= FIRST_PSEUDO_REGISTER
- || GENERAL_REGNO_P (regno)
- || FR_REGNO_P (regno));
-})
-
-;; True if OP is a nonimmediate operand that is (or could be) a GR reg.
-(define_predicate "gr_nonimmediate_operand"
- (match_operand 0 "nonimmediate_operand")
-{
- unsigned int regno;
-
- if (GET_CODE (op) == MEM)
- return true;
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- regno = REGNO (op);
- return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
-})
-
-;; True if OP is a nonimmediate operand that is (or could be) a FR reg.
-(define_predicate "fr_nonimmediate_operand"
- (match_operand 0 "nonimmediate_operand")
-{
- unsigned int regno;
-
- if (GET_CODE (op) == MEM)
- return true;
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- regno = REGNO (op);
- return (regno >= FIRST_PSEUDO_REGISTER || FR_REGNO_P (regno));
-})
-
-;; True if OP is a nonimmediate operand that is (or could be) a GR/FR reg.
-(define_predicate "grfr_nonimmediate_operand"
- (match_operand 0 "nonimmediate_operand")
-{
- unsigned int regno;
-
- if (GET_CODE (op) == MEM)
- return true;
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- regno = REGNO (op);
- return (regno >= FIRST_PSEUDO_REGISTER
- || GENERAL_REGNO_P (regno)
- || FR_REGNO_P (regno));
-})
-
-;; True if OP is a GR register operand, or zero.
-(define_predicate "gr_reg_or_0_operand"
- (ior (match_operand 0 "gr_register_operand")
- (and (match_code "const_int")
- (match_test "op == const0_rtx"))))
-
-;; True if OP is a GR register operand, or a 5 bit immediate operand.
-(define_predicate "gr_reg_or_5bit_operand"
- (ior (match_operand 0 "gr_register_operand")
- (and (match_code "const_int")
- (match_test "INTVAL (op) >= 0 && INTVAL (op) < 32"))))
-
-;; True if OP is a GR register operand, or a 6 bit immediate operand.
-(define_predicate "gr_reg_or_6bit_operand"
- (ior (match_operand 0 "gr_register_operand")
- (and (match_code "const_int")
- (match_test "CONST_OK_FOR_M (INTVAL (op))"))))
-
-;; True if OP is a GR register operand, or an 8 bit immediate operand.
-(define_predicate "gr_reg_or_8bit_operand"
- (ior (match_operand 0 "gr_register_operand")
- (and (match_code "const_int")
- (match_test "CONST_OK_FOR_K (INTVAL (op))"))))
-
-;; True if OP is a GR/FR register operand, or an 8 bit immediate operand.
-(define_predicate "grfr_reg_or_8bit_operand"
- (ior (match_operand 0 "grfr_register_operand")
- (and (match_code "const_int")
- (match_test "CONST_OK_FOR_K (INTVAL (op))"))))
-
-;; True if OP is a register operand, or an 8 bit adjusted immediate operand.
-(define_predicate "gr_reg_or_8bit_adjusted_operand"
- (ior (match_operand 0 "gr_register_operand")
- (and (match_code "const_int")
- (match_test "CONST_OK_FOR_L (INTVAL (op))"))))
-
-;; True if OP is a register operand, or is valid for both an 8 bit
-;; immediate and an 8 bit adjusted immediate operand. This is necessary
-;; because when we emit a compare, we don't know what the condition will be,
-;; so we need the union of the immediates accepted by GT and LT.
-(define_predicate "gr_reg_or_8bit_and_adjusted_operand"
- (ior (match_operand 0 "gr_register_operand")
- (and (match_code "const_int")
- (match_test "CONST_OK_FOR_K (INTVAL (op))
- && CONST_OK_FOR_L (INTVAL (op))"))))
-
-;; True if OP is a register operand, or a 14 bit immediate operand.
-(define_predicate "gr_reg_or_14bit_operand"
- (ior (match_operand 0 "gr_register_operand")
- (and (match_code "const_int")
- (match_test "CONST_OK_FOR_I (INTVAL (op))"))))
-
-;; True if OP is a register operand, or a 22 bit immediate operand.
-(define_predicate "gr_reg_or_22bit_operand"
- (ior (match_operand 0 "gr_register_operand")
- (and (match_code "const_int")
- (match_test "CONST_OK_FOR_J (INTVAL (op))"))))
-
-;; True if OP is a 7 bit immediate operand.
-(define_predicate "dshift_count_operand"
- (and (match_code "const_int")
- (match_test "INTVAL (op) >= 0 && INTVAL (op) < 128")))
-
-;; True if OP is a 6 bit immediate operand.
-(define_predicate "shift_count_operand"
- (and (match_code "const_int")
- (match_test "CONST_OK_FOR_M (INTVAL (op))")))
-
-;; True if OP is a 5 bit immediate operand.
-(define_predicate "shift_32bit_count_operand"
- (and (match_code "const_int")
- (match_test "INTVAL (op) >= 0 && INTVAL (op) < 32")))
-
-;; True if OP is one of the immediate values 2, 4, 8, or 16.
-(define_predicate "shladd_operand"
- (and (match_code "const_int")
- (match_test "INTVAL (op) == 2 || INTVAL (op) == 4 ||
- INTVAL (op) == 8 || INTVAL (op) == 16")))
-
-;; True if OP is one of the immediate values -16, -8, -4, -1, 1, 4, 8, 16.
-(define_predicate "fetchadd_operand"
- (and (match_code "const_int")
- (match_test "INTVAL (op) == -16 || INTVAL (op) == -8 ||
- INTVAL (op) == -4 || INTVAL (op) == -1 ||
- INTVAL (op) == 1 || INTVAL (op) == 4 ||
- INTVAL (op) == 8 || INTVAL (op) == 16")))
-
-
-;; True if OP is a floating-point constant zero, one, or a register.
-(define_predicate "fr_reg_or_fp01_operand"
- (ior (match_operand 0 "fr_register_operand")
- (and (match_code "const_double")
- (match_test "CONST_DOUBLE_OK_FOR_G (op)"))))
-
-;; Like fr_reg_or_fp01_operand, but don't allow any SUBREGs.
-(define_predicate "xfreg_or_fp01_operand"
- (and (match_operand 0 "fr_reg_or_fp01_operand")
- (not (match_code "subreg"))))
-
-;; True if this is a comparison operator, which accepts a normal 8-bit
-;; signed immediate operand.
-(define_predicate "normal_comparison_operator"
- (match_code "eq,ne,gt,le,gtu,leu"))
-
-;; True if this is a comparison operator, which accepts an adjusted 8-bit
-;; signed immediate operand.
-(define_predicate "adjusted_comparison_operator"
- (match_code "lt,ge,ltu,geu"))
-
-;; True if this is a signed inequality operator.
-(define_predicate "signed_inequality_operator"
- (match_code "ge,gt,le,lt"))
-
-;; True if this operator is valid for predication.
-(define_predicate "predicate_operator"
- (match_code "eq,ne"))
-
-;; True if this operator can be used in a conditional operation.
-(define_predicate "condop_operator"
- (match_code "plus,minus,ior,xor,and"))
-
-;; These three are hardware registers that can only be addressed in
-;; DImode. It's not strictly necessary to test mode == DImode here,
-;; but it makes decent insurance against someone writing a
-;; match_operand wrong.
-
-;; True if this is the ar.lc register.
-(define_predicate "ar_lc_reg_operand"
- (and (match_code "reg")
- (match_test "mode == DImode && REGNO (op) == AR_LC_REGNUM")))
-
-;; True if this is the ar.ccv register.
-(define_predicate "ar_ccv_reg_operand"
- (and (match_code "reg")
- (match_test "mode == DImode && REGNO (op) == AR_CCV_REGNUM")))
-
-;; True if this is the ar.pfs register.
-(define_predicate "ar_pfs_reg_operand"
- (and (match_code "reg")
- (match_test "mode == DImode && REGNO (op) == AR_PFS_REGNUM")))
-
-;; True if OP is valid as a base register in a reg + offset address.
-;; ??? Should I copy the flag_omit_frame_pointer and cse_not_expected
-;; checks from pa.c basereg_operand as well? Seems to be OK without them
-;; in test runs.
-(define_predicate "basereg_operand"
- (match_operand 0 "register_operand")
-{
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
- return REG_POINTER (op);
-})
+(include "predicates.md")
\f
;; ::::::::::::::::::::
;; ::
(define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,
fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,
- chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,
- syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,nop_b,nop_f,
- nop_i,nop_m,nop_x,lfetch,pre_cycle"
+ chk_s,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,
+ st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,
+ nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle"
(const_string "unknown"))
;; chk_s has an I and an M form; use type A for convenience.
(eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M")
(eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M")
(eq_attr "itanium_class" "lfetch") (const_string "M")
- (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog") (const_string "A")
+ (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog,mmalua")
+ (const_string "A")
(eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F")
(eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F")
(eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I")
(define_attr "empty" "no,yes" (const_string "no"))
-\f
+;; True iff this insn must be the first insn of an instruction group.
+;; This is true for the alloc instruction, and will also be true of others
+;; when we have full intrinsics support.
+(define_attr "first_insn" "no,yes" (const_string "no"))
+\f
;; DFA descriptions of ia64 processors used for insn scheduling and
;; bundling.
(automata_option "w")
-;;(automata_option "no-minimization")
-
-
(include "itanium1.md")
(include "itanium2.md")
if (GET_CODE (op0) == SUBREG)
op0 = SUBREG_REG (op0);
- /* We must support XFmode loads into general registers for stdarg/vararg
- and unprototyped calls. We split them into DImode loads for convenience.
- We don't need XFmode stores from general regs, because a stdarg/vararg
- routine does a block store to memory of unnamed arguments. */
+ /* We must support XFmode loads into general registers for stdarg/vararg,
+ unprototyped calls, and a rare case where a long double is passed as
+ an argument after a float HFA fills the FP registers. We split them into
+ DImode loads for convenience. We also need to support XFmode stores
+ for the last case. This case does not happen for stdarg/vararg routines,
+ because we do a block store to memory of unnamed arguments. */
if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
{
if (GET_CODE (op1) == SUBREG)
op1 = SUBREG_REG (op1);
else
- /* ??? Maybe we should make a SUBREG here? */
op1 = gen_rtx_REG (TImode, REGNO (op1));
emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1);
abort ();
}
+ if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1])))
+ {
+ /* We're hoping to transform everything that deals with XFmode
+ quantities and GR registers early in the compiler. */
+ if (no_new_pseudos)
+ abort ();
+
+ /* Op0 can't be a GR_REG here, as that case is handled above.
+ If op0 is a register, then we spill op1, so that we now have a
+ MEM operand. This requires creating an XFmode subreg of a TImode reg
+ to force the spill. */
+ if (register_operand (operands[0], XFmode))
+ {
+ rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1]));
+ op1 = gen_rtx_SUBREG (XFmode, op1, 0);
+ operands[1] = spill_xfmode_operand (op1, 0);
+ }
+
+ else if (GET_CODE (operands[0]) == MEM)
+ {
+ rtx in[2];
+
+ in[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[1]));
+ in[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
+
+ emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]);
+ emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]);
+ DONE;
+ }
+
+ else
+ abort ();
+ }
+
if (! reload_in_progress && ! reload_completed)
{
operands[1] = spill_xfmode_operand (operands[1], 0);
})
(define_insn_and_split "*movtf_internal"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=r,r,m")
+ [(set (match_operand:TF 0 "destination_operand" "=r,r,m")
(match_operand:TF 1 "general_operand" "ri,m,r"))]
"ia64_move_ok (operands[0], operands[1])"
"#"
(match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))]
""
"@
- zxt4 %0 = %1
+ addp4 %0 = %1, r0
ld4%O1 %0 = %1%P1
fmix.r %0 = f0, %1"
- [(set_attr "itanium_class" "xtd,ld,fmisc")])
+ [(set_attr "itanium_class" "ialu,ld,fmisc")])
;; Convert between floating point types of different sizes.
[(set_attr "itanium_class" "ishf")])
;; Combine doesn't like to create bit-field insertions into zero.
+(define_insn "*shladdp4_internal"
+ [(set (match_operand:DI 0 "gr_register_operand" "=r")
+ (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
+ (match_operand:DI 2 "shladd_log2_operand" "n"))
+ (match_operand:DI 3 "const_int_operand" "n")))]
+ "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL (operands[2]) == 32"
+ "shladdp4 %0 = %1, %2, r0"
+ [(set_attr "itanium_class" "ialu")])
+
(define_insn "*depz_internal"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
"fnegabs %0 = %1"
[(set_attr "itanium_class" "fmisc")])
-(define_insn "minsf3"
+(define_insn "copysignsf3"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")]
+ UNSPEC_COPYSIGN))]
+ ""
+ "fmerge.s %0 = %F2, %F1"
+ [(set_attr "itanium_class" "fmisc")])
+
+(define_insn "*ncopysignsf3"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (neg:SF (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")]
+ UNSPEC_COPYSIGN)))]
+ ""
+ "fmerge.ns %0 = %F2, %F1"
+ [(set_attr "itanium_class" "fmisc")])
+
+(define_insn "sminsf3"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(smin:SF (match_operand:SF 1 "fr_register_operand" "f")
(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
"fmin %0 = %1, %F2"
[(set_attr "itanium_class" "fmisc")])
-(define_insn "maxsf3"
+(define_insn "smaxsf3"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(smax:SF (match_operand:SF 1 "fr_register_operand" "f")
(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
"fnegabs %0 = %1"
[(set_attr "itanium_class" "fmisc")])
-(define_insn "mindf3"
+(define_insn "copysigndf3"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")]
+ UNSPEC_COPYSIGN))]
+ ""
+ "fmerge.s %0 = %F2, %F1"
+ [(set_attr "itanium_class" "fmisc")])
+
+(define_insn "*ncopysigndf3"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (neg:DF (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")]
+ UNSPEC_COPYSIGN)))]
+ ""
+ "fmerge.ns %0 = %F2, %F1"
+ [(set_attr "itanium_class" "fmisc")])
+
+(define_insn "smindf3"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(smin:DF (match_operand:DF 1 "fr_register_operand" "f")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
"fmin %0 = %1, %F2"
[(set_attr "itanium_class" "fmisc")])
-(define_insn "maxdf3"
+(define_insn "smaxdf3"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(smax:DF (match_operand:DF 1 "fr_register_operand" "f")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
"fnegabs %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
-(define_insn "minxf3"
+(define_insn "copysignxf3"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")]
+ UNSPEC_COPYSIGN))]
+ ""
+ "fmerge.s %0 = %F2, %F1"
+ [(set_attr "itanium_class" "fmisc")])
+
+(define_insn "*ncopysignxf3"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (neg:XF (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")]
+ UNSPEC_COPYSIGN)))]
+ ""
+ "fmerge.ns %0 = %F2, %F1"
+ [(set_attr "itanium_class" "fmisc")])
+
+(define_insn "sminxf3"
[(set (match_operand:XF 0 "fr_register_operand" "=f")
(smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
(match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
"fmin %0 = %F1, %F2"
[(set_attr "itanium_class" "fmisc")])
-(define_insn "maxxf3"
+(define_insn "smaxxf3"
[(set (match_operand:XF 0 "fr_register_operand" "=f")
(smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
(match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
;; ::
;; ::::::::::::::::::::
+(define_expand "ashlti3"
+ [(set (match_operand:TI 0 "gr_register_operand" "")
+ (ashift:TI (match_operand:TI 1 "gr_register_operand" "")
+ (match_operand:DI 2 "nonmemory_operand" "")))]
+ ""
+{
+ if (!dshift_count_operand (operands[2], DImode))
+ FAIL;
+})
+
+(define_insn_and_split "*ashlti3_internal"
+ [(set (match_operand:TI 0 "gr_register_operand" "=&r")
+ (ashift:TI (match_operand:TI 1 "gr_register_operand" "r")
+ (match_operand:DI 2 "dshift_count_operand" "n")))]
+ ""
+ "#"
+ "reload_completed"
+ [(const_int 0)]
+{
+ HOST_WIDE_INT shift = INTVAL (operands[2]);
+ rtx rl = gen_lowpart (DImode, operands[0]);
+ rtx rh = gen_highpart (DImode, operands[0]);
+ rtx lo = gen_lowpart (DImode, operands[1]);
+ rtx shiftlo = GEN_INT (shift & 63);
+
+ if (shift & 64)
+ {
+ emit_move_insn (rl, const0_rtx);
+ if (shift & 63)
+ emit_insn (gen_ashldi3 (rh, lo, shiftlo));
+ else
+ emit_move_insn (rh, lo);
+ }
+ else
+ {
+ rtx hi = gen_highpart (DImode, operands[1]);
+
+ emit_insn (gen_shrp (rh, hi, lo, GEN_INT (-shift & 63)));
+ emit_insn (gen_ashldi3 (rl, lo, shiftlo));
+ }
+ DONE;
+})
+
(define_expand "ashrti3"
[(set (match_operand:TI 0 "gr_register_operand" "")
(ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "")
})
(define_insn_and_split "*ashrti3_internal"
- [(set (match_operand:TI 0 "gr_register_operand" "=r")
+ [(set (match_operand:TI 0 "gr_register_operand" "=&r")
(ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r")
(match_operand:DI 2 "dshift_count_operand" "n")))]
""
[(const_int 0)]
{
HOST_WIDE_INT shift = INTVAL (operands[2]);
- rtx lo = gen_lowpart (DImode, operands[1]);
+ rtx rl = gen_lowpart (DImode, operands[0]);
+ rtx rh = gen_highpart (DImode, operands[0]);
rtx hi = gen_highpart (DImode, operands[1]);
rtx shiftlo = GEN_INT (shift & 63);
if (shift & 64)
{
- emit_insn (gen_ashrdi3 (lo, hi, shiftlo));
- emit_insn (gen_ashrdi3 (hi, hi, GEN_INT (63)));
+ if (shift & 63)
+ emit_insn (gen_ashrdi3 (rl, hi, shiftlo));
+ else
+ emit_move_insn (rl, hi);
+ emit_insn (gen_ashrdi3 (rh, hi, GEN_INT (63)));
}
else
{
- emit_insn (gen_shrp (lo, hi, lo, shiftlo));
- emit_insn (gen_ashrdi3 (hi, hi, shiftlo));
+ rtx lo = gen_lowpart (DImode, operands[1]);
+
+ emit_insn (gen_shrp (rl, hi, lo, shiftlo));
+ emit_insn (gen_ashrdi3 (rh, hi, shiftlo));
}
DONE;
})
})
(define_insn_and_split "*lshrti3_internal"
- [(set (match_operand:TI 0 "gr_register_operand" "=r")
+ [(set (match_operand:TI 0 "gr_register_operand" "=&r")
(lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r")
(match_operand:DI 2 "dshift_count_operand" "n")))]
""
[(const_int 0)]
{
HOST_WIDE_INT shift = INTVAL (operands[2]);
- rtx lo = gen_lowpart (DImode, operands[1]);
+ rtx rl = gen_lowpart (DImode, operands[0]);
+ rtx rh = gen_highpart (DImode, operands[0]);
rtx hi = gen_highpart (DImode, operands[1]);
rtx shiftlo = GEN_INT (shift & 63);
if (shift & 64)
{
- emit_insn (gen_lshrdi3 (lo, hi, shiftlo));
- emit_move_insn (hi, const0_rtx);
+ if (shift & 63)
+ emit_insn (gen_lshrdi3 (rl, hi, shiftlo));
+ else
+ emit_move_insn (rl, hi);
+ emit_move_insn (rh, const0_rtx);
}
else
{
- emit_insn (gen_shrp (lo, hi, lo, shiftlo));
- emit_insn (gen_lshrdi3 (hi, hi, shiftlo));
+ rtx lo = gen_lowpart (DImode, operands[1]);
+
+ emit_insn (gen_shrp (rl, hi, lo, shiftlo));
+ emit_insn (gen_lshrdi3 (rh, hi, shiftlo));
}
DONE;
})
""
"alloc %0 = ar.pfs, %1, %2, %3, %4"
[(set_attr "itanium_class" "syst_m0")
- (set_attr "predicable" "no")])
+ (set_attr "predicable" "no")
+ (set_attr "first_insn" "yes")])
;; Modifies ar.unat
(define_expand "gr_spill"
"addp4_optimize_ok (operands[1], operands[2])"
"addp4 %0 = %1, %2"
[(set_attr "itanium_class" "ialu")])
+
+;; Vector operations
+(include "vect.md")
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