;; GCC machine description for i386 synchronization instructions.
-;; Copyright (C) 2005, 2006, 2007, 2008, 2009
+;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010
;; Free Software Foundation, Inc.
;;
;; This file is part of GCC.
(unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))
(clobber (reg:CC FLAGS_REG))]
"!(TARGET_64BIT || TARGET_SSE2)"
- "lock{%;| }or{l}\t{$0, (%%esp)|DWORD PTR [esp], 0}"
+ "lock{%;} or{l}\t{$0, (%%esp)|DWORD PTR [esp], 0}"
[(set_attr "memory" "unknown")])
;; ??? It would be possible to use cmpxchg8b on pentium for DImode
[(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG)
(match_dup 2)))]
"TARGET_CMPXCHG"
- "lock{%;| }cmpxchg{<imodesuffix>}\t{%3, %1|%1, %3}")
+ "lock{%;} cmpxchg{<imodesuffix>}\t{%3, %1|%1, %3}")
(define_insn "sync_double_compare_and_swap<mode>"
[(set (match_operand:DCASMODE 0 "register_operand" "=A")
UNSPECV_CMPXCHG)
(match_dup 2)))]
""
- "lock{%;| }cmpxchg<doublemodesuffix>b\t%1")
+ "lock{%;} cmpxchg<doublemodesuffix>b\t%1")
;; Theoretically we'd like to use constraint "r" (any reg) for operand
;; 3, but that includes ecx. If operand 3 and 4 are the same (like when
UNSPECV_CMPXCHG)
(match_dup 2)))]
"!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic"
- "xchg{l}\t%%ebx, %3\;lock{%;| }cmpxchg8b\t%1\;xchg{l}\t%%ebx, %3")
+ "xchg{l}\t%%ebx, %3\;lock{%;} cmpxchg8b\t%1\;xchg{l}\t%%ebx, %3")
(define_insn "sync_old_add<mode>"
[(set (match_operand:SWI 0 "register_operand" "=<r>")
(match_operand:SWI 2 "register_operand" "0")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_XADD"
- "lock{%;| }xadd{<imodesuffix>}\t{%0, %1|%1, %0}")
+ "lock{%;} xadd{<imodesuffix>}\t{%0, %1|%1, %0}")
;; Recall that xchg implicitly sets LOCK#, so adding it again wastes space.
(define_insn "sync_lock_test_and_set<mode>"
if (TARGET_USE_INCDEC)
{
if (operands[1] == const1_rtx)
- return "lock{%;| }inc{<imodesuffix>}\t%0";
+ return "lock{%;} inc{<imodesuffix>}\t%0";
if (operands[1] == constm1_rtx)
- return "lock{%;| }dec{<imodesuffix>}\t%0";
+ return "lock{%;} dec{<imodesuffix>}\t%0";
}
if (x86_maybe_negate_const_int (&operands[1], <MODE>mode))
- return "lock{%;| }sub{<imodesuffix>}\t{%1, %0|%0, %1}";
+ return "lock{%;} sub{<imodesuffix>}\t{%1, %0|%0, %1}";
- return "lock{%;| }add{<imodesuffix>}\t{%1, %0|%0, %1}";
+ return "lock{%;} add{<imodesuffix>}\t{%1, %0|%0, %1}";
})
(define_insn "sync_sub<mode>"
if (TARGET_USE_INCDEC)
{
if (operands[1] == const1_rtx)
- return "lock{%;| }dec{<imodesuffix>}\t%0";
+ return "lock{%;} dec{<imodesuffix>}\t%0";
if (operands[1] == constm1_rtx)
- return "lock{%;| }inc{<imodesuffix>}\t%0";
+ return "lock{%;} inc{<imodesuffix>}\t%0";
}
- return "lock{%;| }sub{<imodesuffix>}\t{%1, %0|%0, %1}";
+ return "lock{%;} sub{<imodesuffix>}\t{%1, %0|%0, %1}";
})
(define_insn "sync_<code><mode>"
UNSPECV_LOCK))
(clobber (reg:CC FLAGS_REG))]
""
- "lock{%;| }<logic>{<imodesuffix>}\t{%1, %0|%0, %1}")
+ "lock{%;} <logic>{<imodesuffix>}\t{%1, %0|%0, %1}")