;; GCC machine description for SSE instructions
-;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010
+;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011
;; Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
+;; All vector modes including V1TImode, used in move patterns.
+(define_mode_iterator V16
+ [(V32QI "TARGET_AVX") V16QI
+ (V16HI "TARGET_AVX") V8HI
+ (V8SI "TARGET_AVX") V4SI
+ (V4DI "TARGET_AVX") V2DI
+ V1TI
+ (V8SF "TARGET_AVX") V4SF
+ (V4DF "TARGET_AVX") V2DF])
+
+;; All vector modes
+(define_mode_iterator V
+ [(V32QI "TARGET_AVX") V16QI
+ (V16HI "TARGET_AVX") V8HI
+ (V8SI "TARGET_AVX") V4SI
+ (V4DI "TARGET_AVX") V2DI
+ (V8SF "TARGET_AVX") V4SF
+ (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")])
+
+;; All 128bit vector modes
+(define_mode_iterator V_128
+ [V16QI V8HI V4SI V2DI V4SF (V2DF "TARGET_SSE2")])
+
+;; All 256bit vector modes
+(define_mode_iterator V_256
+ [V32QI V16HI V8SI V4DI V8SF V4DF])
+
+;; All vector float modes
+(define_mode_iterator VF
+ [(V8SF "TARGET_AVX") V4SF
+ (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")])
+
+;; All SFmode vector float modes
+(define_mode_iterator VF1
+ [(V8SF "TARGET_AVX") V4SF])
+
+;; All DFmode vector float modes
+(define_mode_iterator VF2
+ [(V4DF "TARGET_AVX") V2DF])
+
+;; All 128bit vector float modes
+(define_mode_iterator VF_128
+ [V4SF (V2DF "TARGET_SSE2")])
+
+;; All 256bit vector float modes
+(define_mode_iterator VF_256
+ [V8SF V4DF])
+
+;; All vector integer modes
+(define_mode_iterator VI
+ [(V32QI "TARGET_AVX") V16QI
+ (V16HI "TARGET_AVX") V8HI
+ (V8SI "TARGET_AVX") V4SI
+ (V4DI "TARGET_AVX") V2DI])
+
+;; All QImode vector integer modes
+(define_mode_iterator VI1
+ [(V32QI "TARGET_AVX") V16QI])
+
+;; All DImode vector integer modes
+(define_mode_iterator VI8
+ [(V4DI "TARGET_AVX") V2DI])
+
+;; All 128bit vector integer modes
+(define_mode_iterator VI_128 [V16QI V8HI V4SI V2DI])
+
+;; Random 128bit vector integer mode combinations
+(define_mode_iterator VI12_128 [V16QI V8HI])
+(define_mode_iterator VI14_128 [V16QI V4SI])
+(define_mode_iterator VI124_128 [V16QI V8HI V4SI])
+(define_mode_iterator VI24_128 [V8HI V4SI])
+(define_mode_iterator VI248_128 [V8HI V4SI V2DI])
-;; Instruction suffix for sign and zero extensions.
-(define_code_attr extsuffix [(sign_extend "sx") (zero_extend "zx")])
-
-;; 16 byte integral modes handled by SSE
-(define_mode_iterator SSEMODEI [V16QI V8HI V4SI V2DI])
-
-;; All 16-byte vector modes handled by SSE
-(define_mode_iterator SSEMODE [V16QI V8HI V4SI V2DI V4SF V2DF])
-(define_mode_iterator SSEMODE16 [V16QI V8HI V4SI V2DI V1TI V4SF V2DF])
-
-;; 32 byte integral vector modes handled by AVX
-(define_mode_iterator AVX256MODEI [V32QI V16HI V8SI V4DI])
-
-;; All 32-byte vector modes handled by AVX
-(define_mode_iterator AVX256MODE [V32QI V16HI V8SI V4DI V8SF V4DF])
-
-;; All QI vector modes handled by AVX
-(define_mode_iterator AVXMODEQI [V32QI V16QI])
-
-;; All DI vector modes handled by AVX
-(define_mode_iterator AVXMODEDI [V4DI V2DI])
-
-;; All vector modes handled by AVX
-(define_mode_iterator AVXMODE
- [V16QI V8HI V4SI V2DI V4SF V2DF V32QI V16HI V8SI V4DI V8SF V4DF])
-(define_mode_iterator AVXMODE16
- [V16QI V8HI V4SI V2DI V1TI V4SF V2DF V32QI V16HI V8SI V4DI V8SF V4DF])
-
-;; Mix-n-match
-(define_mode_iterator SSEMODE12 [V16QI V8HI])
-(define_mode_iterator SSEMODE24 [V8HI V4SI])
-(define_mode_iterator SSEMODE14 [V16QI V4SI])
-(define_mode_iterator SSEMODE124 [V16QI V8HI V4SI])
-(define_mode_iterator SSEMODE248 [V8HI V4SI V2DI])
-(define_mode_iterator SSEMODE1248 [V16QI V8HI V4SI V2DI])
-(define_mode_iterator SSEMODEF4 [SF DF V4SF V2DF])
-(define_mode_iterator SSEMODEF2P [V4SF V2DF])
-
-(define_mode_iterator AVX256MODEF2P [V8SF V4DF])
-(define_mode_iterator AVX256MODE2P [V8SI V8SF V4DF])
-(define_mode_iterator AVX256MODE24P [V8SI V8SF V4DI V4DF])
-(define_mode_iterator AVX256MODE4P [V4DI V4DF])
-(define_mode_iterator AVX256MODE8P [V8SI V8SF])
-(define_mode_iterator AVXMODEF2P [V4SF V2DF V8SF V4DF])
-(define_mode_iterator AVXMODEF4P [V4SF V4DF])
-(define_mode_iterator AVXMODEFDP [V2DF V4DF])
-(define_mode_iterator AVXMODEFSP [V4SF V8SF])
-(define_mode_iterator AVXMODEDCVTDQ2PS [V4SF V8SF])
-(define_mode_iterator AVXMODEDCVTPS2DQ [V4SI V8SI])
+;; Int-float size matches
+(define_mode_iterator VI4F_128 [V4SI V4SF])
+(define_mode_iterator VI8F_128 [V2DI V2DF])
+(define_mode_iterator VI4F_256 [V8SI V8SF])
+(define_mode_iterator VI8F_256 [V4DI V4DF])
-(define_mode_iterator FMAMODE [SF DF V4SF V2DF V8SF V4DF])
+;; Mapping from float mode to required SSE level
+(define_mode_attr sse
+ [(SF "sse") (DF "sse2")
+ (V4SF "sse") (V2DF "sse2")
+ (V8SF "avx") (V4DF "avx")])
+
+(define_mode_attr sse2
+ [(V16QI "sse2") (V32QI "avx")
+ (V2DI "sse2") (V4DI "avx")])
+
+(define_mode_attr sse3
+ [(V16QI "sse3") (V32QI "avx")])
+
+(define_mode_attr sse4_1
+ [(V4SF "sse4_1") (V2DF "sse4_1")
+ (V8SF "avx") (V4DF "avx")])
+
+(define_mode_attr avxsizesuffix
+ [(V32QI "256") (V16HI "256") (V8SI "256") (V4DI "256")
+ (V16QI "") (V8HI "") (V4SI "") (V2DI "")
+ (V8SF "256") (V4DF "256")
+ (V4SF "") (V2DF "")])
+
+;; SSE instruction mode
+(define_mode_attr sseinsnmode
+ [(V32QI "OI") (V16HI "OI") (V8SI "OI") (V4DI "OI")
+ (V16QI "TI") (V8HI "TI") (V4SI "TI") (V2DI "TI") (V1TI "TI")
+ (V8SF "V8SF") (V4DF "V4DF")
+ (V4SF "V4SF") (V2DF "V2DF")])
+
+;; Mapping of vector float modes to an integer mode of the same size
+(define_mode_attr sseintvecmode
+ [(V8SF "V8SI") (V4DF "V4DI")
+ (V4SF "V4SI") (V2DF "V2DI")])
-;; Int-float size matches
-(define_mode_iterator SSEMODE4S [V4SF V4SI])
-(define_mode_iterator SSEMODE2D [V2DF V2DI])
+;; Mapping of vector modes to a vector mode of double size
+(define_mode_attr ssedoublevecmode
+ [(V32QI "V64QI") (V16HI "V32HI") (V8SI "V16SI") (V4DI "V8DI")
+ (V16QI "V32QI") (V8HI "V16HI") (V4SI "V8SI") (V2DI "V4DI")
+ (V8SF "V16SF") (V4DF "V8DF")
+ (V4SF "V8SF") (V2DF "V4DF")])
+
+;; Mapping of vector modes to a vector mode of half size
+(define_mode_attr ssehalfvecmode
+ [(V32QI "V16QI") (V16HI "V8HI") (V8SI "V4SI") (V4DI "V2DI")
+ (V16QI "V8QI") (V8HI "V4HI") (V4SI "V2SI")
+ (V8SF "V4SF") (V4DF "V2DF")
+ (V4SF "V2SF")])
-;; Modes handled by integer vcond pattern
-(define_mode_iterator SSEMODE124C8 [V16QI V8HI V4SI
- (V2DI "TARGET_SSE4_2")])
+;; Mapping of vector modes back to the scalar modes
+(define_mode_attr ssescalarmode
+ [(V32QI "QI") (V16HI "HI") (V8SI "SI") (V4DI "DI")
+ (V16QI "QI") (V8HI "HI") (V4SI "SI") (V2DI "DI")
+ (V8SF "SF") (V4DF "DF")
+ (V4SF "SF") (V2DF "DF")])
-;; Modes handled by vec_extract_even/odd pattern.
-(define_mode_iterator SSEMODE_EO
- [(V4SF "TARGET_SSE")
- (V2DF "TARGET_SSE2")
- (V2DI "TARGET_SSE2") (V4SI "TARGET_SSE2")
- (V8HI "TARGET_SSE2") (V16QI "TARGET_SSE2")
- (V4DF "TARGET_AVX") (V8SF "TARGET_AVX")])
+;; Number of scalar elements in each vector type
+(define_mode_attr ssescalarnum
+ [(V32QI "32") (V16HI "16") (V8SI "8") (V4DI "4")
+ (V16QI "16") (V8HI "8") (V4SI "4") (V2DI "2")
+ (V8SF "8") (V4DF "4")
+ (V4SF "4") (V2DF "2")])
-;; Modes handled by storent patterns.
-(define_mode_iterator STORENT_MODE
- [(SF "TARGET_SSE4A") (DF "TARGET_SSE4A")
- (SI "TARGET_SSE2") (V2DI "TARGET_SSE2") (V2DF "TARGET_SSE2")
- (V4SF "TARGET_SSE")
- (V4DF "TARGET_AVX") (V8SF "TARGET_AVX")])
+;; SSE scalar suffix for vector modes
+(define_mode_attr ssescalarmodesuffix
+ [(V8SF "ss") (V4DF "sd")
+ (V4SF "ss") (V2DF "sd")
+ (V8SI "ss") (V4DI "sd")
+ (V4SI "d")])
-;; Modes handled by vector float patterns.
-(define_mode_iterator VEC_FLOAT_MODE
- [(V2DF "TARGET_SSE2") (V4SF "TARGET_SSE")
- (V4DF "TARGET_AVX") (V8SF "TARGET_AVX")])
+;; Pack/unpack vector modes
+(define_mode_attr sseunpackmode
+ [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")])
-;; Modes handled by vector extract patterns.
-(define_mode_iterator VEC_EXTRACT_MODE
- [(V2DI "TARGET_SSE") (V4SI "TARGET_SSE")
- (V8HI "TARGET_SSE") (V16QI "TARGET_SSE")
- (V2DF "TARGET_SSE") (V4SF "TARGET_SSE")
- (V4DF "TARGET_AVX") (V8SF "TARGET_AVX")])
+(define_mode_attr ssepackmode
+ [(V8HI "V16QI") (V4SI "V8HI") (V2DI "V4SI")])
-;; Mapping from float mode to required SSE level
-(define_mode_attr sse [(SF "sse") (DF "sse2") (V4SF "sse") (V2DF "sse2")])
+;; Mapping of the max integer size for xop rotate immediate constraint
+(define_mode_attr sserotatemax
+ [(V16QI "7") (V8HI "15") (V4SI "31") (V2DI "63")])
-;; Mapping from integer vector mode to mnemonic suffix
-(define_mode_attr ssevecsize [(V16QI "b") (V8HI "w") (V4SI "d") (V2DI "q")])
+;; Mapping of mode to cast intrinsic name
+(define_mode_attr castmode [(V8SI "si") (V8SF "ps") (V4DF "pd")])
-;; Mapping of the insn mnemonic suffix
-(define_mode_attr ssemodesuffix
- [(SF "ss") (DF "sd") (V4SF "ps") (V2DF "pd") (V8SF "ps") (V4DF "pd")
- (V8SI "ps") (V4DI "pd")])
-(define_mode_attr ssescalarmodesuffix
- [(SF "ss") (DF "sd") (V4SF "ss") (V2DF "sd") (V8SF "ss") (V8SI "ss")
- (V4DF "sd") (V4SI "d") (V4DI "sd")])
+;; Instruction suffix for sign and zero extensions.
+(define_code_attr extsuffix [(sign_extend "sx") (zero_extend "zx")])
-;; Mapping of the max integer size for xop rotate immediate constraint
-(define_mode_attr sserotatemax [(V16QI "7") (V8HI "15") (V4SI "31") (V2DI "63")])
-;; Mapping of vector modes back to the scalar modes
-(define_mode_attr ssescalarmode [(V4SF "SF") (V2DF "DF")
- (V16QI "QI") (V8HI "HI")
- (V4SI "SI") (V2DI "DI")])
-;; Mapping of vector modes to a vector mode of double size
-(define_mode_attr ssedoublesizemode
- [(V2DF "V4DF") (V2DI "V4DI") (V4SF "V8SF") (V4SI "V8SI")
- (V8HI "V16HI") (V16QI "V32QI")
- (V4DF "V8DF") (V8SF "V16SF")
- (V4DI "V8DI") (V8SI "V16SI") (V16HI "V32HI") (V32QI "V64QI")])
+;; Mix-n-match
+(define_mode_iterator AVX256MODE2P [V8SI V8SF V4DF])
-;; Number of scalar elements in each vector type
-(define_mode_attr ssescalarnum
- [(V4SF "4") (V2DF "2") (V16QI "16") (V8HI "8") (V4SI "4") (V2DI "2")
- (V8SF "8") (V4DF "4") (V32QI "32") (V16HI "16") (V8SI "8") (V4DI "4")])
-
-;; Mapping for AVX
-(define_mode_attr avxvecmode
- [(V16QI "TI") (V8HI "TI") (V4SI "TI") (V2DI "TI") (V1TI "TI")
- (V4SF "V4SF") (V8SF "V8SF") (V2DF "V2DF") (V4DF "V4DF")
- (V32QI "OI") (V16HI "OI") (V8SI "OI") (V4DI "OI")])
-(define_mode_attr avxvecpsmode
- [(V16QI "V4SF") (V8HI "V4SF") (V4SI "V4SF") (V2DI "V4SF")
- (V32QI "V8SF") (V16HI "V8SF") (V8SI "V8SF") (V4DI "V8SF")])
-(define_mode_attr avxhalfvecmode
- [(V32QI "V16QI") (V16HI "V8HI") (V8SI "V4SI") (V4DI "V2DI")
- (V8SF "V4SF") (V4DF "V2DF")
- (V16QI "V8QI") (V8HI "V4HI") (V4SI "V2SI") (V4SF "V2SF")])
-(define_mode_attr avxscalarmode
- [(V16QI "QI") (V8HI "HI") (V4SI "SI") (V2DI "DI") (V4SF "SF") (V2DF "DF")
- (V32QI "QI") (V16HI "HI") (V8SI "SI") (V4DI "DI") (V8SF "SF") (V4DF "DF")])
-(define_mode_attr avxcvtvecmode
- [(V4SF "V4SI") (V8SF "V8SI") (V4SI "V4SF") (V8SI "V8SF")])
-(define_mode_attr avxpermvecmode
- [(V2DF "V2DI") (V4SF "V4SI") (V4DF "V4DI") (V8SF "V8SI")])
-(define_mode_attr avxmodesuffixp
- [(V2DF "pd") (V4SI "si") (V4SF "ps") (V8SF "ps") (V8SI "si")
- (V4DF "pd")])
-(define_mode_attr avxmodesuffix
- [(V16QI "") (V32QI "256") (V4SI "") (V4SF "") (V2DF "")
- (V8SI "256") (V8SF "256") (V4DF "256")])
+(define_mode_iterator FMAMODE [SF DF V4SF V2DF V8SF V4DF])
;; Mapping of immediate bits for blend instructions
(define_mode_attr blendbits
[(V8SF "255") (V4SF "15") (V4DF "15") (V2DF "3")])
-;; Mapping of immediate bits for pinsr instructions
-(define_mode_attr pinsrbits [(V16QI "32768") (V8HI "128") (V4SI "8")])
-
;; Patterns whose name begins with "sse{,2,3}_" are invoked by intrinsics.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; All of these patterns are enabled for SSE1 as well as SSE2.
+;; This is essential for maintaining stable calling conventions.
+
(define_expand "mov<mode>"
- [(set (match_operand:AVX256MODE 0 "nonimmediate_operand" "")
- (match_operand:AVX256MODE 1 "nonimmediate_operand" ""))]
- "TARGET_AVX"
+ [(set (match_operand:V16 0 "nonimmediate_operand" "")
+ (match_operand:V16 1 "nonimmediate_operand" ""))]
+ "TARGET_SSE"
{
ix86_expand_vector_move (<MODE>mode, operands);
DONE;
})
-(define_insn "*avx_mov<mode>_internal"
- [(set (match_operand:AVXMODE16 0 "nonimmediate_operand" "=x,x ,m")
- (match_operand:AVXMODE16 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))]
- "TARGET_AVX
+(define_insn "*mov<mode>_internal"
+ [(set (match_operand:V16 0 "nonimmediate_operand" "=x,x ,m")
+ (match_operand:V16 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))]
+ "TARGET_SSE
&& (register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode))"
{
return standard_sse_constant_opcode (insn, operands[1]);
case 1:
case 2:
- if (GET_MODE_ALIGNMENT (<MODE>mode) == 256
- && ((TARGET_AVX256_SPLIT_UNALIGNED_STORE
- && misaligned_operand (operands[0], <MODE>mode))
- || (TARGET_AVX256_SPLIT_UNALIGNED_LOAD
- && misaligned_operand (operands[1], <MODE>mode))))
- gcc_unreachable ();
switch (get_attr_mode (insn))
{
case MODE_V8SF:
case MODE_V4SF:
- if (misaligned_operand (operands[0], <MODE>mode)
- || misaligned_operand (operands[1], <MODE>mode))
+ if (TARGET_AVX
+ && (misaligned_operand (operands[0], <MODE>mode)
+ || misaligned_operand (operands[1], <MODE>mode)))
return "vmovups\t{%1, %0|%0, %1}";
else
- return "vmovaps\t{%1, %0|%0, %1}";
+ return "%vmovaps\t{%1, %0|%0, %1}";
+
case MODE_V4DF:
case MODE_V2DF:
- if (misaligned_operand (operands[0], <MODE>mode)
- || misaligned_operand (operands[1], <MODE>mode))
+ if (TARGET_AVX
+ && (misaligned_operand (operands[0], <MODE>mode)
+ || misaligned_operand (operands[1], <MODE>mode)))
return "vmovupd\t{%1, %0|%0, %1}";
else if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "vmovaps\t{%1, %0|%0, %1}";
+ return "%vmovaps\t{%1, %0|%0, %1}";
else
- return "vmovapd\t{%1, %0|%0, %1}";
- default:
- if (misaligned_operand (operands[0], <MODE>mode)
- || misaligned_operand (operands[1], <MODE>mode))
+ return "%vmovapd\t{%1, %0|%0, %1}";
+
+ case MODE_OI:
+ case MODE_TI:
+ if (TARGET_AVX
+ && (misaligned_operand (operands[0], <MODE>mode)
+ || misaligned_operand (operands[1], <MODE>mode)))
return "vmovdqu\t{%1, %0|%0, %1}";
else if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "vmovaps\t{%1, %0|%0, %1}";
+ return "%vmovaps\t{%1, %0|%0, %1}";
else
- return "vmovdqa\t{%1, %0|%0, %1}";
- }
- default:
- gcc_unreachable ();
- }
-}
- [(set_attr "type" "sselog1,ssemov,ssemov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecmode>")])
-
-;; All of these patterns are enabled for SSE1 as well as SSE2.
-;; This is essential for maintaining stable calling conventions.
-
-(define_expand "mov<mode>"
- [(set (match_operand:SSEMODE16 0 "nonimmediate_operand" "")
- (match_operand:SSEMODE16 1 "nonimmediate_operand" ""))]
- "TARGET_SSE"
-{
- ix86_expand_vector_move (<MODE>mode, operands);
- DONE;
-})
+ return "%vmovdqa\t{%1, %0|%0, %1}";
-(define_insn "*mov<mode>_internal"
- [(set (match_operand:SSEMODE16 0 "nonimmediate_operand" "=x,x ,m")
- (match_operand:SSEMODE16 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))]
- "TARGET_SSE
- && (register_operand (operands[0], <MODE>mode)
- || register_operand (operands[1], <MODE>mode))"
-{
- switch (which_alternative)
- {
- case 0:
- return standard_sse_constant_opcode (insn, operands[1]);
- case 1:
- case 2:
- switch (get_attr_mode (insn))
- {
- case MODE_V4SF:
- return "movaps\t{%1, %0|%0, %1}";
- case MODE_V2DF:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "movaps\t{%1, %0|%0, %1}";
- else
- return "movapd\t{%1, %0|%0, %1}";
default:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "movaps\t{%1, %0|%0, %1}";
- else
- return "movdqa\t{%1, %0|%0, %1}";
+ gcc_unreachable ();
}
default:
gcc_unreachable ();
}
}
[(set_attr "type" "sselog1,ssemov,ssemov")
+ (set_attr "prefix" "maybe_vex")
(set (attr "mode")
- (cond [(ior (ior (ne (symbol_ref "optimize_function_for_size_p (cfun)") (const_int 0))
- (eq (symbol_ref "TARGET_SSE2") (const_int 0)))
+ (cond [(ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (const_string "<sseinsnmode>")
+ (ior (ior
+ (ne (symbol_ref "optimize_function_for_size_p (cfun)")
+ (const_int 0))
+ (eq (symbol_ref "TARGET_SSE2") (const_int 0)))
(and (eq_attr "alternative" "2")
(ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
(const_int 0))))
]
(const_string "TI")))])
+(define_insn "sse2_movq128"
+ [(set (match_operand:V2DI 0 "register_operand" "=x")
+ (vec_concat:V2DI
+ (vec_select:DI
+ (match_operand:V2DI 1 "nonimmediate_operand" "xm")
+ (parallel [(const_int 0)]))
+ (const_int 0)))]
+ "TARGET_SSE2"
+ "%vmovq\t{%1, %0|%0, %1}"
+ [(set_attr "type" "ssemov")
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "mode" "TI")])
+
;; Move a DI from a 32-bit register pair (e.g. %edx:%eax) to an xmm.
;; We'd rather avoid this entirely; if the 32-bit reg pair was loaded
;; from memory, we'd prefer to load the memory directly into the %xmm
})
(define_expand "push<mode>1"
- [(match_operand:AVX256MODE 0 "register_operand" "")]
- "TARGET_AVX"
-{
- ix86_expand_push (<MODE>mode, operands[0]);
- DONE;
-})
-
-(define_expand "push<mode>1"
- [(match_operand:SSEMODE16 0 "register_operand" "")]
+ [(match_operand:V16 0 "register_operand" "")]
"TARGET_SSE"
{
ix86_expand_push (<MODE>mode, operands[0]);
})
(define_expand "movmisalign<mode>"
- [(set (match_operand:AVX256MODE 0 "nonimmediate_operand" "")
- (match_operand:AVX256MODE 1 "nonimmediate_operand" ""))]
- "TARGET_AVX"
-{
- ix86_expand_vector_move_misalign (<MODE>mode, operands);
- DONE;
-})
-
-(define_expand "movmisalign<mode>"
- [(set (match_operand:SSEMODE16 0 "nonimmediate_operand" "")
- (match_operand:SSEMODE16 1 "nonimmediate_operand" ""))]
+ [(set (match_operand:V16 0 "nonimmediate_operand" "")
+ (match_operand:V16 1 "nonimmediate_operand" ""))]
"TARGET_SSE"
{
ix86_expand_vector_move_misalign (<MODE>mode, operands);
DONE;
})
-(define_expand "avx_movu<ssemodesuffix><avxmodesuffix>"
- [(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "")]
+(define_expand "<sse>_movu<ssemodesuffix><avxsizesuffix>"
+ [(set (match_operand:VF 0 "nonimmediate_operand" "")
+ (unspec:VF
+ [(match_operand:VF 1 "nonimmediate_operand" "")]
UNSPEC_MOVU))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
+ "TARGET_SSE"
{
if (MEM_P (operands[0]) && MEM_P (operands[1]))
operands[1] = force_reg (<MODE>mode, operands[1]);
})
-(define_insn "*avx_movu<ssemodesuffix><avxmodesuffix>"
- [(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "=x,m")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm,x")]
+(define_insn "*<sse>_movu<ssemodesuffix><avxsizesuffix>"
+ [(set (match_operand:VF 0 "nonimmediate_operand" "=x,m")
+ (unspec:VF
+ [(match_operand:VF 1 "nonimmediate_operand" "xm,x")]
UNSPEC_MOVU))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
-{
- if (GET_MODE_ALIGNMENT (<MODE>mode) == 256
- && ((TARGET_AVX256_SPLIT_UNALIGNED_STORE
- && misaligned_operand (operands[0], <MODE>mode))
- || (TARGET_AVX256_SPLIT_UNALIGNED_LOAD
- && misaligned_operand (operands[1], <MODE>mode))))
- gcc_unreachable ();
- return "vmovu<ssemodesuffix>\t{%1, %0|%0, %1}";
-}
+ "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+ "%vmovu<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "movu" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "sse2_movq128"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (vec_concat:V2DI
- (vec_select:DI
- (match_operand:V2DI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)]))
- (const_int 0)))]
- "TARGET_SSE2"
- "%vmovq\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov")
(set_attr "prefix" "maybe_vex")
- (set_attr "mode" "TI")])
-
-(define_expand "<sse>_movu<ssemodesuffix>"
- [(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "")
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")]
- UNSPEC_MOVU))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
-{
- if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[1] = force_reg (<MODE>mode, operands[1]);
-})
-
-(define_insn "*<sse>_movu<ssemodesuffix>"
- [(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "=x,m")
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm,x")]
- UNSPEC_MOVU))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "movu<ssemodesuffix>\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov")
- (set_attr "movu" "1")
(set_attr "mode" "<MODE>")])
-(define_expand "avx_movdqu<avxmodesuffix>"
- [(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "")
- (unspec:AVXMODEQI
- [(match_operand:AVXMODEQI 1 "nonimmediate_operand" "")]
- UNSPEC_MOVU))]
- "TARGET_AVX"
-{
- if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[1] = force_reg (<MODE>mode, operands[1]);
-})
-
-(define_insn "*avx_movdqu<avxmodesuffix>"
- [(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "=x,m")
- (unspec:AVXMODEQI
- [(match_operand:AVXMODEQI 1 "nonimmediate_operand" "xm,x")]
- UNSPEC_MOVU))]
- "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
-{
- if (GET_MODE_ALIGNMENT (<MODE>mode) == 256
- && ((TARGET_AVX256_SPLIT_UNALIGNED_STORE
- && misaligned_operand (operands[0], <MODE>mode))
- || (TARGET_AVX256_SPLIT_UNALIGNED_LOAD
- && misaligned_operand (operands[1], <MODE>mode))))
- gcc_unreachable ();
- return "vmovdqu\t{%1, %0|%0, %1}";
-}
- [(set_attr "type" "ssemov")
- (set_attr "movu" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecmode>")])
-
-(define_expand "sse2_movdqu"
- [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
- (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "")]
- UNSPEC_MOVU))]
+(define_expand "<sse2>_movdqu<avxsizesuffix>"
+ [(set (match_operand:VI1 0 "nonimmediate_operand" "")
+ (unspec:VI1 [(match_operand:VI1 1 "nonimmediate_operand" "")]
+ UNSPEC_MOVU))]
"TARGET_SSE2"
{
if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[1] = force_reg (V16QImode, operands[1]);
+ operands[1] = force_reg (<MODE>mode, operands[1]);
})
-(define_insn "*sse2_movdqu"
- [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
- (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
- UNSPEC_MOVU))]
+(define_insn "*<sse2>_movdqu<avxsizesuffix>"
+ [(set (match_operand:VI1 0 "nonimmediate_operand" "=x,m")
+ (unspec:VI1 [(match_operand:VI1 1 "nonimmediate_operand" "xm,x")]
+ UNSPEC_MOVU))]
"TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "movdqu\t{%1, %0|%0, %1}"
+ "%vmovdqu\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "movu" "1")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "avx_movnt<mode>"
- [(set (match_operand:AVXMODEF2P 0 "memory_operand" "=m")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "register_operand" "x")]
- UNSPEC_MOVNT))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
- "vmovnt<ssemodesuffix>\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "<sse>_movnt<mode>"
- [(set (match_operand:SSEMODEF2P 0 "memory_operand" "=m")
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 1 "register_operand" "x")]
- UNSPEC_MOVNT))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "movnt<ssemodesuffix>\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "avx_movnt<mode>"
- [(set (match_operand:AVXMODEDI 0 "memory_operand" "=m")
- (unspec:AVXMODEDI
- [(match_operand:AVXMODEDI 1 "register_operand" "x")]
- UNSPEC_MOVNT))]
- "TARGET_AVX"
- "vmovntdq\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecmode>")])
+ (set (attr "prefix_data16")
+ (if_then_else
+ (ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (const_string "*")
+ (const_string "1")))
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "mode" "<sseinsnmode>")])
-(define_insn "sse2_movntv2di"
- [(set (match_operand:V2DI 0 "memory_operand" "=m")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
- UNSPEC_MOVNT))]
- "TARGET_SSE2"
- "movntdq\t{%1, %0|%0, %1}"
+(define_insn "<sse3>_lddqu<avxsizesuffix>"
+ [(set (match_operand:VI1 0 "register_operand" "=x")
+ (unspec:VI1 [(match_operand:VI1 1 "memory_operand" "m")]
+ UNSPEC_LDDQU))]
+ "TARGET_SSE3"
+ "%vlddqu\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
+ (set_attr "movu" "1")
+ (set (attr "prefix_data16")
+ (if_then_else
+ (ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (const_string "*")
+ (const_string "0")))
+ (set (attr "prefix_rep")
+ (if_then_else
+ (ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (const_string "*")
+ (const_string "1")))
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "mode" "<sseinsnmode>")])
(define_insn "sse2_movntsi"
[(set (match_operand:SI 0 "memory_operand" "=m")
(set_attr "prefix_data16" "0")
(set_attr "mode" "V2DF")])
-(define_insn "avx_lddqu<avxmodesuffix>"
- [(set (match_operand:AVXMODEQI 0 "register_operand" "=x")
- (unspec:AVXMODEQI
- [(match_operand:AVXMODEQI 1 "memory_operand" "m")]
- UNSPEC_LDDQU))]
- "TARGET_AVX"
- "vlddqu\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "movu" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecmode>")])
-
-(define_insn "sse3_lddqu"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")]
- UNSPEC_LDDQU))]
- "TARGET_SSE3"
- "lddqu\t{%1, %0|%0, %1}"
+(define_insn "<sse>_movnt<mode>"
+ [(set (match_operand:VF 0 "memory_operand" "=m")
+ (unspec:VF [(match_operand:VF 1 "register_operand" "x")]
+ UNSPEC_MOVNT))]
+ "TARGET_SSE"
+ "%vmovnt<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
- (set_attr "movu" "1")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_rep" "1")
- (set_attr "mode" "TI")])
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "<sse2>_movnt<mode>"
+ [(set (match_operand:VI8 0 "memory_operand" "=m")
+ (unspec:VI8 [(match_operand:VI8 1 "register_operand" "x")]
+ UNSPEC_MOVNT))]
+ "TARGET_SSE2"
+ "%vmovntdq\t{%1, %0|%0, %1}"
+ [(set_attr "type" "ssecvt")
+ (set (attr "prefix_data16")
+ (if_then_else
+ (ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (const_string "*")
+ (const_string "1")))
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "mode" "<sseinsnmode>")])
; Expand patterns for non-temporal stores. At the moment, only those
; that directly map to insns are defined; it would be possible to
; define patterns for other modes that would expand to several insns.
+;; Modes handled by storent patterns.
+(define_mode_iterator STORENT_MODE
+ [(SI "TARGET_SSE2") (SF "TARGET_SSE4A") (DF "TARGET_SSE4A")
+ (V2DI "TARGET_SSE2")
+ (V8SF "TARGET_AVX") V4SF
+ (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")])
+
(define_expand "storent<mode>"
[(set (match_operand:STORENT_MODE 0 "memory_operand" "")
(unspec:STORENT_MODE
[(match_operand:STORENT_MODE 1 "register_operand" "")]
- UNSPEC_MOVNT))])
+ UNSPEC_MOVNT))]
+ "TARGET_SSE")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "<code><mode>2"
- [(set (match_operand:VEC_FLOAT_MODE 0 "register_operand" "")
- (absneg:VEC_FLOAT_MODE
- (match_operand:VEC_FLOAT_MODE 1 "register_operand" "")))]
- ""
+ [(set (match_operand:VF 0 "register_operand" "")
+ (absneg:VF
+ (match_operand:VF 1 "register_operand" "")))]
+ "TARGET_SSE"
"ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
-(define_insn_and_split "*avx_absneg<mode>2"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x,x")
- (match_operator:AVXMODEF2P 3 "absneg_operator"
- [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "x,m")]))
- (use (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm,x"))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
+(define_insn_and_split "*absneg<mode>2"
+ [(set (match_operand:VF 0 "register_operand" "=x,x,x,x")
+ (match_operator:VF 3 "absneg_operator"
+ [(match_operand:VF 1 "nonimmediate_operand" "0, xm,x, m")]))
+ (use (match_operand:VF 2 "nonimmediate_operand" "xm,0, xm,x"))]
+ "TARGET_SSE"
"#"
- "&& reload_completed"
+ "reload_completed"
[(const_int 0)]
{
+ enum rtx_code absneg_op;
+ rtx op1, op2;
rtx t;
- if (MEM_P (operands[1]))
- t = gen_rtx_fmt_ee (GET_CODE (operands[3]) == NEG ? XOR : AND,
- <MODE>mode, operands[2], operands[1]);
+ if (TARGET_AVX)
+ {
+ if (MEM_P (operands[1]))
+ op1 = operands[2], op2 = operands[1];
+ else
+ op1 = operands[1], op2 = operands[2];
+ }
else
- t = gen_rtx_fmt_ee (GET_CODE (operands[3]) == NEG ? XOR : AND,
- <MODE>mode, operands[1], operands[2]);
- t = gen_rtx_SET (VOIDmode, operands[0], t);
- emit_insn (t);
- DONE;
-})
-
-(define_insn_and_split "*sse_absneg<mode>2"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
- (match_operator:SSEMODEF2P 3 "absneg_operator"
- [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "0,xm")]))
- (use (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm,0"))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "#"
- "&& reload_completed"
- [(const_int 0)]
-{
- rtx t;
+ {
+ op1 = operands[0];
+ if (rtx_equal_p (operands[0], operands[1]))
+ op2 = operands[2];
+ else
+ op2 = operands[1];
+ }
- t = operands[rtx_equal_p (operands[0], operands[1]) ? 2 : 1];
- t = gen_rtx_fmt_ee (GET_CODE (operands[3]) == NEG ? XOR : AND,
- <MODE>mode, operands[0], t);
+ absneg_op = GET_CODE (operands[3]) == NEG ? XOR : AND;
+ t = gen_rtx_fmt_ee (absneg_op, <MODE>mode, op1, op2);
t = gen_rtx_SET (VOIDmode, operands[0], t);
emit_insn (t);
DONE;
-})
-
-(define_expand "<plusminus_insn><mode>3"
- [(set (match_operand:AVX256MODEF2P 0 "register_operand" "")
- (plusminus:AVX256MODEF2P
- (match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "")
- (match_operand:AVX256MODEF2P 2 "nonimmediate_operand" "")))]
- "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
- "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
-
-(define_insn "*avx_<plusminus_insn><mode>3"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (plusminus:AVXMODEF2P
- (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "<comm>x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "v<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecmode>")])
+}
+ [(set_attr "isa" "noavx,noavx,avx,avx")])
(define_expand "<plusminus_insn><mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (plusminus:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
+ [(set (match_operand:VF 0 "register_operand" "")
+ (plusminus:VF
+ (match_operand:VF 1 "nonimmediate_operand" "")
+ (match_operand:VF 2 "nonimmediate_operand" "")))]
+ "TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*<plusminus_insn><mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (plusminus:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "<comm>0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
+ (plusminus:VF
+ (match_operand:VF 1 "nonimmediate_operand" "<comm>0,x")
+ (match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "@
+ <plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
+ v<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseadd")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")])
-(define_insn "*avx_vm<plusminus_insn><mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (plusminus:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "x")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (const_int 1)))]
- "AVX128_VEC_FLOAT_MODE_P (<MODE>mode)"
- "v<plusminus_mnemonic><ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<ssescalarmode>")])
-
(define_insn "<sse>_vm<plusminus_insn><mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (plusminus:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
+ [(set (match_operand:VF_128 0 "register_operand" "=x,x")
+ (vec_merge:VF_128
+ (plusminus:VF_128
+ (match_operand:VF_128 1 "register_operand" "0,x")
+ (match_operand:VF_128 2 "nonimmediate_operand" "xm,xm"))
(match_dup 1)
(const_int 1)))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "<plusminus_mnemonic><ssescalarmodesuffix>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
+ "TARGET_SSE"
+ "@
+ <plusminus_mnemonic><ssescalarmodesuffix>\t{%2, %0|%0, %2}
+ v<plusminus_mnemonic><ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseadd")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<ssescalarmode>")])
(define_expand "mul<mode>3"
- [(set (match_operand:AVX256MODEF2P 0 "register_operand" "")
- (mult:AVX256MODEF2P
- (match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "")
- (match_operand:AVX256MODEF2P 2 "nonimmediate_operand" "")))]
- "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
- "ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
-
-(define_insn "*avx_mul<mode>3"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (mult:AVXMODEF2P
- (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)
- && ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
- "vmul<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssemul")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecmode>")])
-
-(define_expand "mul<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
+ [(set (match_operand:VF 0 "register_operand" "")
+ (mult:VF
+ (match_operand:VF 1 "nonimmediate_operand" "")
+ (match_operand:VF 2 "nonimmediate_operand" "")))]
+ "TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
(define_insn "*mul<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
- && ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
- "mul<ssemodesuffix>\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssemul")
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
+ (mult:VF
+ (match_operand:VF 1 "nonimmediate_operand" "%0,x")
+ (match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE && ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
+ "@
+ mul<ssemodesuffix>\t{%2, %0|%0, %2}
+ vmul<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssemul")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")])
-(define_insn "*avx_vmmul<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "x")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (const_int 1)))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
- "vmul<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssemul")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<ssescalarmode>")])
-
(define_insn "<sse>_vmmul<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
+ [(set (match_operand:VF_128 0 "register_operand" "=x,x")
+ (vec_merge:VF_128
+ (mult:VF_128
+ (match_operand:VF_128 1 "register_operand" "0,x")
+ (match_operand:VF_128 2 "nonimmediate_operand" "xm,xm"))
(match_dup 1)
(const_int 1)))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "mul<ssescalarmodesuffix>\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssemul")
+ "TARGET_SSE"
+ "@
+ mul<ssescalarmodesuffix>\t{%2, %0|%0, %2}
+ vmul<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssemul")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<ssescalarmode>")])
-(define_expand "divv8sf3"
- [(set (match_operand:V8SF 0 "register_operand" "")
- (div:V8SF (match_operand:V8SF 1 "register_operand" "")
- (match_operand:V8SF 2 "nonimmediate_operand" "")))]
- "TARGET_AVX"
-{
- ix86_fixup_binary_operands_no_copy (DIV, V8SFmode, operands);
-
- if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
- && flag_finite_math_only && !flag_trapping_math
- && flag_unsafe_math_optimizations)
- {
- ix86_emit_swdivsf (operands[0], operands[1],
- operands[2], V8SFmode);
- DONE;
- }
-})
-
-(define_expand "divv4df3"
- [(set (match_operand:V4DF 0 "register_operand" "")
- (div:V4DF (match_operand:V4DF 1 "register_operand" "")
- (match_operand:V4DF 2 "nonimmediate_operand" "")))]
- "TARGET_AVX"
- "ix86_fixup_binary_operands_no_copy (DIV, V4DFmode, operands);")
-
-(define_insn "avx_div<mode>3"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (div:AVXMODEF2P
- (match_operand:AVXMODEF2P 1 "register_operand" "x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
- "vdiv<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssediv")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<MODE>")])
+(define_expand "div<mode>3"
+ [(set (match_operand:VF2 0 "register_operand" "")
+ (div:VF2 (match_operand:VF2 1 "register_operand" "")
+ (match_operand:VF2 2 "nonimmediate_operand" "")))]
+ "TARGET_SSE2"
+ "ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands);")
-(define_expand "divv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (div:V4SF (match_operand:V4SF 1 "register_operand" "")
- (match_operand:V4SF 2 "nonimmediate_operand" "")))]
+(define_expand "div<mode>3"
+ [(set (match_operand:VF1 0 "register_operand" "")
+ (div:VF1 (match_operand:VF1 1 "register_operand" "")
+ (match_operand:VF1 2 "nonimmediate_operand" "")))]
"TARGET_SSE"
{
- if (TARGET_SSE_MATH && TARGET_RECIP && optimize_insn_for_speed_p ()
+ ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands);
+
+ if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
&& flag_finite_math_only && !flag_trapping_math
&& flag_unsafe_math_optimizations)
{
- ix86_emit_swdivsf (operands[0], operands[1],
- operands[2], V4SFmode);
+ ix86_emit_swdivsf (operands[0], operands[1], operands[2], <MODE>mode);
DONE;
}
})
-(define_expand "divv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "")
- (div:V2DF (match_operand:V2DF 1 "register_operand" "")
- (match_operand:V2DF 2 "nonimmediate_operand" "")))]
- "TARGET_SSE2")
-
-(define_insn "*avx_div<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (div:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "x")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
- "AVX128_VEC_FLOAT_MODE_P (<MODE>mode)"
- "vdiv<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssediv")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<MODE>")])
-
(define_insn "<sse>_div<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (div:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "div<ssemodesuffix>\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssediv")
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
+ (div:VF
+ (match_operand:VF 1 "register_operand" "0,x")
+ (match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE"
+ "@
+ div<ssemodesuffix>\t{%2, %0|%0, %2}
+ vdiv<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssediv")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")])
-(define_insn "*avx_vmdiv<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (div:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "x")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (const_int 1)))]
- "AVX128_VEC_FLOAT_MODE_P (<MODE>mode)"
- "vdiv<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssediv")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<ssescalarmode>")])
-
(define_insn "<sse>_vmdiv<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (div:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
+ [(set (match_operand:VF_128 0 "register_operand" "=x,x")
+ (vec_merge:VF_128
+ (div:VF_128
+ (match_operand:VF_128 1 "register_operand" "0,x")
+ (match_operand:VF_128 2 "nonimmediate_operand" "xm,xm"))
(match_dup 1)
(const_int 1)))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "div<ssescalarmodesuffix>\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssediv")
+ "TARGET_SSE"
+ "@
+ div<ssescalarmodesuffix>\t{%2, %0|%0, %2}
+ vdiv<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssediv")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<ssescalarmode>")])
-(define_insn "avx_rcpv8sf2"
- [(set (match_operand:V8SF 0 "register_operand" "=x")
- (unspec:V8SF
- [(match_operand:V8SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
- "TARGET_AVX"
- "vrcpps\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V8SF")])
-
-(define_insn "sse_rcpv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (unspec:V4SF
- [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
+(define_insn "<sse>_rcp<mode>2"
+ [(set (match_operand:VF1 0 "register_operand" "=x")
+ (unspec:VF1
+ [(match_operand:VF1 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
"TARGET_SSE"
"%vrcpps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "atom_sse_attr" "rcp")
(set_attr "prefix" "maybe_vex")
- (set_attr "mode" "V4SF")])
-
-(define_insn "*avx_vmrcpv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
- UNSPEC_RCP)
- (match_operand:V4SF 2 "register_operand" "x")
- (const_int 1)))]
- "TARGET_AVX"
- "vrcpss\t{%1, %2, %0|%0, %2, %1}"
- [(set_attr "type" "sse")
- (set_attr "prefix" "vex")
- (set_attr "mode" "SF")])
+ (set_attr "mode" "<MODE>")])
(define_insn "sse_vmrcpv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
+ [(set (match_operand:V4SF 0 "register_operand" "=x,x")
(vec_merge:V4SF
- (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
+ (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,xm")]
UNSPEC_RCP)
- (match_operand:V4SF 2 "register_operand" "0")
+ (match_operand:V4SF 2 "register_operand" "0,x")
(const_int 1)))]
"TARGET_SSE"
- "rcpss\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
+ "@
+ rcpss\t{%1, %0|%0, %1}
+ vrcpss\t{%1, %2, %0|%0, %2, %1}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sse")
(set_attr "atom_sse_attr" "rcp")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "SF")])
-(define_expand "sqrtv8sf2"
- [(set (match_operand:V8SF 0 "register_operand" "")
- (sqrt:V8SF (match_operand:V8SF 1 "nonimmediate_operand" "")))]
- "TARGET_AVX"
-{
- if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
- && flag_finite_math_only && !flag_trapping_math
- && flag_unsafe_math_optimizations)
- {
- ix86_emit_swsqrtsf (operands[0], operands[1], V8SFmode, 0);
- DONE;
- }
-})
-
-(define_insn "avx_sqrtv8sf2"
- [(set (match_operand:V8SF 0 "register_operand" "=x")
- (sqrt:V8SF (match_operand:V8SF 1 "nonimmediate_operand" "xm")))]
- "TARGET_AVX"
- "vsqrtps\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V8SF")])
+(define_expand "sqrt<mode>2"
+ [(set (match_operand:VF2 0 "register_operand" "")
+ (sqrt:VF2 (match_operand:VF2 1 "nonimmediate_operand" "")))]
+ "TARGET_SSE2")
-(define_expand "sqrtv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")))]
+(define_expand "sqrt<mode>2"
+ [(set (match_operand:VF1 0 "register_operand" "")
+ (sqrt:VF1 (match_operand:VF1 1 "nonimmediate_operand" "")))]
"TARGET_SSE"
{
- if (TARGET_SSE_MATH && TARGET_RECIP && optimize_insn_for_speed_p ()
+ if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
&& flag_finite_math_only && !flag_trapping_math
&& flag_unsafe_math_optimizations)
{
- ix86_emit_swsqrtsf (operands[0], operands[1], V4SFmode, 0);
+ ix86_emit_swsqrtsf (operands[0], operands[1], <MODE>mode, false);
DONE;
}
})
-(define_insn "sse_sqrtv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
+(define_insn "<sse>_sqrt<mode>2"
+ [(set (match_operand:VF 0 "register_operand" "=x")
+ (sqrt:VF (match_operand:VF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
- "%vsqrtps\t{%1, %0|%0, %1}"
+ "%vsqrt<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "atom_sse_attr" "sqrt")
(set_attr "prefix" "maybe_vex")
- (set_attr "mode" "V4SF")])
-
-(define_insn "sqrtv4df2"
- [(set (match_operand:V4DF 0 "register_operand" "=x")
- (sqrt:V4DF (match_operand:V4DF 1 "nonimmediate_operand" "xm")))]
- "TARGET_AVX"
- "vsqrtpd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V4DF")])
-
-(define_insn "sqrtv2df2"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (sqrt:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "%vsqrtpd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
- (set_attr "prefix" "maybe_vex")
- (set_attr "mode" "V2DF")])
-
-(define_insn "*avx_vmsqrt<mode>2"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (sqrt:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm"))
- (match_operand:SSEMODEF2P 2 "register_operand" "x")
- (const_int 1)))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
- "vsqrt<ssescalarmodesuffix>\t{%1, %2, %0|%0, %2, %1}"
- [(set_attr "type" "sse")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<ssescalarmode>")])
+ (set_attr "mode" "<MODE>")])
(define_insn "<sse>_vmsqrt<mode>2"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (sqrt:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm"))
- (match_operand:SSEMODEF2P 2 "register_operand" "0")
+ [(set (match_operand:VF_128 0 "register_operand" "=x,x")
+ (vec_merge:VF_128
+ (sqrt:VF_128
+ (match_operand:VF_128 1 "nonimmediate_operand" "xm,xm"))
+ (match_operand:VF_128 2 "register_operand" "0,x")
(const_int 1)))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "sqrt<ssescalarmodesuffix>\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
+ "TARGET_SSE"
+ "@
+ sqrt<ssescalarmodesuffix>\t{%1, %0|%0, %1}
+ vsqrt<ssescalarmodesuffix>\t{%1, %2, %0|%0, %2, %1}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sse")
(set_attr "atom_sse_attr" "sqrt")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<ssescalarmode>")])
-(define_expand "rsqrtv8sf2"
- [(set (match_operand:V8SF 0 "register_operand" "")
- (unspec:V8SF
- [(match_operand:V8SF 1 "nonimmediate_operand" "")] UNSPEC_RSQRT))]
- "TARGET_AVX && TARGET_SSE_MATH"
-{
- ix86_emit_swsqrtsf (operands[0], operands[1], V8SFmode, 1);
- DONE;
-})
-
-(define_insn "avx_rsqrtv8sf2"
- [(set (match_operand:V8SF 0 "register_operand" "=x")
- (unspec:V8SF
- [(match_operand:V8SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
- "TARGET_AVX"
- "vrsqrtps\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V8SF")])
-
-(define_expand "rsqrtv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V4SF
- [(match_operand:V4SF 1 "nonimmediate_operand" "")] UNSPEC_RSQRT))]
+(define_expand "rsqrt<mode>2"
+ [(set (match_operand:VF1 0 "register_operand" "")
+ (unspec:VF1
+ [(match_operand:VF1 1 "nonimmediate_operand" "")] UNSPEC_RSQRT))]
"TARGET_SSE_MATH"
{
- ix86_emit_swsqrtsf (operands[0], operands[1], V4SFmode, 1);
+ ix86_emit_swsqrtsf (operands[0], operands[1], <MODE>mode, true);
DONE;
})
-(define_insn "sse_rsqrtv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (unspec:V4SF
- [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
+(define_insn "<sse>_rsqrt<mode>2"
+ [(set (match_operand:VF1 0 "register_operand" "=x")
+ (unspec:VF1
+ [(match_operand:VF1 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
"TARGET_SSE"
"%vrsqrtps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "prefix" "maybe_vex")
- (set_attr "mode" "V4SF")])
-
-(define_insn "*avx_vmrsqrtv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
- UNSPEC_RSQRT)
- (match_operand:V4SF 2 "register_operand" "x")
- (const_int 1)))]
- "TARGET_AVX"
- "vrsqrtss\t{%1, %2, %0|%0, %2, %1}"
- [(set_attr "type" "sse")
- (set_attr "prefix" "vex")
- (set_attr "mode" "SF")])
+ (set_attr "mode" "<MODE>")])
(define_insn "sse_vmrsqrtv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
+ [(set (match_operand:V4SF 0 "register_operand" "=x,x")
(vec_merge:V4SF
- (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
+ (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,xm")]
UNSPEC_RSQRT)
- (match_operand:V4SF 2 "register_operand" "0")
+ (match_operand:V4SF 2 "register_operand" "0,x")
(const_int 1)))]
"TARGET_SSE"
- "rsqrtss\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
+ "@
+ rsqrtss\t{%1, %0|%0, %1}
+ vrsqrtss\t{%1, %2, %0|%0, %2, %1}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sse")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "SF")])
;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX
;; applied to NaNs. Hopefully the optimizers won't get too smart on us.
(define_expand "<code><mode>3"
- [(set (match_operand:AVX256MODEF2P 0 "register_operand" "")
- (smaxmin:AVX256MODEF2P
- (match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "")
- (match_operand:AVX256MODEF2P 2 "nonimmediate_operand" "")))]
- "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
-{
- if (!flag_finite_math_only)
- operands[1] = force_reg (<MODE>mode, operands[1]);
- ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);
-})
-
-(define_expand "<code><mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (smaxmin:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
+ [(set (match_operand:VF 0 "register_operand" "")
+ (smaxmin:VF
+ (match_operand:VF 1 "nonimmediate_operand" "")
+ (match_operand:VF 2 "nonimmediate_operand" "")))]
+ "TARGET_SSE"
{
if (!flag_finite_math_only)
operands[1] = force_reg (<MODE>mode, operands[1]);
ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);
})
-(define_insn "*avx_<code><mode>3_finite"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (smaxmin:AVXMODEF2P
- (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "v<maxmin_float><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<MODE>")])
-
(define_insn "*<code><mode>3_finite"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (smaxmin:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
+ (smaxmin:VF
+ (match_operand:VF 1 "nonimmediate_operand" "%0,x")
+ (match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE && flag_finite_math_only
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
+ "@
+ <maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}
+ v<maxmin_float><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseadd")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")])
-(define_insn "*avx_<code><mode>3"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (smaxmin:AVXMODEF2P
- (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
- "v<maxmin_float><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecmode>")])
-
(define_insn "*<code><mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (smaxmin:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "<maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
+ (smaxmin:VF
+ (match_operand:VF 1 "register_operand" "0,x")
+ (match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE && !flag_finite_math_only"
+ "@
+ <maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}
+ v<maxmin_float><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseadd")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")])
-(define_insn "*avx_vm<code><mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (smaxmin:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "x")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (const_int 1)))]
- "AVX128_VEC_FLOAT_MODE_P (<MODE>mode)"
- "v<maxmin_float><ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sse")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<ssescalarmode>")])
-
(define_insn "<sse>_vm<code><mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (smaxmin:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
+ [(set (match_operand:VF_128 0 "register_operand" "=x,x")
+ (vec_merge:VF_128
+ (smaxmin:VF_128
+ (match_operand:VF_128 1 "register_operand" "0,x")
+ (match_operand:VF_128 2 "nonimmediate_operand" "xm,xm"))
(match_dup 1)
(const_int 1)))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "<maxmin_float><ssescalarmodesuffix>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
+ "TARGET_SSE"
+ "@
+ <maxmin_float><ssescalarmodesuffix>\t{%2, %0|%0, %2}
+ v<maxmin_float><ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sse")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<ssescalarmode>")])
;; These versions of the min/max patterns implement exactly the operations
;; Their operands are not commutative, and thus they may be used in the
;; presence of -0.0 and NaN.
-(define_insn "*avx_ieee_smin<mode>3"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "register_operand" "x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")]
- UNSPEC_IEEE_MIN))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
- "vmin<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecmode>")])
-
-(define_insn "*avx_ieee_smax<mode>3"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "register_operand" "x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")]
- UNSPEC_IEEE_MAX))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
- "vmax<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecmode>")])
-
(define_insn "*ieee_smin<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 1 "register_operand" "0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")]
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
+ (unspec:VF
+ [(match_operand:VF 1 "register_operand" "0,x")
+ (match_operand:VF 2 "nonimmediate_operand" "xm,xm")]
UNSPEC_IEEE_MIN))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "min<ssemodesuffix>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
+ "TARGET_SSE"
+ "@
+ min<ssemodesuffix>\t{%2, %0|%0, %2}
+ vmin<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseadd")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")])
(define_insn "*ieee_smax<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 1 "register_operand" "0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")]
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
+ (unspec:VF
+ [(match_operand:VF 1 "register_operand" "0,x")
+ (match_operand:VF 2 "nonimmediate_operand" "xm,xm")]
UNSPEC_IEEE_MAX))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "max<ssemodesuffix>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
+ "TARGET_SSE"
+ "@
+ max<ssemodesuffix>\t{%2, %0|%0, %2}
+ vmax<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseadd")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")])
-(define_insn "avx_addsubv8sf3"
- [(set (match_operand:V8SF 0 "register_operand" "=x")
- (vec_merge:V8SF
- (plus:V8SF
- (match_operand:V8SF 1 "register_operand" "x")
- (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
- (minus:V8SF (match_dup 1) (match_dup 2))
- (const_int 170)))]
- "TARGET_AVX"
- "vaddsubps\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V8SF")])
-
(define_insn "avx_addsubv4df3"
[(set (match_operand:V4DF 0 "register_operand" "=x")
(vec_merge:V4DF
(set_attr "prefix" "vex")
(set_attr "mode" "V4DF")])
-(define_insn "*avx_addsubv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (plus:V4SF
- (match_operand:V4SF 1 "register_operand" "x")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
- (minus:V4SF (match_dup 1) (match_dup 2))
- (const_int 10)))]
+(define_insn "sse3_addsubv2df3"
+ [(set (match_operand:V2DF 0 "register_operand" "=x,x")
+ (vec_merge:V2DF
+ (plus:V2DF
+ (match_operand:V2DF 1 "register_operand" "0,x")
+ (match_operand:V2DF 2 "nonimmediate_operand" "xm,xm"))
+ (minus:V2DF (match_dup 1) (match_dup 2))
+ (const_int 2)))]
+ "TARGET_SSE3"
+ "@
+ addsubpd\t{%2, %0|%0, %2}
+ vaddsubpd\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseadd")
+ (set_attr "atom_unit" "complex")
+ (set_attr "prefix" "orig,vex")
+ (set_attr "mode" "V2DF")])
+
+(define_insn "avx_addsubv8sf3"
+ [(set (match_operand:V8SF 0 "register_operand" "=x")
+ (vec_merge:V8SF
+ (plus:V8SF
+ (match_operand:V8SF 1 "register_operand" "x")
+ (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
+ (minus:V8SF (match_dup 1) (match_dup 2))
+ (const_int 170)))]
"TARGET_AVX"
"vaddsubps\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseadd")
(set_attr "prefix" "vex")
- (set_attr "mode" "V4SF")])
+ (set_attr "mode" "V8SF")])
(define_insn "sse3_addsubv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
+ [(set (match_operand:V4SF 0 "register_operand" "=x,x")
(vec_merge:V4SF
(plus:V4SF
- (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
+ (match_operand:V4SF 1 "register_operand" "0,x")
+ (match_operand:V4SF 2 "nonimmediate_operand" "xm,xm"))
(minus:V4SF (match_dup 1) (match_dup 2))
(const_int 10)))]
"TARGET_SSE3"
- "addsubps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "prefix_rep" "1")
+ "@
+ addsubps\t{%2, %0|%0, %2}
+ vaddsubps\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseadd")
+ (set_attr "prefix" "orig,vex")
+ (set_attr "prefix_rep" "1,*")
(set_attr "mode" "V4SF")])
-(define_insn "*avx_addsubv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_merge:V2DF
- (plus:V2DF
- (match_operand:V2DF 1 "register_operand" "x")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
- (minus:V2DF (match_dup 1) (match_dup 2))
- (const_int 2)))]
- "TARGET_AVX"
- "vaddsubpd\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V2DF")])
-
-(define_insn "sse3_addsubv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_merge:V2DF
- (plus:V2DF
- (match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
- (minus:V2DF (match_dup 1) (match_dup 2))
- (const_int 2)))]
- "TARGET_SSE3"
- "addsubpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "atom_unit" "complex")
- (set_attr "mode" "V2DF")])
-
(define_insn "avx_h<plusminus_insn>v4df3"
[(set (match_operand:V4DF 0 "register_operand" "=x")
(vec_concat:V4DF
(set_attr "prefix" "vex")
(set_attr "mode" "V4DF")])
-(define_insn "avx_h<plusminus_insn>v8sf3"
- [(set (match_operand:V8SF 0 "register_operand" "=x")
- (vec_concat:V8SF
- (vec_concat:V4SF
- (vec_concat:V2SF
- (plusminus:SF
- (vec_select:SF
+(define_insn "sse3_h<plusminus_insn>v2df3"
+ [(set (match_operand:V2DF 0 "register_operand" "=x,x")
+ (vec_concat:V2DF
+ (plusminus:DF
+ (vec_select:DF
+ (match_operand:V2DF 1 "register_operand" "0,x")
+ (parallel [(const_int 0)]))
+ (vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
+ (plusminus:DF
+ (vec_select:DF
+ (match_operand:V2DF 2 "nonimmediate_operand" "xm,xm")
+ (parallel [(const_int 0)]))
+ (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))]
+ "TARGET_SSE3"
+ "@
+ h<plusminus_mnemonic>pd\t{%2, %0|%0, %2}
+ vh<plusminus_mnemonic>pd\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseadd")
+ (set_attr "prefix" "orig,vex")
+ (set_attr "mode" "V2DF")])
+
+(define_insn "avx_h<plusminus_insn>v8sf3"
+ [(set (match_operand:V8SF 0 "register_operand" "=x")
+ (vec_concat:V8SF
+ (vec_concat:V4SF
+ (vec_concat:V2SF
+ (plusminus:SF
+ (vec_select:SF
(match_operand:V8SF 1 "register_operand" "x")
(parallel [(const_int 0)]))
(vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
-(define_insn "*avx_h<plusminus_insn>v4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_concat:V4SF
- (vec_concat:V2SF
- (plusminus:SF
- (vec_select:SF
- (match_operand:V4SF 1 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
- (plusminus:SF
- (vec_select:SF (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:SF (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2SF
- (plusminus:SF
- (vec_select:SF
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)]))
- (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))
- (plusminus:SF
- (vec_select:SF (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:SF (match_dup 2) (parallel [(const_int 3)]))))))]
- "TARGET_AVX"
- "vh<plusminus_mnemonic>ps\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V4SF")])
-
(define_insn "sse3_h<plusminus_insn>v4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
+ [(set (match_operand:V4SF 0 "register_operand" "=x,x")
(vec_concat:V4SF
(vec_concat:V2SF
(plusminus:SF
(vec_select:SF
- (match_operand:V4SF 1 "register_operand" "0")
+ (match_operand:V4SF 1 "register_operand" "0,x")
(parallel [(const_int 0)]))
(vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
(plusminus:SF
(vec_concat:V2SF
(plusminus:SF
(vec_select:SF
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")
+ (match_operand:V4SF 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)]))
(vec_select:SF (match_dup 2) (parallel [(const_int 1)])))
(plusminus:SF
(vec_select:SF (match_dup 2) (parallel [(const_int 2)]))
(vec_select:SF (match_dup 2) (parallel [(const_int 3)]))))))]
"TARGET_SSE3"
- "h<plusminus_mnemonic>ps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
+ "@
+ h<plusminus_mnemonic>ps\t{%2, %0|%0, %2}
+ vh<plusminus_mnemonic>ps\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseadd")
(set_attr "atom_unit" "complex")
- (set_attr "prefix_rep" "1")
+ (set_attr "prefix" "orig,vex")
+ (set_attr "prefix_rep" "1,*")
(set_attr "mode" "V4SF")])
-(define_insn "*avx_h<plusminus_insn>v2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_concat:V2DF
- (plusminus:DF
- (vec_select:DF
- (match_operand:V2DF 1 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
- (plusminus:DF
- (vec_select:DF
- (match_operand:V2DF 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)]))
- (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))]
+(define_expand "reduc_splus_v4df"
+ [(match_operand:V4DF 0 "register_operand" "")
+ (match_operand:V4DF 1 "register_operand" "")]
"TARGET_AVX"
- "vh<plusminus_mnemonic>pd\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V2DF")])
+{
+ rtx tmp = gen_reg_rtx (V4DFmode);
+ rtx tmp2 = gen_reg_rtx (V4DFmode);
+ emit_insn (gen_avx_haddv4df3 (tmp, operands[1], operands[1]));
+ emit_insn (gen_avx_vperm2f128v4df3 (tmp2, tmp, tmp, GEN_INT (1)));
+ emit_insn (gen_addv4df3 (operands[0], tmp, tmp2));
+ DONE;
+})
-(define_insn "sse3_h<plusminus_insn>v2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_concat:V2DF
- (plusminus:DF
- (vec_select:DF
- (match_operand:V2DF 1 "register_operand" "0")
- (parallel [(const_int 0)]))
- (vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
- (plusminus:DF
- (vec_select:DF
- (match_operand:V2DF 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)]))
- (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))]
+(define_expand "reduc_splus_v2df"
+ [(match_operand:V2DF 0 "register_operand" "")
+ (match_operand:V2DF 1 "register_operand" "")]
"TARGET_SSE3"
- "h<plusminus_mnemonic>pd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "V2DF")])
+{
+ emit_insn (gen_sse3_haddv2df3 (operands[0], operands[1], operands[1]));
+ DONE;
+})
(define_expand "reduc_splus_v8sf"
[(match_operand:V8SF 0 "register_operand" "")
DONE;
})
-(define_expand "reduc_splus_v4df"
- [(match_operand:V4DF 0 "register_operand" "")
- (match_operand:V4DF 1 "register_operand" "")]
- "TARGET_AVX"
-{
- rtx tmp = gen_reg_rtx (V4DFmode);
- rtx tmp2 = gen_reg_rtx (V4DFmode);
- emit_insn (gen_avx_haddv4df3 (tmp, operands[1], operands[1]));
- emit_insn (gen_avx_vperm2f128v4df3 (tmp2, tmp, tmp, GEN_INT (1)));
- emit_insn (gen_addv4df3 (operands[0], tmp, tmp2));
- DONE;
-})
-
-(define_expand "reduc_splus_v2df"
- [(match_operand:V2DF 0 "register_operand" "")
- (match_operand:V2DF 1 "register_operand" "")]
- "TARGET_SSE3"
-{
- emit_insn (gen_sse3_haddv2df3 (operands[0], operands[1], operands[1]));
- DONE;
-})
(define_expand "reduc_smax_v4sf"
[(match_operand:V4SF 0 "register_operand" "")
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(define_insn "avx_cmp<ssemodesuffix><mode>3"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "register_operand" "x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
+(define_insn "avx_cmp<mode>3"
+ [(set (match_operand:VF 0 "register_operand" "=x")
+ (unspec:VF
+ [(match_operand:VF 1 "register_operand" "x")
+ (match_operand:VF 2 "nonimmediate_operand" "xm")
(match_operand:SI 3 "const_0_to_31_operand" "n")]
UNSPEC_PCMP))]
"TARGET_AVX"
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
-(define_insn "avx_cmp<ssescalarmodesuffix><mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (vec_merge:SSEMODEF2P
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 1 "register_operand" "x")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")
+(define_insn "avx_vmcmp<mode>3"
+ [(set (match_operand:VF_128 0 "register_operand" "=x")
+ (vec_merge:VF_128
+ (unspec:VF_128
+ [(match_operand:VF_128 1 "register_operand" "x")
+ (match_operand:VF_128 2 "nonimmediate_operand" "xm")
(match_operand:SI 3 "const_0_to_31_operand" "n")]
UNSPEC_PCMP)
(match_dup 1)
(set_attr "prefix" "vex")
(set_attr "mode" "<ssescalarmode>")])
-;; We don't promote 128bit vector compare intrinsics. But vectorizer
-;; may generate 256bit vector compare instructions.
-(define_insn "*avx_maskcmp<mode>3"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (match_operator:AVXMODEF2P 3 "avx_comparison_float_operator"
- [(match_operand:AVXMODEF2P 1 "register_operand" "x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")]))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
- "vcmp%D3<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssecmp")
- (set_attr "prefix" "vex")
+(define_insn "*<sse>_maskcmp<mode>3_comm"
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
+ (match_operator:VF 3 "sse_comparison_operator"
+ [(match_operand:VF 1 "register_operand" "%0,x")
+ (match_operand:VF 2 "nonimmediate_operand" "xm,xm")]))]
+ "TARGET_SSE
+ && GET_RTX_CLASS (GET_CODE (operands[3])) == RTX_COMM_COMPARE"
+ "@
+ cmp%D3<ssemodesuffix>\t{%2, %0|%0, %2}
+ vcmp%D3<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssecmp")
(set_attr "length_immediate" "1")
- (set_attr "mode" "<avxvecmode>")])
+ (set_attr "prefix" "orig,vex")
+ (set_attr "mode" "<MODE>")])
(define_insn "<sse>_maskcmp<mode>3"
- [(set (match_operand:SSEMODEF4 0 "register_operand" "=x")
- (match_operator:SSEMODEF4 3 "sse_comparison_operator"
- [(match_operand:SSEMODEF4 1 "register_operand" "0")
- (match_operand:SSEMODEF4 2 "nonimmediate_operand" "xm")]))]
- "!TARGET_XOP
- && (SSE_FLOAT_MODE_P (<MODE>mode) || SSE_VEC_FLOAT_MODE_P (<MODE>mode))"
- "cmp%D3<ssemodesuffix>\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecmp")
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
+ (match_operator:VF 3 "sse_comparison_operator"
+ [(match_operand:VF 1 "register_operand" "0,x")
+ (match_operand:VF 2 "nonimmediate_operand" "xm,xm")]))]
+ "TARGET_SSE"
+ "@
+ cmp%D3<ssemodesuffix>\t{%2, %0|%0, %2}
+ vcmp%D3<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssecmp")
(set_attr "length_immediate" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")])
-(define_insn "*avx_vmmaskcmp<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (match_operator:SSEMODEF2P 3 "sse_comparison_operator"
- [(match_operand:SSEMODEF2P 1 "register_operand" "x")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")])
- (match_dup 1)
- (const_int 1)))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
- "vcmp%D3<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssecmp")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<ssescalarmode>")])
-
(define_insn "<sse>_vmmaskcmp<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (match_operator:SSEMODEF2P 3 "sse_comparison_operator"
- [(match_operand:SSEMODEF2P 1 "register_operand" "0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")])
+ [(set (match_operand:VF_128 0 "register_operand" "=x,x")
+ (vec_merge:VF_128
+ (match_operator:VF_128 3 "sse_comparison_operator"
+ [(match_operand:VF_128 1 "register_operand" "0,x")
+ (match_operand:VF_128 2 "nonimmediate_operand" "xm,xm")])
(match_dup 1)
(const_int 1)))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "cmp%D3<ssescalarmodesuffix>\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecmp")
- (set_attr "length_immediate" "1")
+ "TARGET_SSE"
+ "@
+ cmp%D3<ssescalarmodesuffix>\t{%2, %0|%0, %2}
+ vcmp%D3<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssecmp")
+ (set_attr "length_immediate" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<ssescalarmode>")])
(define_insn "<sse>_comi"
(match_operand:<ssevecmode> 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)]))))]
"SSE_FLOAT_MODE_P (<MODE>mode)"
- "%vcomis<ssemodefsuffix>\t{%1, %0|%0, %1}"
+ "%vcomi<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecomi")
(set_attr "prefix" "maybe_vex")
(set_attr "prefix_rep" "0")
(match_operand:<ssevecmode> 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0)]))))]
"SSE_FLOAT_MODE_P (<MODE>mode)"
- "%vucomis<ssemodefsuffix>\t{%1, %0|%0, %1}"
+ "%vucomi<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecomi")
(set_attr "prefix" "maybe_vex")
(set_attr "prefix_rep" "0")
(set_attr "mode" "<MODE>")])
(define_expand "vcond<mode>"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "")
- (if_then_else:AVXMODEF2P
+ [(set (match_operand:VF 0 "register_operand" "")
+ (if_then_else:VF
(match_operator 3 ""
- [(match_operand:AVXMODEF2P 4 "nonimmediate_operand" "")
- (match_operand:AVXMODEF2P 5 "nonimmediate_operand" "")])
- (match_operand:AVXMODEF2P 1 "general_operand" "")
- (match_operand:AVXMODEF2P 2 "general_operand" "")))]
- "(SSE_VEC_FLOAT_MODE_P (<MODE>mode)
- || AVX_VEC_FLOAT_MODE_P (<MODE>mode))"
+ [(match_operand:VF 4 "nonimmediate_operand" "")
+ (match_operand:VF 5 "nonimmediate_operand" "")])
+ (match_operand:VF 1 "general_operand" "")
+ (match_operand:VF 2 "general_operand" "")))]
+ "TARGET_SSE"
{
bool ok = ix86_expand_fp_vcond (operands);
gcc_assert (ok);
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(define_insn "avx_andnot<mode>3"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (and:AVXMODEF2P
- (not:AVXMODEF2P
- (match_operand:AVXMODEF2P 1 "register_operand" "x"))
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
- "vandn<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecmode>")])
-
(define_insn "<sse>_andnot<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (and:SSEMODEF2P
- (not:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "0"))
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "andn<ssemodesuffix>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "<MODE>")])
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
+ (and:VF
+ (not:VF
+ (match_operand:VF 1 "register_operand" "0,x"))
+ (match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE"
+{
+ static char buf[32];
+ const char *insn;
+ const char *suffix
+ = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : "<ssemodesuffix>";
-(define_expand "<code><mode>3"
- [(set (match_operand:AVX256MODEF2P 0 "register_operand" "")
- (any_logic:AVX256MODEF2P
- (match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "")
- (match_operand:AVX256MODEF2P 2 "nonimmediate_operand" "")))]
- "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
- "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
+ switch (which_alternative)
+ {
+ case 0:
+ insn = "andn%s\t{%%2, %%0|%%0, %%2}";
+ break;
+ case 1:
+ insn = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
+ break;
+ default:
+ gcc_unreachable ();
+ }
-(define_insn "*avx_<code><mode>3"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (any_logic:AVXMODEF2P
- (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
-{
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "v<logic>ps\t{%2, %1, %0|%0, %1, %2}";
- else
- return "v<logic><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}";
+ snprintf (buf, sizeof (buf), insn, suffix);
+ return buf;
}
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecmode>")])
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix" "orig,vex")
+ (set_attr "mode" "<MODE>")])
(define_expand "<code><mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (any_logic:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
+ [(set (match_operand:VF 0 "register_operand" "")
+ (any_logic:VF
+ (match_operand:VF 1 "nonimmediate_operand" "")
+ (match_operand:VF 2 "nonimmediate_operand" "")))]
+ "TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*<code><mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (any_logic:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
+ (any_logic:VF
+ (match_operand:VF 1 "nonimmediate_operand" "%0,x")
+ (match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
{
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "<logic>ps\t{%2, %0|%0, %2}";
- else
- return "<logic><ssemodesuffix>\t{%2, %0|%0, %2}";
+ static char buf[32];
+ const char *insn;
+ const char *suffix
+ = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : "<ssemodesuffix>";
+
+ switch (which_alternative)
+ {
+ case 0:
+ insn = "<logic>%s\t{%%2, %%0|%%0, %%2}";
+ break;
+ case 1:
+ insn = "v<logic>%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
+ break;
+ default:
+ gcc_unreachable ();
+ }
+
+ snprintf (buf, sizeof (buf), insn, suffix);
+ return buf;
}
- [(set_attr "type" "sselog")
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")])
(define_expand "copysign<mode>3"
[(set (match_dup 4)
- (and:VEC_FLOAT_MODE
- (not:VEC_FLOAT_MODE (match_dup 3))
- (match_operand:VEC_FLOAT_MODE 1 "nonimmediate_operand" "")))
+ (and:VF
+ (not:VF (match_dup 3))
+ (match_operand:VF 1 "nonimmediate_operand" "")))
(set (match_dup 5)
- (and:VEC_FLOAT_MODE (match_dup 3)
- (match_operand:VEC_FLOAT_MODE 2 "nonimmediate_operand" "")))
- (set (match_operand:VEC_FLOAT_MODE 0 "register_operand" "")
- (ior:VEC_FLOAT_MODE (match_dup 4) (match_dup 5)))]
- ""
+ (and:VF (match_dup 3)
+ (match_operand:VF 2 "nonimmediate_operand" "")))
+ (set (match_operand:VF 0 "register_operand" "")
+ (ior:VF (match_dup 4) (match_dup 5)))]
+ "TARGET_SSE"
{
operands[3] = ix86_build_signbit_mask (<MODE>mode, 1, 0);
;; allocation lossage. These patterns do not allow memory operands
;; because the native instructions read the full 128-bits.
-(define_insn "*avx_andnot<mode>3"
- [(set (match_operand:MODEF 0 "register_operand" "=x")
- (and:MODEF
- (not:MODEF
- (match_operand:MODEF 1 "register_operand" "x"))
- (match_operand:MODEF 2 "register_operand" "x")))]
- "AVX_FLOAT_MODE_P (<MODE>mode)"
- "vandnp<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<ssevecmode>")])
-
(define_insn "*andnot<mode>3"
- [(set (match_operand:MODEF 0 "register_operand" "=x")
+ [(set (match_operand:MODEF 0 "register_operand" "=x,x")
(and:MODEF
(not:MODEF
- (match_operand:MODEF 1 "register_operand" "0"))
- (match_operand:MODEF 2 "register_operand" "x")))]
+ (match_operand:MODEF 1 "register_operand" "0,x"))
+ (match_operand:MODEF 2 "register_operand" "x,x")))]
"SSE_FLOAT_MODE_P (<MODE>mode)"
- "andnp<ssemodefsuffix>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "<ssevecmode>")])
-
-(define_insn "*avx_<code><mode>3"
- [(set (match_operand:MODEF 0 "register_operand" "=x")
- (any_logic:MODEF
- (match_operand:MODEF 1 "register_operand" "x")
- (match_operand:MODEF 2 "register_operand" "x")))]
- "AVX_FLOAT_MODE_P (<MODE>mode)"
{
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "v<logic>ps\t{%2, %1, %0|%0, %1, %2}";
- else
- return "v<logic>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}";
+ static char buf[32];
+ const char *insn;
+ const char *suffix
+ = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : "<ssevecmodesuffix>";
+
+ switch (which_alternative)
+ {
+ case 0:
+ insn = "andn%s\t{%%2, %%0|%%0, %%2}";
+ break;
+ case 1:
+ insn = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
+ break;
+ default:
+ gcc_unreachable ();
+ }
+
+ snprintf (buf, sizeof (buf), insn, suffix);
+ return buf;
}
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<ssevecmode>")])
(define_insn "*<code><mode>3"
- [(set (match_operand:MODEF 0 "register_operand" "=x")
+ [(set (match_operand:MODEF 0 "register_operand" "=x,x")
(any_logic:MODEF
- (match_operand:MODEF 1 "register_operand" "0")
- (match_operand:MODEF 2 "register_operand" "x")))]
+ (match_operand:MODEF 1 "register_operand" "%0,x")
+ (match_operand:MODEF 2 "register_operand" "x,x")))]
"SSE_FLOAT_MODE_P (<MODE>mode)"
{
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "<logic>ps\t{%2, %0|%0, %2}";
- else
- return "<logic>p<ssemodefsuffix>\t{%2, %0|%0, %2}";
+ static char buf[32];
+ const char *insn;
+ const char *suffix
+ = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : "<ssevecmodesuffix>";
+
+ switch (which_alternative)
+ {
+ case 0:
+ insn = "<logic>%s\t{%%2, %%0|%%0, %%2}";
+ break;
+ case 1:
+ insn = "v<logic>%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
+ break;
+ default:
+ gcc_unreachable ();
+ }
+
+ snprintf (buf, sizeof (buf), insn, suffix);
+ return buf;
}
- [(set_attr "type" "sselog")
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<ssevecmode>")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(match_operand:FMAMODE 1 "nonimmediate_operand")
(match_operand:FMAMODE 2 "nonimmediate_operand")
(match_operand:FMAMODE 3 "nonimmediate_operand")))]
- "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH"
- "")
+ "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH")
(define_expand "fms<mode>4"
[(set (match_operand:FMAMODE 0 "register_operand")
(match_operand:FMAMODE 1 "nonimmediate_operand")
(match_operand:FMAMODE 2 "nonimmediate_operand")
(neg:FMAMODE (match_operand:FMAMODE 3 "nonimmediate_operand"))))]
- "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH"
- "")
+ "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH")
(define_expand "fnma<mode>4"
[(set (match_operand:FMAMODE 0 "register_operand")
(neg:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand"))
(match_operand:FMAMODE 2 "nonimmediate_operand")
(match_operand:FMAMODE 3 "nonimmediate_operand")))]
- "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH"
- "")
+ "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH")
(define_expand "fnms<mode>4"
[(set (match_operand:FMAMODE 0 "register_operand")
(neg:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand"))
(match_operand:FMAMODE 2 "nonimmediate_operand")
(neg:FMAMODE (match_operand:FMAMODE 3 "nonimmediate_operand"))))]
- "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH"
- "")
+ "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH")
;; The builtin for fma4intrin.h is not constrained by SSE math enabled.
(define_expand "fma4i_fmadd_<mode>"
(match_operand:FMAMODE 1 "nonimmediate_operand")
(match_operand:FMAMODE 2 "nonimmediate_operand")
(match_operand:FMAMODE 3 "nonimmediate_operand")))]
- "TARGET_FMA || TARGET_FMA4"
- "")
+ "TARGET_FMA || TARGET_FMA4")
(define_insn "*fma4i_fmadd_<mode>"
[(set (match_operand:FMAMODE 0 "register_operand" "=x,x")
;; entire destination register, with the high-order elements zeroed.
(define_expand "fma4i_vmfmadd_<mode>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand")
- (vec_merge:SSEMODEF2P
- (fma:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand")
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand"))
+ [(set (match_operand:VF_128 0 "register_operand")
+ (vec_merge:VF_128
+ (fma:VF_128
+ (match_operand:VF_128 1 "nonimmediate_operand")
+ (match_operand:VF_128 2 "nonimmediate_operand")
+ (match_operand:VF_128 3 "nonimmediate_operand"))
(match_dup 4)
(const_int 1)))]
"TARGET_FMA4"
})
(define_insn "*fma4i_vmfmadd_<mode>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
- (vec_merge:SSEMODEF2P
- (fma:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%x,x")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" " x,m")
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
- (match_operand:SSEMODEF2P 4 "const0_operand" "")
+ [(set (match_operand:VF_128 0 "register_operand" "=x,x")
+ (vec_merge:VF_128
+ (fma:VF_128
+ (match_operand:VF_128 1 "nonimmediate_operand" "%x,x")
+ (match_operand:VF_128 2 "nonimmediate_operand" " x,m")
+ (match_operand:VF_128 3 "nonimmediate_operand" "xm,x"))
+ (match_operand:VF_128 4 "const0_operand" "")
(const_int 1)))]
"TARGET_FMA4"
"vfmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
(set_attr "mode" "<MODE>")])
(define_insn "*fma4i_vmfmsub_<mode>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
- (vec_merge:SSEMODEF2P
- (fma:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%x,x")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" " x,m")
- (neg:SSEMODEF2P
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x")))
- (match_operand:SSEMODEF2P 4 "const0_operand" "")
+ [(set (match_operand:VF_128 0 "register_operand" "=x,x")
+ (vec_merge:VF_128
+ (fma:VF_128
+ (match_operand:VF_128 1 "nonimmediate_operand" "%x,x")
+ (match_operand:VF_128 2 "nonimmediate_operand" " x,m")
+ (neg:VF_128
+ (match_operand:VF_128 3 "nonimmediate_operand" "xm,x")))
+ (match_operand:VF_128 4 "const0_operand" "")
(const_int 1)))]
"TARGET_FMA4"
"vfmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
(set_attr "mode" "<MODE>")])
(define_insn "*fma4i_vmfnmadd_<mode>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
- (vec_merge:SSEMODEF2P
- (fma:SSEMODEF2P
- (neg:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%x,x"))
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" " x,m")
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
- (match_operand:SSEMODEF2P 4 "const0_operand" "")
+ [(set (match_operand:VF_128 0 "register_operand" "=x,x")
+ (vec_merge:VF_128
+ (fma:VF_128
+ (neg:VF_128
+ (match_operand:VF_128 1 "nonimmediate_operand" "%x,x"))
+ (match_operand:VF_128 2 "nonimmediate_operand" " x,m")
+ (match_operand:VF_128 3 "nonimmediate_operand" "xm,x"))
+ (match_operand:VF_128 4 "const0_operand" "")
(const_int 1)))]
"TARGET_FMA4"
"vfnmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
(set_attr "mode" "<MODE>")])
(define_insn "*fma4i_vmfnmsub_<mode>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
- (vec_merge:SSEMODEF2P
- (fma:SSEMODEF2P
- (neg:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%x,x"))
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" " x,m")
- (neg:SSEMODEF2P
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x")))
- (match_operand:SSEMODEF2P 4 "const0_operand" "")
+ [(set (match_operand:VF_128 0 "register_operand" "=x,x")
+ (vec_merge:VF_128
+ (fma:VF_128
+ (neg:VF_128
+ (match_operand:VF_128 1 "nonimmediate_operand" "%x,x"))
+ (match_operand:VF_128 2 "nonimmediate_operand" " x,m")
+ (neg:VF_128
+ (match_operand:VF_128 3 "nonimmediate_operand" "xm,x")))
+ (match_operand:VF_128 4 "const0_operand" "")
(const_int 1)))]
"TARGET_FMA4"
"vfnmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
;; But this doesn't seem useful in practice.
(define_expand "fmaddsub_<mode>"
- [(set (match_operand:AVXMODEF2P 0 "register_operand")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "nonimmediate_operand")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand")
- (match_operand:AVXMODEF2P 3 "nonimmediate_operand")]
+ [(set (match_operand:VF 0 "register_operand")
+ (unspec:VF
+ [(match_operand:VF 1 "nonimmediate_operand")
+ (match_operand:VF 2 "nonimmediate_operand")
+ (match_operand:VF 3 "nonimmediate_operand")]
UNSPEC_FMADDSUB))]
- "TARGET_FMA || TARGET_FMA4"
- "")
+ "TARGET_FMA || TARGET_FMA4")
(define_insn "*fma4_fmaddsub_<mode>"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x,x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x,x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" " x,m")
- (match_operand:AVXMODEF2P 3 "nonimmediate_operand" "xm,x")]
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
+ (unspec:VF
+ [(match_operand:VF 1 "nonimmediate_operand" "%x,x")
+ (match_operand:VF 2 "nonimmediate_operand" " x,m")
+ (match_operand:VF 3 "nonimmediate_operand" "xm,x")]
UNSPEC_FMADDSUB))]
"TARGET_FMA4"
- "vfmaddsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ "vfmaddsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
(define_insn "*fma4_fmsubadd_<mode>"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x,x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x,x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" " x,m")
- (neg:AVXMODEF2P
- (match_operand:AVXMODEF2P 3 "nonimmediate_operand" "xm,x"))]
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
+ (unspec:VF
+ [(match_operand:VF 1 "nonimmediate_operand" "%x,x")
+ (match_operand:VF 2 "nonimmediate_operand" " x,m")
+ (neg:VF
+ (match_operand:VF 3 "nonimmediate_operand" "xm,x"))]
UNSPEC_FMADDSUB))]
"TARGET_FMA4"
- "vfmsubaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ "vfmsubadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
"TARGET_FMA"
"@
vfmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
- vfmadd312<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
+ vfmadd213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
vfmadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
"TARGET_FMA"
"@
vfmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
- vfmsub312<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
+ vfmsub213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
vfmsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "*fma_fmadd_<mode>"
+(define_insn "*fma_fnmadd_<mode>"
[(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x")
(fma:FMAMODE
(neg:FMAMODE
"TARGET_FMA"
"@
vfnmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
- vfnmadd312<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
+ vfnmadd213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
vfnmadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "*fma_fmsub_<mode>"
+(define_insn "*fma_fnmsub_<mode>"
[(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x")
(fma:FMAMODE
(neg:FMAMODE
"TARGET_FMA"
"@
vfnmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
- vfnmsub312<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
+ vfnmsub231<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
vfnmsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
(define_insn "*fma_fmaddsub_<mode>"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x,x,x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%0, 0,x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm, x,xm")
- (match_operand:AVXMODEF2P 3 "nonimmediate_operand" " x,xm,0")]
+ [(set (match_operand:VF 0 "register_operand" "=x,x,x")
+ (unspec:VF
+ [(match_operand:VF 1 "nonimmediate_operand" "%0, 0,x")
+ (match_operand:VF 2 "nonimmediate_operand" "xm, x,xm")
+ (match_operand:VF 3 "nonimmediate_operand" " x,xm,0")]
UNSPEC_FMADDSUB))]
"TARGET_FMA"
"@
(set_attr "mode" "<MODE>")])
(define_insn "*fma_fmsubadd_<mode>"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x,x,x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%0, 0,x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm, x,xm")
- (neg:AVXMODEF2P
- (match_operand:AVXMODEF2P 3 "nonimmediate_operand" " x,xm,0"))]
+ [(set (match_operand:VF 0 "register_operand" "=x,x,x")
+ (unspec:VF
+ [(match_operand:VF 1 "nonimmediate_operand" "%0, 0,x")
+ (match_operand:VF 2 "nonimmediate_operand" "xm, x,xm")
+ (neg:VF
+ (match_operand:VF 3 "nonimmediate_operand" " x,xm,0"))]
UNSPEC_FMADDSUB))]
"TARGET_FMA"
"@
(set_attr "prefix_rep" "0")
(set_attr "mode" "SF")])
-(define_insn "*avx_cvtsi2ss"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (vec_duplicate:V4SF
- (float:SF (match_operand:SI 2 "nonimmediate_operand" "rm")))
- (match_operand:V4SF 1 "register_operand" "x")
- (const_int 1)))]
- "TARGET_AVX"
- "vcvtsi2ss\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseicvt")
- (set_attr "prefix" "vex")
- (set_attr "mode" "SF")])
-
(define_insn "sse_cvtsi2ss"
- [(set (match_operand:V4SF 0 "register_operand" "=x,x")
+ [(set (match_operand:V4SF 0 "register_operand" "=x,x,x")
(vec_merge:V4SF
(vec_duplicate:V4SF
- (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,m")))
- (match_operand:V4SF 1 "register_operand" "0,0")
+ (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,m,rm")))
+ (match_operand:V4SF 1 "register_operand" "0,0,x")
(const_int 1)))]
"TARGET_SSE"
- "cvtsi2ss\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseicvt")
- (set_attr "athlon_decode" "vector,double")
- (set_attr "amdfam10_decode" "vector,double")
- (set_attr "bdver1_decode" "double,direct")
- (set_attr "mode" "SF")])
-
-(define_insn "*avx_cvtsi2ssq"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (vec_duplicate:V4SF
- (float:SF (match_operand:DI 2 "nonimmediate_operand" "rm")))
- (match_operand:V4SF 1 "register_operand" "x")
- (const_int 1)))]
- "TARGET_AVX && TARGET_64BIT"
- "vcvtsi2ssq\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseicvt")
- (set_attr "length_vex" "4")
- (set_attr "prefix" "vex")
+ "@
+ cvtsi2ss\t{%2, %0|%0, %2}
+ cvtsi2ss\t{%2, %0|%0, %2}
+ vcvtsi2ss\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "type" "sseicvt")
+ (set_attr "athlon_decode" "vector,double,*")
+ (set_attr "amdfam10_decode" "vector,double,*")
+ (set_attr "bdver1_decode" "double,direct,*")
+ (set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "SF")])
(define_insn "sse_cvtsi2ssq"
- [(set (match_operand:V4SF 0 "register_operand" "=x,x")
+ [(set (match_operand:V4SF 0 "register_operand" "=x,x,x")
(vec_merge:V4SF
(vec_duplicate:V4SF
- (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
- (match_operand:V4SF 1 "register_operand" "0,0")
+ (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,m,rm")))
+ (match_operand:V4SF 1 "register_operand" "0,0,x")
(const_int 1)))]
"TARGET_SSE && TARGET_64BIT"
- "cvtsi2ssq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseicvt")
- (set_attr "prefix_rex" "1")
- (set_attr "athlon_decode" "vector,double")
- (set_attr "amdfam10_decode" "vector,double")
- (set_attr "bdver1_decode" "double,direct")
+ "@
+ cvtsi2ssq\t{%2, %0|%0, %2}
+ cvtsi2ssq\t{%2, %0|%0, %2}
+ vcvtsi2ssq\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "type" "sseicvt")
+ (set_attr "athlon_decode" "vector,double,*")
+ (set_attr "amdfam10_decode" "vector,double,*")
+ (set_attr "bdver1_decode" "double,direct,*")
+ (set_attr "length_vex" "*,*,4")
+ (set_attr "prefix_rex" "1,1,*")
+ (set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "SF")])
(define_insn "sse_cvtss2si"
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "DI")])
-(define_insn "avx_cvtdq2ps<avxmodesuffix>"
- [(set (match_operand:AVXMODEDCVTDQ2PS 0 "register_operand" "=x")
- (float:AVXMODEDCVTDQ2PS
- (match_operand:<avxcvtvecmode> 1 "nonimmediate_operand" "xm")))]
+(define_insn "avx_cvtdq2ps256"
+ [(set (match_operand:V8SF 0 "register_operand" "=x")
+ (float:V8SF (match_operand:V8SI 1 "nonimmediate_operand" "xm")))]
"TARGET_AVX"
"vcvtdq2ps\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecmode>")])
+ (set_attr "mode" "V8SF")])
(define_insn "sse2_cvtdq2ps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
- "cvtdq2ps\t{%1, %0|%0, %1}"
+ "%vcvtdq2ps\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
+ (set_attr "prefix" "maybe_vex")
(set_attr "mode" "V4SF")])
(define_expand "sse2_cvtudq2ps"
operands[i] = gen_reg_rtx (V4SFmode);
})
-(define_insn "avx_cvtps2dq<avxmodesuffix>"
- [(set (match_operand:AVXMODEDCVTPS2DQ 0 "register_operand" "=x")
- (unspec:AVXMODEDCVTPS2DQ
- [(match_operand:<avxcvtvecmode> 1 "nonimmediate_operand" "xm")]
- UNSPEC_FIX_NOTRUNC))]
+(define_insn "avx_cvtps2dq256"
+ [(set (match_operand:V8SI 0 "register_operand" "=x")
+ (unspec:V8SI [(match_operand:V8SF 1 "nonimmediate_operand" "xm")]
+ UNSPEC_FIX_NOTRUNC))]
"TARGET_AVX"
"vcvtps2dq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecmode>")])
+ (set_attr "mode" "OI")])
(define_insn "sse2_cvtps2dq"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
UNSPEC_FIX_NOTRUNC))]
"TARGET_SSE2"
- "cvtps2dq\t{%1, %0|%0, %1}"
+ "%vcvtps2dq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
- (set_attr "prefix_data16" "1")
+ (set (attr "prefix_data16")
+ (if_then_else
+ (ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (const_string "*")
+ (const_string "1")))
+ (set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
-(define_insn "avx_cvttps2dq<avxmodesuffix>"
- [(set (match_operand:AVXMODEDCVTPS2DQ 0 "register_operand" "=x")
- (fix:AVXMODEDCVTPS2DQ
- (match_operand:<avxcvtvecmode> 1 "nonimmediate_operand" "xm")))]
+(define_insn "avx_cvttps2dq256"
+ [(set (match_operand:V8SI 0 "register_operand" "=x")
+ (fix:V8SI (match_operand:V8SF 1 "nonimmediate_operand" "xm")))]
"TARGET_AVX"
"vcvttps2dq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecmode>")])
+ (set_attr "mode" "OI")])
(define_insn "sse2_cvttps2dq"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
- "cvttps2dq\t{%1, %0|%0, %1}"
+ "%vcvttps2dq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
- (set_attr "prefix_rep" "1")
+ (set (attr "prefix_rep")
+ (if_then_else
+ (ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (const_string "*")
+ (const_string "1")))
+ (set (attr "prefix_data16")
+ (if_then_else
+ (ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (const_string "*")
+ (const_string "0")))
(set_attr "prefix_data16" "0")
+ (set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
"cvtpd2pi\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "unit" "mmx")
+ (set_attr "bdver1_decode" "double")
(set_attr "prefix_data16" "1")
- (set_attr "mode" "DI")
- (set_attr "bdver1_decode" "double")])
+ (set_attr "mode" "DI")])
(define_insn "sse2_cvttpd2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y")
"cvttpd2pi\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "unit" "mmx")
+ (set_attr "bdver1_decode" "double")
(set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")
- (set_attr "bdver1_decode" "double")])
-
-(define_insn "*avx_cvtsi2sd"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_merge:V2DF
- (vec_duplicate:V2DF
- (float:DF (match_operand:SI 2 "nonimmediate_operand" "rm")))
- (match_operand:V2DF 1 "register_operand" "x")
- (const_int 1)))]
- "TARGET_AVX"
- "vcvtsi2sd\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseicvt")
- (set_attr "prefix" "vex")
- (set_attr "mode" "DF")])
+ (set_attr "mode" "TI")])
(define_insn "sse2_cvtsi2sd"
- [(set (match_operand:V2DF 0 "register_operand" "=x,x")
+ [(set (match_operand:V2DF 0 "register_operand" "=x,x,x")
(vec_merge:V2DF
(vec_duplicate:V2DF
- (float:DF (match_operand:SI 2 "nonimmediate_operand" "r,m")))
- (match_operand:V2DF 1 "register_operand" "0,0")
+ (float:DF (match_operand:SI 2 "nonimmediate_operand" "r,m,rm")))
+ (match_operand:V2DF 1 "register_operand" "0,0,x")
(const_int 1)))]
"TARGET_SSE2"
- "cvtsi2sd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseicvt")
- (set_attr "mode" "DF")
- (set_attr "athlon_decode" "double,direct")
- (set_attr "amdfam10_decode" "vector,double")
- (set_attr "bdver1_decode" "double,direct")])
-
-(define_insn "*avx_cvtsi2sdq"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_merge:V2DF
- (vec_duplicate:V2DF
- (float:DF (match_operand:DI 2 "nonimmediate_operand" "rm")))
- (match_operand:V2DF 1 "register_operand" "x")
- (const_int 1)))]
- "TARGET_AVX && TARGET_64BIT"
- "vcvtsi2sdq\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseicvt")
- (set_attr "length_vex" "4")
- (set_attr "prefix" "vex")
+ "@
+ cvtsi2sd\t{%2, %0|%0, %2}
+ cvtsi2sd\t{%2, %0|%0, %2}
+ vcvtsi2sd\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "type" "sseicvt")
+ (set_attr "athlon_decode" "double,direct,*")
+ (set_attr "amdfam10_decode" "vector,double,*")
+ (set_attr "bdver1_decode" "double,direct,*")
+ (set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "DF")])
(define_insn "sse2_cvtsi2sdq"
- [(set (match_operand:V2DF 0 "register_operand" "=x,x")
+ [(set (match_operand:V2DF 0 "register_operand" "=x,x,x")
(vec_merge:V2DF
(vec_duplicate:V2DF
- (float:DF (match_operand:DI 2 "nonimmediate_operand" "r,m")))
- (match_operand:V2DF 1 "register_operand" "0,0")
+ (float:DF (match_operand:DI 2 "nonimmediate_operand" "r,m,rm")))
+ (match_operand:V2DF 1 "register_operand" "0,0,x")
(const_int 1)))]
"TARGET_SSE2 && TARGET_64BIT"
- "cvtsi2sdq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseicvt")
- (set_attr "prefix_rex" "1")
- (set_attr "mode" "DF")
- (set_attr "athlon_decode" "double,direct")
- (set_attr "amdfam10_decode" "vector,double")
- (set_attr "bdver1_decode" "double,direct")])
+ "@
+ cvtsi2sdq\t{%2, %0|%0, %2}
+ cvtsi2sdq\t{%2, %0|%0, %2}
+ vcvtsi2sdq\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "type" "sseicvt")
+ (set_attr "athlon_decode" "double,direct,*")
+ (set_attr "amdfam10_decode" "vector,double,*")
+ (set_attr "bdver1_decode" "double,direct,*")
+ (set_attr "length_vex" "*,*,4")
+ (set_attr "prefix_rex" "1,1,*")
+ (set_attr "prefix" "orig,orig,vex")
+ (set_attr "mode" "DF")])
(define_insn "sse2_cvtsd2si"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(parallel [(const_int 0)]))]
UNSPEC_FIX_NOTRUNC))]
"TARGET_SSE2 && TARGET_64BIT"
- "%vcvtsd2siq\t{%1, %0|%0, %1}"
+ "%vcvtsd2si{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "bdver1_decode" "double,double")
(unspec:DI [(match_operand:DF 1 "nonimmediate_operand" "x,m")]
UNSPEC_FIX_NOTRUNC))]
"TARGET_SSE2 && TARGET_64BIT"
- "%vcvtsd2siq\t{%1, %0|%0, %1}"
+ "%vcvtsd2si{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
"TARGET_SSE2"
"%vcvttsd2si\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
- (set_attr "prefix_rep" "1")
- (set_attr "prefix" "maybe_vex")
- (set_attr "mode" "SI")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
- (set_attr "bdver1_decode" "double,double")])
+ (set_attr "bdver1_decode" "double,double")
+ (set_attr "prefix_rep" "1")
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "mode" "SI")])
(define_insn "sse2_cvttsd2siq"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(match_operand:V2DF 1 "nonimmediate_operand" "x,m")
(parallel [(const_int 0)]))))]
"TARGET_SSE2 && TARGET_64BIT"
- "%vcvttsd2siq\t{%1, %0|%0, %1}"
+ "%vcvttsd2si{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
- (set_attr "prefix_rep" "1")
- (set_attr "prefix" "maybe_vex")
- (set_attr "mode" "DI")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
- (set_attr "bdver1_decode" "double,double")])
+ (set_attr "bdver1_decode" "double,double")
+ (set_attr "prefix_rep" "1")
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "mode" "DI")])
(define_insn "avx_cvtdq2pd256"
[(set (match_operand:V4DF 0 "register_operand" "=x")
(float:V4DF
(vec_select:V4SI
(match_operand:V8SI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))]
+ (parallel [(const_int 0) (const_int 1)
+ (const_int 2) (const_int 3)]))))]
"TARGET_AVX"
"vcvtdq2pd\t{%x1, %0|%0, %x1}"
[(set_attr "type" "ssecvt")
UNSPEC_FIX_NOTRUNC)
(match_operand:V2SI 2 "const0_operand" "")))]
"TARGET_SSE2"
- "* return TARGET_AVX ? \"vcvtpd2dq{x}\t{%1, %0|%0, %1}\"
- : \"cvtpd2dq\t{%1, %0|%0, %1}\";"
+{
+ if (TARGET_AVX)
+ return "vcvtpd2dq{x}\t{%1, %0|%0, %1}";
+ else
+ return "cvtpd2dq\t{%1, %0|%0, %1}";
+}
[(set_attr "type" "ssecvt")
(set_attr "prefix_rep" "1")
(set_attr "prefix_data16" "0")
(fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
(match_operand:V2SI 2 "const0_operand" "")))]
"TARGET_SSE2"
- "* return TARGET_AVX ? \"vcvttpd2dq{x}\t{%1, %0|%0, %1}\"
- : \"cvttpd2dq\t{%1, %0|%0, %1}\";"
+{
+ if (TARGET_AVX)
+ return "vcvttpd2dq{x}\t{%1, %0|%0, %1}";
+ else
+ return "cvttpd2dq\t{%1, %0|%0, %1}";
+}
[(set_attr "type" "ssecvt")
- (set_attr "prefix" "maybe_vex")
- (set_attr "mode" "TI")
(set_attr "amdfam10_decode" "double")
(set_attr "athlon_decode" "vector")
- (set_attr "bdver1_decode" "double")])
-
-(define_insn "*avx_cvtsd2ss"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (vec_duplicate:V4SF
- (float_truncate:V2SF
- (match_operand:V2DF 2 "nonimmediate_operand" "xm")))
- (match_operand:V4SF 1 "register_operand" "x")
- (const_int 1)))]
- "TARGET_AVX"
- "vcvtsd2ss\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "prefix" "vex")
- (set_attr "mode" "SF")])
+ (set_attr "bdver1_decode" "double")
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "mode" "TI")])
(define_insn "sse2_cvtsd2ss"
- [(set (match_operand:V4SF 0 "register_operand" "=x,x")
+ [(set (match_operand:V4SF 0 "register_operand" "=x,x,x")
(vec_merge:V4SF
(vec_duplicate:V4SF
(float_truncate:V2SF
- (match_operand:V2DF 2 "nonimmediate_operand" "x,m")))
- (match_operand:V4SF 1 "register_operand" "0,0")
+ (match_operand:V2DF 2 "nonimmediate_operand" "x,m,xm")))
+ (match_operand:V4SF 1 "register_operand" "0,0,x")
(const_int 1)))]
"TARGET_SSE2"
- "cvtsd2ss\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "athlon_decode" "vector,double")
- (set_attr "amdfam10_decode" "vector,double")
- (set_attr "bdver1_decode" "direct,direct")
+ "@
+ cvtsd2ss\t{%2, %0|%0, %2}
+ cvtsd2ss\t{%2, %0|%0, %2}
+ vcvtsd2ss\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "type" "ssecvt")
+ (set_attr "athlon_decode" "vector,double,*")
+ (set_attr "amdfam10_decode" "vector,double,*")
+ (set_attr "bdver1_decode" "direct,direct,*")
+ (set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "SF")])
-(define_insn "*avx_cvtss2sd"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_merge:V2DF
- (float_extend:V2DF
- (vec_select:V2SF
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0) (const_int 1)])))
- (match_operand:V2DF 1 "register_operand" "x")
- (const_int 1)))]
- "TARGET_AVX"
- "vcvtss2sd\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "prefix" "vex")
- (set_attr "mode" "DF")])
-
(define_insn "sse2_cvtss2sd"
- [(set (match_operand:V2DF 0 "register_operand" "=x,x")
+ [(set (match_operand:V2DF 0 "register_operand" "=x,x,x")
(vec_merge:V2DF
(float_extend:V2DF
(vec_select:V2SF
- (match_operand:V4SF 2 "nonimmediate_operand" "x,m")
+ (match_operand:V4SF 2 "nonimmediate_operand" "x,m,xm")
(parallel [(const_int 0) (const_int 1)])))
- (match_operand:V2DF 1 "register_operand" "0,0")
+ (match_operand:V2DF 1 "register_operand" "0,0,x")
(const_int 1)))]
"TARGET_SSE2"
- "cvtss2sd\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "amdfam10_decode" "vector,double")
- (set_attr "athlon_decode" "direct,direct")
- (set_attr "bdver1_decode" "direct,direct")
+ "@
+ cvtss2sd\t{%2, %0|%0, %2}
+ cvtss2sd\t{%2, %0|%0, %2}
+ vcvtss2sd\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "type" "ssecvt")
+ (set_attr "amdfam10_decode" "vector,double,*")
+ (set_attr "athlon_decode" "direct,direct,*")
+ (set_attr "bdver1_decode" "direct,direct,*")
+ (set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "DF")])
(define_insn "avx_cvtpd2ps256"
(match_operand:V2DF 1 "nonimmediate_operand" "xm"))
(match_operand:V2SF 2 "const0_operand" "")))]
"TARGET_SSE2"
- "* return TARGET_AVX ? \"vcvtpd2ps{x}\t{%1, %0|%0, %1}\"
- : \"cvtpd2ps\t{%1, %0|%0, %1}\";"
+{
+ if (TARGET_AVX)
+ return "vcvtpd2ps{x}\t{%1, %0|%0, %1}";
+ else
+ return "cvtpd2ps\t{%1, %0|%0, %1}";
+}
[(set_attr "type" "ssecvt")
- (set_attr "prefix_data16" "1")
- (set_attr "prefix" "maybe_vex")
- (set_attr "mode" "V4SF")
(set_attr "amdfam10_decode" "double")
(set_attr "athlon_decode" "vector")
- (set_attr "bdver1_decode" "double")])
+ (set_attr "bdver1_decode" "double")
+ (set_attr "prefix_data16" "1")
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "mode" "V4SF")])
(define_insn "avx_cvtps2pd256"
[(set (match_operand:V4DF 0 "register_operand" "=x")
(float_extend:V4DF
(vec_select:V4SF
(match_operand:V8SF 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))]
+ (parallel [(const_int 0) (const_int 1)
+ (const_int 2) (const_int 3)]))))]
"TARGET_AVX"
"vcvtps2pd\t{%x1, %0|%0, %x1}"
[(set_attr "type" "ssecvt")
"TARGET_SSE2"
"%vcvtps2pd\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
- (set_attr "prefix" "maybe_vex")
- (set_attr "mode" "V2DF")
- (set_attr "prefix_data16" "0")
(set_attr "amdfam10_decode" "direct")
(set_attr "athlon_decode" "double")
- (set_attr "bdver1_decode" "double")])
+ (set_attr "bdver1_decode" "double")
+ (set_attr "prefix_data16" "0")
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "mode" "V2DF")])
(define_expand "vec_unpacks_hi_v4sf"
[(set (match_dup 2)
(vec_concat:V8SF
(match_dup 2)
(match_operand:V4SF 1 "nonimmediate_operand" ""))
- (parallel [(const_int 6)
- (const_int 7)
- (const_int 2)
- (const_int 3)])))
+ (parallel [(const_int 6) (const_int 7)
+ (const_int 2) (const_int 3)])))
(set (match_operand:V2DF 0 "register_operand" "")
(float_extend:V2DF
(vec_select:V2SF
[(set (match_dup 2)
(vec_select:V4SF
(match_operand:V8SF 1 "nonimmediate_operand" "")
- (parallel [(const_int 4)
- (const_int 5)
- (const_int 6)
- (const_int 7)])))
+ (parallel [(const_int 4) (const_int 5)
+ (const_int 6) (const_int 7)])))
(set (match_operand:V4DF 0 "register_operand" "")
(float_extend:V4DF
(match_dup 2)))]
"TARGET_AVX"
-{
- operands[2] = gen_reg_rtx (V4SFmode);
-})
+ "operands[2] = gen_reg_rtx (V4SFmode);")
(define_expand "vec_unpacks_lo_v4sf"
[(set (match_operand:V2DF 0 "register_operand" "")
(float_extend:V4DF
(vec_select:V4SF
(match_operand:V8SF 1 "nonimmediate_operand" "")
- (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))]
+ (parallel [(const_int 0) (const_int 1)
+ (const_int 2) (const_int 3)]))))]
"TARGET_AVX")
(define_expand "vec_unpacks_float_hi_v8hi"
[(set (match_dup 2)
(vec_select:V4SI
(match_operand:V4SI 1 "nonimmediate_operand" "")
- (parallel [(const_int 2)
- (const_int 3)
- (const_int 2)
- (const_int 3)])))
+ (parallel [(const_int 2) (const_int 3)
+ (const_int 2) (const_int 3)])))
(set (match_operand:V2DF 0 "register_operand" "")
(float:V2DF
(vec_select:V2SI
[(set (match_dup 2)
(vec_select:V4SI
(match_operand:V8SI 1 "nonimmediate_operand" "")
- (parallel [(const_int 4)
- (const_int 5)
- (const_int 6)
- (const_int 7)])))
+ (parallel [(const_int 4) (const_int 5)
+ (const_int 6) (const_int 7)])))
(set (match_operand:V4DF 0 "register_operand" "")
(float:V4DF
(match_dup 2)))]
(float:V4DF
(vec_select:V4SI
(match_operand:V8SI 1 "nonimmediate_operand" "")
- (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))]
+ (parallel [(const_int 0) (const_int 1)
+ (const_int 2) (const_int 3)]))))]
"TARGET_AVX")
(define_expand "vec_unpacku_float_hi_v4si"
[(set (match_dup 5)
(vec_select:V4SI
(match_operand:V4SI 1 "nonimmediate_operand" "")
- (parallel [(const_int 2)
- (const_int 3)
- (const_int 2)
- (const_int 3)])))
+ (parallel [(const_int 2) (const_int 3)
+ (const_int 2) (const_int 3)])))
(set (match_dup 6)
(float:V2DF
(vec_select:V2SI
ix86_build_const_vector (V2DFmode, 1, x));
operands[5] = gen_reg_rtx (V4SImode);
-
+
for (i = 6; i < 9; i++)
operands[i] = gen_reg_rtx (V2DFmode);
})
"TARGET_SSE"
{
rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
-
+
emit_insn (gen_sse_movhlps (dst, operands[1], operands[2]));
/* Fix up the destination if needed. */
DONE;
})
-(define_insn "*avx_movhlps"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
- (vec_select:V4SF
- (vec_concat:V8SF
- (match_operand:V4SF 1 "nonimmediate_operand" " x,x,0")
- (match_operand:V4SF 2 "nonimmediate_operand" " x,o,x"))
- (parallel [(const_int 6)
- (const_int 7)
- (const_int 2)
- (const_int 3)])))]
- "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "@
- vmovhlps\t{%2, %1, %0|%0, %1, %2}
- vmovlps\t{%H2, %1, %0|%0, %1, %H2}
- vmovhps\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V4SF,V2SF,V2SF")])
-
(define_insn "sse_movhlps"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
+ [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,x,x,m")
(vec_select:V4SF
(vec_concat:V8SF
- (match_operand:V4SF 1 "nonimmediate_operand" " 0,0,0")
- (match_operand:V4SF 2 "nonimmediate_operand" " x,o,x"))
+ (match_operand:V4SF 1 "nonimmediate_operand" " 0,x,0,x,0")
+ (match_operand:V4SF 2 "nonimmediate_operand" " x,x,o,o,x"))
(parallel [(const_int 6)
(const_int 7)
(const_int 2)
"TARGET_SSE && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
movhlps\t{%2, %0|%0, %2}
+ vmovhlps\t{%2, %1, %0|%0, %1, %2}
movlps\t{%H2, %0|%0, %H2}
- movhps\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "V4SF,V2SF,V2SF")])
+ vmovlps\t{%H2, %1, %0|%0, %1, %H2}
+ %vmovhps\t{%2, %0|%0, %2}"
+ [(set_attr "isa" "noavx,avx,noavx,avx,*")
+ (set_attr "type" "ssemov")
+ (set_attr "prefix" "orig,vex,orig,vex,maybe_vex")
+ (set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")])
(define_expand "sse_movlhps_exp"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "")
"TARGET_SSE"
{
rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
-
+
emit_insn (gen_sse_movlhps (dst, operands[1], operands[2]));
/* Fix up the destination if needed. */
DONE;
})
-(define_insn "*avx_movlhps"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
- (vec_select:V4SF
- (vec_concat:V8SF
- (match_operand:V4SF 1 "nonimmediate_operand" " x,x,0")
- (match_operand:V4SF 2 "nonimmediate_operand" " x,m,x"))
- (parallel [(const_int 0)
- (const_int 1)
- (const_int 4)
- (const_int 5)])))]
- "TARGET_AVX && ix86_binary_operator_ok (UNKNOWN, V4SFmode, operands)"
- "@
- vmovlhps\t{%2, %1, %0|%0, %1, %2}
- vmovhps\t{%2, %1, %0|%0, %1, %2}
- vmovlps\t{%2, %H0|%H0, %2}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V4SF,V2SF,V2SF")])
-
(define_insn "sse_movlhps"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
+ [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,x,x,o")
(vec_select:V4SF
(vec_concat:V8SF
- (match_operand:V4SF 1 "nonimmediate_operand" " 0,0,0")
- (match_operand:V4SF 2 "nonimmediate_operand" " x,m,x"))
+ (match_operand:V4SF 1 "nonimmediate_operand" " 0,x,0,x,0")
+ (match_operand:V4SF 2 "nonimmediate_operand" " x,x,m,x,x"))
(parallel [(const_int 0)
(const_int 1)
(const_int 4)
"TARGET_SSE && ix86_binary_operator_ok (UNKNOWN, V4SFmode, operands)"
"@
movlhps\t{%2, %0|%0, %2}
+ vmovlhps\t{%2, %1, %0|%0, %1, %2}
movhps\t{%2, %0|%0, %2}
- movlps\t{%2, %H0|%H0, %2}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "V4SF,V2SF,V2SF")])
+ vmovhps\t{%2, %1, %0|%0, %1, %2}
+ %vmovlps\t{%2, %H0|%H0, %2}"
+ [(set_attr "isa" "noavx,avx,noavx,avx,*")
+ (set_attr "type" "ssemov")
+ (set_attr "prefix" "orig,vex,orig,vex,maybe_vex")
+ (set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")])
;; Recall that the 256-bit unpck insns only shuffle within their lanes.
(define_insn "avx_unpckhps256"
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
-(define_insn "*avx_interleave_highv4sf"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_select:V4SF
- (vec_concat:V8SF
- (match_operand:V4SF 1 "register_operand" "x")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
- (parallel [(const_int 2) (const_int 6)
- (const_int 3) (const_int 7)])))]
- "TARGET_AVX"
- "vunpckhps\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V4SF")])
-
(define_expand "vec_interleave_highv8sf"
[(set (match_dup 3)
(vec_select:V8SF
})
(define_insn "vec_interleave_highv4sf"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
+ [(set (match_operand:V4SF 0 "register_operand" "=x,x")
(vec_select:V4SF
(vec_concat:V8SF
- (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
+ (match_operand:V4SF 1 "register_operand" "0,x")
+ (match_operand:V4SF 2 "nonimmediate_operand" "xm,xm"))
(parallel [(const_int 2) (const_int 6)
(const_int 3) (const_int 7)])))]
"TARGET_SSE"
- "unpckhps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
+ "@
+ unpckhps\t{%2, %0|%0, %2}
+ vunpckhps\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "V4SF")])
;; Recall that the 256-bit unpck insns only shuffle within their lanes.
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
-(define_insn "*avx_interleave_lowv4sf"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_select:V4SF
- (vec_concat:V8SF
- (match_operand:V4SF 1 "register_operand" "x")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
- (parallel [(const_int 0) (const_int 4)
- (const_int 1) (const_int 5)])))]
- "TARGET_AVX"
- "vunpcklps\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V4SF")])
-
(define_expand "vec_interleave_lowv8sf"
[(set (match_dup 3)
(vec_select:V8SF
})
(define_insn "vec_interleave_lowv4sf"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
+ [(set (match_operand:V4SF 0 "register_operand" "=x,x")
(vec_select:V4SF
(vec_concat:V8SF
- (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
+ (match_operand:V4SF 1 "register_operand" "0,x")
+ (match_operand:V4SF 2 "nonimmediate_operand" "xm,xm"))
(parallel [(const_int 0) (const_int 4)
(const_int 1) (const_int 5)])))]
"TARGET_SSE"
- "unpcklps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
+ "@
+ unpcklps\t{%2, %0|%0, %2}
+ vunpcklps\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "V4SF")])
;; These are modeled with the same vec_concat as the others so that we
DONE;
})
-(define_insn "*avx_shufps_<mode>"
- [(set (match_operand:SSEMODE4S 0 "register_operand" "=x")
- (vec_select:SSEMODE4S
- (vec_concat:<ssedoublesizemode>
- (match_operand:SSEMODE4S 1 "register_operand" "x")
- (match_operand:SSEMODE4S 2 "nonimmediate_operand" "xm"))
- (parallel [(match_operand 3 "const_0_to_3_operand" "")
- (match_operand 4 "const_0_to_3_operand" "")
- (match_operand 5 "const_4_to_7_operand" "")
- (match_operand 6 "const_4_to_7_operand" "")])))]
- "TARGET_AVX"
-{
- int mask = 0;
- mask |= INTVAL (operands[3]) << 0;
- mask |= INTVAL (operands[4]) << 2;
- mask |= (INTVAL (operands[5]) - 4) << 4;
- mask |= (INTVAL (operands[6]) - 4) << 6;
- operands[3] = GEN_INT (mask);
-
- return "vshufps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
-}
- [(set_attr "type" "sselog")
- (set_attr "length_immediate" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V4SF")])
-
(define_insn "sse_shufps_<mode>"
- [(set (match_operand:SSEMODE4S 0 "register_operand" "=x")
- (vec_select:SSEMODE4S
- (vec_concat:<ssedoublesizemode>
- (match_operand:SSEMODE4S 1 "register_operand" "0")
- (match_operand:SSEMODE4S 2 "nonimmediate_operand" "xm"))
+ [(set (match_operand:VI4F_128 0 "register_operand" "=x,x")
+ (vec_select:VI4F_128
+ (vec_concat:<ssedoublevecmode>
+ (match_operand:VI4F_128 1 "register_operand" "0,x")
+ (match_operand:VI4F_128 2 "nonimmediate_operand" "xm,xm"))
(parallel [(match_operand 3 "const_0_to_3_operand" "")
(match_operand 4 "const_0_to_3_operand" "")
(match_operand 5 "const_4_to_7_operand" "")
mask |= (INTVAL (operands[6]) - 4) << 6;
operands[3] = GEN_INT (mask);
- return "shufps\t{%3, %2, %0|%0, %2, %3}";
+ switch (which_alternative)
+ {
+ case 0:
+ return "shufps\t{%3, %2, %0|%0, %2, %3}";
+ case 1:
+ return "vshufps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
+ default:
+ gcc_unreachable ();
+ }
}
- [(set_attr "type" "sselog")
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
(set_attr "length_immediate" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "V4SF")])
(define_insn "sse_storehps"
"TARGET_SSE"
{
rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
-
+
emit_insn (gen_sse_loadhps (dst, operands[1], operands[2]));
/* Fix up the destination if needed. */
DONE;
})
-(define_insn "*avx_loadhps"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
- (vec_concat:V4SF
- (vec_select:V2SF
- (match_operand:V4SF 1 "nonimmediate_operand" "x,x,0")
- (parallel [(const_int 0) (const_int 1)]))
- (match_operand:V2SF 2 "nonimmediate_operand" "m,x,x")))]
- "TARGET_AVX"
- "@
- vmovhps\t{%2, %1, %0|%0, %1, %2}
- vmovlhps\t{%2, %1, %0|%0, %1, %2}
- vmovlps\t{%2, %H0|%H0, %2}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V2SF,V4SF,V2SF")])
-
(define_insn "sse_loadhps"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
+ [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,x,x,o")
(vec_concat:V4SF
(vec_select:V2SF
- (match_operand:V4SF 1 "nonimmediate_operand" "0,0,0")
+ (match_operand:V4SF 1 "nonimmediate_operand" " 0,x,0,x,0")
(parallel [(const_int 0) (const_int 1)]))
- (match_operand:V2SF 2 "nonimmediate_operand" "m,x,x")))]
+ (match_operand:V2SF 2 "nonimmediate_operand" " m,m,x,x,x")))]
"TARGET_SSE"
"@
movhps\t{%2, %0|%0, %2}
+ vmovhps\t{%2, %1, %0|%0, %1, %2}
movlhps\t{%2, %0|%0, %2}
- movlps\t{%2, %H0|%H0, %2}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "V2SF,V4SF,V2SF")])
-
-(define_insn "*avx_storelps"
- [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
- (vec_select:V2SF
- (match_operand:V4SF 1 "nonimmediate_operand" "x,x,m")
- (parallel [(const_int 0) (const_int 1)])))]
- "TARGET_AVX"
- "@
- vmovlps\t{%1, %0|%0, %1}
- vmovaps\t{%1, %0|%0, %1}
- vmovlps\t{%1, %0, %0|%0, %0, %1}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V2SF,V2DF,V2SF")])
+ vmovlhps\t{%2, %1, %0|%0, %1, %2}
+ %vmovlps\t{%2, %H0|%H0, %2}"
+ [(set_attr "isa" "noavx,avx,noavx,avx,*")
+ (set_attr "type" "ssemov")
+ (set_attr "prefix" "orig,vex,orig,vex,maybe_vex")
+ (set_attr "mode" "V2SF,V2SF,V4SF,V4SF,V2SF")])
(define_insn "sse_storelps"
- [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
+ [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
(vec_select:V2SF
- (match_operand:V4SF 1 "nonimmediate_operand" "x,x,m")
+ (match_operand:V4SF 1 "nonimmediate_operand" " x,x,m")
(parallel [(const_int 0) (const_int 1)])))]
"TARGET_SSE"
"@
- movlps\t{%1, %0|%0, %1}
- movaps\t{%1, %0|%0, %1}
- movlps\t{%1, %0|%0, %1}"
+ %vmovlps\t{%1, %0|%0, %1}
+ %vmovaps\t{%1, %0|%0, %1}
+ %vmovlps\t{%1, %d0|%d0, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "prefix" "maybe_vex")
(set_attr "mode" "V2SF,V4SF,V2SF")])
(define_expand "sse_loadlps_exp"
"TARGET_SSE"
{
rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
-
+
emit_insn (gen_sse_loadlps (dst, operands[1], operands[2]));
/* Fix up the destination if needed. */
DONE;
})
-(define_insn "*avx_loadlps"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
- (vec_concat:V4SF
- (match_operand:V2SF 2 "nonimmediate_operand" "x,m,x")
- (vec_select:V2SF
- (match_operand:V4SF 1 "nonimmediate_operand" "x,x,0")
- (parallel [(const_int 2) (const_int 3)]))))]
- "TARGET_AVX"
- "@
- shufps\t{$0xe4, %1, %2, %0|%0, %2, %1, 0xe4}
- vmovlps\t{%2, %1, %0|%0, %1, %2}
- vmovlps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog,ssemov,ssemov")
- (set_attr "length_immediate" "1,*,*")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V4SF,V2SF,V2SF")])
-
(define_insn "sse_loadlps"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
+ [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,x,x,m")
(vec_concat:V4SF
- (match_operand:V2SF 2 "nonimmediate_operand" "0,m,x")
+ (match_operand:V2SF 2 "nonimmediate_operand" " 0,x,m,x,x")
(vec_select:V2SF
- (match_operand:V4SF 1 "nonimmediate_operand" "x,0,0")
+ (match_operand:V4SF 1 "nonimmediate_operand" " x,x,0,x,0")
(parallel [(const_int 2) (const_int 3)]))))]
"TARGET_SSE"
"@
shufps\t{$0xe4, %1, %0|%0, %1, 0xe4}
+ vshufps\t{$0xe4, %1, %2, %0|%0, %2, %1, 0xe4}
movlps\t{%2, %0|%0, %2}
- movlps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog,ssemov,ssemov")
- (set_attr "length_immediate" "1,*,*")
- (set_attr "mode" "V4SF,V2SF,V2SF")])
+ vmovlps\t{%2, %1, %0|%0, %1, %2}
+ %vmovlps\t{%2, %0|%0, %2}"
+ [(set_attr "isa" "noavx,avx,noavx,avx,*")
+ (set_attr "type" "sselog,sselog,ssemov,ssemov,ssemov")
+ (set_attr "length_immediate" "1,1,*,*,*")
+ (set_attr "prefix" "orig,vex,orig,vex,maybe_vex")
+ (set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")])
-(define_insn "*avx_movss"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
+(define_insn "sse_movss"
+ [(set (match_operand:V4SF 0 "register_operand" "=x,x")
(vec_merge:V4SF
- (match_operand:V4SF 2 "register_operand" "x")
- (match_operand:V4SF 1 "register_operand" "x")
- (const_int 1)))]
- "TARGET_AVX"
- "vmovss\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "SF")])
-
-(define_insn "sse_movss"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (match_operand:V4SF 2 "register_operand" "x")
- (match_operand:V4SF 1 "register_operand" "0")
+ (match_operand:V4SF 2 "register_operand" " x,x")
+ (match_operand:V4SF 1 "register_operand" " 0,x")
(const_int 1)))]
"TARGET_SSE"
- "movss\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssemov")
+ "@
+ movss\t{%2, %0|%0, %2}
+ vmovss\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssemov")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "SF")])
(define_expand "vec_dupv4sf"
"TARGET_SSE"
{
if (!TARGET_AVX)
- operands[1] = force_reg (V4SFmode, operands[1]);
+ operands[1] = force_reg (SFmode, operands[1]);
})
(define_insn "*vec_dupv4sf_avx"
(set_attr "length_immediate" "1")
(set_attr "mode" "V4SF")])
-(define_insn "*vec_concatv2sf_avx"
- [(set (match_operand:V2SF 0 "register_operand" "=x,x,x,*y ,*y")
- (vec_concat:V2SF
- (match_operand:SF 1 "nonimmediate_operand" " x,x,m, x , m")
- (match_operand:SF 2 "vector_move_operand" " x,m,C,*ym, C")))]
- "TARGET_AVX"
- "@
- vunpcklps\t{%2, %1, %0|%0, %1, %2}
- vinsertps\t{$0x10, %2, %1, %0|%0, %1, %2, 0x10}
- vmovss\t{%1, %0|%0, %1}
- punpckldq\t{%2, %0|%0, %2}
- movd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
- (set_attr "length_immediate" "*,1,*,*,*")
- (set_attr "prefix_extra" "*,1,*,*,*")
- (set (attr "prefix")
- (if_then_else (eq_attr "alternative" "3,4")
- (const_string "orig")
- (const_string "vex")))
- (set_attr "mode" "V4SF,V4SF,SF,DI,DI")])
-
;; Although insertps takes register source, we prefer
;; unpcklps with register source since it is shorter.
(define_insn "*vec_concatv2sf_sse4_1"
- [(set (match_operand:V2SF 0 "register_operand" "=x,x,x,*y ,*y")
+ [(set (match_operand:V2SF 0 "register_operand" "=x,x,x,x,x,*y ,*y")
(vec_concat:V2SF
- (match_operand:SF 1 "nonimmediate_operand" " 0,0,m, 0 , m")
- (match_operand:SF 2 "vector_move_operand" " x,m,C,*ym, C")))]
+ (match_operand:SF 1 "nonimmediate_operand" " 0,x,0,x,m, 0 , m")
+ (match_operand:SF 2 "vector_move_operand" " x,x,m,m,C,*ym, C")))]
"TARGET_SSE4_1"
"@
unpcklps\t{%2, %0|%0, %2}
+ vunpcklps\t{%2, %1, %0|%0, %1, %2}
insertps\t{$0x10, %2, %0|%0, %2, 0x10}
- movss\t{%1, %0|%0, %1}
+ vinsertps\t{$0x10, %2, %1, %0|%0, %1, %2, 0x10}
+ %vmovss\t{%1, %0|%0, %1}
punpckldq\t{%2, %0|%0, %2}
movd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
- (set_attr "prefix_data16" "*,1,*,*,*")
- (set_attr "prefix_extra" "*,1,*,*,*")
- (set_attr "length_immediate" "*,1,*,*,*")
- (set_attr "mode" "V4SF,V4SF,SF,DI,DI")])
+ [(set_attr "isa" "noavx,avx,noavx,avx,*,*,*")
+ (set_attr "type" "sselog,sselog,sselog,sselog,ssemov,mmxcvt,mmxmov")
+ (set_attr "prefix_data16" "*,*,1,*,*,*,*")
+ (set_attr "prefix_extra" "*,*,1,1,*,*,*")
+ (set_attr "length_immediate" "*,*,1,1,*,*,*")
+ (set_attr "prefix" "orig,vex,orig,vex,maybe_vex,orig,orig")
+ (set_attr "mode" "V4SF,V4SF,V4SF,V4SF,SF,DI,DI")])
;; ??? In theory we can match memory for the MMX alternative, but allowing
;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE
[(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
(set_attr "mode" "V4SF,SF,DI,DI")])
-(define_insn "*vec_concatv4sf_avx"
- [(set (match_operand:V4SF 0 "register_operand" "=x,x")
- (vec_concat:V4SF
- (match_operand:V2SF 1 "register_operand" " x,x")
- (match_operand:V2SF 2 "nonimmediate_operand" " x,m")))]
- "TARGET_AVX"
- "@
- vmovlhps\t{%2, %1, %0|%0, %1, %2}
- vmovhps\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V4SF,V2SF")])
-
-(define_insn "*vec_concatv4sf_sse"
- [(set (match_operand:V4SF 0 "register_operand" "=x,x")
+(define_insn "*vec_concatv4sf"
+ [(set (match_operand:V4SF 0 "register_operand" "=x,x,x,x")
(vec_concat:V4SF
- (match_operand:V2SF 1 "register_operand" " 0,0")
- (match_operand:V2SF 2 "nonimmediate_operand" " x,m")))]
+ (match_operand:V2SF 1 "register_operand" " 0,x,0,x")
+ (match_operand:V2SF 2 "nonimmediate_operand" " x,x,m,m")))]
"TARGET_SSE"
"@
movlhps\t{%2, %0|%0, %2}
- movhps\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "V4SF,V2SF")])
+ vmovlhps\t{%2, %1, %0|%0, %1, %2}
+ movhps\t{%2, %0|%0, %2}
+ vmovhps\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx,noavx,avx")
+ (set_attr "type" "ssemov")
+ (set_attr "prefix" "orig,vex,orig,vex")
+ (set_attr "mode" "V4SF,V4SF,V2SF,V2SF")])
(define_expand "vec_init<mode>"
- [(match_operand:SSEMODE 0 "register_operand" "")
+ [(match_operand:V_128 0 "register_operand" "")
(match_operand 1 "" "")]
"TARGET_SSE"
{
DONE;
})
-(define_insn "*vec_set<mode>_0_avx"
- [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand" "=x,x, x,x, x,m")
- (vec_merge:SSEMODE4S
- (vec_duplicate:SSEMODE4S
- (match_operand:<ssescalarmode> 2
- "general_operand" " x,m,*r,x,*rm,x*rfF"))
- (match_operand:SSEMODE4S 1 "vector_move_operand" " C,C, C,x, x,0")
- (const_int 1)))]
- "TARGET_AVX"
- "@
- vinsertps\t{$0xe, %2, %2, %0|%0, %2, %2, 0xe}
- vmov<ssescalarmodesuffix>\t{%2, %0|%0, %2}
- vmovd\t{%2, %0|%0, %2}
- vmovss\t{%2, %1, %0|%0, %1, %2}
- vpinsrd\t{$0, %2, %1, %0|%0, %1, %2, 0}
- #"
- [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,*")
- (set_attr "prefix_extra" "*,*,*,*,1,*")
- (set_attr "length_immediate" "*,*,*,*,1,*")
- (set_attr "prefix" "vex")
- (set_attr "mode" "SF,<ssescalarmode>,SI,SF,TI,*")])
-
-(define_insn "*vec_set<mode>_0_sse4_1"
- [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand" "=x,x, x,x, x,m")
- (vec_merge:SSEMODE4S
- (vec_duplicate:SSEMODE4S
- (match_operand:<ssescalarmode> 2
- "general_operand" " x,m,*r,x,*rm,*rfF"))
- (match_operand:SSEMODE4S 1 "vector_move_operand" " C,C, C,0, 0,0")
- (const_int 1)))]
- "TARGET_SSE4_1"
- "@
- insertps\t{$0xe, %2, %0|%0, %2, 0xe}
- mov<ssescalarmodesuffix>\t{%2, %0|%0, %2}
- movd\t{%2, %0|%0, %2}
- movss\t{%2, %0|%0, %2}
- pinsrd\t{$0, %2, %0|%0, %2, 0}
- #"
- [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,*")
- (set_attr "prefix_extra" "*,*,*,*,1,*")
- (set_attr "length_immediate" "*,*,*,*,1,*")
- (set_attr "mode" "SF,<ssescalarmode>,SI,SF,TI,*")])
-
-(define_insn "*vec_set<mode>_0_sse2"
- [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand" "=x, x,x,m")
- (vec_merge:SSEMODE4S
- (vec_duplicate:SSEMODE4S
- (match_operand:<ssescalarmode> 2
- "general_operand" " m,*r,x,x*rfF"))
- (match_operand:SSEMODE4S 1 "vector_move_operand" " C, C,0,0")
- (const_int 1)))]
- "TARGET_SSE2"
- "@
- mov<ssescalarmodesuffix>\t{%2, %0|%0, %2}
- movd\t{%2, %0|%0, %2}
- movss\t{%2, %0|%0, %2}
- #"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "<ssescalarmode>,SI,SF,*")])
-
+;; Avoid combining registers from different units in a single alternative,
+;; see comment above inline_secondary_memory_needed function in i386.c
(define_insn "vec_set<mode>_0"
- [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand" "=x,x,m")
- (vec_merge:SSEMODE4S
- (vec_duplicate:SSEMODE4S
- (match_operand:<ssescalarmode> 2
- "general_operand" " m,x,x*rfF"))
- (match_operand:SSEMODE4S 1 "vector_move_operand" " C,0,0")
+ [(set (match_operand:VI4F_128 0 "nonimmediate_operand"
+ "=Y4,Y2,Y2,x,x,x,Y4 ,x ,m,m ,m")
+ (vec_merge:VI4F_128
+ (vec_duplicate:VI4F_128
+ (match_operand:<ssescalarmode> 2 "general_operand"
+ " Y4,m ,*r,m,x,x,*rm,*rm,x,fF,*r"))
+ (match_operand:VI4F_128 1 "vector_move_operand"
+ " C ,C ,C ,C,0,x,0 ,x ,0,0 ,0")
(const_int 1)))]
"TARGET_SSE"
"@
+ %vinsertps\t{$0xe, %d2, %0|%0, %d2, 0xe}
+ %vmov<ssescalarmodesuffix>\t{%2, %0|%0, %2}
+ %vmovd\t{%2, %0|%0, %2}
movss\t{%2, %0|%0, %2}
movss\t{%2, %0|%0, %2}
+ vmovss\t{%2, %1, %0|%0, %1, %2}
+ pinsrd\t{$0, %2, %0|%0, %2, 0}
+ vpinsrd\t{$0, %2, %1, %0|%0, %1, %2, 0}
+ #
+ #
#"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "SF,SF,*")])
+ [(set_attr "isa" "*,*,*,noavx,noavx,avx,noavx,avx,*,*,*")
+ (set (attr "type")
+ (cond [(eq_attr "alternative" "0,6,7")
+ (const_string "sselog")
+ (eq_attr "alternative" "9")
+ (const_string "fmov")
+ (eq_attr "alternative" "10")
+ (const_string "imov")
+ ]
+ (const_string "ssemov")))
+ (set_attr "prefix_extra" "*,*,*,*,*,*,1,1,*,*,*")
+ (set_attr "length_immediate" "*,*,*,*,*,*,1,1,*,*,*")
+ (set_attr "prefix" "maybe_vex,maybe_vex,maybe_vex,orig,orig,vex,orig,vex,*,*,*")
+ (set_attr "mode" "SF,<ssescalarmode>,SI,SF,SF,SF,TI,TI,*,*,*")])
;; A subset is vec_setv4sf.
-(define_insn "*vec_setv4sf_avx"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (vec_duplicate:V4SF
- (match_operand:SF 2 "nonimmediate_operand" "xm"))
- (match_operand:V4SF 1 "register_operand" "x")
- (match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))]
- "TARGET_AVX"
-{
- operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])) << 4);
- return "vinsertps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
-}
- [(set_attr "type" "sselog")
- (set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V4SF")])
-
(define_insn "*vec_setv4sf_sse4_1"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
+ [(set (match_operand:V4SF 0 "register_operand" "=x,x")
(vec_merge:V4SF
(vec_duplicate:V4SF
- (match_operand:SF 2 "nonimmediate_operand" "xm"))
- (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))]
- "TARGET_SSE4_1"
+ (match_operand:SF 2 "nonimmediate_operand" "xm,xm"))
+ (match_operand:V4SF 1 "register_operand" "0,x")
+ (match_operand:SI 3 "const_int_operand" "")))]
+ "TARGET_SSE4_1
+ && ((unsigned) exact_log2 (INTVAL (operands[3]))
+ < GET_MODE_NUNITS (V4SFmode))"
{
operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])) << 4);
- return "insertps\t{%3, %2, %0|%0, %2, %3}";
+ switch (which_alternative)
+ {
+ case 0:
+ return "insertps\t{%3, %2, %0|%0, %2, %3}";
+ case 1:
+ return "vinsertps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
+ default:
+ gcc_unreachable ();
+ }
}
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "V4SF")])
-
-(define_insn "*avx_insertps"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (unspec:V4SF [(match_operand:V4SF 2 "nonimmediate_operand" "xm")
- (match_operand:V4SF 1 "register_operand" "x")
- (match_operand:SI 3 "const_0_to_255_operand" "n")]
- UNSPEC_INSERTPS))]
- "TARGET_AVX"
- "vinsertps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "V4SF")])
(define_insn "sse4_1_insertps"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (unspec:V4SF [(match_operand:V4SF 2 "register_operand" "x")
- (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:SI 3 "const_0_to_255_operand" "n")]
+ [(set (match_operand:V4SF 0 "register_operand" "=x,x")
+ (unspec:V4SF [(match_operand:V4SF 2 "nonimmediate_operand" "xm,xm")
+ (match_operand:V4SF 1 "register_operand" "0,x")
+ (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
UNSPEC_INSERTPS))]
"TARGET_SSE4_1"
- "insertps\t{%3, %2, %0|%0, %2, %3}";
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
+{
+ if (MEM_P (operands[2]))
+ {
+ unsigned count_s = INTVAL (operands[3]) >> 6;
+ if (count_s)
+ operands[3] = GEN_INT (INTVAL (operands[3]) & 0x3f);
+ operands[2] = adjust_address_nv (operands[2], SFmode, count_s * 4);
+ }
+ switch (which_alternative)
+ {
+ case 0:
+ return "insertps\t{%3, %2, %0|%0, %2, %3}";
+ case 1:
+ return "vinsertps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
+ default:
+ gcc_unreachable ();
+ }
+}
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "V4SF")])
(define_split
- [(set (match_operand:SSEMODE4S 0 "memory_operand" "")
- (vec_merge:SSEMODE4S
- (vec_duplicate:SSEMODE4S
+ [(set (match_operand:VI4F_128 0 "memory_operand" "")
+ (vec_merge:VI4F_128
+ (vec_duplicate:VI4F_128
(match_operand:<ssescalarmode> 1 "nonmemory_operand" ""))
(match_dup 0)
(const_int 1)))]
})
(define_expand "vec_set<mode>"
- [(match_operand:SSEMODE 0 "register_operand" "")
+ [(match_operand:V_128 0 "register_operand" "")
(match_operand:<ssescalarmode> 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")]
"TARGET_SSE"
})
(define_expand "avx_vextractf128<mode>"
- [(match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "")
- (match_operand:AVX256MODE 1 "register_operand" "")
+ [(match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "")
+ (match_operand:V_256 1 "register_operand" "")
(match_operand:SI 2 "const_0_to_1_operand" "")]
"TARGET_AVX"
{
})
(define_insn_and_split "vec_extract_lo_<mode>"
- [(set (match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "=x,m")
- (vec_select:<avxhalfvecmode>
- (match_operand:AVX256MODE4P 1 "nonimmediate_operand" "xm,x")
+ [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=x,m")
+ (vec_select:<ssehalfvecmode>
+ (match_operand:VI8F_256 1 "nonimmediate_operand" "xm,x")
(parallel [(const_int 0) (const_int 1)])))]
"TARGET_AVX"
"#"
{
rtx op1 = operands[1];
if (REG_P (op1))
- op1 = gen_rtx_REG (<avxhalfvecmode>mode, REGNO (op1));
+ op1 = gen_rtx_REG (<ssehalfvecmode>mode, REGNO (op1));
else
- op1 = gen_lowpart (<avxhalfvecmode>mode, op1);
+ op1 = gen_lowpart (<ssehalfvecmode>mode, op1);
emit_move_insn (operands[0], op1);
DONE;
})
(define_insn "vec_extract_hi_<mode>"
- [(set (match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "=x,m")
- (vec_select:<avxhalfvecmode>
- (match_operand:AVX256MODE4P 1 "register_operand" "x,x")
+ [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=x,m")
+ (vec_select:<ssehalfvecmode>
+ (match_operand:VI8F_256 1 "register_operand" "x,x")
(parallel [(const_int 2) (const_int 3)])))]
"TARGET_AVX"
"vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
(set_attr "mode" "V8SF")])
(define_insn_and_split "vec_extract_lo_<mode>"
- [(set (match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "=x,m")
- (vec_select:<avxhalfvecmode>
- (match_operand:AVX256MODE8P 1 "nonimmediate_operand" "xm,x")
+ [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=x,m")
+ (vec_select:<ssehalfvecmode>
+ (match_operand:VI4F_256 1 "nonimmediate_operand" "xm,x")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))]
"TARGET_AVX"
{
rtx op1 = operands[1];
if (REG_P (op1))
- op1 = gen_rtx_REG (<avxhalfvecmode>mode, REGNO (op1));
+ op1 = gen_rtx_REG (<ssehalfvecmode>mode, REGNO (op1));
else
- op1 = gen_lowpart (<avxhalfvecmode>mode, op1);
+ op1 = gen_lowpart (<ssehalfvecmode>mode, op1);
emit_move_insn (operands[0], op1);
DONE;
})
(define_insn "vec_extract_hi_<mode>"
- [(set (match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "=x,m")
- (vec_select:<avxhalfvecmode>
- (match_operand:AVX256MODE8P 1 "register_operand" "x,x")
+ [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=x,m")
+ (vec_select:<ssehalfvecmode>
+ (match_operand:VI4F_256 1 "register_operand" "x,x")
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)])))]
"TARGET_AVX"
DONE;
})
+;; Modes handled by vec_extract patterns.
+(define_mode_iterator VEC_EXTRACT_MODE
+ [V16QI V8HI V4SI V2DI
+ (V8SF "TARGET_AVX") V4SF
+ (V4DF "TARGET_AVX") V2DF])
+
(define_expand "vec_extract<mode>"
- [(match_operand:<avxscalarmode> 0 "register_operand" "")
+ [(match_operand:<ssescalarmode> 0 "register_operand" "")
(match_operand:VEC_EXTRACT_MODE 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")]
"TARGET_SSE"
operands[2] = force_reg (V2DFmode, operands[2]);
})
-(define_insn "*avx_interleave_highv2df"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,m")
- (vec_select:V2DF
- (vec_concat:V4DF
- (match_operand:V2DF 1 "nonimmediate_operand" " x,o,o,x")
- (match_operand:V2DF 2 "nonimmediate_operand" " x,1,x,0"))
- (parallel [(const_int 1)
- (const_int 3)])))]
- "TARGET_AVX && ix86_vec_interleave_v2df_operator_ok (operands, 1)"
- "@
- vunpckhpd\t{%2, %1, %0|%0, %1, %2}
- vmovddup\t{%H1, %0|%0, %H1}
- vmovlpd\t{%H1, %2, %0|%0, %2, %H1}
- vmovhpd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sselog,sselog,ssemov,ssemov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V2DF,V2DF,V1DF,V1DF")])
-
-(define_insn "*sse3_interleave_highv2df"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,m")
- (vec_select:V2DF
- (vec_concat:V4DF
- (match_operand:V2DF 1 "nonimmediate_operand" " 0,o,o,x")
- (match_operand:V2DF 2 "nonimmediate_operand" " x,1,0,0"))
- (parallel [(const_int 1)
- (const_int 3)])))]
- "TARGET_SSE3 && ix86_vec_interleave_v2df_operator_ok (operands, 1)"
- "@
- unpckhpd\t{%2, %0|%0, %2}
- movddup\t{%H1, %0|%0, %H1}
- movlpd\t{%H1, %0|%0, %H1}
- movhpd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sselog,sselog,ssemov,ssemov")
- (set_attr "prefix_data16" "*,*,1,1")
- (set_attr "mode" "V2DF,V2DF,V1DF,V1DF")])
-
-(define_insn "*sse2_interleave_highv2df"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
+(define_insn "*vec_interleave_highv2df"
+ [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,Y3,x,x,m")
(vec_select:V2DF
(vec_concat:V4DF
- (match_operand:V2DF 1 "nonimmediate_operand" " 0,o,x")
- (match_operand:V2DF 2 "nonimmediate_operand" " x,0,0"))
+ (match_operand:V2DF 1 "nonimmediate_operand" " 0,x,o ,o,o,x")
+ (match_operand:V2DF 2 "nonimmediate_operand" " x,x,1 ,0,x,0"))
(parallel [(const_int 1)
(const_int 3)])))]
"TARGET_SSE2 && ix86_vec_interleave_v2df_operator_ok (operands, 1)"
"@
unpckhpd\t{%2, %0|%0, %2}
+ vunpckhpd\t{%2, %1, %0|%0, %1, %2}
+ %vmovddup\t{%H1, %0|%0, %H1}
movlpd\t{%H1, %0|%0, %H1}
- movhpd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sselog,ssemov,ssemov")
- (set_attr "prefix_data16" "*,1,1")
- (set_attr "mode" "V2DF,V1DF,V1DF")])
+ vmovlpd\t{%H1, %2, %0|%0, %2, %H1}
+ %vmovhpd\t{%1, %0|%0, %1}"
+ [(set_attr "isa" "noavx,avx,*,noavx,avx,*")
+ (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov")
+ (set_attr "prefix_data16" "*,*,*,1,*,1")
+ (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex")
+ (set_attr "mode" "V2DF,V2DF,V2DF,V1DF,V1DF,V1DF")])
;; Recall that the 256-bit unpck insns only shuffle within their lanes.
(define_expand "avx_movddup256"
operands[1] = force_reg (V2DFmode, operands[1]);
})
-(define_insn "*avx_interleave_lowv2df"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,o")
- (vec_select:V2DF
- (vec_concat:V4DF
- (match_operand:V2DF 1 "nonimmediate_operand" " x,m,x,0")
- (match_operand:V2DF 2 "nonimmediate_operand" " x,1,m,x"))
- (parallel [(const_int 0)
- (const_int 2)])))]
- "TARGET_AVX && ix86_vec_interleave_v2df_operator_ok (operands, 0)"
- "@
- vunpcklpd\t{%2, %1, %0|%0, %1, %2}
- vmovddup\t{%1, %0|%0, %1}
- vmovhpd\t{%2, %1, %0|%0, %1, %2}
- vmovlpd\t{%2, %H0|%H0, %2}"
- [(set_attr "type" "sselog,sselog,ssemov,ssemov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V2DF,V2DF,V1DF,V1DF")])
-
-(define_insn "*sse3_interleave_lowv2df"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,o")
- (vec_select:V2DF
- (vec_concat:V4DF
- (match_operand:V2DF 1 "nonimmediate_operand" " 0,m,0,0")
- (match_operand:V2DF 2 "nonimmediate_operand" " x,1,m,x"))
- (parallel [(const_int 0)
- (const_int 2)])))]
- "TARGET_SSE3 && ix86_vec_interleave_v2df_operator_ok (operands, 0)"
- "@
- unpcklpd\t{%2, %0|%0, %2}
- movddup\t{%1, %0|%0, %1}
- movhpd\t{%2, %0|%0, %2}
- movlpd\t{%2, %H0|%H0, %2}"
- [(set_attr "type" "sselog,sselog,ssemov,ssemov")
- (set_attr "prefix_data16" "*,*,1,1")
- (set_attr "mode" "V2DF,V2DF,V1DF,V1DF")])
-
-(define_insn "*sse2_interleave_lowv2df"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,o")
+(define_insn "*vec_interleave_lowv2df"
+ [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,Y3,x,x,o")
(vec_select:V2DF
(vec_concat:V4DF
- (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,0")
- (match_operand:V2DF 2 "nonimmediate_operand" " x,m,x"))
+ (match_operand:V2DF 1 "nonimmediate_operand" " 0,x,m ,0,x,0")
+ (match_operand:V2DF 2 "nonimmediate_operand" " x,x,1 ,m,m,x"))
(parallel [(const_int 0)
(const_int 2)])))]
"TARGET_SSE2 && ix86_vec_interleave_v2df_operator_ok (operands, 0)"
"@
unpcklpd\t{%2, %0|%0, %2}
+ vunpcklpd\t{%2, %1, %0|%0, %1, %2}
+ %vmovddup\t{%1, %0|%0, %1}
movhpd\t{%2, %0|%0, %2}
- movlpd\t{%2, %H0|%H0, %2}"
- [(set_attr "type" "sselog,ssemov,ssemov")
- (set_attr "prefix_data16" "*,1,1")
- (set_attr "mode" "V2DF,V1DF,V1DF")])
+ vmovhpd\t{%2, %1, %0|%0, %1, %2}
+ %vmovlpd\t{%2, %H0|%H0, %2}"
+ [(set_attr "isa" "noavx,avx,*,noavx,avx,*")
+ (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov")
+ (set_attr "prefix_data16" "*,*,*,1,*,1")
+ (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex")
+ (set_attr "mode" "V2DF,V2DF,V2DF,V1DF,V1DF,V1DF")])
(define_split
[(set (match_operand:V2DF 0 "memory_operand" "")
DONE;
})
+;; Modes handled by vec_extract_even/odd pattern.
+(define_mode_iterator VEC_EXTRACT_EVENODD_MODE
+ [(V16QI "TARGET_SSE2")
+ (V8HI "TARGET_SSE2")
+ (V4SI "TARGET_SSE2")
+ (V2DI "TARGET_SSE2")
+ (V8SF "TARGET_AVX") V4SF
+ (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")])
+
(define_expand "vec_extract_even<mode>"
- [(match_operand:SSEMODE_EO 0 "register_operand" "")
- (match_operand:SSEMODE_EO 1 "register_operand" "")
- (match_operand:SSEMODE_EO 2 "register_operand" "")]
- ""
+ [(match_operand:VEC_EXTRACT_EVENODD_MODE 0 "register_operand" "")
+ (match_operand:VEC_EXTRACT_EVENODD_MODE 1 "register_operand" "")
+ (match_operand:VEC_EXTRACT_EVENODD_MODE 2 "register_operand" "")]
+ "TARGET_SSE"
{
ix86_expand_vec_extract_even_odd (operands[0], operands[1], operands[2], 0);
DONE;
})
(define_expand "vec_extract_odd<mode>"
- [(match_operand:SSEMODE_EO 0 "register_operand" "")
- (match_operand:SSEMODE_EO 1 "register_operand" "")
- (match_operand:SSEMODE_EO 2 "register_operand" "")]
- ""
+ [(match_operand:VEC_EXTRACT_EVENODD_MODE 0 "register_operand" "")
+ (match_operand:VEC_EXTRACT_EVENODD_MODE 1 "register_operand" "")
+ (match_operand:VEC_EXTRACT_EVENODD_MODE 2 "register_operand" "")]
+ "TARGET_SSE"
{
ix86_expand_vec_extract_even_odd (operands[0], operands[1], operands[2], 1);
DONE;
})
;; punpcklqdq and punpckhqdq are shorter than shufpd.
-(define_insn "*avx_interleave_highv2di"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (vec_select:V2DI
- (vec_concat:V4DI
- (match_operand:V2DI 1 "register_operand" "x")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
- (parallel [(const_int 1)
- (const_int 3)])))]
- "TARGET_AVX"
- "vpunpckhqdq\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
(define_insn "vec_interleave_highv2di"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
+ [(set (match_operand:V2DI 0 "register_operand" "=x,x")
(vec_select:V2DI
(vec_concat:V4DI
- (match_operand:V2DI 1 "register_operand" "0")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
+ (match_operand:V2DI 1 "register_operand" "0,x")
+ (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm"))
(parallel [(const_int 1)
(const_int 3)])))]
"TARGET_SSE2"
- "punpckhqdq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_interleave_lowv2di"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (vec_select:V2DI
- (vec_concat:V4DI
- (match_operand:V2DI 1 "register_operand" "x")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
- (parallel [(const_int 0)
- (const_int 2)])))]
- "TARGET_AVX"
- "vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
+ "@
+ punpckhqdq\t{%2, %0|%0, %2}
+ vpunpckhqdq\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "vec_interleave_lowv2di"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
+ [(set (match_operand:V2DI 0 "register_operand" "=x,x")
(vec_select:V2DI
(vec_concat:V4DI
- (match_operand:V2DI 1 "register_operand" "0")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
+ (match_operand:V2DI 1 "register_operand" "0,x")
+ (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm"))
(parallel [(const_int 0)
(const_int 2)])))]
"TARGET_SSE2"
- "punpcklqdq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
+ "@
+ punpcklqdq\t{%2, %0|%0, %2}
+ vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
-(define_insn "*avx_shufpd_<mode>"
- [(set (match_operand:SSEMODE2D 0 "register_operand" "=x")
- (vec_select:SSEMODE2D
- (vec_concat:<ssedoublesizemode>
- (match_operand:SSEMODE2D 1 "register_operand" "x")
- (match_operand:SSEMODE2D 2 "nonimmediate_operand" "xm"))
- (parallel [(match_operand 3 "const_0_to_1_operand" "")
- (match_operand 4 "const_2_to_3_operand" "")])))]
- "TARGET_AVX"
-{
- int mask;
- mask = INTVAL (operands[3]);
- mask |= (INTVAL (operands[4]) - 2) << 1;
- operands[3] = GEN_INT (mask);
-
- return "vshufpd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
-}
- [(set_attr "type" "sselog")
- (set_attr "length_immediate" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V2DF")])
-
(define_insn "sse2_shufpd_<mode>"
- [(set (match_operand:SSEMODE2D 0 "register_operand" "=x")
- (vec_select:SSEMODE2D
- (vec_concat:<ssedoublesizemode>
- (match_operand:SSEMODE2D 1 "register_operand" "0")
- (match_operand:SSEMODE2D 2 "nonimmediate_operand" "xm"))
+ [(set (match_operand:VI8F_128 0 "register_operand" "=x,x")
+ (vec_select:VI8F_128
+ (vec_concat:<ssedoublevecmode>
+ (match_operand:VI8F_128 1 "register_operand" "0,x")
+ (match_operand:VI8F_128 2 "nonimmediate_operand" "xm,xm"))
(parallel [(match_operand 3 "const_0_to_1_operand" "")
(match_operand 4 "const_2_to_3_operand" "")])))]
"TARGET_SSE2"
mask |= (INTVAL (operands[4]) - 2) << 1;
operands[3] = GEN_INT (mask);
- return "shufpd\t{%3, %2, %0|%0, %2, %3}";
+ switch (which_alternative)
+ {
+ case 0:
+ return "shufpd\t{%3, %2, %0|%0, %2, %3}";
+ case 1:
+ return "vshufpd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
+ default:
+ gcc_unreachable ();
+ }
}
- [(set_attr "type" "sselog")
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
(set_attr "length_immediate" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "V2DF")])
;; Avoid combining registers from different units in a single alternative,
;; see comment above inline_secondary_memory_needed function in i386.c
-(define_insn "*avx_storehpd"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,*f,r")
- (vec_select:DF
- (match_operand:V2DF 1 "nonimmediate_operand" " x,x,o,o,o")
- (parallel [(const_int 1)])))]
- "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "@
- vmovhpd\t{%1, %0|%0, %1}
- vunpckhpd\t{%1, %1, %0|%0, %1, %1}
- #
- #
- #"
- [(set_attr "type" "ssemov,sselog1,ssemov,fmov,imov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V1DF,V2DF,DF,DF,DF")])
-
(define_insn "sse2_storehpd"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,*f,r")
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,x,*f,r")
(vec_select:DF
- (match_operand:V2DF 1 "nonimmediate_operand" " x,0,o,o,o")
+ (match_operand:V2DF 1 "nonimmediate_operand" " x,0,x,o,o,o")
(parallel [(const_int 1)])))]
"TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
- movhpd\t{%1, %0|%0, %1}
+ %vmovhpd\t{%1, %0|%0, %1}
unpckhpd\t%0, %0
+ vunpckhpd\t{%d1, %0|%0, %d1}
#
#
#"
- [(set_attr "type" "ssemov,sselog1,ssemov,fmov,imov")
- (set_attr "prefix_data16" "1,*,*,*,*")
- (set_attr "mode" "V1DF,V2DF,DF,DF,DF")])
+ [(set_attr "isa" "*,noavx,avx,*,*,*")
+ (set_attr "type" "ssemov,sselog1,sselog1,ssemov,fmov,imov")
+ (set (attr "prefix_data16")
+ (if_then_else
+ (and (eq_attr "alternative" "0")
+ (eq (symbol_ref "TARGET_AVX") (const_int 0)))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "prefix" "maybe_vex,orig,vex,*,*,*")
+ (set_attr "mode" "V1DF,V1DF,V2DF,DF,DF,DF")])
(define_split
[(set (match_operand:DF 0 "register_operand" "")
[(set (match_dup 0) (match_dup 1))]
"operands[1] = adjust_address (operands[1], DFmode, 8);")
+(define_insn "*vec_extractv2df_1_sse"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x")
+ (vec_select:DF
+ (match_operand:V2DF 1 "nonimmediate_operand" "x,x,o")
+ (parallel [(const_int 1)])))]
+ "!TARGET_SSE2 && TARGET_SSE
+ && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+ "@
+ movhps\t{%1, %0|%0, %1}
+ movhlps\t{%1, %0|%0, %1}
+ movlps\t{%H1, %0|%0, %H1}"
+ [(set_attr "type" "ssemov")
+ (set_attr "mode" "V2SF,V4SF,V2SF")])
+
;; Avoid combining registers from different units in a single alternative,
;; see comment above inline_secondary_memory_needed function in i386.c
(define_insn "sse2_storelpd"
DONE;
})
-(define_expand "sse2_loadhpd_exp"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
- (vec_concat:V2DF
- (vec_select:DF
- (match_operand:V2DF 1 "nonimmediate_operand" "")
- (parallel [(const_int 0)]))
- (match_operand:DF 2 "nonimmediate_operand" "")))]
- "TARGET_SSE2"
+(define_insn "*vec_extractv2df_0_sse"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x")
+ (vec_select:DF
+ (match_operand:V2DF 1 "nonimmediate_operand" "x,x,m")
+ (parallel [(const_int 0)])))]
+ "!TARGET_SSE2 && TARGET_SSE
+ && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+ "@
+ movlps\t{%1, %0|%0, %1}
+ movaps\t{%1, %0|%0, %1}
+ movlps\t{%1, %0|%0, %1}"
+ [(set_attr "type" "ssemov")
+ (set_attr "mode" "V2SF,V4SF,V2SF")])
+
+(define_expand "sse2_loadhpd_exp"
+ [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
+ (vec_concat:V2DF
+ (vec_select:DF
+ (match_operand:V2DF 1 "nonimmediate_operand" "")
+ (parallel [(const_int 0)]))
+ (match_operand:DF 2 "nonimmediate_operand" "")))]
+ "TARGET_SSE2"
{
rtx dst = ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);
-
+
emit_insn (gen_sse2_loadhpd (dst, operands[1], operands[2]));
/* Fix up the destination if needed. */
;; Avoid combining registers from different units in a single alternative,
;; see comment above inline_secondary_memory_needed function in i386.c
-(define_insn "*avx_loadhpd"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,o,o,o")
- (vec_concat:V2DF
- (vec_select:DF
- (match_operand:V2DF 1 "nonimmediate_operand" " x,x,0,0,0")
- (parallel [(const_int 0)]))
- (match_operand:DF 2 "nonimmediate_operand" " m,x,x,*f,r")))]
- "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "@
- vmovhpd\t{%2, %1, %0|%0, %1, %2}
- vunpcklpd\t{%2, %1, %0|%0, %1, %2}
- #
- #
- #"
- [(set_attr "type" "ssemov,sselog,ssemov,fmov,imov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V1DF,V2DF,DF,DF,DF")])
-
(define_insn "sse2_loadhpd"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,o,o,o")
+ [(set (match_operand:V2DF 0 "nonimmediate_operand"
+ "=x,x,x,x,o,o ,o")
(vec_concat:V2DF
(vec_select:DF
- (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,x,0,0,0")
+ (match_operand:V2DF 1 "nonimmediate_operand"
+ " 0,x,0,x,0,0 ,0")
(parallel [(const_int 0)]))
- (match_operand:DF 2 "nonimmediate_operand" " m,x,0,x,*f,r")))]
+ (match_operand:DF 2 "nonimmediate_operand"
+ " m,m,x,x,x,*f,r")))]
"TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
movhpd\t{%2, %0|%0, %2}
+ vmovhpd\t{%2, %1, %0|%0, %1, %2}
unpcklpd\t{%2, %0|%0, %2}
- shufpd\t{$1, %1, %0|%0, %1, 1}
+ vunpcklpd\t{%2, %1, %0|%0, %1, %2}
#
#
#"
- [(set_attr "type" "ssemov,sselog,sselog,ssemov,fmov,imov")
- (set_attr "prefix_data16" "1,*,*,*,*,*")
- (set_attr "length_immediate" "*,*,1,*,*,*")
- (set_attr "mode" "V1DF,V2DF,V2DF,DF,DF,DF")])
+ [(set_attr "isa" "noavx,avx,noavx,avx,*,*,*")
+ (set_attr "type" "ssemov,ssemov,sselog,sselog,ssemov,fmov,imov")
+ (set_attr "prefix_data16" "1,*,*,*,*,*,*")
+ (set_attr "prefix" "orig,vex,orig,vex,*,*,*")
+ (set_attr "mode" "V1DF,V1DF,V2DF,V2DF,DF,DF,DF")])
(define_split
[(set (match_operand:V2DF 0 "memory_operand" "")
"TARGET_SSE2"
{
rtx dst = ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);
-
+
emit_insn (gen_sse2_loadlpd (dst, operands[1], operands[2]));
/* Fix up the destination if needed. */
;; Avoid combining registers from different units in a single alternative,
;; see comment above inline_secondary_memory_needed function in i386.c
-(define_insn "*avx_loadlpd"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,m,m,m")
- (vec_concat:V2DF
- (match_operand:DF 2 "nonimmediate_operand" " m,m,x,x,x,*f,r")
- (vec_select:DF
- (match_operand:V2DF 1 "vector_move_operand" " C,x,x,o,0,0,0")
- (parallel [(const_int 1)]))))]
- "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "@
- vmovsd\t{%2, %0|%0, %2}
- vmovlpd\t{%2, %1, %0|%0, %1, %2}
- vmovsd\t{%2, %1, %0|%0, %1, %2}
- vmovhpd\t{%H1, %2, %0|%0, %2, %H1}
- #
- #
- #"
- [(set_attr "type" "ssemov,ssemov,ssemov,ssemov,ssemov,fmov,imov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "DF,V1DF,V1DF,V1DF,DF,DF,DF")])
-
(define_insn "sse2_loadlpd"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,x,m,m,m")
+ [(set (match_operand:V2DF 0 "nonimmediate_operand"
+ "=x,x,x,x,x,x,x,x,m,m ,m")
(vec_concat:V2DF
- (match_operand:DF 2 "nonimmediate_operand" " m,m,x,0,0,x,*f,r")
+ (match_operand:DF 2 "nonimmediate_operand"
+ " m,m,m,x,x,0,0,x,x,*f,r")
(vec_select:DF
- (match_operand:V2DF 1 "vector_move_operand" " C,0,0,x,o,0,0,0")
+ (match_operand:V2DF 1 "vector_move_operand"
+ " C,0,x,0,x,x,o,o,0,0 ,0")
(parallel [(const_int 1)]))))]
"TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
- movsd\t{%2, %0|%0, %2}
+ %vmovsd\t{%2, %0|%0, %2}
movlpd\t{%2, %0|%0, %2}
+ vmovlpd\t{%2, %1, %0|%0, %1, %2}
movsd\t{%2, %0|%0, %2}
+ vmovsd\t{%2, %1, %0|%0, %1, %2}
shufpd\t{$2, %1, %0|%0, %1, 2}
movhpd\t{%H1, %0|%0, %H1}
+ vmovhpd\t{%H1, %2, %0|%0, %2, %H1}
#
#
#"
- [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov,fmov,imov")
- (set_attr "prefix_data16" "*,1,*,*,1,*,*,*")
- (set_attr "length_immediate" "*,*,*,1,*,*,*,*")
- (set_attr "mode" "DF,V1DF,V1DF,V2DF,V1DF,DF,DF,DF")])
+ [(set_attr "isa" "*,noavx,avx,noavx,avx,noavx,noavx,avx,*,*,*")
+ (set (attr "type")
+ (cond [(eq_attr "alternative" "5")
+ (const_string "sselog")
+ (eq_attr "alternative" "9")
+ (const_string "fmov")
+ (eq_attr "alternative" "10")
+ (const_string "imov")
+ ]
+ (const_string "ssemov")))
+ (set_attr "prefix_data16" "*,1,*,*,*,*,1,*,*,*,*")
+ (set_attr "length_immediate" "*,*,*,*,*,1,*,*,*,*,*")
+ (set_attr "prefix" "maybe_vex,orig,vex,orig,vex,orig,orig,vex,*,*,*")
+ (set_attr "mode" "DF,V1DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,DF,DF,DF")])
(define_split
[(set (match_operand:V2DF 0 "memory_operand" "")
[(set (match_dup 0) (match_dup 1))]
"operands[0] = adjust_address (operands[0], DFmode, 8);")
-;; Not sure these two are ever used, but it doesn't hurt to have
-;; them. -aoliva
-(define_insn "*vec_extractv2df_1_sse"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x")
- (vec_select:DF
- (match_operand:V2DF 1 "nonimmediate_operand" "x,x,o")
- (parallel [(const_int 1)])))]
- "!TARGET_SSE2 && TARGET_SSE
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "@
- movhps\t{%1, %0|%0, %1}
- movhlps\t{%1, %0|%0, %1}
- movlps\t{%H1, %0|%0, %H1}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "V2SF,V4SF,V2SF")])
-
-(define_insn "*vec_extractv2df_0_sse"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x")
- (vec_select:DF
- (match_operand:V2DF 1 "nonimmediate_operand" "x,x,m")
- (parallel [(const_int 0)])))]
- "!TARGET_SSE2 && TARGET_SSE
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "@
- movlps\t{%1, %0|%0, %1}
- movaps\t{%1, %0|%0, %1}
- movlps\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "V2SF,V4SF,V2SF")])
-
-(define_insn "*avx_movsd"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m,x,o")
- (vec_merge:V2DF
- (match_operand:V2DF 2 "nonimmediate_operand" " x,m,x,x,0")
- (match_operand:V2DF 1 "nonimmediate_operand" " x,x,0,o,x")
- (const_int 1)))]
- "TARGET_AVX"
- "@
- vmovsd\t{%2, %1, %0|%0, %1, %2}
- vmovlpd\t{%2, %1, %0|%0, %1, %2}
- vmovlpd\t{%2, %0|%0, %2}
- vmovhps\t{%H1, %2, %0|%0, %2, %H1}
- vmovhps\t{%1, %H0|%H0, %1}"
- [(set_attr "type" "ssemov,ssemov,ssemov,ssemov,ssemov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "DF,V1DF,V1DF,V1DF,V1DF")])
-
(define_insn "sse2_movsd"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m,x,x,o")
+ [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,m,x,x,x,o")
(vec_merge:V2DF
- (match_operand:V2DF 2 "nonimmediate_operand" " x,m,x,0,0,0")
- (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,0,x,o,x")
+ (match_operand:V2DF 2 "nonimmediate_operand" " x,x,m,m,x,0,0,x,0")
+ (match_operand:V2DF 1 "nonimmediate_operand" " 0,x,0,x,0,x,o,o,x")
(const_int 1)))]
"TARGET_SSE2"
"@
movsd\t{%2, %0|%0, %2}
+ vmovsd\t{%2, %1, %0|%0, %1, %2}
movlpd\t{%2, %0|%0, %2}
- movlpd\t{%2, %0|%0, %2}
+ vmovlpd\t{%2, %1, %0|%0, %1, %2}
+ %vmovlpd\t{%2, %0|%0, %2}
shufpd\t{$2, %1, %0|%0, %1, 2}
movhps\t{%H1, %0|%0, %H1}
- movhps\t{%1, %H0|%H0, %1}"
- [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
- (set_attr "prefix_data16" "*,1,1,*,*,*")
- (set_attr "length_immediate" "*,*,*,1,*,*")
- (set_attr "mode" "DF,V1DF,V1DF,V2DF,V1DF,V1DF")])
+ vmovhps\t{%H1, %2, %0|%0, %2, %H1}
+ %vmovhps\t{%1, %H0|%H0, %1}"
+ [(set_attr "isa" "noavx,avx,noavx,avx,*,noavx,noavx,avx,*")
+ (set (attr "type")
+ (if_then_else
+ (eq_attr "alternative" "5")
+ (const_string "sselog")
+ (const_string "ssemov")))
+ (set (attr "prefix_data16")
+ (if_then_else
+ (and (eq_attr "alternative" "2,4")
+ (eq (symbol_ref "TARGET_AVX") (const_int 0)))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "length_immediate" "*,*,*,*,*,1,*,*,*")
+ (set_attr "prefix" "orig,vex,orig,vex,maybe_vex,orig,orig,vex,maybe_vex")
+ (set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")])
+
+(define_expand "vec_dupv2df"
+ [(set (match_operand:V2DF 0 "register_operand" "")
+ (vec_duplicate:V2DF
+ (match_operand:DF 1 "nonimmediate_operand" "")))]
+ "TARGET_SSE2"
+{
+ if (!TARGET_SSE3)
+ operands[1] = force_reg (DFmode, operands[1]);
+})
(define_insn "*vec_dupv2df_sse3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "DF")])
-(define_insn "vec_dupv2df"
+(define_insn "*vec_dupv2df"
[(set (match_operand:V2DF 0 "register_operand" "=x")
(vec_duplicate:V2DF
(match_operand:DF 1 "register_operand" "0")))]
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "DF")])
-(define_insn "*vec_concatv2df_avx"
- [(set (match_operand:V2DF 0 "register_operand" "=x,x,x")
- (vec_concat:V2DF
- (match_operand:DF 1 "nonimmediate_operand" " x,x,m")
- (match_operand:DF 2 "vector_move_operand" " x,m,C")))]
- "TARGET_AVX"
- "@
- vunpcklpd\t{%2, %1, %0|%0, %1, %2}
- vmovhpd\t{%2, %1, %0|%0, %1, %2}
- vmovsd\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "DF,V1DF,DF")])
-
(define_insn "*vec_concatv2df"
- [(set (match_operand:V2DF 0 "register_operand" "=Y2,Y2,Y2,x,x")
+ [(set (match_operand:V2DF 0 "register_operand" "=Y2,x,Y2,x,Y2,x,x")
(vec_concat:V2DF
- (match_operand:DF 1 "nonimmediate_operand" " 0 ,0 ,m ,0,0")
- (match_operand:DF 2 "vector_move_operand" " Y2,m ,C ,x,m")))]
+ (match_operand:DF 1 "nonimmediate_operand" " 0 ,x,0 ,x,m ,0,0")
+ (match_operand:DF 2 "vector_move_operand" " Y2,x,m ,m,C ,x,m")))]
"TARGET_SSE"
"@
unpcklpd\t{%2, %0|%0, %2}
+ vunpcklpd\t{%2, %1, %0|%0, %1, %2}
movhpd\t{%2, %0|%0, %2}
- movsd\t{%1, %0|%0, %1}
+ vmovhpd\t{%2, %1, %0|%0, %1, %2}
+ %vmovsd\t{%1, %0|%0, %1}
movlhps\t{%2, %0|%0, %2}
movhps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog,ssemov,ssemov,ssemov,ssemov")
- (set_attr "prefix_data16" "*,1,*,*,*")
- (set_attr "mode" "V2DF,V1DF,DF,V4SF,V2SF")])
+ [(set_attr "isa" "noavx,avx,noavx,avx,*,noavx,noavx")
+ (set (attr "type")
+ (if_then_else
+ (eq_attr "alternative" "0,1")
+ (const_string "sselog")
+ (const_string "ssemov")))
+ (set_attr "prefix_data16" "*,*,1,*,*,*,*")
+ (set_attr "prefix" "orig,vex,orig,vex,maybe_vex,orig,orig")
+ (set_attr "mode" "V2DF,V2DF,V1DF,V1DF,DF,V4SF,V2SF")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "neg<mode>2"
- [(set (match_operand:SSEMODEI 0 "register_operand" "")
- (minus:SSEMODEI
+ [(set (match_operand:VI_128 0 "register_operand" "")
+ (minus:VI_128
(match_dup 2)
- (match_operand:SSEMODEI 1 "nonimmediate_operand" "")))]
+ (match_operand:VI_128 1 "nonimmediate_operand" "")))]
"TARGET_SSE2"
"operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
(define_expand "<plusminus_insn><mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "")
- (plusminus:SSEMODEI
- (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:VI_128 0 "register_operand" "")
+ (plusminus:VI_128
+ (match_operand:VI_128 1 "nonimmediate_operand" "")
+ (match_operand:VI_128 2 "nonimmediate_operand" "")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
-(define_insn "*avx_<plusminus_insn><mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (plusminus:SSEMODEI
- (match_operand:SSEMODEI 1 "nonimmediate_operand" "<comm>x")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "vp<plusminus_mnemonic><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "*<plusminus_insn><mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (plusminus:SSEMODEI
- (match_operand:SSEMODEI 1 "nonimmediate_operand" "<comm>0")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
+ [(set (match_operand:VI_128 0 "register_operand" "=x,x")
+ (plusminus:VI_128
+ (match_operand:VI_128 1 "nonimmediate_operand" "<comm>0,x")
+ (match_operand:VI_128 2 "nonimmediate_operand" "xm,xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "p<plusminus_mnemonic><ssevecsize>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_data16" "1")
+ "@
+ p<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
+ vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_expand "sse2_<plusminus_insn><mode>3"
- [(set (match_operand:SSEMODE12 0 "register_operand" "")
- (sat_plusminus:SSEMODE12
- (match_operand:SSEMODE12 1 "nonimmediate_operand" "")
- (match_operand:SSEMODE12 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:VI12_128 0 "register_operand" "")
+ (sat_plusminus:VI12_128
+ (match_operand:VI12_128 1 "nonimmediate_operand" "")
+ (match_operand:VI12_128 2 "nonimmediate_operand" "")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
-(define_insn "*avx_<plusminus_insn><mode>3"
- [(set (match_operand:SSEMODE12 0 "register_operand" "=x")
- (sat_plusminus:SSEMODE12
- (match_operand:SSEMODE12 1 "nonimmediate_operand" "<comm>x")
- (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "vp<plusminus_mnemonic><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "*sse2_<plusminus_insn><mode>3"
- [(set (match_operand:SSEMODE12 0 "register_operand" "=x")
- (sat_plusminus:SSEMODE12
- (match_operand:SSEMODE12 1 "nonimmediate_operand" "<comm>0")
- (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
+ [(set (match_operand:VI12_128 0 "register_operand" "=x,x")
+ (sat_plusminus:VI12_128
+ (match_operand:VI12_128 1 "nonimmediate_operand" "<comm>0,x")
+ (match_operand:VI12_128 2 "nonimmediate_operand" "xm,xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "p<plusminus_mnemonic><ssevecsize>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_data16" "1")
+ "@
+ p<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
+ vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn_and_split "mulv16qi3"
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
-(define_insn "*avx_mulv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%x")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
- "vpmullw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseimul")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "*mulv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%0")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
+ [(set (match_operand:V8HI 0 "register_operand" "=x,x")
+ (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%0,x")
+ (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
- "pmullw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseimul")
- (set_attr "prefix_data16" "1")
+ "@
+ pmullw\t{%2, %0|%0, %2}
+ vpmullw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseimul")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_expand "<s>mulv8hi3_highpart"
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
-(define_insn "*avx_<s>mulv8hi3_highpart"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (truncate:V8HI
- (lshiftrt:V8SI
- (mult:V8SI
- (any_extend:V8SI
- (match_operand:V8HI 1 "nonimmediate_operand" "%x"))
- (any_extend:V8SI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
- (const_int 16))))]
- "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
- "vpmulh<u>w\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseimul")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "*<s>mulv8hi3_highpart"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
+ [(set (match_operand:V8HI 0 "register_operand" "=x,x")
(truncate:V8HI
(lshiftrt:V8SI
(mult:V8SI
(any_extend:V8SI
- (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
+ (match_operand:V8HI 1 "nonimmediate_operand" "%0,x"))
(any_extend:V8SI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
+ (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")))
(const_int 16))))]
"TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
- "pmulh<u>w\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseimul")
- (set_attr "prefix_data16" "1")
+ "@
+ pmulh<u>w\t{%2, %0|%0, %2}
+ vpmulh<u>w\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseimul")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_expand "sse2_umulv2siv2di3"
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);")
-(define_insn "*avx_umulv2siv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (mult:V2DI
- (zero_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "%x")
- (parallel [(const_int 0) (const_int 2)])))
- (zero_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0) (const_int 2)])))))]
- "TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
- "vpmuludq\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseimul")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "*sse2_umulv2siv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
+ [(set (match_operand:V2DI 0 "register_operand" "=x,x")
(mult:V2DI
(zero_extend:V2DI
(vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "%0")
+ (match_operand:V4SI 1 "nonimmediate_operand" "%0,x")
(parallel [(const_int 0) (const_int 2)])))
(zero_extend:V2DI
(vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")
+ (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0) (const_int 2)])))))]
"TARGET_SSE2 && ix86_binary_operator_ok (MULT, V4SImode, operands)"
- "pmuludq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseimul")
- (set_attr "prefix_data16" "1")
+ "@
+ pmuludq\t{%2, %0|%0, %2}
+ vpmuludq\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseimul")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_expand "sse4_1_mulv2siv2di3"
"TARGET_SSE4_1"
"ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);")
-(define_insn "*avx_mulv2siv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (mult:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "%x")
- (parallel [(const_int 0) (const_int 2)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0) (const_int 2)])))))]
- "TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
- "vpmuldq\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseimul")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "*sse4_1_mulv2siv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
+ [(set (match_operand:V2DI 0 "register_operand" "=x,x")
(mult:V2DI
(sign_extend:V2DI
(vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "%0")
+ (match_operand:V4SI 1 "nonimmediate_operand" "%0,x")
(parallel [(const_int 0) (const_int 2)])))
(sign_extend:V2DI
(vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")
+ (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0) (const_int 2)])))))]
"TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, V4SImode, operands)"
- "pmuldq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseimul")
+ "@
+ pmuldq\t{%2, %0|%0, %2}
+ vpmuldq\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseimul")
+ (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_expand "sse2_pmaddwd"
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
-(define_insn "*avx_pmaddwd"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (plus:V4SI
- (mult:V4SI
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 1 "nonimmediate_operand" "%x")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)])))
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)]))))
- (mult:V4SI
- (sign_extend:V4SI
- (vec_select:V4HI (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))
- (sign_extend:V4SI
- (vec_select:V4HI (match_dup 2)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)]))))))]
- "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
- "vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "*sse2_pmaddwd"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
+ [(set (match_operand:V4SI 0 "register_operand" "=x,x")
(plus:V4SI
(mult:V4SI
(sign_extend:V4SI
(vec_select:V4HI
- (match_operand:V8HI 1 "nonimmediate_operand" "%0")
+ (match_operand:V8HI 1 "nonimmediate_operand" "%0,x")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
(const_int 6)])))
(sign_extend:V4SI
(vec_select:V4HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")
+ (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
(const_int 5)
(const_int 7)]))))))]
"TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
- "pmaddwd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
+ "@
+ pmaddwd\t{%2, %0|%0, %2}
+ vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
(set_attr "atom_unit" "simul")
- (set_attr "prefix_data16" "1")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_expand "mulv4si3"
ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);
})
-(define_insn "*avx_mulv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "%x")
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
- "vpmulld\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseimul")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "*sse4_1_mulv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "%0")
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
+ [(set (match_operand:V4SI 0 "register_operand" "=x,x")
+ (mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "%0,x")
+ (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm")))]
"TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, V4SImode, operands)"
- "pmulld\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseimul")
+ "@
+ pmulld\t{%2, %0|%0, %2}
+ vpmulld\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseimul")
(set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn_and_split "*sse2_mulv4si3"
DONE;
})
-(define_insn "*avx_ashr<mode>3"
- [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
- (ashiftrt:SSEMODE24
- (match_operand:SSEMODE24 1 "register_operand" "x")
- (match_operand:SI 2 "nonmemory_operand" "xN")))]
- "TARGET_AVX"
- "vpsra<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "prefix" "vex")
+(define_insn "ashr<mode>3"
+ [(set (match_operand:VI24_128 0 "register_operand" "=x,x")
+ (ashiftrt:VI24_128
+ (match_operand:VI24_128 1 "register_operand" "0,x")
+ (match_operand:SI 2 "nonmemory_operand" "xN,xN")))]
+ "TARGET_SSE2"
+ "@
+ psra<ssemodesuffix>\t{%2, %0|%0, %2}
+ vpsra<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseishft")
(set (attr "length_immediate")
(if_then_else (match_operand 2 "const_int_operand" "")
(const_string "1")
(const_string "0")))
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
-(define_insn "ashr<mode>3"
- [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
- (ashiftrt:SSEMODE24
- (match_operand:SSEMODE24 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "xN")))]
+(define_insn "lshr<mode>3"
+ [(set (match_operand:VI248_128 0 "register_operand" "=x,x")
+ (lshiftrt:VI248_128
+ (match_operand:VI248_128 1 "register_operand" "0,x")
+ (match_operand:SI 2 "nonmemory_operand" "xN,xN")))]
"TARGET_SSE2"
- "psra<ssevecsize>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "prefix_data16" "1")
+ "@
+ psrl<ssemodesuffix>\t{%2, %0|%0, %2}
+ vpsrl<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseishft")
(set (attr "length_immediate")
(if_then_else (match_operand 2 "const_int_operand" "")
(const_string "1")
(const_string "0")))
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_lshrv1ti3"
- [(set (match_operand:V1TI 0 "register_operand" "=x")
- (lshiftrt:V1TI
- (match_operand:V1TI 1 "register_operand" "x")
- (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
- "TARGET_AVX"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
- return "vpsrldq\t{%2, %1, %0|%0, %1, %2}";
-}
- [(set_attr "type" "sseishft")
- (set_attr "prefix" "vex")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_lshr<mode>3"
- [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
- (lshiftrt:SSEMODE248
- (match_operand:SSEMODE248 1 "register_operand" "x")
- (match_operand:SI 2 "nonmemory_operand" "xN")))]
- "TARGET_AVX"
- "vpsrl<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "prefix" "vex")
- (set (attr "length_immediate")
- (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "1")
- (const_string "0")))
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_lshrv1ti3"
- [(set (match_operand:V1TI 0 "register_operand" "=x")
- (lshiftrt:V1TI
- (match_operand:V1TI 1 "register_operand" "0")
- (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
- "TARGET_SSE2"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
- return "psrldq\t{%2, %0|%0, %2}";
-}
- [(set_attr "type" "sseishft")
- (set_attr "prefix_data16" "1")
- (set_attr "length_immediate" "1")
- (set_attr "atom_unit" "sishuf")
- (set_attr "mode" "TI")])
-
-(define_insn "lshr<mode>3"
- [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
- (lshiftrt:SSEMODE248
- (match_operand:SSEMODE248 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "xN")))]
- "TARGET_SSE2"
- "psrl<ssevecsize>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "prefix_data16" "1")
- (set (attr "length_immediate")
- (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "1")
- (const_string "0")))
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_ashlv1ti3"
- [(set (match_operand:V1TI 0 "register_operand" "=x")
- (ashift:V1TI (match_operand:V1TI 1 "register_operand" "x")
- (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
- "TARGET_AVX"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
- return "vpslldq\t{%2, %1, %0|%0, %1, %2}";
-}
- [(set_attr "type" "sseishft")
- (set_attr "prefix" "vex")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_ashl<mode>3"
- [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
- (ashift:SSEMODE248
- (match_operand:SSEMODE248 1 "register_operand" "x")
- (match_operand:SI 2 "nonmemory_operand" "xN")))]
- "TARGET_AVX"
- "vpsll<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "prefix" "vex")
- (set (attr "length_immediate")
- (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "1")
- (const_string "0")))
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_ashlv1ti3"
- [(set (match_operand:V1TI 0 "register_operand" "=x")
- (ashift:V1TI (match_operand:V1TI 1 "register_operand" "0")
- (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
- "TARGET_SSE2"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
- return "pslldq\t{%2, %0|%0, %2}";
-}
- [(set_attr "type" "sseishft")
- (set_attr "prefix_data16" "1")
- (set_attr "length_immediate" "1")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "ashl<mode>3"
- [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
- (ashift:SSEMODE248
- (match_operand:SSEMODE248 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "xN")))]
+ [(set (match_operand:VI248_128 0 "register_operand" "=x,x")
+ (ashift:VI248_128
+ (match_operand:VI248_128 1 "register_operand" "0,x")
+ (match_operand:SI 2 "nonmemory_operand" "xN,xN")))]
"TARGET_SSE2"
- "psll<ssevecsize>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "prefix_data16" "1")
+ "@
+ psll<ssemodesuffix>\t{%2, %0|%0, %2}
+ vpsll<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseishft")
(set (attr "length_immediate")
(if_then_else (match_operand 2 "const_int_operand" "")
(const_string "1")
(const_string "0")))
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_expand "vec_shl_<mode>"
- [(set (match_operand:SSEMODEI 0 "register_operand" "")
+ [(set (match_operand:VI_128 0 "register_operand" "")
(ashift:V1TI
- (match_operand:SSEMODEI 1 "register_operand" "")
+ (match_operand:VI_128 1 "register_operand" "")
(match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))]
"TARGET_SSE2"
{
operands[1] = gen_lowpart (V1TImode, operands[1]);
})
+(define_insn "sse2_ashlv1ti3"
+ [(set (match_operand:V1TI 0 "register_operand" "=x,x")
+ (ashift:V1TI
+ (match_operand:V1TI 1 "register_operand" "0,x")
+ (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n,n")))]
+ "TARGET_SSE2"
+{
+ operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
+
+ switch (which_alternative)
+ {
+ case 0:
+ return "pslldq\t{%2, %0|%0, %2}";
+ case 1:
+ return "vpslldq\t{%2, %1, %0|%0, %1, %2}";
+ default:
+ gcc_unreachable ();
+ }
+}
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseishft")
+ (set_attr "length_immediate" "1")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
+ (set_attr "mode" "TI")])
+
(define_expand "vec_shr_<mode>"
- [(set (match_operand:SSEMODEI 0 "register_operand" "")
+ [(set (match_operand:VI_128 0 "register_operand" "")
(lshiftrt:V1TI
- (match_operand:SSEMODEI 1 "register_operand" "")
+ (match_operand:VI_128 1 "register_operand" "")
(match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))]
"TARGET_SSE2"
{
operands[1] = gen_lowpart (V1TImode, operands[1]);
})
-(define_insn "*avx_<code><mode>3"
- [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
- (umaxmin:SSEMODE124
- (match_operand:SSEMODE124 1 "nonimmediate_operand" "%x")
- (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "vp<maxmin_int><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set (attr "prefix_extra")
- (if_then_else (match_operand:V16QI 0 "" "")
- (const_string "0")
- (const_string "1")))
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
-(define_expand "<code>v16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "")
- (umaxmin:V16QI
- (match_operand:V16QI 1 "nonimmediate_operand" "")
- (match_operand:V16QI 2 "nonimmediate_operand" "")))]
+(define_insn "sse2_lshrv1ti3"
+ [(set (match_operand:V1TI 0 "register_operand" "=x,x")
+ (lshiftrt:V1TI
+ (match_operand:V1TI 1 "register_operand" "0,x")
+ (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n,n")))]
"TARGET_SSE2"
- "ix86_fixup_binary_operands_no_copy (<CODE>, V16QImode, operands);")
+{
+ operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
-(define_insn "*<code>v16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (umaxmin:V16QI
- (match_operand:V16QI 1 "nonimmediate_operand" "%0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)"
- "p<maxmin_int>b\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_data16" "1")
+ switch (which_alternative)
+ {
+ case 0:
+ return "psrldq\t{%2, %0|%0, %2}";
+ case 1:
+ return "vpsrldq\t{%2, %1, %0|%0, %1, %2}";
+ default:
+ gcc_unreachable ();
+ }
+}
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseishft")
+ (set_attr "length_immediate" "1")
+ (set_attr "atom_unit" "sishuf")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
-(define_insn "*avx_<code><mode>3"
- [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
- (smaxmin:SSEMODE124
- (match_operand:SSEMODE124 1 "nonimmediate_operand" "%x")
- (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "vp<maxmin_int><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set (attr "prefix_extra")
- (if_then_else (match_operand:V8HI 0 "" "")
- (const_string "0")
- (const_string "1")))
- (set_attr "prefix" "vex")
+(define_insn "*sse4_1_<code><mode>3"
+ [(set (match_operand:VI14_128 0 "register_operand" "=x,x")
+ (smaxmin:VI14_128
+ (match_operand:VI14_128 1 "nonimmediate_operand" "%0,x")
+ (match_operand:VI14_128 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "@
+ p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
+ vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
+ (set_attr "prefix_extra" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
-(define_expand "<code>v8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "")
- (smaxmin:V8HI
- (match_operand:V8HI 1 "nonimmediate_operand" "")
- (match_operand:V8HI 2 "nonimmediate_operand" "")))]
- "TARGET_SSE2"
- "ix86_fixup_binary_operands_no_copy (<CODE>, V8HImode, operands);")
-
(define_insn "*<code>v8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
+ [(set (match_operand:V8HI 0 "register_operand" "=x,x")
(smaxmin:V8HI
- (match_operand:V8HI 1 "nonimmediate_operand" "%0")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
+ (match_operand:V8HI 1 "nonimmediate_operand" "%0,x")
+ (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)"
- "p<maxmin_int>w\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_data16" "1")
+ "@
+ p<maxmin_int>w\t{%2, %0|%0, %2}
+ vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix_extra" "*,1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
-(define_expand "umaxv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "")
- (umax:V8HI (match_operand:V8HI 1 "register_operand" "")
- (match_operand:V8HI 2 "nonimmediate_operand" "")))]
+(define_expand "smax<mode>3"
+ [(set (match_operand:VI14_128 0 "register_operand" "")
+ (smax:VI14_128 (match_operand:VI14_128 1 "register_operand" "")
+ (match_operand:VI14_128 2 "register_operand" "")))]
"TARGET_SSE2"
{
if (TARGET_SSE4_1)
- ix86_fixup_binary_operands_no_copy (UMAX, V8HImode, operands);
+ ix86_fixup_binary_operands_no_copy (SMAX, <MODE>mode, operands);
else
{
- rtx op0 = operands[0], op2 = operands[2], op3 = op0;
- if (rtx_equal_p (op3, op2))
- op3 = gen_reg_rtx (V8HImode);
- emit_insn (gen_sse2_ussubv8hi3 (op3, operands[1], op2));
- emit_insn (gen_addv8hi3 (op0, op3, op2));
+ rtx xops[6];
+ bool ok;
+
+ xops[0] = operands[0];
+ xops[1] = operands[1];
+ xops[2] = operands[2];
+ xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
+ xops[4] = operands[1];
+ xops[5] = operands[2];
+ ok = ix86_expand_int_vcond (xops);
+ gcc_assert (ok);
DONE;
}
})
-(define_expand "smax<mode>3"
- [(set (match_operand:SSEMODE14 0 "register_operand" "")
- (smax:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "")
- (match_operand:SSEMODE14 2 "register_operand" "")))]
+(define_expand "smin<mode>3"
+ [(set (match_operand:VI14_128 0 "register_operand" "")
+ (smin:VI14_128 (match_operand:VI14_128 1 "register_operand" "")
+ (match_operand:VI14_128 2 "register_operand" "")))]
"TARGET_SSE2"
{
if (TARGET_SSE4_1)
- ix86_fixup_binary_operands_no_copy (SMAX, <MODE>mode, operands);
+ ix86_fixup_binary_operands_no_copy (SMIN, <MODE>mode, operands);
else
{
rtx xops[6];
bool ok;
xops[0] = operands[0];
- xops[1] = operands[1];
- xops[2] = operands[2];
+ xops[1] = operands[2];
+ xops[2] = operands[1];
xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
xops[4] = operands[1];
xops[5] = operands[2];
}
})
-(define_insn "*sse4_1_<code><mode>3"
- [(set (match_operand:SSEMODE14 0 "register_operand" "=x")
- (smaxmin:SSEMODE14
- (match_operand:SSEMODE14 1 "nonimmediate_operand" "%0")
- (match_operand:SSEMODE14 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "p<maxmin_int><ssevecsize>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1")
- (set_attr "mode" "TI")])
+(define_expand "<code>v8hi3"
+ [(set (match_operand:V8HI 0 "register_operand" "")
+ (smaxmin:V8HI
+ (match_operand:V8HI 1 "nonimmediate_operand" "")
+ (match_operand:V8HI 2 "nonimmediate_operand" "")))]
+ "TARGET_SSE2"
+ "ix86_fixup_binary_operands_no_copy (<CODE>, V8HImode, operands);")
(define_expand "smaxv2di3"
[(set (match_operand:V2DI 0 "register_operand" "")
DONE;
})
-(define_expand "umaxv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "")
- (umax:V4SI (match_operand:V4SI 1 "register_operand" "")
- (match_operand:V4SI 2 "register_operand" "")))]
- "TARGET_SSE2"
-{
- if (TARGET_SSE4_1)
- ix86_fixup_binary_operands_no_copy (UMAX, V4SImode, operands);
- else
- {
- rtx xops[6];
- bool ok;
-
- xops[0] = operands[0];
- xops[1] = operands[1];
- xops[2] = operands[2];
- xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
- xops[4] = operands[1];
- xops[5] = operands[2];
- ok = ix86_expand_int_vcond (xops);
- gcc_assert (ok);
- DONE;
- }
-})
-
-(define_insn "*sse4_1_<code><mode>3"
- [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
- (umaxmin:SSEMODE24
- (match_operand:SSEMODE24 1 "nonimmediate_operand" "%0")
- (match_operand:SSEMODE24 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "p<maxmin_int><ssevecsize>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1")
- (set_attr "mode" "TI")])
-
-(define_expand "umaxv2di3"
+(define_expand "sminv2di3"
[(set (match_operand:V2DI 0 "register_operand" "")
- (umax:V2DI (match_operand:V2DI 1 "register_operand" "")
+ (smin:V2DI (match_operand:V2DI 1 "register_operand" "")
(match_operand:V2DI 2 "register_operand" "")))]
"TARGET_SSE4_2"
{
bool ok;
xops[0] = operands[0];
- xops[1] = operands[1];
- xops[2] = operands[2];
- xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
+ xops[1] = operands[2];
+ xops[2] = operands[1];
+ xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
xops[4] = operands[1];
xops[5] = operands[2];
ok = ix86_expand_int_vcond (xops);
DONE;
})
-(define_expand "smin<mode>3"
- [(set (match_operand:SSEMODE14 0 "register_operand" "")
- (smin:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "")
- (match_operand:SSEMODE14 2 "register_operand" "")))]
+(define_insn "*sse4_1_<code><mode>3"
+ [(set (match_operand:VI24_128 0 "register_operand" "=x,x")
+ (umaxmin:VI24_128
+ (match_operand:VI24_128 1 "nonimmediate_operand" "%0,x")
+ (match_operand:VI24_128 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "@
+ p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
+ vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
+ (set_attr "prefix_extra" "1,*")
+ (set_attr "prefix" "orig,vex")
+ (set_attr "mode" "TI")])
+
+(define_insn "*<code>v16qi3"
+ [(set (match_operand:V16QI 0 "register_operand" "=x,x")
+ (umaxmin:V16QI
+ (match_operand:V16QI 1 "nonimmediate_operand" "%0,x")
+ (match_operand:V16QI 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)"
+ "@
+ p<maxmin_int>b\t{%2, %0|%0, %2}
+ vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix_extra" "*,1")
+ (set_attr "prefix" "orig,vex")
+ (set_attr "mode" "TI")])
+
+(define_expand "<code>v16qi3"
+ [(set (match_operand:V16QI 0 "register_operand" "")
+ (umaxmin:V16QI
+ (match_operand:V16QI 1 "nonimmediate_operand" "")
+ (match_operand:V16QI 2 "nonimmediate_operand" "")))]
+ "TARGET_SSE2"
+ "ix86_fixup_binary_operands_no_copy (<CODE>, V16QImode, operands);")
+
+(define_expand "umaxv8hi3"
+ [(set (match_operand:V8HI 0 "register_operand" "")
+ (umax:V8HI (match_operand:V8HI 1 "register_operand" "")
+ (match_operand:V8HI 2 "nonimmediate_operand" "")))]
"TARGET_SSE2"
{
if (TARGET_SSE4_1)
- ix86_fixup_binary_operands_no_copy (SMIN, <MODE>mode, operands);
+ ix86_fixup_binary_operands_no_copy (UMAX, V8HImode, operands);
+ else
+ {
+ rtx op0 = operands[0], op2 = operands[2], op3 = op0;
+ if (rtx_equal_p (op3, op2))
+ op3 = gen_reg_rtx (V8HImode);
+ emit_insn (gen_sse2_ussubv8hi3 (op3, operands[1], op2));
+ emit_insn (gen_addv8hi3 (op0, op3, op2));
+ DONE;
+ }
+})
+
+(define_expand "umaxv4si3"
+ [(set (match_operand:V4SI 0 "register_operand" "")
+ (umax:V4SI (match_operand:V4SI 1 "register_operand" "")
+ (match_operand:V4SI 2 "register_operand" "")))]
+ "TARGET_SSE2"
+{
+ if (TARGET_SSE4_1)
+ ix86_fixup_binary_operands_no_copy (UMAX, V4SImode, operands);
else
{
rtx xops[6];
bool ok;
xops[0] = operands[0];
- xops[1] = operands[2];
- xops[2] = operands[1];
- xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
+ xops[1] = operands[1];
+ xops[2] = operands[2];
+ xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
xops[4] = operands[1];
xops[5] = operands[2];
ok = ix86_expand_int_vcond (xops);
}
})
-(define_expand "sminv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "")
- (smin:V2DI (match_operand:V2DI 1 "register_operand" "")
- (match_operand:V2DI 2 "register_operand" "")))]
- "TARGET_SSE4_2"
-{
- rtx xops[6];
- bool ok;
-
- xops[0] = operands[0];
- xops[1] = operands[2];
- xops[2] = operands[1];
- xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
- xops[4] = operands[1];
- xops[5] = operands[2];
- ok = ix86_expand_int_vcond (xops);
- gcc_assert (ok);
- DONE;
-})
-
(define_expand "umin<mode>3"
- [(set (match_operand:SSEMODE24 0 "register_operand" "")
- (umin:SSEMODE24 (match_operand:SSEMODE24 1 "register_operand" "")
- (match_operand:SSEMODE24 2 "register_operand" "")))]
+ [(set (match_operand:VI24_128 0 "register_operand" "")
+ (umin:VI24_128 (match_operand:VI24_128 1 "register_operand" "")
+ (match_operand:VI24_128 2 "register_operand" "")))]
"TARGET_SSE2"
{
if (TARGET_SSE4_1)
}
})
+(define_expand "umaxv2di3"
+ [(set (match_operand:V2DI 0 "register_operand" "")
+ (umax:V2DI (match_operand:V2DI 1 "register_operand" "")
+ (match_operand:V2DI 2 "register_operand" "")))]
+ "TARGET_SSE4_2"
+{
+ rtx xops[6];
+ bool ok;
+
+ xops[0] = operands[0];
+ xops[1] = operands[1];
+ xops[2] = operands[2];
+ xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
+ xops[4] = operands[1];
+ xops[5] = operands[2];
+ ok = ix86_expand_int_vcond (xops);
+ gcc_assert (ok);
+ DONE;
+})
+
(define_expand "uminv2di3"
[(set (match_operand:V2DI 0 "register_operand" "")
(umin:V2DI (match_operand:V2DI 1 "register_operand" "")
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(define_expand "sse2_eq<mode>3"
- [(set (match_operand:SSEMODE124 0 "register_operand" "")
- (eq:SSEMODE124
- (match_operand:SSEMODE124 1 "nonimmediate_operand" "")
- (match_operand:SSEMODE124 2 "nonimmediate_operand" "")))]
- "TARGET_SSE2 && !TARGET_XOP "
- "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
-
-(define_insn "*avx_eq<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (eq:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "%x")
- (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
- "vpcmpeq<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssecmp")
- (set (attr "prefix_extra")
- (if_then_else (match_operand:V2DI 0 "" "")
- (const_string "1")
- (const_string "*")))
- (set_attr "prefix" "vex")
+(define_insn "*sse4_1_eqv2di3"
+ [(set (match_operand:V2DI 0 "register_operand" "=x,x")
+ (eq:V2DI
+ (match_operand:V2DI 1 "nonimmediate_operand" "%0,x")
+ (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE4_1 && ix86_binary_operator_ok (EQ, V2DImode, operands)"
+ "@
+ pcmpeqq\t{%2, %0|%0, %2}
+ vpcmpeqq\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssecmp")
+ (set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "*sse2_eq<mode>3"
- [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
- (eq:SSEMODE124
- (match_operand:SSEMODE124 1 "nonimmediate_operand" "%0")
- (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
+ [(set (match_operand:VI124_128 0 "register_operand" "=x,x")
+ (eq:VI124_128
+ (match_operand:VI124_128 1 "nonimmediate_operand" "%0,x")
+ (match_operand:VI124_128 2 "nonimmediate_operand" "xm,xm")))]
"TARGET_SSE2 && !TARGET_XOP
&& ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
- "pcmpeq<ssevecsize>\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecmp")
- (set_attr "prefix_data16" "1")
+ "@
+ pcmpeq<ssemodesuffix>\t{%2, %0|%0, %2}
+ vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssecmp")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
+(define_expand "sse2_eq<mode>3"
+ [(set (match_operand:VI124_128 0 "register_operand" "")
+ (eq:VI124_128
+ (match_operand:VI124_128 1 "nonimmediate_operand" "")
+ (match_operand:VI124_128 2 "nonimmediate_operand" "")))]
+ "TARGET_SSE2 && !TARGET_XOP "
+ "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
+
(define_expand "sse4_1_eqv2di3"
[(set (match_operand:V2DI 0 "register_operand" "")
(eq:V2DI
"TARGET_SSE4_1"
"ix86_fixup_binary_operands_no_copy (EQ, V2DImode, operands);")
-(define_insn "*sse4_1_eqv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (eq:V2DI
- (match_operand:V2DI 1 "nonimmediate_operand" "%0")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE4_1 && ix86_binary_operator_ok (EQ, V2DImode, operands)"
- "pcmpeqq\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecmp")
+(define_insn "sse4_2_gtv2di3"
+ [(set (match_operand:V2DI 0 "register_operand" "=x,x")
+ (gt:V2DI
+ (match_operand:V2DI 1 "register_operand" "0,x")
+ (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE4_2"
+ "@
+ pcmpgtq\t{%2, %0|%0, %2}
+ vpcmpgtq\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssecmp")
(set_attr "prefix_extra" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_gt<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (gt:SSEMODE1248
- (match_operand:SSEMODE1248 1 "register_operand" "x")
- (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX"
- "vpcmpgt<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssecmp")
- (set (attr "prefix_extra")
- (if_then_else (match_operand:V2DI 0 "" "")
- (const_string "1")
- (const_string "*")))
- (set_attr "prefix" "vex")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "sse2_gt<mode>3"
- [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
- (gt:SSEMODE124
- (match_operand:SSEMODE124 1 "register_operand" "0")
- (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
+ [(set (match_operand:VI124_128 0 "register_operand" "=x,x")
+ (gt:VI124_128
+ (match_operand:VI124_128 1 "register_operand" "0,x")
+ (match_operand:VI124_128 2 "nonimmediate_operand" "xm,xm")))]
"TARGET_SSE2 && !TARGET_XOP"
- "pcmpgt<ssevecsize>\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecmp")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "sse4_2_gtv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (gt:V2DI
- (match_operand:V2DI 1 "register_operand" "0")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE4_2"
- "pcmpgtq\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecmp")
- (set_attr "prefix_extra" "1")
+ "@
+ pcmpgt<ssemodesuffix>\t{%2, %0|%0, %2}
+ vpcmpgt<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssecmp")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_expand "vcond<mode>"
- [(set (match_operand:SSEMODE124C8 0 "register_operand" "")
- (if_then_else:SSEMODE124C8
+ [(set (match_operand:VI124_128 0 "register_operand" "")
+ (if_then_else:VI124_128
(match_operator 3 ""
- [(match_operand:SSEMODE124C8 4 "nonimmediate_operand" "")
- (match_operand:SSEMODE124C8 5 "nonimmediate_operand" "")])
- (match_operand:SSEMODE124C8 1 "general_operand" "")
- (match_operand:SSEMODE124C8 2 "general_operand" "")))]
+ [(match_operand:VI124_128 4 "nonimmediate_operand" "")
+ (match_operand:VI124_128 5 "nonimmediate_operand" "")])
+ (match_operand:VI124_128 1 "general_operand" "")
+ (match_operand:VI124_128 2 "general_operand" "")))]
"TARGET_SSE2"
{
bool ok = ix86_expand_int_vcond (operands);
DONE;
})
+(define_expand "vcondv2di"
+ [(set (match_operand:V2DI 0 "register_operand" "")
+ (if_then_else:V2DI
+ (match_operator 3 ""
+ [(match_operand:V2DI 4 "nonimmediate_operand" "")
+ (match_operand:V2DI 5 "nonimmediate_operand" "")])
+ (match_operand:V2DI 1 "general_operand" "")
+ (match_operand:V2DI 2 "general_operand" "")))]
+ "TARGET_SSE4_2"
+{
+ bool ok = ix86_expand_int_vcond (operands);
+ gcc_assert (ok);
+ DONE;
+})
+
(define_expand "vcondu<mode>"
- [(set (match_operand:SSEMODE124C8 0 "register_operand" "")
- (if_then_else:SSEMODE124C8
+ [(set (match_operand:VI124_128 0 "register_operand" "")
+ (if_then_else:VI124_128
(match_operator 3 ""
- [(match_operand:SSEMODE124C8 4 "nonimmediate_operand" "")
- (match_operand:SSEMODE124C8 5 "nonimmediate_operand" "")])
- (match_operand:SSEMODE124C8 1 "general_operand" "")
- (match_operand:SSEMODE124C8 2 "general_operand" "")))]
+ [(match_operand:VI124_128 4 "nonimmediate_operand" "")
+ (match_operand:VI124_128 5 "nonimmediate_operand" "")])
+ (match_operand:VI124_128 1 "general_operand" "")
+ (match_operand:VI124_128 2 "general_operand" "")))]
"TARGET_SSE2"
{
bool ok = ix86_expand_int_vcond (operands);
DONE;
})
+(define_expand "vconduv2di"
+ [(set (match_operand:V2DI 0 "register_operand" "")
+ (if_then_else:V2DI
+ (match_operator 3 ""
+ [(match_operand:V2DI 4 "nonimmediate_operand" "")
+ (match_operand:V2DI 5 "nonimmediate_operand" "")])
+ (match_operand:V2DI 1 "general_operand" "")
+ (match_operand:V2DI 2 "general_operand" "")))]
+ "TARGET_SSE4_2"
+{
+ bool ok = ix86_expand_int_vcond (operands);
+ gcc_assert (ok);
+ DONE;
+})
+
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Parallel bitwise logical operations
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "one_cmpl<mode>2"
- [(set (match_operand:SSEMODEI 0 "register_operand" "")
- (xor:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
- (match_dup 2)))]
- "TARGET_SSE2"
+ [(set (match_operand:VI 0 "register_operand" "")
+ (xor:VI (match_operand:VI 1 "nonimmediate_operand" "")
+ (match_dup 2)))]
+ "TARGET_SSE"
{
int i, n = GET_MODE_NUNITS (<MODE>mode);
rtvec v = rtvec_alloc (n);
operands[2] = force_reg (<MODE>mode, gen_rtx_CONST_VECTOR (<MODE>mode, v));
})
-(define_insn "*avx_andnot<mode>3"
- [(set (match_operand:AVX256MODEI 0 "register_operand" "=x")
- (and:AVX256MODEI
- (not:AVX256MODEI (match_operand:AVX256MODEI 1 "register_operand" "x"))
- (match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX"
- "vandnps\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecpsmode>")])
-
-(define_insn "*sse_andnot<mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (and:SSEMODEI
- (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "0"))
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "(TARGET_SSE && !TARGET_SSE2)"
- "andnps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "V4SF")])
+(define_expand "sse2_andnot<mode>3"
+ [(set (match_operand:VI_128 0 "register_operand" "")
+ (and:VI_128
+ (not:VI_128 (match_operand:VI_128 1 "register_operand" ""))
+ (match_operand:VI_128 2 "nonimmediate_operand" "")))]
+ "TARGET_SSE2")
-(define_insn "*avx_andnot<mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (and:SSEMODEI
- (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "x"))
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX"
- "vpandn\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
+(define_insn "*andnot<mode>3"
+ [(set (match_operand:VI 0 "register_operand" "=x,x")
+ (and:VI
+ (not:VI (match_operand:VI 1 "register_operand" "0,x"))
+ (match_operand:VI 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE"
+{
+ static char buf[32];
+ const char *ops;
+ const char *tmp
+ = (get_attr_mode (insn) == MODE_TI) ? "pandn" : "andnps";
-(define_insn "sse2_andnot<mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (and:SSEMODEI
- (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "0"))
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "pandn\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
+ switch (which_alternative)
+ {
+ case 0:
+ ops = "%s\t{%%2, %%0|%%0, %%2}";
+ break;
+ case 1:
+ ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
+ break;
+ default:
+ gcc_unreachable ();
+ }
-(define_insn "*andnottf3"
- [(set (match_operand:TF 0 "register_operand" "=x")
- (and:TF
- (not:TF (match_operand:TF 1 "register_operand" "0"))
- (match_operand:TF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "pandn\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
+ snprintf (buf, sizeof (buf), ops, tmp);
+ return buf;
+}
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set (attr "prefix_data16")
+ (if_then_else
+ (and (eq_attr "alternative" "0")
+ (eq_attr "mode" "TI"))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "prefix" "orig,vex")
+ (set (attr "mode")
+ (cond [(ne (symbol_ref "GET_MODE_SIZE (<MODE>mode) > 128") (const_int 0))
+ (const_string "V8SF")
+ (ne (symbol_ref "TARGET_SSE2") (const_int 0))
+ (const_string "TI")
+ ]
+ (const_string "V4SF")))])
(define_expand "<code><mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "")
- (any_logic:SSEMODEI
- (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:VI 0 "register_operand" "")
+ (any_logic:VI
+ (match_operand:VI 1 "nonimmediate_operand" "")
+ (match_operand:VI 2 "nonimmediate_operand" "")))]
"TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
-(define_insn "*avx_<code><mode>3"
- [(set (match_operand:AVX256MODEI 0 "register_operand" "=x")
- (any_logic:AVX256MODEI
- (match_operand:AVX256MODEI 1 "nonimmediate_operand" "%x")
- (match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecpsmode>")])
-
-(define_insn "*sse_<code><mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (any_logic:SSEMODEI
- (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "(TARGET_SSE && !TARGET_SSE2)
+(define_insn "*<code><mode>3"
+ [(set (match_operand:VI 0 "register_operand" "=x,x")
+ (any_logic:VI
+ (match_operand:VI 1 "nonimmediate_operand" "%0,x")
+ (match_operand:VI 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<logic>ps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "V4SF")])
+{
+ static char buf[32];
+ const char *ops;
+ const char *tmp
+ = (get_attr_mode (insn) == MODE_TI) ? "p<logic>" : "<logic>ps";
-(define_insn "*avx_<code><mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (any_logic:SSEMODEI
- (match_operand:SSEMODEI 1 "nonimmediate_operand" "%x")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "vp<logic>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
+ switch (which_alternative)
+ {
+ case 0:
+ ops = "%s\t{%%2, %%0|%%0, %%2}";
+ break;
+ case 1:
+ ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
+ break;
+ default:
+ gcc_unreachable ();
+ }
-(define_insn "*sse2_<code><mode>3"
- [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
- (any_logic:SSEMODEI
- (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
- (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "p<logic>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
+ snprintf (buf, sizeof (buf), ops, tmp);
+ return buf;
+}
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set (attr "prefix_data16")
+ (if_then_else
+ (and (eq_attr "alternative" "0")
+ (eq_attr "mode" "TI"))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "prefix" "orig,vex")
+ (set (attr "mode")
+ (cond [(ne (symbol_ref "GET_MODE_SIZE (<MODE>mode) > 128") (const_int 0))
+ (const_string "V8SF")
+ (ne (symbol_ref "TARGET_SSE2") (const_int 0))
+ (const_string "TI")
+ ]
+ (const_string "V4SF")))])
+
+(define_insn "*andnottf3"
+ [(set (match_operand:TF 0 "register_operand" "=x,x")
+ (and:TF
+ (not:TF (match_operand:TF 1 "register_operand" "0,x"))
+ (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE2"
+ "@
+ pandn\t{%2, %0|%0, %2}
+ vpandn\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_expand "<code>tf3"
"ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);")
(define_insn "*<code>tf3"
- [(set (match_operand:TF 0 "register_operand" "=x")
+ [(set (match_operand:TF 0 "register_operand" "=x,x")
(any_logic:TF
- (match_operand:TF 1 "nonimmediate_operand" "%0")
- (match_operand:TF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
- "p<logic>\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
+ (match_operand:TF 1 "nonimmediate_operand" "%0,x")
+ (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))]
+ "TARGET_SSE2
+ && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
+ "@
+ p<logic>\t{%2, %0|%0, %2}
+ vp<logic>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(define_expand "vec_pack_trunc_v8hi"
- [(match_operand:V16QI 0 "register_operand" "")
- (match_operand:V8HI 1 "register_operand" "")
- (match_operand:V8HI 2 "register_operand" "")]
- "TARGET_SSE2"
-{
- rtx op1 = gen_lowpart (V16QImode, operands[1]);
- rtx op2 = gen_lowpart (V16QImode, operands[2]);
- ix86_expand_vec_extract_even_odd (operands[0], op1, op2, 0);
- DONE;
-})
-
-(define_expand "vec_pack_trunc_v4si"
- [(match_operand:V8HI 0 "register_operand" "")
- (match_operand:V4SI 1 "register_operand" "")
- (match_operand:V4SI 2 "register_operand" "")]
- "TARGET_SSE2"
-{
- rtx op1 = gen_lowpart (V8HImode, operands[1]);
- rtx op2 = gen_lowpart (V8HImode, operands[2]);
- ix86_expand_vec_extract_even_odd (operands[0], op1, op2, 0);
- DONE;
-})
-
-(define_expand "vec_pack_trunc_v2di"
- [(match_operand:V4SI 0 "register_operand" "")
- (match_operand:V2DI 1 "register_operand" "")
- (match_operand:V2DI 2 "register_operand" "")]
+(define_expand "vec_pack_trunc_<mode>"
+ [(match_operand:<ssepackmode> 0 "register_operand" "")
+ (match_operand:VI248_128 1 "register_operand" "")
+ (match_operand:VI248_128 2 "register_operand" "")]
"TARGET_SSE2"
{
- rtx op1 = gen_lowpart (V4SImode, operands[1]);
- rtx op2 = gen_lowpart (V4SImode, operands[2]);
+ rtx op1 = gen_lowpart (<ssepackmode>mode, operands[1]);
+ rtx op2 = gen_lowpart (<ssepackmode>mode, operands[2]);
ix86_expand_vec_extract_even_odd (operands[0], op1, op2, 0);
DONE;
})
-(define_insn "*avx_packsswb"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (vec_concat:V16QI
- (ss_truncate:V8QI
- (match_operand:V8HI 1 "register_operand" "x"))
- (ss_truncate:V8QI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
- "TARGET_AVX"
- "vpacksswb\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "sse2_packsswb"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
+ [(set (match_operand:V16QI 0 "register_operand" "=x,x")
(vec_concat:V16QI
(ss_truncate:V8QI
- (match_operand:V8HI 1 "register_operand" "0"))
+ (match_operand:V8HI 1 "register_operand" "0,x"))
(ss_truncate:V8QI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
+ (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm"))))]
"TARGET_SSE2"
- "packsswb\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_packssdw"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (vec_concat:V8HI
- (ss_truncate:V4HI
- (match_operand:V4SI 1 "register_operand" "x"))
- (ss_truncate:V4HI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
- "TARGET_AVX"
- "vpackssdw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
+ "@
+ packsswb\t{%2, %0|%0, %2}
+ vpacksswb\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "sse2_packssdw"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
+ [(set (match_operand:V8HI 0 "register_operand" "=x,x")
(vec_concat:V8HI
(ss_truncate:V4HI
- (match_operand:V4SI 1 "register_operand" "0"))
+ (match_operand:V4SI 1 "register_operand" "0,x"))
(ss_truncate:V4HI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
+ (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm"))))]
"TARGET_SSE2"
- "packssdw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_packuswb"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (vec_concat:V16QI
- (us_truncate:V8QI
- (match_operand:V8HI 1 "register_operand" "x"))
- (us_truncate:V8QI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
- "TARGET_AVX"
- "vpackuswb\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
+ "@
+ packssdw\t{%2, %0|%0, %2}
+ vpackssdw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "sse2_packuswb"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
+ [(set (match_operand:V16QI 0 "register_operand" "=x,x")
(vec_concat:V16QI
(us_truncate:V8QI
- (match_operand:V8HI 1 "register_operand" "0"))
+ (match_operand:V8HI 1 "register_operand" "0,x"))
(us_truncate:V8QI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
+ (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm"))))]
"TARGET_SSE2"
- "packuswb\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_interleave_highv16qi"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (vec_select:V16QI
- (vec_concat:V32QI
- (match_operand:V16QI 1 "register_operand" "x")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
- (parallel [(const_int 8) (const_int 24)
- (const_int 9) (const_int 25)
- (const_int 10) (const_int 26)
- (const_int 11) (const_int 27)
- (const_int 12) (const_int 28)
- (const_int 13) (const_int 29)
- (const_int 14) (const_int 30)
- (const_int 15) (const_int 31)])))]
- "TARGET_AVX"
- "vpunpckhbw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
+ "@
+ packuswb\t{%2, %0|%0, %2}
+ vpackuswb\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "vec_interleave_highv16qi"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
+ [(set (match_operand:V16QI 0 "register_operand" "=x,x")
(vec_select:V16QI
(vec_concat:V32QI
- (match_operand:V16QI 1 "register_operand" "0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
+ (match_operand:V16QI 1 "register_operand" "0,x")
+ (match_operand:V16QI 2 "nonimmediate_operand" "xm,xm"))
(parallel [(const_int 8) (const_int 24)
(const_int 9) (const_int 25)
(const_int 10) (const_int 26)
(const_int 11) (const_int 27)
(const_int 12) (const_int 28)
(const_int 13) (const_int 29)
- (const_int 14) (const_int 30)
- (const_int 15) (const_int 31)])))]
- "TARGET_SSE2"
- "punpckhbw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_interleave_lowv16qi"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (vec_select:V16QI
- (vec_concat:V32QI
- (match_operand:V16QI 1 "register_operand" "x")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
- (parallel [(const_int 0) (const_int 16)
- (const_int 1) (const_int 17)
- (const_int 2) (const_int 18)
- (const_int 3) (const_int 19)
- (const_int 4) (const_int 20)
- (const_int 5) (const_int 21)
- (const_int 6) (const_int 22)
- (const_int 7) (const_int 23)])))]
- "TARGET_AVX"
- "vpunpcklbw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
+ (const_int 14) (const_int 30)
+ (const_int 15) (const_int 31)])))]
+ "TARGET_SSE2"
+ "@
+ punpckhbw\t{%2, %0|%0, %2}
+ vpunpckhbw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "vec_interleave_lowv16qi"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
+ [(set (match_operand:V16QI 0 "register_operand" "=x,x")
(vec_select:V16QI
(vec_concat:V32QI
- (match_operand:V16QI 1 "register_operand" "0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
+ (match_operand:V16QI 1 "register_operand" "0,x")
+ (match_operand:V16QI 2 "nonimmediate_operand" "xm,xm"))
(parallel [(const_int 0) (const_int 16)
(const_int 1) (const_int 17)
(const_int 2) (const_int 18)
(const_int 6) (const_int 22)
(const_int 7) (const_int 23)])))]
"TARGET_SSE2"
- "punpcklbw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_interleave_highv8hi"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (vec_select:V8HI
- (vec_concat:V16HI
- (match_operand:V8HI 1 "register_operand" "x")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
- (parallel [(const_int 4) (const_int 12)
- (const_int 5) (const_int 13)
- (const_int 6) (const_int 14)
- (const_int 7) (const_int 15)])))]
- "TARGET_AVX"
- "vpunpckhwd\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
+ "@
+ punpcklbw\t{%2, %0|%0, %2}
+ vpunpcklbw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "vec_interleave_highv8hi"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
+ [(set (match_operand:V8HI 0 "register_operand" "=x,x")
(vec_select:V8HI
(vec_concat:V16HI
- (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
+ (match_operand:V8HI 1 "register_operand" "0,x")
+ (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm"))
(parallel [(const_int 4) (const_int 12)
(const_int 5) (const_int 13)
(const_int 6) (const_int 14)
(const_int 7) (const_int 15)])))]
"TARGET_SSE2"
- "punpckhwd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_interleave_lowv8hi"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (vec_select:V8HI
- (vec_concat:V16HI
- (match_operand:V8HI 1 "register_operand" "x")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
- (parallel [(const_int 0) (const_int 8)
- (const_int 1) (const_int 9)
- (const_int 2) (const_int 10)
- (const_int 3) (const_int 11)])))]
- "TARGET_AVX"
- "vpunpcklwd\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
+ "@
+ punpckhwd\t{%2, %0|%0, %2}
+ vpunpckhwd\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "vec_interleave_lowv8hi"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
+ [(set (match_operand:V8HI 0 "register_operand" "=x,x")
(vec_select:V8HI
(vec_concat:V16HI
- (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
+ (match_operand:V8HI 1 "register_operand" "0,x")
+ (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm"))
(parallel [(const_int 0) (const_int 8)
(const_int 1) (const_int 9)
(const_int 2) (const_int 10)
(const_int 3) (const_int 11)])))]
"TARGET_SSE2"
- "punpcklwd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_interleave_highv4si"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (vec_select:V4SI
- (vec_concat:V8SI
- (match_operand:V4SI 1 "register_operand" "x")
- (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
- (parallel [(const_int 2) (const_int 6)
- (const_int 3) (const_int 7)])))]
- "TARGET_AVX"
- "vpunpckhdq\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
+ "@
+ punpcklwd\t{%2, %0|%0, %2}
+ vpunpcklwd\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "vec_interleave_highv4si"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
+ [(set (match_operand:V4SI 0 "register_operand" "=x,x")
(vec_select:V4SI
(vec_concat:V8SI
- (match_operand:V4SI 1 "register_operand" "0")
- (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
+ (match_operand:V4SI 1 "register_operand" "0,x")
+ (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm"))
(parallel [(const_int 2) (const_int 6)
(const_int 3) (const_int 7)])))]
"TARGET_SSE2"
- "punpckhdq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_interleave_lowv4si"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (vec_select:V4SI
- (vec_concat:V8SI
- (match_operand:V4SI 1 "register_operand" "x")
- (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
- (parallel [(const_int 0) (const_int 4)
- (const_int 1) (const_int 5)])))]
- "TARGET_AVX"
- "vpunpckldq\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix" "vex")
+ "@
+ punpckhdq\t{%2, %0|%0, %2}
+ vpunpckhdq\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "vec_interleave_lowv4si"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
+ [(set (match_operand:V4SI 0 "register_operand" "=x,x")
(vec_select:V4SI
(vec_concat:V8SI
- (match_operand:V4SI 1 "register_operand" "0")
- (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
+ (match_operand:V4SI 1 "register_operand" "0,x")
+ (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm"))
(parallel [(const_int 0) (const_int 4)
(const_int 1) (const_int 5)])))]
"TARGET_SSE2"
- "punpckldq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_pinsr<ssevecsize>"
- [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
- (vec_merge:SSEMODE124
- (vec_duplicate:SSEMODE124
- (match_operand:<avxscalarmode> 2 "nonimmediate_operand" "rm"))
- (match_operand:SSEMODE124 1 "register_operand" "x")
- (match_operand:SI 3 "const_pow2_1_to_<pinsrbits>_operand" "n")))]
- "TARGET_AVX"
+ "@
+ punpckldq\t{%2, %0|%0, %2}
+ vpunpckldq\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
+ (set_attr "mode" "TI")])
+
+;; Modes handled by pinsr patterns.
+(define_mode_iterator PINSR_MODE
+ [(V16QI "TARGET_SSE4_1") V8HI
+ (V4SI "TARGET_SSE4_1")
+ (V2DI "TARGET_SSE4_1 && TARGET_64BIT")])
+
+(define_mode_attr sse2p4_1
+ [(V16QI "sse4_1") (V8HI "sse2")
+ (V4SI "sse4_1") (V2DI "sse4_1")])
+
+;; sse4_1_pinsrd must come before sse2_loadld since it is preferred.
+(define_insn "<sse2p4_1>_pinsr<ssemodesuffix>"
+ [(set (match_operand:PINSR_MODE 0 "register_operand" "=x,x,x,x")
+ (vec_merge:PINSR_MODE
+ (vec_duplicate:PINSR_MODE
+ (match_operand:<ssescalarmode> 2 "nonimmediate_operand" "r,m,r,m"))
+ (match_operand:PINSR_MODE 1 "register_operand" "0,0,x,x")
+ (match_operand:SI 3 "const_int_operand" "")))]
+ "TARGET_SSE2
+ && ((unsigned) exact_log2 (INTVAL (operands[3]))
+ < GET_MODE_NUNITS (<MODE>mode))"
{
operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
- if (MEM_P (operands[2]))
- return "vpinsr<ssevecsize>\t{%3, %2, %1, %0|%0, %1, %2, %3}";
- else
- return "vpinsr<ssevecsize>\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
+
+ switch (which_alternative)
+ {
+ case 0:
+ if (GET_MODE_SIZE (<ssescalarmode>mode) < GET_MODE_SIZE (SImode))
+ return "pinsr<ssemodesuffix>\t{%3, %k2, %0|%0, %k2, %3}";
+ /* FALLTHRU */
+ case 1:
+ return "pinsr<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}";
+ case 2:
+ if (GET_MODE_SIZE (<ssescalarmode>mode) < GET_MODE_SIZE (SImode))
+ return "vpinsr<ssemodesuffix>\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
+ /* FALLTHRU */
+ case 3:
+ return "vpinsr<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}";
+ default:
+ gcc_unreachable ();
+ }
}
- [(set_attr "type" "sselog")
+ [(set_attr "isa" "noavx,noavx,avx,avx")
+ (set_attr "type" "sselog")
+ (set (attr "prefix_rex")
+ (if_then_else
+ (and (eq (symbol_ref "TARGET_AVX") (const_int 0))
+ (eq (const_string "<MODE>mode") (const_string "V2DImode")))
+ (const_string "1")
+ (const_string "*")))
+ (set (attr "prefix_data16")
+ (if_then_else
+ (and (eq (symbol_ref "TARGET_AVX") (const_int 0))
+ (eq (const_string "<MODE>mode") (const_string "V8HImode")))
+ (const_string "1")
+ (const_string "*")))
(set (attr "prefix_extra")
- (if_then_else (match_operand:V8HI 0 "" "")
- (const_string "0")
+ (if_then_else
+ (and (eq (symbol_ref "TARGET_AVX") (const_int 0))
+ (eq (const_string "<MODE>mode") (const_string "V8HImode")))
+ (const_string "*")
(const_string "1")))
(set_attr "length_immediate" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
-(define_insn "*sse4_1_pinsrb"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (vec_merge:V16QI
- (vec_duplicate:V16QI
- (match_operand:QI 2 "nonimmediate_operand" "rm"))
- (match_operand:V16QI 1 "register_operand" "0")
- (match_operand:SI 3 "const_pow2_1_to_32768_operand" "n")))]
- "TARGET_SSE4_1"
-{
- operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
- if (MEM_P (operands[2]))
- return "pinsrb\t{%3, %2, %0|%0, %2, %3}";
- else
- return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
-}
- [(set_attr "type" "sselog")
- (set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*sse2_pinsrw"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (vec_merge:V8HI
- (vec_duplicate:V8HI
- (match_operand:HI 2 "nonimmediate_operand" "rm"))
- (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:SI 3 "const_pow2_1_to_128_operand" "n")))]
- "TARGET_SSE2"
-{
- operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
- if (MEM_P (operands[2]))
- return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
- else
- return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
-}
- [(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "TI")])
-
-;; It must come before sse2_loadld since it is preferred.
-(define_insn "*sse4_1_pinsrd"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (vec_merge:V4SI
- (vec_duplicate:V4SI
- (match_operand:SI 2 "nonimmediate_operand" "rm"))
- (match_operand:V4SI 1 "register_operand" "0")
- (match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))]
- "TARGET_SSE4_1"
-{
- operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
- return "pinsrd\t{%3, %2, %0|%0, %2, %3}";
-}
- [(set_attr "type" "sselog")
- (set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_pinsrq"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (vec_merge:V2DI
- (vec_duplicate:V2DI
- (match_operand:DI 2 "nonimmediate_operand" "rm"))
- (match_operand:V2DI 1 "register_operand" "x")
- (match_operand:SI 3 "const_pow2_1_to_2_operand" "n")))]
- "TARGET_AVX && TARGET_64BIT"
-{
- operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
- return "vpinsrq\t{%3, %2, %1, %0|%0, %1, %2, %3}";
-}
- [(set_attr "type" "sselog")
- (set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
-(define_insn "*sse4_1_pinsrq"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (vec_merge:V2DI
- (vec_duplicate:V2DI
- (match_operand:DI 2 "nonimmediate_operand" "rm"))
- (match_operand:V2DI 1 "register_operand" "0")
- (match_operand:SI 3 "const_pow2_1_to_2_operand" "n")))]
- "TARGET_SSE4_1 && TARGET_64BIT"
-{
- operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
- return "pinsrq\t{%3, %2, %0|%0, %2, %3}";
-}
- [(set_attr "type" "sselog")
- (set_attr "prefix_rex" "1")
- (set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "1")
+ (set_attr "prefix" "orig,orig,vex,vex")
(set_attr "mode" "TI")])
(define_insn "*sse4_1_pextrb_<mode>"
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
-;; It must come before *vec_extractv2di_1_sse since it is preferred.
+;; It must come before *vec_extractv2di_1_rex64 since it is preferred.
(define_insn "*sse4_1_pextrq"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(vec_select:DI
"TARGET_SSE"
"operands[2] = CONST0_RTX (V4SImode);")
-(define_insn "*avx_loadld"
- [(set (match_operand:V4SI 0 "register_operand" "=x,Yi,x")
- (vec_merge:V4SI
- (vec_duplicate:V4SI
- (match_operand:SI 2 "nonimmediate_operand" "m ,r ,x"))
- (match_operand:V4SI 1 "reg_or_0_operand" "C ,C ,x")
- (const_int 1)))]
- "TARGET_AVX"
- "@
- vmovd\t{%2, %0|%0, %2}
- vmovd\t{%2, %0|%0, %2}
- vmovss\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI,TI,V4SF")])
-
(define_insn "sse2_loadld"
- [(set (match_operand:V4SI 0 "register_operand" "=Y2,Yi,x,x")
+ [(set (match_operand:V4SI 0 "register_operand" "=Y2,Yi,x,x,x")
(vec_merge:V4SI
(vec_duplicate:V4SI
- (match_operand:SI 2 "nonimmediate_operand" "m ,r ,m,x"))
- (match_operand:V4SI 1 "reg_or_0_operand" "C ,C ,C,0")
+ (match_operand:SI 2 "nonimmediate_operand" "m ,r ,m,x,x"))
+ (match_operand:V4SI 1 "reg_or_0_operand" "C ,C ,C,0,x")
(const_int 1)))]
"TARGET_SSE"
"@
- movd\t{%2, %0|%0, %2}
- movd\t{%2, %0|%0, %2}
+ %vmovd\t{%2, %0|%0, %2}
+ %vmovd\t{%2, %0|%0, %2}
movss\t{%2, %0|%0, %2}
- movss\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "TI,TI,V4SF,SF")])
+ movss\t{%2, %0|%0, %2}
+ vmovss\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,*,noavx,noavx,avx")
+ (set_attr "type" "ssemov")
+ (set_attr "prefix" "maybe_vex,maybe_vex,orig,orig,vex")
+ (set_attr "mode" "TI,TI,V4SF,SF,SF")])
(define_insn_and_split "sse2_stored"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mx,r")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=xm,r")
(vec_select:SI
(match_operand:V4SI 1 "register_operand" "x,Yi")
(parallel [(const_int 0)])))]
"TARGET_SSE")
(define_insn "*sse2_storeq_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=mx,*r,r")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=xm,*r,r")
(vec_select:DI
(match_operand:V2DI 1 "nonimmediate_operand" "x,Yi,o")
(parallel [(const_int 0)])))]
"@
#
#
- %vmov{q}\t{%1, %0|%0, %1}"
+ mov{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "*,*,imov")
- (set_attr "prefix" "*,*,maybe_vex")
(set_attr "mode" "*,*,DI")])
(define_insn "*sse2_storeq"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=mx")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=xm")
(vec_select:DI
(match_operand:V2DI 1 "register_operand" "x")
(parallel [(const_int 0)])))]
[(set (match_dup 0) (match_dup 1))]
"operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));")
-(define_insn "*vec_extractv2di_1_rex64_avx"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,r")
- (vec_select:DI
- (match_operand:V2DI 1 "nonimmediate_operand" "x,x,o,o")
- (parallel [(const_int 1)])))]
- "TARGET_64BIT
- && TARGET_AVX
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "@
- vmovhps\t{%1, %0|%0, %1}
- vpsrldq\t{$8, %1, %0|%0, %1, 8}
- vmovq\t{%H1, %0|%0, %H1}
- vmov{q}\t{%H1, %0|%0, %H1}"
- [(set_attr "type" "ssemov,sseishft1,ssemov,imov")
- (set_attr "length_immediate" "*,1,*,*")
- (set_attr "memory" "*,none,*,*")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V2SF,TI,TI,DI")])
-
(define_insn "*vec_extractv2di_1_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,r")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,x,r")
(vec_select:DI
- (match_operand:V2DI 1 "nonimmediate_operand" "x,0,o,o")
+ (match_operand:V2DI 1 "nonimmediate_operand" " x,0,x,o,o")
(parallel [(const_int 1)])))]
"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
- movhps\t{%1, %0|%0, %1}
+ %vmovhps\t{%1, %0|%0, %1}
psrldq\t{$8, %0|%0, 8}
- movq\t{%H1, %0|%0, %H1}
+ vpsrldq\t{$8, %1, %0|%0, %1, 8}
+ %vmovq\t{%H1, %0|%0, %H1}
mov{q}\t{%H1, %0|%0, %H1}"
- [(set_attr "type" "ssemov,sseishft1,ssemov,imov")
- (set_attr "length_immediate" "*,1,*,*")
- (set_attr "memory" "*,none,*,*")
- (set_attr "mode" "V2SF,TI,TI,DI")])
-
-(define_insn "*vec_extractv2di_1_avx"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x")
+ [(set_attr "isa" "*,noavx,avx,*,*")
+ (set_attr "type" "ssemov,sseishft1,sseishft1,ssemov,imov")
+ (set_attr "length_immediate" "*,1,1,*,*")
+ (set_attr "memory" "*,none,none,*,*")
+ (set_attr "prefix" "maybe_vex,orig,vex,maybe_vex,orig")
+ (set_attr "mode" "V2SF,TI,TI,TI,DI")])
+
+(define_insn "*vec_extractv2di_1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=m,Y2,Y2,Y2,x,x")
(vec_select:DI
- (match_operand:V2DI 1 "nonimmediate_operand" "x,x,o")
+ (match_operand:V2DI 1 "nonimmediate_operand" " x,0 ,Y2,o ,x,o")
(parallel [(const_int 1)])))]
- "!TARGET_64BIT
- && TARGET_AVX
+ "!TARGET_64BIT && TARGET_SSE
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
- vmovhps\t{%1, %0|%0, %1}
- vpsrldq\t{$8, %1, %0|%0, %1, 8}
- vmovq\t{%H1, %0|%0, %H1}"
- [(set_attr "type" "ssemov,sseishft1,ssemov")
- (set_attr "length_immediate" "*,1,*")
- (set_attr "memory" "*,none,*")
- (set_attr "prefix" "vex")
- (set_attr "mode" "V2SF,TI,TI")])
-
-(define_insn "*vec_extractv2di_1_sse2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x")
- (vec_select:DI
- (match_operand:V2DI 1 "nonimmediate_operand" "x,0,o")
- (parallel [(const_int 1)])))]
- "!TARGET_64BIT
- && TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "@
- movhps\t{%1, %0|%0, %1}
+ %vmovhps\t{%1, %0|%0, %1}
psrldq\t{$8, %0|%0, 8}
- movq\t{%H1, %0|%0, %H1}"
- [(set_attr "type" "ssemov,sseishft1,ssemov")
- (set_attr "length_immediate" "*,1,*")
- (set_attr "memory" "*,none,*")
- (set_attr "mode" "V2SF,TI,TI")])
-
-;; Not sure this is ever used, but it doesn't hurt to have it. -aoliva
-(define_insn "*vec_extractv2di_1_sse"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x")
- (vec_select:DI
- (match_operand:V2DI 1 "nonimmediate_operand" "x,x,o")
- (parallel [(const_int 1)])))]
- "!TARGET_SSE2 && TARGET_SSE
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "@
- movhps\t{%1, %0|%0, %1}
+ vpsrldq\t{$8, %1, %0|%0, %1, 8}
+ %vmovq\t{%H1, %0|%0, %H1}
movhlps\t{%1, %0|%0, %1}
movlps\t{%H1, %0|%0, %H1}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "V2SF,V4SF,V2SF")])
+ [(set_attr "isa" "*,noavx,avx,*,noavx,noavx")
+ (set_attr "type" "ssemov,sseishft1,sseishft1,ssemov,ssemov,ssemov")
+ (set_attr "length_immediate" "*,1,1,*,*,*")
+ (set_attr "memory" "*,none,none,*,*,*")
+ (set_attr "prefix" "maybe_vex,orig,vex,maybe_vex,orig,orig")
+ (set_attr "mode" "V2SF,TI,TI,TI,V4SF,V2SF")])
(define_insn "*vec_dupv4si_avx"
- [(set (match_operand:V4SI 0 "register_operand" "=x,x")
+ [(set (match_operand:V4SI 0 "register_operand" "=x,x")
(vec_duplicate:V4SI
- (match_operand:SI 1 "register_operand" "x,m")))]
+ (match_operand:SI 1 "nonimmediate_operand" " x,m")))]
"TARGET_AVX"
"@
vpshufd\t{$0, %1, %0|%0, %1, 0}
(match_operand:SI 1 "register_operand" " Y2,0")))]
"TARGET_SSE"
"@
- %vpshufd\t{$0, %1, %0|%0, %1, 0}
+ pshufd\t{$0, %1, %0|%0, %1, 0}
shufps\t{$0, %0, %0|%0, %0, 0}"
[(set_attr "type" "sselog1")
(set_attr "length_immediate" "1")
(set_attr "mode" "TI,V4SF")])
-(define_insn "*vec_dupv2di_avx"
- [(set (match_operand:V2DI 0 "register_operand" "=x,x")
- (vec_duplicate:V2DI
- (match_operand:DI 1 "nonimmediate_operand" " x,m")))]
- "TARGET_AVX"
- "@
- vpunpcklqdq\t{%1, %1, %0|%0, %1, %1}
- vmovddup\t{%1, %0|%0, %1}"
- [(set_attr "type" "sselog1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI,DF")])
-
(define_insn "*vec_dupv2di_sse3"
- [(set (match_operand:V2DI 0 "register_operand" "=x,x")
+ [(set (match_operand:V2DI 0 "register_operand" "=x,x,x")
(vec_duplicate:V2DI
- (match_operand:DI 1 "nonimmediate_operand" " 0,m")))]
+ (match_operand:DI 1 "nonimmediate_operand" " 0,x,m")))]
"TARGET_SSE3"
"@
punpcklqdq\t%0, %0
- movddup\t{%1, %0|%0, %1}"
- [(set_attr "type" "sselog1")
- (set_attr "mode" "TI,DF")])
+ vpunpcklqdq\t{%d1, %0|%0, %d1}
+ %vmovddup\t{%1, %0|%0, %1}"
+ [(set_attr "isa" "noavx,avx,*")
+ (set_attr "type" "sselog1")
+ (set_attr "prefix" "orig,vex,maybe_vex")
+ (set_attr "mode" "TI,TI,DF")])
(define_insn "*vec_dupv2di"
[(set (match_operand:V2DI 0 "register_operand" "=Y2,x")
[(set_attr "type" "sselog1,ssemov")
(set_attr "mode" "TI,V4SF")])
-(define_insn "*vec_concatv2si_avx"
- [(set (match_operand:V2SI 0 "register_operand" "=x,x,x ,*y ,*y")
- (vec_concat:V2SI
- (match_operand:SI 1 "nonimmediate_operand" "x ,x,rm, 0 ,rm")
- (match_operand:SI 2 "vector_move_operand" "rm,x,C ,*ym,C")))]
- "TARGET_AVX"
- "@
- vpinsrd\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}
- vpunpckldq\t{%2, %1, %0|%0, %1, %2}
- vmovd\t{%1, %0|%0, %1}
- punpckldq\t{%2, %0|%0, %2}
- movd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
- (set_attr "prefix_extra" "1,*,*,*,*")
- (set_attr "length_immediate" "1,*,*,*,*")
- (set (attr "prefix")
- (if_then_else (eq_attr "alternative" "3,4")
- (const_string "orig")
- (const_string "vex")))
- (set_attr "mode" "TI,TI,TI,DI,DI")])
-
(define_insn "*vec_concatv2si_sse4_1"
- [(set (match_operand:V2SI 0 "register_operand" "=x,x,x ,*y ,*y")
+ [(set (match_operand:V2SI 0 "register_operand" "=x, x,x,x, x, *y,*y")
(vec_concat:V2SI
- (match_operand:SI 1 "nonimmediate_operand" "0 ,0,rm, 0 ,rm")
- (match_operand:SI 2 "vector_move_operand" "rm,x,C ,*ym,C")))]
+ (match_operand:SI 1 "nonimmediate_operand" " 0, x,0,x,rm, 0,rm")
+ (match_operand:SI 2 "vector_move_operand" "rm,rm,x,x, C,*ym, C")))]
"TARGET_SSE4_1"
"@
- pinsrd\t{$0x1, %2, %0|%0, %2, 0x1}
+ pinsrd\t{$1, %2, %0|%0, %2, 1}
+ vpinsrd\t{$1, %2, %1, %0|%0, %1, %2, 1}
punpckldq\t{%2, %0|%0, %2}
- movd\t{%1, %0|%0, %1}
+ vpunpckldq\t{%2, %1, %0|%0, %1, %2}
+ %vmovd\t{%1, %0|%0, %1}
punpckldq\t{%2, %0|%0, %2}
movd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
- (set_attr "prefix_extra" "1,*,*,*,*")
- (set_attr "length_immediate" "1,*,*,*,*")
- (set_attr "mode" "TI,TI,TI,DI,DI")])
+ [(set_attr "isa" "noavx,avx,noavx,avx,*,*,*")
+ (set_attr "type" "sselog,sselog,sselog,sselog,ssemov,mmxcvt,mmxmov")
+ (set_attr "prefix_extra" "1,1,*,*,*,*,*")
+ (set_attr "length_immediate" "1,1,*,*,*,*,*")
+ (set_attr "prefix" "orig,vex,orig,vex,maybe_vex,orig,orig")
+ (set_attr "mode" "TI,TI,TI,TI,TI,DI,DI")])
;; ??? In theory we can match memory for the MMX alternative, but allowing
;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE
[(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
(set_attr "mode" "V4SF,V4SF,DI,DI")])
-(define_insn "*vec_concatv4si_1_avx"
- [(set (match_operand:V4SI 0 "register_operand" "=x,x")
- (vec_concat:V4SI
- (match_operand:V2SI 1 "register_operand" " x,x")
- (match_operand:V2SI 2 "nonimmediate_operand" " x,m")))]
- "TARGET_AVX"
- "@
- vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}
- vmovhps\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog,ssemov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI,V2SF")])
-
-(define_insn "*vec_concatv4si_1"
- [(set (match_operand:V4SI 0 "register_operand" "=Y2,x,x")
+(define_insn "*vec_concatv4si"
+ [(set (match_operand:V4SI 0 "register_operand" "=Y2,x,x,x,x")
(vec_concat:V4SI
- (match_operand:V2SI 1 "register_operand" " 0 ,0,0")
- (match_operand:V2SI 2 "nonimmediate_operand" " Y2,x,m")))]
+ (match_operand:V2SI 1 "register_operand" " 0 ,x,0,0,x")
+ (match_operand:V2SI 2 "nonimmediate_operand" " Y2,x,x,m,m")))]
"TARGET_SSE"
"@
punpcklqdq\t{%2, %0|%0, %2}
- movlhps\t{%2, %0|%0, %2}
- movhps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog,ssemov,ssemov")
- (set_attr "mode" "TI,V4SF,V2SF")])
-
-(define_insn "*vec_concatv2di_avx"
- [(set (match_operand:V2DI 0 "register_operand" "=x,?x,x,x")
- (vec_concat:V2DI
- (match_operand:DI 1 "nonimmediate_operand" " m,*y,x,x")
- (match_operand:DI 2 "vector_move_operand" " C, C,x,m")))]
- "!TARGET_64BIT && TARGET_AVX"
- "@
- vmovq\t{%1, %0|%0, %1}
- movq2dq\t{%1, %0|%0, %1}
vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}
+ movlhps\t{%2, %0|%0, %2}
+ movhps\t{%2, %0|%0, %2}
vmovhps\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssemov,ssemov,sselog,ssemov")
- (set (attr "prefix")
- (if_then_else (eq_attr "alternative" "1")
- (const_string "orig")
- (const_string "vex")))
- (set_attr "mode" "TI,TI,TI,V2SF")])
-
-(define_insn "vec_concatv2di"
- [(set (match_operand:V2DI 0 "register_operand" "=Y2 ,?Y2,Y2,x,x")
+ [(set_attr "isa" "noavx,avx,noavx,noavx,avx")
+ (set_attr "type" "sselog,sselog,ssemov,ssemov,ssemov")
+ (set_attr "prefix" "orig,vex,orig,orig,vex")
+ (set_attr "mode" "TI,TI,V4SF,V2SF,V2SF")])
+
+;; movd instead of movq is required to handle broken assemblers.
+(define_insn "*vec_concatv2di_rex64"
+ [(set (match_operand:V2DI 0 "register_operand"
+ "=Y4,x ,x ,Yi,!x,x,x,x,x")
(vec_concat:V2DI
- (match_operand:DI 1 "nonimmediate_operand" " mY2,*y ,0 ,0,0")
- (match_operand:DI 2 "vector_move_operand" " C , C,Y2,x,m")))]
- "!TARGET_64BIT && TARGET_SSE"
+ (match_operand:DI 1 "nonimmediate_operand"
+ " 0 ,x ,xm,r ,*y,0,x,0,x")
+ (match_operand:DI 2 "vector_move_operand"
+ " rm,rm,C ,C ,C ,x,x,m,m")))]
+ "TARGET_64BIT"
"@
- movq\t{%1, %0|%0, %1}
+ pinsrq\t{$1, %2, %0|%0, %2, 1}
+ vpinsrq\t{$1, %2, %1, %0|%0, %1, %2, 1}
+ %vmovq\t{%1, %0|%0, %1}
+ %vmovd\t{%1, %0|%0, %1}
movq2dq\t{%1, %0|%0, %1}
punpcklqdq\t{%2, %0|%0, %2}
- movlhps\t{%2, %0|%0, %2}
- movhps\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssemov,ssemov,sselog,ssemov,ssemov")
- (set_attr "mode" "TI,TI,TI,V4SF,V2SF")])
-
-(define_insn "*vec_concatv2di_rex64_avx"
- [(set (match_operand:V2DI 0 "register_operand" "=x,x,Yi,!x,x,x")
- (vec_concat:V2DI
- (match_operand:DI 1 "nonimmediate_operand" " x,m,r ,*y,x,x")
- (match_operand:DI 2 "vector_move_operand" "rm,C,C ,C ,x,m")))]
- "TARGET_64BIT && TARGET_AVX"
- "@
- vpinsrq\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}
- vmovq\t{%1, %0|%0, %1}
- vmovq\t{%1, %0|%0, %1}
- movq2dq\t{%1, %0|%0, %1}
vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}
+ movhps\t{%2, %0|%0, %2}
vmovhps\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,ssemov")
- (set_attr "prefix_extra" "1,*,*,*,*,*")
- (set_attr "length_immediate" "1,*,*,*,*,*")
- (set (attr "prefix")
- (if_then_else (eq_attr "alternative" "3")
- (const_string "orig")
- (const_string "vex")))
- (set_attr "mode" "TI,TI,TI,TI,TI,V2SF")])
-
-(define_insn "*vec_concatv2di_rex64_sse4_1"
- [(set (match_operand:V2DI 0 "register_operand" "=x ,x ,Yi,!x,x,x,x")
- (vec_concat:V2DI
- (match_operand:DI 1 "nonimmediate_operand" " 0 ,mx,r ,*y,0,0,0")
- (match_operand:DI 2 "vector_move_operand" " rm,C ,C ,C ,x,x,m")))]
- "TARGET_64BIT && TARGET_SSE4_1"
- "@
- pinsrq\t{$0x1, %2, %0|%0, %2, 0x1}
- movq\t{%1, %0|%0, %1}
- movd\t{%1, %0|%0, %1}
- movq2dq\t{%1, %0|%0, %1}
- punpcklqdq\t{%2, %0|%0, %2}
- movlhps\t{%2, %0|%0, %2}
- movhps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
- (set_attr "prefix_rex" "1,*,1,*,*,*,*")
- (set_attr "prefix_extra" "1,*,*,*,*,*,*")
- (set_attr "length_immediate" "1,*,*,*,*,*,*")
- (set_attr "mode" "TI,TI,TI,TI,TI,V4SF,V2SF")])
-
-(define_insn "*vec_concatv2di_rex64_sse"
- [(set (match_operand:V2DI 0 "register_operand" "=Y2 ,Yi,!Y2,Y2,x,x")
+ [(set_attr "isa" "noavx,avx,*,*,*,noavx,avx,noavx,avx")
+ (set (attr "type")
+ (if_then_else
+ (eq_attr "alternative" "0,1,5,6")
+ (const_string "sselog")
+ (const_string "ssemov")))
+ (set (attr "prefix_rex")
+ (if_then_else
+ (and (eq_attr "alternative" "0,3")
+ (eq (symbol_ref "TARGET_AVX") (const_int 0)))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "prefix_extra" "1,1,*,*,*,*,*,*,*")
+ (set_attr "length_immediate" "1,1,*,*,*,*,*,*,*")
+ (set_attr "prefix" "orig,vex,maybe_vex,maybe_vex,orig,orig,vex,orig,vex")
+ (set_attr "mode" "TI,TI,TI,TI,TI,TI,TI,V2SF,V2SF")])
+
+(define_insn "vec_concatv2di"
+ [(set (match_operand:V2DI 0 "register_operand" "=Y2,?Y2,Y2,x,x,x,x")
(vec_concat:V2DI
- (match_operand:DI 1 "nonimmediate_operand" " mY2,r ,*y ,0 ,0,0")
- (match_operand:DI 2 "vector_move_operand" " C ,C ,C ,Y2,x,m")))]
- "TARGET_64BIT && TARGET_SSE"
+ (match_operand:DI 1 "nonimmediate_operand" "Y2m,*y , 0,x,0,0,x")
+ (match_operand:DI 2 "vector_move_operand" " C , C ,Y2,x,x,m,m")))]
+ "!TARGET_64BIT && TARGET_SSE"
"@
- movq\t{%1, %0|%0, %1}
- movd\t{%1, %0|%0, %1}
+ %vmovq\t{%1, %0|%0, %1}
movq2dq\t{%1, %0|%0, %1}
punpcklqdq\t{%2, %0|%0, %2}
+ vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}
movlhps\t{%2, %0|%0, %2}
- movhps\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
- (set_attr "prefix_rex" "*,1,*,*,*,*")
- (set_attr "mode" "TI,TI,TI,TI,V4SF,V2SF")])
-
-(define_expand "vec_unpacku_hi_v16qi"
- [(match_operand:V8HI 0 "register_operand" "")
- (match_operand:V16QI 1 "register_operand" "")]
- "TARGET_SSE2"
-{
- if (TARGET_SSE4_1)
- ix86_expand_sse4_unpack (operands, true, true);
- else
- ix86_expand_sse_unpack (operands, true, true);
- DONE;
-})
-
-(define_expand "vec_unpacks_hi_v16qi"
- [(match_operand:V8HI 0 "register_operand" "")
- (match_operand:V16QI 1 "register_operand" "")]
- "TARGET_SSE2"
-{
- if (TARGET_SSE4_1)
- ix86_expand_sse4_unpack (operands, false, true);
- else
- ix86_expand_sse_unpack (operands, false, true);
- DONE;
-})
-
-(define_expand "vec_unpacku_lo_v16qi"
- [(match_operand:V8HI 0 "register_operand" "")
- (match_operand:V16QI 1 "register_operand" "")]
- "TARGET_SSE2"
-{
- if (TARGET_SSE4_1)
- ix86_expand_sse4_unpack (operands, true, false);
- else
- ix86_expand_sse_unpack (operands, true, false);
- DONE;
-})
-
-(define_expand "vec_unpacks_lo_v16qi"
- [(match_operand:V8HI 0 "register_operand" "")
- (match_operand:V16QI 1 "register_operand" "")]
- "TARGET_SSE2"
-{
- if (TARGET_SSE4_1)
- ix86_expand_sse4_unpack (operands, false, false);
- else
- ix86_expand_sse_unpack (operands, false, false);
- DONE;
-})
-
-(define_expand "vec_unpacku_hi_v8hi"
- [(match_operand:V4SI 0 "register_operand" "")
- (match_operand:V8HI 1 "register_operand" "")]
- "TARGET_SSE2"
-{
- if (TARGET_SSE4_1)
- ix86_expand_sse4_unpack (operands, true, true);
- else
- ix86_expand_sse_unpack (operands, true, true);
- DONE;
-})
-
-(define_expand "vec_unpacks_hi_v8hi"
- [(match_operand:V4SI 0 "register_operand" "")
- (match_operand:V8HI 1 "register_operand" "")]
- "TARGET_SSE2"
-{
- if (TARGET_SSE4_1)
- ix86_expand_sse4_unpack (operands, false, true);
- else
- ix86_expand_sse_unpack (operands, false, true);
- DONE;
-})
-
-(define_expand "vec_unpacku_lo_v8hi"
- [(match_operand:V4SI 0 "register_operand" "")
- (match_operand:V8HI 1 "register_operand" "")]
- "TARGET_SSE2"
-{
- if (TARGET_SSE4_1)
- ix86_expand_sse4_unpack (operands, true, false);
- else
- ix86_expand_sse_unpack (operands, true, false);
- DONE;
-})
-
-(define_expand "vec_unpacks_lo_v8hi"
- [(match_operand:V4SI 0 "register_operand" "")
- (match_operand:V8HI 1 "register_operand" "")]
- "TARGET_SSE2"
-{
- if (TARGET_SSE4_1)
- ix86_expand_sse4_unpack (operands, false, false);
- else
- ix86_expand_sse_unpack (operands, false, false);
- DONE;
-})
-
-(define_expand "vec_unpacku_hi_v4si"
- [(match_operand:V2DI 0 "register_operand" "")
- (match_operand:V4SI 1 "register_operand" "")]
+ movhps\t{%2, %0|%0, %2}
+ vmovhps\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,*,noavx,avx,noavx,noavx,avx")
+ (set_attr "type" "ssemov,ssemov,sselog,sselog,ssemov,ssemov,ssemov")
+ (set_attr "prefix" "maybe_vex,orig,orig,vex,orig,orig,vex")
+ (set_attr "mode" "TI,TI,TI,TI,V4SF,V2SF,V2SF")])
+
+(define_expand "vec_unpacks_lo_<mode>"
+ [(match_operand:<sseunpackmode> 0 "register_operand" "")
+ (match_operand:VI124_128 1 "register_operand" "")]
"TARGET_SSE2"
-{
- if (TARGET_SSE4_1)
- ix86_expand_sse4_unpack (operands, true, true);
- else
- ix86_expand_sse_unpack (operands, true, true);
- DONE;
-})
+ "ix86_expand_sse_unpack (operands, false, false); DONE;")
-(define_expand "vec_unpacks_hi_v4si"
- [(match_operand:V2DI 0 "register_operand" "")
- (match_operand:V4SI 1 "register_operand" "")]
+(define_expand "vec_unpacks_hi_<mode>"
+ [(match_operand:<sseunpackmode> 0 "register_operand" "")
+ (match_operand:VI124_128 1 "register_operand" "")]
"TARGET_SSE2"
-{
- if (TARGET_SSE4_1)
- ix86_expand_sse4_unpack (operands, false, true);
- else
- ix86_expand_sse_unpack (operands, false, true);
- DONE;
-})
+ "ix86_expand_sse_unpack (operands, false, true); DONE;")
-(define_expand "vec_unpacku_lo_v4si"
- [(match_operand:V2DI 0 "register_operand" "")
- (match_operand:V4SI 1 "register_operand" "")]
+(define_expand "vec_unpacku_lo_<mode>"
+ [(match_operand:<sseunpackmode> 0 "register_operand" "")
+ (match_operand:VI124_128 1 "register_operand" "")]
"TARGET_SSE2"
-{
- if (TARGET_SSE4_1)
- ix86_expand_sse4_unpack (operands, true, false);
- else
- ix86_expand_sse_unpack (operands, true, false);
- DONE;
-})
+ "ix86_expand_sse_unpack (operands, true, false); DONE;")
-(define_expand "vec_unpacks_lo_v4si"
- [(match_operand:V2DI 0 "register_operand" "")
- (match_operand:V4SI 1 "register_operand" "")]
+(define_expand "vec_unpacku_hi_<mode>"
+ [(match_operand:<sseunpackmode> 0 "register_operand" "")
+ (match_operand:VI124_128 1 "register_operand" "")]
"TARGET_SSE2"
-{
- if (TARGET_SSE4_1)
- ix86_expand_sse4_unpack (operands, false, false);
- else
- ix86_expand_sse_unpack (operands, false, false);
- DONE;
-})
+ "ix86_expand_sse_unpack (operands, true, true); DONE;")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (PLUS, V16QImode, operands);")
-(define_insn "*avx_uavgv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (truncate:V16QI
- (lshiftrt:V16HI
- (plus:V16HI
- (plus:V16HI
- (zero_extend:V16HI
- (match_operand:V16QI 1 "nonimmediate_operand" "%x"))
- (zero_extend:V16HI
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")))
- (const_vector:V16QI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
- (const_int 1))))]
- "TARGET_AVX && ix86_binary_operator_ok (PLUS, V16QImode, operands)"
- "vpavgb\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "*sse2_uavgv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
+ [(set (match_operand:V16QI 0 "register_operand" "=x,x")
(truncate:V16QI
(lshiftrt:V16HI
(plus:V16HI
(plus:V16HI
(zero_extend:V16HI
- (match_operand:V16QI 1 "nonimmediate_operand" "%0"))
+ (match_operand:V16QI 1 "nonimmediate_operand" "%0,x"))
(zero_extend:V16HI
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")))
+ (match_operand:V16QI 2 "nonimmediate_operand" "xm,xm")))
(const_vector:V16QI [(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(const_int 1) (const_int 1)]))
(const_int 1))))]
"TARGET_SSE2 && ix86_binary_operator_ok (PLUS, V16QImode, operands)"
- "pavgb\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_data16" "1")
+ "@
+ pavgb\t{%2, %0|%0, %2}
+ vpavgb\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_expand "sse2_uavgv8hi3"
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (PLUS, V8HImode, operands);")
-(define_insn "*avx_uavgv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (truncate:V8HI
- (lshiftrt:V8SI
- (plus:V8SI
- (plus:V8SI
- (zero_extend:V8SI
- (match_operand:V8HI 1 "nonimmediate_operand" "%x"))
- (zero_extend:V8SI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
- (const_vector:V8HI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
- (const_int 1))))]
- "TARGET_AVX && ix86_binary_operator_ok (PLUS, V8HImode, operands)"
- "vpavgw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "*sse2_uavgv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
+ [(set (match_operand:V8HI 0 "register_operand" "=x,x")
(truncate:V8HI
(lshiftrt:V8SI
(plus:V8SI
(plus:V8SI
(zero_extend:V8SI
- (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
+ (match_operand:V8HI 1 "nonimmediate_operand" "%0,x"))
(zero_extend:V8SI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
+ (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")))
(const_vector:V8HI [(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(const_int 1) (const_int 1)]))
(const_int 1))))]
"TARGET_SSE2 && ix86_binary_operator_ok (PLUS, V8HImode, operands)"
- "pavgw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_data16" "1")
+ "@
+ pavgw\t{%2, %0|%0, %2}
+ vpavgw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
;; The correct representation for this is absolutely enormous, and
;; surely not generally useful.
-(define_insn "*avx_psadbw"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "x")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
- UNSPEC_PSADBW))]
- "TARGET_AVX"
- "vpsadbw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "sse2_psadbw"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
+ [(set (match_operand:V2DI 0 "register_operand" "=x,x")
+ (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0,x")
+ (match_operand:V16QI 2 "nonimmediate_operand" "xm,xm")]
UNSPEC_PSADBW))]
"TARGET_SSE2"
- "psadbw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
+ "@
+ psadbw\t{%2, %0|%0, %2}
+ vpsadbw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
(set_attr "atom_unit" "simul")
- (set_attr "prefix_data16" "1")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
-(define_insn "avx_movmsk<ssemodesuffix>256"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI
- [(match_operand:AVX256MODEF2P 1 "register_operand" "x")]
- UNSPEC_MOVMSK))]
- "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
- "vmovmsk<ssemodesuffix>\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "<sse>_movmsk<ssemodesuffix>"
+(define_insn "<sse>_movmsk<ssemodesuffix><avxsizesuffix>"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI
- [(match_operand:SSEMODEF2P 1 "register_operand" "x")]
+ [(match_operand:VF 1 "register_operand" "x")]
UNSPEC_MOVMSK))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
+ "TARGET_SSE"
"%vmovmsk<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix" "maybe_vex")
"TARGET_SSE2")
(define_insn "*sse2_maskmovdqu"
- [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
- (match_operand:V16QI 2 "register_operand" "x")
- (mem:V16QI (match_dup 0))]
- UNSPEC_MASKMOV))]
- "TARGET_SSE2 && !TARGET_64BIT"
- ;; @@@ check ordering of operands in intel/nonintel syntax
- "%vmaskmovdqu\t{%2, %1|%1, %2}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix_data16" "1")
- ;; The implicit %rdi operand confuses default length_vex computation.
- (set_attr "length_vex" "3")
- (set_attr "prefix" "maybe_vex")
- (set_attr "mode" "TI")])
-
-(define_insn "*sse2_maskmovdqu_rex64"
- [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
+ [(set (mem:V16QI (match_operand:P 0 "register_operand" "D"))
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
(match_operand:V16QI 2 "register_operand" "x")
(mem:V16QI (match_dup 0))]
UNSPEC_MASKMOV))]
- "TARGET_SSE2 && TARGET_64BIT"
- ;; @@@ check ordering of operands in intel/nonintel syntax
+ "TARGET_SSE2"
"%vmaskmovdqu\t{%2, %1|%1, %2}"
[(set_attr "type" "ssemov")
(set_attr "prefix_data16" "1")
;; The implicit %rdi operand confuses default length_vex computation.
(set (attr "length_vex")
- (symbol_ref ("REGNO (operands[2]) >= FIRST_REX_SSE_REG ? 3 + 1 : 2 + 1")))
+ (symbol_ref ("3 + REX_SSE_REGNO_P (REGNO (operands[2]))")))
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(define_insn "*avx_phaddwv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (vec_concat:V8HI
- (vec_concat:V4HI
- (vec_concat:V2HI
- (plus:HI
- (vec_select:HI
- (match_operand:V8HI 1 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (plus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (plus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
- (plus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
- (vec_concat:V4HI
- (vec_concat:V2HI
- (plus:HI
- (vec_select:HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (plus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (plus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
- (plus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
- "TARGET_AVX"
- "vphaddw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "ssse3_phaddwv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
+ [(set (match_operand:V8HI 0 "register_operand" "=x,x")
(vec_concat:V8HI
(vec_concat:V4HI
(vec_concat:V2HI
(plus:HI
(vec_select:HI
- (match_operand:V8HI 1 "register_operand" "0")
+ (match_operand:V8HI 1 "register_operand" "0,x")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
(plus:HI
(vec_concat:V2HI
(plus:HI
(vec_select:HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")
+ (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
(plus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
"TARGET_SSSE3"
- "phaddw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
+ "@
+ phaddw\t{%2, %0|%0, %2}
+ vphaddw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
- (set_attr "prefix_data16" "1")
+ (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "ssse3_phaddwv4hi3"
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
-(define_insn "*avx_phadddv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (vec_concat:V4SI
- (vec_concat:V2SI
- (plus:SI
- (vec_select:SI
- (match_operand:V4SI 1 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
- (plus:SI
- (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2SI
- (plus:SI
- (vec_select:SI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
- (plus:SI
- (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
- "TARGET_AVX"
- "vphaddd\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "ssse3_phadddv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
+ [(set (match_operand:V4SI 0 "register_operand" "=x,x")
(vec_concat:V4SI
(vec_concat:V2SI
(plus:SI
(vec_select:SI
- (match_operand:V4SI 1 "register_operand" "0")
+ (match_operand:V4SI 1 "register_operand" "0,x")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
(plus:SI
(vec_concat:V2SI
(plus:SI
(vec_select:SI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")
+ (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
(plus:SI
(vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
- "TARGET_SSSE3"
- "phaddd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
+ "TARGET_SSSE3"
+ "@
+ phaddd\t{%2, %0|%0, %2}
+ vphaddd\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
- (set_attr "prefix_data16" "1")
+ (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "ssse3_phadddv2si3"
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
-(define_insn "*avx_phaddswv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (vec_concat:V8HI
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI
- (match_operand:V8HI 1 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ss_plus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
- (ss_plus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
- "TARGET_AVX"
- "vphaddsw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "ssse3_phaddswv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
+ [(set (match_operand:V8HI 0 "register_operand" "=x,x")
(vec_concat:V8HI
(vec_concat:V4HI
(vec_concat:V2HI
(ss_plus:HI
(vec_select:HI
- (match_operand:V8HI 1 "register_operand" "0")
+ (match_operand:V8HI 1 "register_operand" "0,x")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
(ss_plus:HI
(vec_concat:V2HI
(ss_plus:HI
(vec_select:HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")
+ (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
(ss_plus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
"TARGET_SSSE3"
- "phaddsw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
+ "@
+ phaddsw\t{%2, %0|%0, %2}
+ vphaddsw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
- (set_attr "prefix_data16" "1")
+ (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "ssse3_phaddswv4hi3"
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
-(define_insn "*avx_phsubwv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (vec_concat:V8HI
- (vec_concat:V4HI
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI
- (match_operand:V8HI 1 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
- (minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
- (vec_concat:V4HI
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
- (minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
- "TARGET_AVX"
- "vphsubw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "ssse3_phsubwv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
+ [(set (match_operand:V8HI 0 "register_operand" "=x,x")
(vec_concat:V8HI
(vec_concat:V4HI
(vec_concat:V2HI
(minus:HI
(vec_select:HI
- (match_operand:V8HI 1 "register_operand" "0")
+ (match_operand:V8HI 1 "register_operand" "0,x")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
(minus:HI
(vec_concat:V2HI
(minus:HI
(vec_select:HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")
+ (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
(minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
"TARGET_SSSE3"
- "phsubw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
+ "@
+ phsubw\t{%2, %0|%0, %2}
+ vphsubw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
- (set_attr "prefix_data16" "1")
+ (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "ssse3_phsubwv4hi3"
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
-(define_insn "*avx_phsubdv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (vec_concat:V4SI
- (vec_concat:V2SI
- (minus:SI
- (vec_select:SI
- (match_operand:V4SI 1 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
- (minus:SI
- (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2SI
- (minus:SI
- (vec_select:SI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
- (minus:SI
- (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
- "TARGET_AVX"
- "vphsubd\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "ssse3_phsubdv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
+ [(set (match_operand:V4SI 0 "register_operand" "=x,x")
(vec_concat:V4SI
(vec_concat:V2SI
(minus:SI
(vec_select:SI
- (match_operand:V4SI 1 "register_operand" "0")
+ (match_operand:V4SI 1 "register_operand" "0,x")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
(minus:SI
(vec_concat:V2SI
(minus:SI
(vec_select:SI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")
+ (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
(minus:SI
(vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
"TARGET_SSSE3"
- "phsubd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
+ "@
+ phsubd\t{%2, %0|%0, %2}
+ vphsubd\t{%2, %1, %0|%0, %1, %2}"
+
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
- (set_attr "prefix_data16" "1")
+ (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "ssse3_phsubdv2si3"
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
-(define_insn "*avx_phsubswv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (vec_concat:V8HI
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI
- (match_operand:V8HI 1 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ss_minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
- (ss_minus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
- "TARGET_AVX"
- "vphsubsw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "ssse3_phsubswv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
+ [(set (match_operand:V8HI 0 "register_operand" "=x,x")
(vec_concat:V8HI
(vec_concat:V4HI
(vec_concat:V2HI
(ss_minus:HI
(vec_select:HI
- (match_operand:V8HI 1 "register_operand" "0")
+ (match_operand:V8HI 1 "register_operand" "0,x")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
(ss_minus:HI
(vec_concat:V2HI
(ss_minus:HI
(vec_select:HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")
+ (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
(ss_minus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
"TARGET_SSSE3"
- "phsubsw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
+ "@
+ phsubsw\t{%2, %0|%0, %2}
+ vphsubsw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
- (set_attr "prefix_data16" "1")
+ (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "ssse3_phsubswv4hi3"
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
-(define_insn "*avx_pmaddubsw128"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (ss_plus:V8HI
- (mult:V8HI
- (zero_extend:V8HI
- (vec_select:V8QI
- (match_operand:V16QI 1 "register_operand" "x")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)
- (const_int 8)
- (const_int 10)
- (const_int 12)
- (const_int 14)])))
- (sign_extend:V8HI
- (vec_select:V8QI
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)
- (const_int 8)
- (const_int 10)
- (const_int 12)
- (const_int 14)]))))
- (mult:V8HI
- (zero_extend:V8HI
- (vec_select:V8QI (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)
- (const_int 9)
- (const_int 11)
- (const_int 13)
- (const_int 15)])))
- (sign_extend:V8HI
- (vec_select:V8QI (match_dup 2)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)
- (const_int 9)
- (const_int 11)
- (const_int 13)
- (const_int 15)]))))))]
- "TARGET_AVX"
- "vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "ssse3_pmaddubsw128"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
+ [(set (match_operand:V8HI 0 "register_operand" "=x,x")
(ss_plus:V8HI
(mult:V8HI
(zero_extend:V8HI
(vec_select:V8QI
- (match_operand:V16QI 1 "register_operand" "0")
+ (match_operand:V16QI 1 "register_operand" "0,x")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
(const_int 14)])))
(sign_extend:V8HI
(vec_select:V8QI
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")
+ (match_operand:V16QI 2 "nonimmediate_operand" "xm,xm")
(parallel [(const_int 0)
(const_int 2)
(const_int 4)
(const_int 13)
(const_int 15)]))))))]
"TARGET_SSSE3"
- "pmaddubsw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
+ "@
+ pmaddubsw\t{%2, %0|%0, %2}
+ vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
(set_attr "atom_unit" "simul")
- (set_attr "prefix_data16" "1")
+ (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "ssse3_pmaddubsw"
(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(const_int 1) (const_int 1)]))
- (const_int 1))))]
- "TARGET_SSSE3"
- "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
-
-(define_insn "*avx_pmulhrswv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (truncate:V8HI
- (lshiftrt:V8SI
- (plus:V8SI
- (lshiftrt:V8SI
- (mult:V8SI
- (sign_extend:V8SI
- (match_operand:V8HI 1 "nonimmediate_operand" "%x"))
- (sign_extend:V8SI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
- (const_int 14))
- (const_vector:V8HI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
- (const_int 1))))]
- "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
- "vpmulhrsw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseimul")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
+ (const_int 1))))]
+ "TARGET_SSSE3"
+ "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
(define_insn "*ssse3_pmulhrswv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
+ [(set (match_operand:V8HI 0 "register_operand" "=x,x")
(truncate:V8HI
(lshiftrt:V8SI
(plus:V8SI
(lshiftrt:V8SI
(mult:V8SI
(sign_extend:V8SI
- (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
+ (match_operand:V8HI 1 "nonimmediate_operand" "%0,x"))
(sign_extend:V8SI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
+ (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")))
(const_int 14))
(const_vector:V8HI [(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(const_int 1) (const_int 1)]))
(const_int 1))))]
"TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
- "pmulhrsw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseimul")
- (set_attr "prefix_data16" "1")
+ "@
+ pmulhrsw\t{%2, %0|%0, %2}
+ vpmulhrsw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseimul")
+ (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_expand "ssse3_pmulhrswv4hi3"
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
-(define_insn "*avx_pshufbv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
- UNSPEC_PSHUFB))]
- "TARGET_AVX"
- "vpshufb\t{%2, %1, %0|%0, %1, %2}";
- [(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "ssse3_pshufbv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
+ [(set (match_operand:V16QI 0 "register_operand" "=x,x")
+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0,x")
+ (match_operand:V16QI 2 "nonimmediate_operand" "xm,xm")]
UNSPEC_PSHUFB))]
"TARGET_SSSE3"
- "pshufb\t{%2, %0|%0, %2}";
- [(set_attr "type" "sselog1")
- (set_attr "prefix_data16" "1")
+ "@
+ pshufb\t{%2, %0|%0, %2}
+ vpshufb\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog1")
+ (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "ssse3_pshufbv8qi3"
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
-(define_insn "*avx_psign<mode>3"
- [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
- (unspec:SSEMODE124
- [(match_operand:SSEMODE124 1 "register_operand" "x")
- (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")]
- UNSPEC_PSIGN))]
- "TARGET_AVX"
- "vpsign<ssevecsize>\t{%2, %1, %0|%0, %1, %2}";
- [(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "ssse3_psign<mode>3"
- [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
- (unspec:SSEMODE124
- [(match_operand:SSEMODE124 1 "register_operand" "0")
- (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")]
+ [(set (match_operand:VI124_128 0 "register_operand" "=x,x")
+ (unspec:VI124_128
+ [(match_operand:VI124_128 1 "register_operand" "0,x")
+ (match_operand:VI124_128 2 "nonimmediate_operand" "xm,xm")]
UNSPEC_PSIGN))]
"TARGET_SSSE3"
- "psign<ssevecsize>\t{%2, %0|%0, %2}";
- [(set_attr "type" "sselog1")
- (set_attr "prefix_data16" "1")
+ "@
+ psign<ssemodesuffix>\t{%2, %0|%0, %2}
+ vpsign<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog1")
+ (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "ssse3_psign<mode>3"
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
-(define_insn "*avx_palignrti"
- [(set (match_operand:TI 0 "register_operand" "=x")
- (unspec:TI [(match_operand:TI 1 "register_operand" "x")
- (match_operand:TI 2 "nonimmediate_operand" "xm")
- (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
- UNSPEC_PALIGNR))]
- "TARGET_AVX"
-{
- operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
- return "vpalignr\t{%3, %2, %1, %0|%0, %1, %2, %3}";
-}
- [(set_attr "type" "sseishft")
- (set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "ssse3_palignrti"
- [(set (match_operand:TI 0 "register_operand" "=x")
- (unspec:TI [(match_operand:TI 1 "register_operand" "0")
- (match_operand:TI 2 "nonimmediate_operand" "xm")
- (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
+ [(set (match_operand:TI 0 "register_operand" "=x,x")
+ (unspec:TI [(match_operand:TI 1 "register_operand" "0,x")
+ (match_operand:TI 2 "nonimmediate_operand" "xm,xm")
+ (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n")]
UNSPEC_PALIGNR))]
"TARGET_SSSE3"
{
operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
- return "palignr\t{%3, %2, %0|%0, %2, %3}";
+
+ switch (which_alternative)
+ {
+ case 0:
+ return "palignr\t{%3, %2, %0|%0, %2, %3}";
+ case 1:
+ return "vpalignr\t{%3, %2, %1, %0|%0, %1, %2, %3}";
+ default:
+ gcc_unreachable ();
+ }
}
- [(set_attr "type" "sseishft")
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseishft")
(set_attr "atom_unit" "sishuf")
- (set_attr "prefix_data16" "1")
+ (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "ssse3_palignrdi"
(set_attr "mode" "DI")])
(define_insn "abs<mode>2"
- [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
- (abs:SSEMODE124 (match_operand:SSEMODE124 1 "nonimmediate_operand" "xm")))]
+ [(set (match_operand:VI124_128 0 "register_operand" "=x")
+ (abs:VI124_128
+ (match_operand:VI124_128 1 "nonimmediate_operand" "xm")))]
"TARGET_SSSE3"
- "%vpabs<ssevecsize>\t{%1, %0|%0, %1}"
+ "%vpabs<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "sselog1")
(set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(define_insn "abs<mode>2"
[(set (match_operand:MMXMODEI 0 "register_operand" "=y")
- (abs:MMXMODEI (match_operand:MMXMODEI 1 "nonimmediate_operand" "ym")))]
+ (abs:MMXMODEI
+ (match_operand:MMXMODEI 1 "nonimmediate_operand" "ym")))]
"TARGET_SSSE3"
"pabs<mmxvecsize>\t{%1, %0|%0, %1}";
[(set_attr "type" "sselog1")
[(match_operand:MODEF 1 "register_operand" "x")]
UNSPEC_MOVNT))]
"TARGET_SSE4A"
- "movnts<ssemodefsuffix>\t{%1, %0|%0, %1}"
+ "movnt<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "mode" "<MODE>")])
[(set (match_operand:<ssescalarmode> 0 "memory_operand" "=m")
(unspec:<ssescalarmode>
[(vec_select:<ssescalarmode>
- (match_operand:SSEMODEF2P 1 "register_operand" "x")
+ (match_operand:VF_128 1 "register_operand" "x")
(parallel [(const_int 0)]))]
UNSPEC_MOVNT))]
"TARGET_SSE4A"
(define_insn "sse4a_extrqi"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
- (match_operand 2 "const_int_operand" "")
- (match_operand 3 "const_int_operand" "")]
+ (match_operand 2 "const_0_to_255_operand" "")
+ (match_operand 3 "const_0_to_255_operand" "")]
UNSPEC_EXTRQI))]
"TARGET_SSE4A"
"extrq\t{%3, %2, %0|%0, %2, %3}"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
(match_operand:V2DI 2 "register_operand" "x")
- (match_operand 3 "const_int_operand" "")
- (match_operand 4 "const_int_operand" "")]
+ (match_operand 3 "const_0_to_255_operand" "")
+ (match_operand 4 "const_0_to_255_operand" "")]
UNSPEC_INSERTQI))]
"TARGET_SSE4A"
"insertq\t{%4, %3, %2, %0|%0, %2, %3, %4}"
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(define_insn "avx_blend<ssemodesuffix><avxmodesuffix>"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (vec_merge:AVXMODEF2P
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
- (match_operand:AVXMODEF2P 1 "register_operand" "x")
- (match_operand:SI 3 "const_0_to_<blendbits>_operand" "n")))]
- "TARGET_AVX"
- "vblend<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecmode>")])
-
-(define_insn "avx_blendv<ssemodesuffix><avxmodesuffix>"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "register_operand" "x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
- (match_operand:AVXMODEF2P 3 "register_operand" "x")]
- UNSPEC_BLENDV))]
- "TARGET_AVX"
- "vblendv<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecmode>")])
-
-(define_insn "sse4_1_blend<ssemodesuffix>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")
- (match_operand:SSEMODEF2P 1 "register_operand" "0")
- (match_operand:SI 3 "const_0_to_<blendbits>_operand" "n")))]
+(define_insn "<sse4_1>_blend<ssemodesuffix><avxsizesuffix>"
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
+ (vec_merge:VF
+ (match_operand:VF 2 "nonimmediate_operand" "xm,xm")
+ (match_operand:VF 1 "register_operand" "0,x")
+ (match_operand:SI 3 "const_0_to_<blendbits>_operand" "")))]
"TARGET_SSE4_1"
- "blend<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix_data16" "1")
- (set_attr "prefix_extra" "1")
+ "@
+ blend<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
+ vblend<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssemov")
(set_attr "length_immediate" "1")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")])
-(define_insn "sse4_1_blendv<ssemodesuffix>"
- [(set (match_operand:SSEMODEF2P 0 "reg_not_xmm0_operand" "=x")
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 1 "reg_not_xmm0_operand" "0")
- (match_operand:SSEMODEF2P 2 "nonimm_not_xmm0_operand" "xm")
- (match_operand:SSEMODEF2P 3 "register_operand" "Yz")]
+(define_insn "<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>"
+ [(set (match_operand:VF 0 "reg_not_xmm0_operand_maybe_avx" "=x,x")
+ (unspec:VF
+ [(match_operand:VF 1 "reg_not_xmm0_operand_maybe_avx" "0,x")
+ (match_operand:VF 2 "nonimm_not_xmm0_operand_maybe_avx" "xm,xm")
+ (match_operand:VF 3 "register_operand" "Yz,x")]
UNSPEC_BLENDV))]
"TARGET_SSE4_1"
- "blendv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix_data16" "1")
+ "@
+ blendv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
+ vblendv<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssemov")
+ (set_attr "length_immediate" "1")
+ (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")])
-(define_insn "avx_dp<ssemodesuffix><avxmodesuffix>"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
- (match_operand:SI 3 "const_0_to_255_operand" "n")]
- UNSPEC_DP))]
- "TARGET_AVX"
- "vdp<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemul")
- (set_attr "prefix" "vex")
- (set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "<avxvecmode>")])
-
-(define_insn "sse4_1_dp<ssemodesuffix>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")
- (match_operand:SI 3 "const_0_to_255_operand" "n")]
+(define_insn "<sse4_1>_dp<ssemodesuffix><avxsizesuffix>"
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
+ (unspec:VF
+ [(match_operand:VF 1 "nonimmediate_operand" "%0,x")
+ (match_operand:VF 2 "nonimmediate_operand" "xm,xm")
+ (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
UNSPEC_DP))]
"TARGET_SSE4_1"
- "dp<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "ssemul")
- (set_attr "prefix_data16" "1")
- (set_attr "prefix_extra" "1")
+ "@
+ dp<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
+ vdp<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssemul")
(set_attr "length_immediate" "1")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")])
(define_insn "sse4_1_movntdqa"
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
-(define_insn "*avx_mpsadbw"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")
- (match_operand:SI 3 "const_0_to_255_operand" "n")]
- UNSPEC_MPSADBW))]
- "TARGET_AVX"
- "vmpsadbw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "sselog1")
- (set_attr "prefix" "vex")
- (set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "TI")])
-
(define_insn "sse4_1_mpsadbw"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")
- (match_operand:SI 3 "const_0_to_255_operand" "n")]
+ [(set (match_operand:V16QI 0 "register_operand" "=x,x")
+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0,x")
+ (match_operand:V16QI 2 "nonimmediate_operand" "xm,xm")
+ (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
UNSPEC_MPSADBW))]
"TARGET_SSE4_1"
- "mpsadbw\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
+ "@
+ mpsadbw\t{%3, %2, %0|%0, %2, %3}
+ vmpsadbw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog1")
(set_attr "length_immediate" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_packusdw"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (vec_concat:V8HI
- (us_truncate:V4HI
- (match_operand:V4SI 1 "register_operand" "x"))
- (us_truncate:V4HI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
- "TARGET_AVX"
- "vpackusdw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog")
(set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "sse4_1_packusdw"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
+ [(set (match_operand:V8HI 0 "register_operand" "=x,x")
(vec_concat:V8HI
(us_truncate:V4HI
- (match_operand:V4SI 1 "register_operand" "0"))
+ (match_operand:V4SI 1 "register_operand" "0,x"))
(us_truncate:V4HI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
+ (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm"))))]
"TARGET_SSE4_1"
- "packusdw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_extra" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_pblendvb"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")
- (match_operand:V16QI 3 "register_operand" "x")]
- UNSPEC_BLENDV))]
- "TARGET_AVX"
- "vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemov")
+ "@
+ packusdw\t{%2, %0|%0, %2}
+ vpackusdw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
(set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "1")
- (set_attr "prefix" "vex")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "sse4_1_pblendvb"
- [(set (match_operand:V16QI 0 "reg_not_xmm0_operand" "=x")
- (unspec:V16QI [(match_operand:V16QI 1 "reg_not_xmm0_operand" "0")
- (match_operand:V16QI 2 "nonimm_not_xmm0_operand" "xm")
- (match_operand:V16QI 3 "register_operand" "Yz")]
- UNSPEC_BLENDV))]
+ [(set (match_operand:V16QI 0 "reg_not_xmm0_operand" "=x,x")
+ (unspec:V16QI
+ [(match_operand:V16QI 1 "reg_not_xmm0_operand_maybe_avx" "0,x")
+ (match_operand:V16QI 2 "nonimm_not_xmm0_operand_maybe_avx" "xm,xm")
+ (match_operand:V16QI 3 "register_operand" "Yz,x")]
+ UNSPEC_BLENDV))]
"TARGET_SSE4_1"
- "pblendvb\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix_extra" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_pblendw"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (vec_merge:V8HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")
- (match_operand:V8HI 1 "register_operand" "x")
- (match_operand:SI 3 "const_0_to_255_operand" "n")))]
- "TARGET_AVX"
- "vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix" "vex")
+ "@
+ pblendvb\t{%3, %2, %0|%0, %2, %3}
+ vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "1")
+ (set_attr "length_immediate" "*,1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "sse4_1_pblendw"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
+ [(set (match_operand:V8HI 0 "register_operand" "=x,x")
(vec_merge:V8HI
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")
- (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:SI 3 "const_0_to_255_operand" "n")))]
+ (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")
+ (match_operand:V8HI 1 "register_operand" "0,x")
+ (match_operand:SI 3 "const_0_to_255_operand" "n,n")))]
"TARGET_SSE4_1"
- "pblendw\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "ssemov")
+ "@
+ pblendw\t{%3, %2, %0|%0, %2, %3}
+ vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "sse4_1_phminposuw"
;; ptestps/ptestpd are very similar to comiss and ucomiss when
;; setting FLAGS_REG. But it is not a really compare instruction.
-(define_insn "avx_vtest<ssemodesuffix><avxmodesuffix>"
+(define_insn "avx_vtest<ssemodesuffix><avxsizesuffix>"
[(set (reg:CC FLAGS_REG)
- (unspec:CC [(match_operand:AVXMODEF2P 0 "register_operand" "x")
- (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm")]
+ (unspec:CC [(match_operand:VF 0 "register_operand" "x")
+ (match_operand:VF 1 "nonimmediate_operand" "xm")]
UNSPEC_VTESTP))]
"TARGET_AVX"
"vtest<ssemodesuffix>\t{%1, %0|%0, %1}"
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
-(define_insn "avx_round<ssemodesuffix>256"
- [(set (match_operand:AVX256MODEF2P 0 "register_operand" "=x")
- (unspec:AVX256MODEF2P
- [(match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "xm")
- (match_operand:SI 2 "const_0_to_15_operand" "n")]
- UNSPEC_ROUND))]
- "TARGET_AVX"
- "vround<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "sse4_1_round<ssemodesuffix>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm")
+(define_insn "<sse4_1>_round<ssemodesuffix><avxsizesuffix>"
+ [(set (match_operand:VF 0 "register_operand" "=x")
+ (unspec:VF
+ [(match_operand:VF 1 "nonimmediate_operand" "xm")
(match_operand:SI 2 "const_0_to_15_operand" "n")]
UNSPEC_ROUND))]
"TARGET_ROUND"
"%vround<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecvt")
- (set_attr "prefix_data16" "1")
+ (set (attr "prefix_data16")
+ (if_then_else
+ (ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (const_string "*")
+ (const_string "1")))
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "<MODE>")])
-(define_insn "*avx_round<ssescalarmodesuffix>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 2 "register_operand" "x")
- (match_operand:SI 3 "const_0_to_15_operand" "n")]
- UNSPEC_ROUND)
- (match_operand:SSEMODEF2P 1 "register_operand" "x")
- (const_int 1)))]
- "TARGET_AVX"
- "vround<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssecvt")
- (set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<MODE>")])
-
(define_insn "sse4_1_round<ssescalarmodesuffix>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 2 "register_operand" "x")
- (match_operand:SI 3 "const_0_to_15_operand" "n")]
+ [(set (match_operand:VF_128 0 "register_operand" "=x,x")
+ (vec_merge:VF_128
+ (unspec:VF_128
+ [(match_operand:VF_128 2 "register_operand" "x,x")
+ (match_operand:SI 3 "const_0_to_15_operand" "n,n")]
UNSPEC_ROUND)
- (match_operand:SSEMODEF2P 1 "register_operand" "0")
+ (match_operand:VF_128 1 "register_operand" "0,x")
(const_int 1)))]
"TARGET_ROUND"
- "round<ssescalarmodesuffix>\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "ssecvt")
- (set_attr "prefix_data16" "1")
- (set_attr "prefix_extra" "1")
+ "@
+ round<ssescalarmodesuffix>\t{%3, %2, %0|%0, %2, %3}
+ vround<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "ssecvt")
(set_attr "length_immediate" "1")
+ (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "<MODE>")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(set_attr "mode" "TI")])
;; XOP parallel XMM conditional moves
-(define_insn "xop_pcmov_<mode>"
- [(set (match_operand:SSEMODE 0 "register_operand" "=x,x")
- (if_then_else:SSEMODE
- (match_operand:SSEMODE 3 "nonimmediate_operand" "x,m")
- (match_operand:SSEMODE 1 "vector_move_operand" "x,x")
- (match_operand:SSEMODE 2 "vector_move_operand" "xm,x")))]
- "TARGET_XOP"
- "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "sse4arg")])
-
-(define_insn "xop_pcmov_<mode>256"
- [(set (match_operand:AVX256MODE 0 "register_operand" "=x,x")
- (if_then_else:AVX256MODE
- (match_operand:AVX256MODE 3 "nonimmediate_operand" "x,m")
- (match_operand:AVX256MODE 1 "vector_move_operand" "x,x")
- (match_operand:AVX256MODE 2 "vector_move_operand" "xm,x")))]
+(define_insn "xop_pcmov_<mode><avxsizesuffix>"
+ [(set (match_operand:V 0 "register_operand" "=x,x")
+ (if_then_else:V
+ (match_operand:V 3 "nonimmediate_operand" "x,m")
+ (match_operand:V 1 "vector_move_operand" "x,x")
+ (match_operand:V 2 "vector_move_operand" "xm,x")))]
"TARGET_XOP"
"vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "sse4arg")])
;; XOP packed rotate instructions
(define_expand "rotl<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "")
- (rotate:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "")
+ [(set (match_operand:VI_128 0 "register_operand" "")
+ (rotate:VI_128
+ (match_operand:VI_128 1 "nonimmediate_operand" "")
(match_operand:SI 2 "general_operand")))]
"TARGET_XOP"
{
})
(define_expand "rotr<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "")
- (rotatert:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "")
+ [(set (match_operand:VI_128 0 "register_operand" "")
+ (rotatert:VI_128
+ (match_operand:VI_128 1 "nonimmediate_operand" "")
(match_operand:SI 2 "general_operand")))]
"TARGET_XOP"
{
})
(define_insn "xop_rotl<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (rotate:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm")
+ [(set (match_operand:VI_128 0 "register_operand" "=x")
+ (rotate:VI_128
+ (match_operand:VI_128 1 "nonimmediate_operand" "xm")
(match_operand:SI 2 "const_0_to_<sserotatemax>_operand" "n")))]
"TARGET_XOP"
- "vprot<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
+ "vprot<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
(set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "xop_rotr<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (rotatert:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm")
+ [(set (match_operand:VI_128 0 "register_operand" "=x")
+ (rotatert:VI_128
+ (match_operand:VI_128 1 "nonimmediate_operand" "xm")
(match_operand:SI 2 "const_0_to_<sserotatemax>_operand" "n")))]
"TARGET_XOP"
{
operands[3] = GEN_INT ((<ssescalarnum> * 8) - INTVAL (operands[2]));
- return \"vprot<ssevecsize>\t{%3, %1, %0|%0, %1, %3}\";
+ return \"vprot<ssemodesuffix>\t{%3, %1, %0|%0, %1, %3}\";
}
[(set_attr "type" "sseishft")
(set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_expand "vrotr<mode>3"
- [(match_operand:SSEMODE1248 0 "register_operand" "")
- (match_operand:SSEMODE1248 1 "register_operand" "")
- (match_operand:SSEMODE1248 2 "register_operand" "")]
+ [(match_operand:VI_128 0 "register_operand" "")
+ (match_operand:VI_128 1 "register_operand" "")
+ (match_operand:VI_128 2 "register_operand" "")]
"TARGET_XOP"
{
rtx reg = gen_reg_rtx (<MODE>mode);
})
(define_expand "vrotl<mode>3"
- [(match_operand:SSEMODE1248 0 "register_operand" "")
- (match_operand:SSEMODE1248 1 "register_operand" "")
- (match_operand:SSEMODE1248 2 "register_operand" "")]
+ [(match_operand:VI_128 0 "register_operand" "")
+ (match_operand:VI_128 1 "register_operand" "")
+ (match_operand:VI_128 2 "register_operand" "")]
"TARGET_XOP"
{
emit_insn (gen_xop_vrotl<mode>3 (operands[0], operands[1], operands[2]));
})
(define_insn "xop_vrotl<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x,x")
- (if_then_else:SSEMODE1248
- (ge:SSEMODE1248
- (match_operand:SSEMODE1248 2 "nonimmediate_operand" "x,m")
+ [(set (match_operand:VI_128 0 "register_operand" "=x,x")
+ (if_then_else:VI_128
+ (ge:VI_128
+ (match_operand:VI_128 2 "nonimmediate_operand" "x,m")
(const_int 0))
- (rotate:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm,x")
+ (rotate:VI_128
+ (match_operand:VI_128 1 "nonimmediate_operand" "xm,x")
(match_dup 2))
- (rotatert:SSEMODE1248
+ (rotatert:VI_128
(match_dup 1)
- (neg:SSEMODE1248 (match_dup 2)))))]
+ (neg:VI_128 (match_dup 2)))))]
"TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "vprot<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
+ "vprot<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "0")
(set_attr "prefix_extra" "2")
;; XOP packed shift instructions.
;; FIXME: add V2DI back in
(define_expand "vlshr<mode>3"
- [(match_operand:SSEMODE124 0 "register_operand" "")
- (match_operand:SSEMODE124 1 "register_operand" "")
- (match_operand:SSEMODE124 2 "register_operand" "")]
+ [(match_operand:VI124_128 0 "register_operand" "")
+ (match_operand:VI124_128 1 "register_operand" "")
+ (match_operand:VI124_128 2 "register_operand" "")]
"TARGET_XOP"
{
rtx neg = gen_reg_rtx (<MODE>mode);
})
(define_expand "vashr<mode>3"
- [(match_operand:SSEMODE124 0 "register_operand" "")
- (match_operand:SSEMODE124 1 "register_operand" "")
- (match_operand:SSEMODE124 2 "register_operand" "")]
+ [(match_operand:VI124_128 0 "register_operand" "")
+ (match_operand:VI124_128 1 "register_operand" "")
+ (match_operand:VI124_128 2 "register_operand" "")]
"TARGET_XOP"
{
rtx neg = gen_reg_rtx (<MODE>mode);
})
(define_expand "vashl<mode>3"
- [(match_operand:SSEMODE124 0 "register_operand" "")
- (match_operand:SSEMODE124 1 "register_operand" "")
- (match_operand:SSEMODE124 2 "register_operand" "")]
+ [(match_operand:VI124_128 0 "register_operand" "")
+ (match_operand:VI124_128 1 "register_operand" "")
+ (match_operand:VI124_128 2 "register_operand" "")]
"TARGET_XOP"
{
emit_insn (gen_xop_ashl<mode>3 (operands[0], operands[1], operands[2]));
})
(define_insn "xop_ashl<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x,x")
- (if_then_else:SSEMODE1248
- (ge:SSEMODE1248
- (match_operand:SSEMODE1248 2 "nonimmediate_operand" "x,m")
+ [(set (match_operand:VI_128 0 "register_operand" "=x,x")
+ (if_then_else:VI_128
+ (ge:VI_128
+ (match_operand:VI_128 2 "nonimmediate_operand" "x,m")
(const_int 0))
- (ashift:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm,x")
+ (ashift:VI_128
+ (match_operand:VI_128 1 "nonimmediate_operand" "xm,x")
(match_dup 2))
- (ashiftrt:SSEMODE1248
+ (ashiftrt:VI_128
(match_dup 1)
- (neg:SSEMODE1248 (match_dup 2)))))]
+ (neg:VI_128 (match_dup 2)))))]
"TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "vpsha<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
+ "vpsha<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "0")
(set_attr "prefix_extra" "2")
(set_attr "mode" "TI")])
(define_insn "xop_lshl<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x,x")
- (if_then_else:SSEMODE1248
- (ge:SSEMODE1248
- (match_operand:SSEMODE1248 2 "nonimmediate_operand" "x,m")
+ [(set (match_operand:VI_128 0 "register_operand" "=x,x")
+ (if_then_else:VI_128
+ (ge:VI_128
+ (match_operand:VI_128 2 "nonimmediate_operand" "x,m")
(const_int 0))
- (ashift:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm,x")
+ (ashift:VI_128
+ (match_operand:VI_128 1 "nonimmediate_operand" "xm,x")
(match_dup 2))
- (lshiftrt:SSEMODE1248
+ (lshiftrt:VI_128
(match_dup 1)
- (neg:SSEMODE1248 (match_dup 2)))))]
+ (neg:VI_128 (match_dup 2)))))]
"TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "vpshl<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
+ "vpshl<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "0")
(set_attr "prefix_extra" "2")
;; scalar insns
(define_expand "xop_vmfrcz<mode>2"
- [(set (match_operand:SSEMODEF2P 0 "register_operand")
- (vec_merge:SSEMODEF2P
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 1 "nonimmediate_operand")]
+ [(set (match_operand:VF_128 0 "register_operand")
+ (vec_merge:VF_128
+ (unspec:VF_128
+ [(match_operand:VF_128 1 "nonimmediate_operand")]
UNSPEC_FRCZ)
(match_dup 3)
(const_int 1)))]
})
(define_insn "*xop_vmfrcz_<mode>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm")]
+ [(set (match_operand:VF_128 0 "register_operand" "=x")
+ (vec_merge:VF_128
+ (unspec:VF_128
+ [(match_operand:VF_128 1 "nonimmediate_operand" "xm")]
UNSPEC_FRCZ)
- (match_operand:SSEMODEF2P 2 "const0_operand")
+ (match_operand:VF_128 2 "const0_operand")
(const_int 1)))]
"TARGET_XOP"
"vfrcz<ssescalarmodesuffix>\t{%1, %0|%0, %1}"
(set_attr "mode" "<MODE>")])
(define_insn "xop_maskcmp<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (match_operator:SSEMODE1248 1 "ix86_comparison_int_operator"
- [(match_operand:SSEMODE1248 2 "register_operand" "x")
- (match_operand:SSEMODE1248 3 "nonimmediate_operand" "xm")]))]
+ [(set (match_operand:VI_128 0 "register_operand" "=x")
+ (match_operator:VI_128 1 "ix86_comparison_int_operator"
+ [(match_operand:VI_128 2 "register_operand" "x")
+ (match_operand:VI_128 3 "nonimmediate_operand" "xm")]))]
"TARGET_XOP"
- "vpcom%Y1<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
+ "vpcom%Y1<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sse4arg")
(set_attr "prefix_data16" "0")
(set_attr "prefix_rep" "0")
(set_attr "mode" "TI")])
(define_insn "xop_maskcmp_uns<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (match_operator:SSEMODE1248 1 "ix86_comparison_uns_operator"
- [(match_operand:SSEMODE1248 2 "register_operand" "x")
- (match_operand:SSEMODE1248 3 "nonimmediate_operand" "xm")]))]
+ [(set (match_operand:VI_128 0 "register_operand" "=x")
+ (match_operator:VI_128 1 "ix86_comparison_uns_operator"
+ [(match_operand:VI_128 2 "register_operand" "x")
+ (match_operand:VI_128 3 "nonimmediate_operand" "xm")]))]
"TARGET_XOP"
- "vpcom%Y1u<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
+ "vpcom%Y1u<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssecmp")
(set_attr "prefix_data16" "0")
(set_attr "prefix_rep" "0")
;; and pcomneu* not to be converted to the signed ones in case somebody needs
;; the exact instruction generated for the intrinsic.
(define_insn "xop_maskcmp_uns2<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (unspec:SSEMODE1248
- [(match_operator:SSEMODE1248 1 "ix86_comparison_uns_operator"
- [(match_operand:SSEMODE1248 2 "register_operand" "x")
- (match_operand:SSEMODE1248 3 "nonimmediate_operand" "xm")])]
+ [(set (match_operand:VI_128 0 "register_operand" "=x")
+ (unspec:VI_128
+ [(match_operator:VI_128 1 "ix86_comparison_uns_operator"
+ [(match_operand:VI_128 2 "register_operand" "x")
+ (match_operand:VI_128 3 "nonimmediate_operand" "xm")])]
UNSPEC_XOP_UNSIGNED_CMP))]
"TARGET_XOP"
- "vpcom%Y1u<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
+ "vpcom%Y1u<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssecmp")
(set_attr "prefix_data16" "0")
(set_attr "prefix_extra" "2")
;; Pcomtrue and pcomfalse support. These are useless instructions, but are
;; being added here to be complete.
(define_insn "xop_pcom_tf<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (unspec:SSEMODE1248
- [(match_operand:SSEMODE1248 1 "register_operand" "x")
- (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm")
+ [(set (match_operand:VI_128 0 "register_operand" "=x")
+ (unspec:VI_128
+ [(match_operand:VI_128 1 "register_operand" "x")
+ (match_operand:VI_128 2 "nonimmediate_operand" "xm")
(match_operand:SI 3 "const_int_operand" "n")]
UNSPEC_XOP_TRUEFALSE))]
"TARGET_XOP"
{
return ((INTVAL (operands[3]) != 0)
- ? "vpcomtrue<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
- : "vpcomfalse<ssevecsize>\t{%2, %1, %0|%0, %1, %2}");
+ ? "vpcomtrue<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ : "vpcomfalse<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}");
}
[(set_attr "type" "ssecmp")
(set_attr "prefix_data16" "0")
(set_attr "mode" "TI")])
(define_insn "xop_vpermil2<mode>3"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "register_operand" "x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "%x")
- (match_operand:<avxpermvecmode> 3 "nonimmediate_operand" "xm")
+ [(set (match_operand:VF 0 "register_operand" "=x")
+ (unspec:VF
+ [(match_operand:VF 1 "register_operand" "x")
+ (match_operand:VF 2 "nonimmediate_operand" "%x")
+ (match_operand:<sseintvecmode> 3 "nonimmediate_operand" "xm")
(match_operand:SI 4 "const_0_to_3_operand" "n")]
UNSPEC_VPERMIL2))]
"TARGET_XOP"
(set_attr "mode" "<MODE>")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(define_insn "*avx_aesenc"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
- UNSPEC_AESENC))]
- "TARGET_AES && TARGET_AVX"
- "vaesenc\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
(define_insn "aesenc"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
+ [(set (match_operand:V2DI 0 "register_operand" "=x,x")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x")
+ (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")]
UNSPEC_AESENC))]
"TARGET_AES"
- "aesenc\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_aesenclast"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
- UNSPEC_AESENCLAST))]
- "TARGET_AES && TARGET_AVX"
- "vaesenclast\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog1")
+ "@
+ aesenc\t{%2, %0|%0, %2}
+ vaesenc\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "aesenclast"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
+ [(set (match_operand:V2DI 0 "register_operand" "=x,x")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x")
+ (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")]
UNSPEC_AESENCLAST))]
"TARGET_AES"
- "aesenclast\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_aesdec"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
- UNSPEC_AESDEC))]
- "TARGET_AES && TARGET_AVX"
- "vaesdec\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog1")
+ "@
+ aesenclast\t{%2, %0|%0, %2}
+ vaesenclast\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "aesdec"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
+ [(set (match_operand:V2DI 0 "register_operand" "=x,x")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x")
+ (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")]
UNSPEC_AESDEC))]
"TARGET_AES"
- "aesdec\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*avx_aesdeclast"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
- UNSPEC_AESDECLAST))]
- "TARGET_AES && TARGET_AVX"
- "vaesdeclast\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog1")
+ "@
+ aesdec\t{%2, %0|%0, %2}
+ vaesdec\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "aesdeclast"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
+ [(set (match_operand:V2DI 0 "register_operand" "=x,x")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x")
+ (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")]
UNSPEC_AESDECLAST))]
"TARGET_AES"
- "aesdeclast\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog1")
+ "@
+ aesdeclast\t{%2, %0|%0, %2}
+ vaesdeclast\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "aesimc"
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
-(define_insn "*vpclmulqdq"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")
- (match_operand:SI 3 "const_0_to_255_operand" "n")]
- UNSPEC_PCLMUL))]
- "TARGET_PCLMUL && TARGET_AVX"
- "vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "TI")])
-
(define_insn "pclmulqdq"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")
- (match_operand:SI 3 "const_0_to_255_operand" "n")]
+ [(set (match_operand:V2DI 0 "register_operand" "=x,x")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x")
+ (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")
+ (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
UNSPEC_PCLMUL))]
"TARGET_PCLMUL"
- "pclmulqdq\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "sselog1")
+ "@
+ pclmulqdq\t{%3, %2, %0|%0, %2, %3}
+ vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
+ (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_expand "avx_vzeroall"
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
-(define_insn_and_split "vec_dup<mode>"
- [(set (match_operand:AVX256MODE24P 0 "register_operand" "=x,x")
- (vec_duplicate:AVX256MODE24P
- (match_operand:<avxscalarmode> 1 "nonimmediate_operand" "m,?x")))]
+;; Modes handled by AVX vec_dup patterns.
+(define_mode_iterator AVX_VEC_DUP_MODE
+ [V8SI V8SF V4DI V4DF])
+
+(define_insn "vec_dup<mode>"
+ [(set (match_operand:AVX_VEC_DUP_MODE 0 "register_operand" "=x,x")
+ (vec_duplicate:AVX_VEC_DUP_MODE
+ (match_operand:<ssescalarmode> 1 "nonimmediate_operand" "m,?x")))]
"TARGET_AVX"
"@
vbroadcast<ssescalarmodesuffix>\t{%1, %0|%0, %1}
#"
- "&& reload_completed && REG_P (operands[1])"
- [(set (match_dup 2) (vec_duplicate:<avxhalfvecmode> (match_dup 1)))
- (set (match_dup 0) (vec_concat:AVX256MODE24P (match_dup 2) (match_dup 2)))]
- "operands[2] = gen_rtx_REG (<avxhalfvecmode>mode, REGNO (operands[0]));"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
+(define_split
+ [(set (match_operand:AVX_VEC_DUP_MODE 0 "register_operand" "")
+ (vec_duplicate:AVX_VEC_DUP_MODE
+ (match_operand:<ssescalarmode> 1 "register_operand" "")))]
+ "TARGET_AVX && reload_completed"
+ [(set (match_dup 2)
+ (vec_duplicate:<ssehalfvecmode> (match_dup 1)))
+ (set (match_dup 0)
+ (vec_concat:AVX_VEC_DUP_MODE (match_dup 2) (match_dup 2)))]
+ "operands[2] = gen_rtx_REG (<ssehalfvecmode>mode, REGNO (operands[0]));")
+
(define_insn "avx_vbroadcastf128_<mode>"
- [(set (match_operand:AVX256MODE 0 "register_operand" "=x,x,x")
- (vec_concat:AVX256MODE
- (match_operand:<avxhalfvecmode> 1 "nonimmediate_operand" "m,0,?x")
+ [(set (match_operand:V_256 0 "register_operand" "=x,x,x")
+ (vec_concat:V_256
+ (match_operand:<ssehalfvecmode> 1 "nonimmediate_operand" "m,0,?x")
(match_dup 1)))]
"TARGET_AVX"
"@
(set_attr "mode" "SF,SF,V4SF")])
(define_insn_and_split "*avx_vperm_broadcast_<mode>"
- [(set (match_operand:AVX256MODEF2P 0 "register_operand" "=x,x,x")
- (vec_select:AVX256MODEF2P
- (match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "m,o,?x")
+ [(set (match_operand:VF_256 0 "register_operand" "=x,x,x")
+ (vec_select:VF_256
+ (match_operand:VF_256 1 "nonimmediate_operand" "m,o,?x")
(match_parallel 2 "avx_vbroadcast_operand"
[(match_operand 3 "const_int_operand" "C,n,n")])))]
"TARGET_AVX"
"#"
"&& reload_completed"
- [(set (match_dup 0) (vec_duplicate:AVX256MODEF2P (match_dup 1)))]
+ [(set (match_dup 0) (vec_duplicate:VF_256 (match_dup 1)))]
{
rtx op0 = operands[0], op1 = operands[1];
int elt = INTVAL (operands[3]);
DONE;
}
- operands[1] = adjust_address_nv (op1, <avxscalarmode>mode,
- elt * GET_MODE_SIZE (<avxscalarmode>mode));
+ operands[1] = adjust_address_nv (op1, <ssescalarmode>mode,
+ elt * GET_MODE_SIZE (<ssescalarmode>mode));
})
(define_expand "avx_vpermil<mode>"
- [(set (match_operand:AVXMODEFDP 0 "register_operand" "")
- (vec_select:AVXMODEFDP
- (match_operand:AVXMODEFDP 1 "nonimmediate_operand" "")
+ [(set (match_operand:VF2 0 "register_operand" "")
+ (vec_select:VF2
+ (match_operand:VF2 1 "nonimmediate_operand" "")
(match_operand:SI 2 "const_0_to_255_operand" "")))]
"TARGET_AVX"
{
})
(define_expand "avx_vpermil<mode>"
- [(set (match_operand:AVXMODEFSP 0 "register_operand" "")
- (vec_select:AVXMODEFSP
- (match_operand:AVXMODEFSP 1 "nonimmediate_operand" "")
+ [(set (match_operand:VF1 0 "register_operand" "")
+ (vec_select:VF1
+ (match_operand:VF1 1 "nonimmediate_operand" "")
(match_operand:SI 2 "const_0_to_255_operand" "")))]
"TARGET_AVX"
{
})
(define_insn "*avx_vpermilp<mode>"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (vec_select:AVXMODEF2P
- (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm")
- (match_parallel 2 "avx_vpermilp_<mode>_operand"
+ [(set (match_operand:VF 0 "register_operand" "=x")
+ (vec_select:VF
+ (match_operand:VF 1 "nonimmediate_operand" "xm")
+ (match_parallel 2 ""
[(match_operand 3 "const_int_operand" "")])))]
- "TARGET_AVX"
+ "TARGET_AVX
+ && avx_vpermilp_parallel (operands[2], <MODE>mode)"
{
int mask = avx_vpermilp_parallel (operands[2], <MODE>mode) - 1;
operands[2] = GEN_INT (mask);
(set_attr "mode" "<MODE>")])
(define_insn "avx_vpermilvar<mode>3"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "register_operand" "x")
- (match_operand:<avxpermvecmode> 2 "nonimmediate_operand" "xm")]
+ [(set (match_operand:VF 0 "register_operand" "=x")
+ (unspec:VF
+ [(match_operand:VF 1 "register_operand" "x")
+ (match_operand:<sseintvecmode> 2 "nonimmediate_operand" "xm")]
UNSPEC_VPERMIL))]
"TARGET_AVX"
"vpermil<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
for (i = 0; i < nelt2; ++i)
perm[i + nelt2] = GEN_INT (base + i);
- t2 = gen_rtx_VEC_CONCAT (<ssedoublesizemode>mode,
+ t2 = gen_rtx_VEC_CONCAT (<ssedoublevecmode>mode,
operands[1], operands[2]);
t1 = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, perm));
t2 = gen_rtx_VEC_SELECT (<MODE>mode, t2, t1);
(define_insn "*avx_vperm2f128<mode>_nozero"
[(set (match_operand:AVX256MODE2P 0 "register_operand" "=x")
(vec_select:AVX256MODE2P
- (vec_concat:<ssedoublesizemode>
+ (vec_concat:<ssedoublevecmode>
(match_operand:AVX256MODE2P 1 "register_operand" "x")
(match_operand:AVX256MODE2P 2 "nonimmediate_operand" "xm"))
- (match_parallel 3 "avx_vperm2f128_<mode>_operand"
+ (match_parallel 3 ""
[(match_operand 4 "const_int_operand" "")])))]
- "TARGET_AVX"
+ "TARGET_AVX
+ && avx_vperm2f128_parallel (operands[3], <MODE>mode)"
{
int mask = avx_vperm2f128_parallel (operands[3], <MODE>mode) - 1;
operands[3] = GEN_INT (mask);
(set_attr "mode" "V8SF")])
(define_expand "avx_vinsertf128<mode>"
- [(match_operand:AVX256MODE 0 "register_operand" "")
- (match_operand:AVX256MODE 1 "register_operand" "")
- (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "")
+ [(match_operand:V_256 0 "register_operand" "")
+ (match_operand:V_256 1 "register_operand" "")
+ (match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" "")
(match_operand:SI 3 "const_0_to_1_operand" "")]
"TARGET_AVX"
{
})
(define_insn "vec_set_lo_<mode>"
- [(set (match_operand:AVX256MODE4P 0 "register_operand" "=x")
- (vec_concat:AVX256MODE4P
- (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "xm")
- (vec_select:<avxhalfvecmode>
- (match_operand:AVX256MODE4P 1 "register_operand" "x")
+ [(set (match_operand:VI8F_256 0 "register_operand" "=x")
+ (vec_concat:VI8F_256
+ (match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" "xm")
+ (vec_select:<ssehalfvecmode>
+ (match_operand:VI8F_256 1 "register_operand" "x")
(parallel [(const_int 2) (const_int 3)]))))]
"TARGET_AVX"
"vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
(set_attr "mode" "V8SF")])
(define_insn "vec_set_hi_<mode>"
- [(set (match_operand:AVX256MODE4P 0 "register_operand" "=x")
- (vec_concat:AVX256MODE4P
- (vec_select:<avxhalfvecmode>
- (match_operand:AVX256MODE4P 1 "register_operand" "x")
+ [(set (match_operand:VI8F_256 0 "register_operand" "=x")
+ (vec_concat:VI8F_256
+ (vec_select:<ssehalfvecmode>
+ (match_operand:VI8F_256 1 "register_operand" "x")
(parallel [(const_int 0) (const_int 1)]))
- (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "xm")))]
+ (match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" "xm")))]
"TARGET_AVX"
"vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
[(set_attr "type" "sselog")
(set_attr "mode" "V8SF")])
(define_insn "vec_set_lo_<mode>"
- [(set (match_operand:AVX256MODE8P 0 "register_operand" "=x")
- (vec_concat:AVX256MODE8P
- (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "xm")
- (vec_select:<avxhalfvecmode>
- (match_operand:AVX256MODE8P 1 "register_operand" "x")
+ [(set (match_operand:VI4F_256 0 "register_operand" "=x")
+ (vec_concat:VI4F_256
+ (match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" "xm")
+ (vec_select:<ssehalfvecmode>
+ (match_operand:VI4F_256 1 "register_operand" "x")
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)]))))]
"TARGET_AVX"
(set_attr "mode" "V8SF")])
(define_insn "vec_set_hi_<mode>"
- [(set (match_operand:AVX256MODE8P 0 "register_operand" "=x")
- (vec_concat:AVX256MODE8P
- (vec_select:<avxhalfvecmode>
- (match_operand:AVX256MODE8P 1 "register_operand" "x")
+ [(set (match_operand:VI4F_256 0 "register_operand" "=x")
+ (vec_concat:VI4F_256
+ (vec_select:<ssehalfvecmode>
+ (match_operand:VI4F_256 1 "register_operand" "x")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)]))
- (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "xm")))]
+ (match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" "xm")))]
"TARGET_AVX"
"vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
-(define_insn "avx_maskload<ssemodesuffix><avxmodesuffix>"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "memory_operand" "m")
- (match_operand:<avxpermvecmode> 2 "register_operand" "x")
+(define_expand "avx_maskload<ssemodesuffix><avxsizesuffix>"
+ [(set (match_operand:VF 0 "register_operand" "")
+ (unspec:VF
+ [(match_operand:<sseintvecmode> 2 "register_operand" "")
+ (match_operand:VF 1 "memory_operand" "")
(match_dup 0)]
- UNSPEC_MASKLOAD))]
- "TARGET_AVX"
- "vmaskmov<ssemodesuffix>\t{%1, %2, %0|%0, %2, %1}"
- [(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<MODE>")])
+ UNSPEC_MASKMOV))]
+ "TARGET_AVX")
-(define_insn "avx_maskstore<ssemodesuffix><avxmodesuffix>"
- [(set (match_operand:AVXMODEF2P 0 "memory_operand" "=m")
- (unspec:AVXMODEF2P
- [(match_operand:<avxpermvecmode> 1 "register_operand" "x")
- (match_operand:AVXMODEF2P 2 "register_operand" "x")
+(define_expand "avx_maskstore<ssemodesuffix><avxsizesuffix>"
+ [(set (match_operand:VF 0 "memory_operand" "")
+ (unspec:VF
+ [(match_operand:<sseintvecmode> 1 "register_operand" "")
+ (match_operand:VF 2 "register_operand" "")
(match_dup 0)]
- UNSPEC_MASKSTORE))]
- "TARGET_AVX"
+ UNSPEC_MASKMOV))]
+ "TARGET_AVX")
+
+(define_insn "*avx_maskmov<ssemodesuffix><avxsizesuffix>"
+ [(set (match_operand:VF 0 "nonimmediate_operand" "=x,m")
+ (unspec:VF
+ [(match_operand:<sseintvecmode> 1 "register_operand" "x,x")
+ (match_operand:VF 2 "nonimmediate_operand" "m,x")
+ (match_dup 0)]
+ UNSPEC_MASKMOV))]
+ "TARGET_AVX
+ && (REG_P (operands[0]) == MEM_P (operands[2]))"
"vmaskmov<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
-(define_insn_and_split "avx_<avxmodesuffixp><avxmodesuffix>_<avxmodesuffixp>"
+(define_insn_and_split "avx_<castmode><avxsizesuffix>_<castmode>"
[(set (match_operand:AVX256MODE2P 0 "nonimmediate_operand" "=x,m")
(unspec:AVX256MODE2P
- [(match_operand:<avxhalfvecmode> 1 "nonimmediate_operand" "xm,x")]
+ [(match_operand:<ssehalfvecmode> 1 "nonimmediate_operand" "xm,x")]
UNSPEC_CAST))]
"TARGET_AVX"
"#"
"&& reload_completed"
[(const_int 0)]
{
+ rtx op0 = operands[0];
rtx op1 = operands[1];
- if (REG_P (op1))
- op1 = gen_rtx_REG (<MODE>mode, REGNO (op1));
+ if (REG_P (op0))
+ op0 = gen_rtx_REG (<ssehalfvecmode>mode, REGNO (op0));
else
- op1 = gen_lowpart (<MODE>mode, op1);
- emit_move_insn (operands[0], op1);
+ op1 = gen_rtx_REG (<MODE>mode, REGNO (op1));
+ emit_move_insn (op0, op1);
DONE;
})
(define_expand "vec_init<mode>"
- [(match_operand:AVX256MODE 0 "register_operand" "")
+ [(match_operand:V_256 0 "register_operand" "")
(match_operand 1 "" "")]
"TARGET_AVX"
{
})
(define_insn "*vec_concat<mode>_avx"
- [(set (match_operand:AVX256MODE 0 "register_operand" "=x,x")
- (vec_concat:AVX256MODE
- (match_operand:<avxhalfvecmode> 1 "register_operand" "x,x")
- (match_operand:<avxhalfvecmode> 2 "vector_move_operand" "xm,C")))]
+ [(set (match_operand:V_256 0 "register_operand" "=x,x")
+ (vec_concat:V_256
+ (match_operand:<ssehalfvecmode> 1 "register_operand" "x,x")
+ (match_operand:<ssehalfvecmode> 2 "vector_move_operand" "xm,C")))]
"TARGET_AVX"
{
switch (which_alternative)
(set_attr "prefix_extra" "1,*")
(set_attr "length_immediate" "1,*")
(set_attr "prefix" "vex")
- (set_attr "mode" "<avxvecmode>")])
+ (set_attr "mode" "<sseinsnmode>")])
(define_insn "vcvtph2ps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
[(set (match_operand:V8HI 0 "register_operand" "")
(vec_concat:V8HI
(unspec:V4HI [(match_operand:V4SF 1 "register_operand" "")
- (match_operand:SI 2 "immediate_operand" "")]
+ (match_operand:SI 2 "const_0_to_255_operand" "")]
UNSPEC_VCVTPS2PH)
(match_dup 3)))]
"TARGET_F16C"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(vec_concat:V8HI
(unspec:V4HI [(match_operand:V4SF 1 "register_operand" "x")
- (match_operand:SI 2 "immediate_operand" "N")]
+ (match_operand:SI 2 "const_0_to_255_operand" "N")]
UNSPEC_VCVTPS2PH)
(match_operand:V4HI 3 "const0_operand" "")))]
"TARGET_F16C"
(define_insn "*vcvtps2ph_store"
[(set (match_operand:V4HI 0 "memory_operand" "=m")
(unspec:V4HI [(match_operand:V4SF 1 "register_operand" "x")
- (match_operand:SI 2 "immediate_operand" "N")]
+ (match_operand:SI 2 "const_0_to_255_operand" "N")]
UNSPEC_VCVTPS2PH))]
"TARGET_F16C"
"vcvtps2ph\t{%2, %1, %0|%0, %1, %2}"
(define_insn "vcvtps2ph256"
[(set (match_operand:V8HI 0 "nonimmediate_operand" "=xm")
(unspec:V8HI [(match_operand:V8SF 1 "register_operand" "x")
- (match_operand:SI 2 "immediate_operand" "N")]
+ (match_operand:SI 2 "const_0_to_255_operand" "N")]
UNSPEC_VCVTPS2PH))]
"TARGET_F16C"
"vcvtps2ph\t{%2, %1, %0|%0, %1, %2}"
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