2008-05-21 H.J. Lu <hongjiu.lu@intel.com>

[pf3gnuchains/gcc-fork.git] / gcc / config / i386 / sse.md

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 5f0f9d3..b2aba51 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -2260,10 +2260,10 @@
 ;; Although insertps takes register source, we prefer
 ;; unpcklps with register source since it is shorter.
 (define_insn "*vec_concatv2sf_sse4_1"
-  [(set (match_operand:V2SF 0 "register_operand"     "=x,x,x,*y,*y")
+  [(set (match_operand:V2SF 0 "register_operand"     "=x,x,x,*y ,*y")
        (vec_concat:V2SF
-         (match_operand:SF 1 "nonimmediate_operand" " 0,0,m, 0, m")
-         (match_operand:SF 2 "vector_move_operand"  " x,m,C,*y, C")))]
+         (match_operand:SF 1 "nonimmediate_operand" " 0,0,m, 0 , m")
+         (match_operand:SF 2 "vector_move_operand"  " x,m,C,*ym, C")))]
   "TARGET_SSE4_1"
   "@
    unpcklps\t{%2, %0|%0, %2}
@@ -2304,8 +2304,8 @@
   [(set_attr "type" "ssemov")
    (set_attr "mode" "V4SF,V2SF")])
 
-(define_expand "vec_initv4sf"
-  [(match_operand:V4SF 0 "register_operand" "")
+(define_expand "vec_init<mode>"
+  [(match_operand:SSEMODE 0 "register_operand" "")
    (match_operand 1 "" "")]
   "TARGET_SSE"
 {
@@ -2808,15 +2808,6 @@
   DONE;
 })
 
-(define_expand "vec_initv2df"
-  [(match_operand:V2DF 0 "register_operand" "")
-   (match_operand 1 "" "")]
-  "TARGET_SSE"
-{
-  ix86_expand_vector_init (false, operands[0], operands[1]);
-  DONE;
-})
-
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Parallel integral arithmetic
@@ -4952,15 +4943,6 @@
   DONE;
 })
 
-(define_expand "vec_initv2di"
-  [(match_operand:V2DI 0 "register_operand" "")
-   (match_operand 1 "" "")]
-  "TARGET_SSE"
-{
-  ix86_expand_vector_init (false, operands[0], operands[1]);
-  DONE;
-})
-
 (define_expand "vec_setv4si"
   [(match_operand:V4SI 0 "register_operand" "")
    (match_operand:SI 1 "register_operand" "")
@@ -4983,15 +4965,6 @@
   DONE;
 })
 
-(define_expand "vec_initv4si"
-  [(match_operand:V4SI 0 "register_operand" "")
-   (match_operand 1 "" "")]
-  "TARGET_SSE"
-{
-  ix86_expand_vector_init (false, operands[0], operands[1]);
-  DONE;
-})
-
 (define_expand "vec_setv8hi"
   [(match_operand:V8HI 0 "register_operand" "")
    (match_operand:HI 1 "register_operand" "")
@@ -5014,15 +4987,6 @@
   DONE;
 })
 
-(define_expand "vec_initv8hi"
-  [(match_operand:V8HI 0 "register_operand" "")
-   (match_operand 1 "" "")]
-  "TARGET_SSE"
-{
-  ix86_expand_vector_init (false, operands[0], operands[1]);
-  DONE;
-})
-
 (define_expand "vec_setv16qi"
   [(match_operand:V16QI 0 "register_operand" "")
    (match_operand:QI 1 "register_operand" "")
@@ -5045,15 +5009,6 @@
   DONE;
 })
 
-(define_expand "vec_initv16qi"
-  [(match_operand:V16QI 0 "register_operand" "")
-   (match_operand 1 "" "")]
-  "TARGET_SSE"
-{
-  ix86_expand_vector_init (false, operands[0], operands[1]);
-  DONE;
-})
-
 (define_expand "vec_unpacku_hi_v16qi"
   [(match_operand:V8HI 0 "register_operand" "")
    (match_operand:V16QI 1 "register_operand" "")]