(match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
"AVX_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "v<maxminfprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
+ "v<maxmin_float>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseadd")
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<maxminfprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
+ "<maxmin_float>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")])
(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
(match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
"AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
- "v<maxminfprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
+ "v<maxmin_float>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseadd")
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecmode>")])
(match_operand:SSEMODEF2P 1 "register_operand" "0")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "<maxminfprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
+ "<maxmin_float>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")])
(match_dup 1)
(const_int 1)))]
"AVX128_VEC_FLOAT_MODE_P (<MODE>mode)"
- "v<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
+ "v<maxmin_float>s<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sse")
(set_attr "prefix" "vex")
(set_attr "mode" "<ssescalarmode>")])
(match_dup 1)
(const_int 1)))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
- "<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
+ "<maxmin_float>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "<ssescalarmode>")])
(set_attr "mode" "<MODE>")])
(define_expand "vcond<mode>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (if_then_else:SSEMODEF2P
+ [(set (match_operand:AVXMODEF2P 0 "register_operand" "")
+ (if_then_else:AVXMODEF2P
(match_operator 3 ""
- [(match_operand:SSEMODEF2P 4 "nonimmediate_operand" "")
- (match_operand:SSEMODEF2P 5 "nonimmediate_operand" "")])
- (match_operand:SSEMODEF2P 1 "general_operand" "")
- (match_operand:SSEMODEF2P 2 "general_operand" "")))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
+ [(match_operand:AVXMODEF2P 4 "nonimmediate_operand" "")
+ (match_operand:AVXMODEF2P 5 "nonimmediate_operand" "")])
+ (match_operand:AVXMODEF2P 1 "general_operand" "")
+ (match_operand:AVXMODEF2P 2 "general_operand" "")))]
+ "(SSE_VEC_FLOAT_MODE_P (<MODE>mode)
+ || AVX_VEC_FLOAT_MODE_P (<MODE>mode))"
{
bool ok = ix86_expand_fp_vcond (operands);
gcc_assert (ok);
(match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
"AVX_VEC_FLOAT_MODE_P (<MODE>mode)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "v<logicprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
+ "v<logic>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecmode>")])
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<logicprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
+ "<logic>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "<MODE>")])
(match_operand:MODEF 1 "register_operand" "x")
(match_operand:MODEF 2 "register_operand" "x")))]
"AVX_FLOAT_MODE_P (<MODE>mode)"
- "v<logicprefix>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
+ "v<logic>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "<ssevecmode>")])
(match_operand:MODEF 1 "register_operand" "0")
(match_operand:MODEF 2 "register_operand" "x")))]
"SSE_FLOAT_MODE_P (<MODE>mode)"
- "<logicprefix>p<ssemodefsuffix>\t{%2, %0|%0, %2}"
+ "<logic>p<ssemodefsuffix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "<ssevecmode>")])
(match_operand:SSEMODE124 1 "nonimmediate_operand" "%x")
(match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
"TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "vp<maxminiprefix><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
+ "vp<maxmin_int><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
(set (attr "prefix_extra")
(if_then_else
(match_operand:V16QI 1 "nonimmediate_operand" "%0")
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)"
- "p<maxminiprefix>b\t{%2, %0|%0, %2}"
+ "p<maxmin_int>b\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(match_operand:V8HI 1 "nonimmediate_operand" "%0")
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)"
- "p<maxminiprefix>w\t{%2, %0|%0, %2}"
+ "p<maxmin_int>w\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(match_operand:SSEMODE14 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODE14 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "p<maxminiprefix><ssevecsize>\t{%2, %0|%0, %2}"
+ "p<maxmin_int><ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
+(define_expand "smaxv2di3"
+ [(set (match_operand:V2DI 0 "register_operand" "")
+ (smax:V2DI (match_operand:V2DI 1 "register_operand" "")
+ (match_operand:V2DI 2 "register_operand" "")))]
+ "TARGET_SSE4_2"
+{
+ rtx xops[6];
+ bool ok;
+
+ xops[0] = operands[0];
+ xops[1] = operands[1];
+ xops[2] = operands[2];
+ xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
+ xops[4] = operands[1];
+ xops[5] = operands[2];
+ ok = ix86_expand_int_vcond (xops);
+ gcc_assert (ok);
+ DONE;
+})
+
(define_expand "umaxv4si3"
[(set (match_operand:V4SI 0 "register_operand" "")
(umax:V4SI (match_operand:V4SI 1 "register_operand" "")
(match_operand:SSEMODE24 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODE24 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "p<maxminiprefix><ssevecsize>\t{%2, %0|%0, %2}"
+ "p<maxmin_int><ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
+(define_expand "umaxv2di3"
+ [(set (match_operand:V2DI 0 "register_operand" "")
+ (umax:V2DI (match_operand:V2DI 1 "register_operand" "")
+ (match_operand:V2DI 2 "register_operand" "")))]
+ "TARGET_SSE4_2"
+{
+ rtx xops[6];
+ bool ok;
+
+ xops[0] = operands[0];
+ xops[1] = operands[1];
+ xops[2] = operands[2];
+ xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
+ xops[4] = operands[1];
+ xops[5] = operands[2];
+ ok = ix86_expand_int_vcond (xops);
+ gcc_assert (ok);
+ DONE;
+})
+
(define_expand "smin<mode>3"
[(set (match_operand:SSEMODE14 0 "register_operand" "")
(smin:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "")
}
})
+(define_expand "sminv2di3"
+ [(set (match_operand:V2DI 0 "register_operand" "")
+ (smin:V2DI (match_operand:V2DI 1 "register_operand" "")
+ (match_operand:V2DI 2 "register_operand" "")))]
+ "TARGET_SSE4_2"
+{
+ rtx xops[6];
+ bool ok;
+
+ xops[0] = operands[0];
+ xops[1] = operands[2];
+ xops[2] = operands[1];
+ xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
+ xops[4] = operands[1];
+ xops[5] = operands[2];
+ ok = ix86_expand_int_vcond (xops);
+ gcc_assert (ok);
+ DONE;
+})
+
(define_expand "umin<mode>3"
[(set (match_operand:SSEMODE24 0 "register_operand" "")
(umin:SSEMODE24 (match_operand:SSEMODE24 1 "register_operand" "")
}
})
+(define_expand "uminv2di3"
+ [(set (match_operand:V2DI 0 "register_operand" "")
+ (umin:V2DI (match_operand:V2DI 1 "register_operand" "")
+ (match_operand:V2DI 2 "register_operand" "")))]
+ "TARGET_SSE4_2"
+{
+ rtx xops[6];
+ bool ok;
+
+ xops[0] = operands[0];
+ xops[1] = operands[2];
+ xops[2] = operands[1];
+ xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
+ xops[4] = operands[1];
+ xops[5] = operands[2];
+ ok = ix86_expand_int_vcond (xops);
+ gcc_assert (ok);
+ DONE;
+})
+
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Parallel integral comparisons
(match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))]
"TARGET_AVX
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "v<logicprefix>ps\t{%2, %1, %0|%0, %1, %2}"
+ "v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecpsmode>")])
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"(TARGET_SSE && !TARGET_SSE2)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<logicprefix>ps\t{%2, %0|%0, %2}"
+ "<logic>ps\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "V4SF")])
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"TARGET_AVX
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "vp<logicprefix>\t{%2, %1, %0|%0, %1, %2}"
+ "vp<logic>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "p<logicprefix>\t{%2, %0|%0, %2}"
+ "p<logic>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(match_operand:TF 1 "nonimmediate_operand" "%0")
(match_operand:TF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
- "p<logicprefix>\t{%2, %0|%0, %2}"
+ "p<logic>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
{
operands[3] = CONST0_RTX (V2DImode);
}
- [(set_attr "type" "ssemuladd")
+ [(set_attr "type" "ssemul")
(set_attr "mode" "TI")])
(define_insn "xop_pmacsdqh"
{
operands[3] = CONST0_RTX (V2DImode);
}
- [(set_attr "type" "ssemuladd")
+ [(set_attr "type" "ssemul")
(set_attr "mode" "TI")])
;; XOP parallel integer multiply/add instructions for the intrinisics
(set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
+(define_insn "xop_vpermil2<mode>3"
+ [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
+ (unspec:AVXMODEF2P
+ [(match_operand:AVXMODEF2P 1 "register_operand" "x")
+ (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "%x")
+ (match_operand:<avxpermvecmode> 3 "nonimmediate_operand" "xm")
+ (match_operand:SI 4 "const_0_to_3_operand" "n")]
+ UNSPEC_VPERMIL2))]
+ "TARGET_XOP"
+ "vpermil2p<avxmodesuffixf2c>\t{%4, %3, %2, %1, %0|%0, %1, %2, %3, %4}"
+ [(set_attr "type" "sse4arg")
+ (set_attr "length_immediate" "1")
+ (set_attr "mode" "<MODE>")])
+
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_insn "*avx_aesenc"
[(set (match_operand:V2DI 0 "register_operand" "=x")
UNSPEC_VPERMIL2F128))]
"TARGET_AVX"
{
- int mask = INTVAL (operands[2]);
+ int mask = INTVAL (operands[3]);
if ((mask & 0x88) == 0)
{
rtx perm[<ssescalarnum>], t1, t2;